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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s4 5---6name: ctlz_zero_undef_s32_s7legalized: true8 9body: |10 bb.0:11 liveins: $sgpr012 ; CHECK-LABEL: name: ctlz_zero_undef_s32_s13 ; CHECK: liveins: $sgpr014 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr016 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)17 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)18 %0:_(s32) = COPY $sgpr019 %1:_(s32) = G_CTLZ_ZERO_UNDEF %020 S_ENDPGM 0, implicit %121...22 23---24name: ctlz_zero_undef_s32_v25legalized: true26 27body: |28 bb.0:29 liveins: $vgpr0_vgpr130 ; CHECK-LABEL: name: ctlz_zero_undef_s32_v31 ; CHECK: liveins: $vgpr0_vgpr132 ; CHECK-NEXT: {{ $}}33 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr034 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s32)35 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)36 %0:_(s32) = COPY $vgpr037 %1:_(s32) = G_CTLZ_ZERO_UNDEF %038 S_ENDPGM 0, implicit %139...40 41---42name: ctlz_zero_undef_s64_s43legalized: true44 45body: |46 bb.0:47 liveins: $sgpr0_sgpr148 ; CHECK-LABEL: name: ctlz_zero_undef_s64_s49 ; CHECK: liveins: $sgpr0_sgpr150 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr152 ; CHECK-NEXT: [[CTLZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTLZ_ZERO_UNDEF [[COPY]](s64)53 ; CHECK-NEXT: S_ENDPGM 0, implicit [[CTLZ_ZERO_UNDEF]](s32)54 %0:_(s64) = COPY $sgpr0_sgpr155 %1:_(s32) = G_CTLZ_ZERO_UNDEF %056 S_ENDPGM 0, implicit %157...58 59---60name: ctlz_zero_undef_s64_v61legalized: true62 63body: |64 bb.0:65 liveins: $vgpr0_vgpr166 ; CHECK-LABEL: name: ctlz_zero_undef_s64_v67 ; CHECK: liveins: $vgpr0_vgpr168 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr170 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)71 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[UV1]](s32)72 ; CHECK-NEXT: [[AMDGPU_FFBH_U32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBH_U32 [[UV]](s32)73 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 3274 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[AMDGPU_FFBH_U32_1]], [[C]]75 ; CHECK-NEXT: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBH_U32_]], [[ADD]]76 ; CHECK-NEXT: S_ENDPGM 0, implicit [[UMIN]](s32)77 %0:_(s64) = COPY $vgpr0_vgpr178 %1:_(s32) = G_CTLZ_ZERO_UNDEF %079 S_ENDPGM 0, implicit %180...81