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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s3# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s4 5---6name: fmul_ss7legalized: true8 9body: |10 bb.0:11 liveins: $sgpr0, $sgpr112 ; CHECK-LABEL: name: fmul_ss13 ; CHECK: liveins: $sgpr0, $sgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr016 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr117 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)18 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)19 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY2]], [[COPY3]]20 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FMUL]]21 %0:_(s32) = COPY $sgpr022 %1:_(s32) = COPY $sgpr123 %2:_(s32) = G_FMUL %0, %124...25 26---27name: fmul_sv28legalized: true29 30body: |31 bb.0:32 liveins: $sgpr0, $vgpr033 ; CHECK-LABEL: name: fmul_sv34 ; CHECK: liveins: $sgpr0, $vgpr035 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr037 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr038 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)39 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY2]], [[COPY1]]40 %0:_(s32) = COPY $sgpr041 %1:_(s32) = COPY $vgpr042 %2:_(s32) = G_FMUL %0, %143...44 45---46name: fmul_vs47legalized: true48 49body: |50 bb.0:51 liveins: $sgpr0, $vgpr052 ; CHECK-LABEL: name: fmul_vs53 ; CHECK: liveins: $sgpr0, $vgpr054 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr056 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr057 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)58 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY2]]59 %0:_(s32) = COPY $vgpr060 %1:_(s32) = COPY $sgpr061 %2:_(s32) = G_FMUL %0, %162...63 64---65name: fmul_vv66legalized: true67 68body: |69 bb.0:70 liveins: $vgpr0, $vgpr171 ; CHECK-LABEL: name: fmul_vv72 ; CHECK: liveins: $vgpr0, $vgpr173 ; CHECK-NEXT: {{ $}}74 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr075 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr176 ; CHECK-NEXT: [[FMUL:%[0-9]+]]:vgpr(s32) = G_FMUL [[COPY]], [[COPY1]]77 %0:_(s32) = COPY $vgpr078 %1:_(s32) = COPY $vgpr179 %2:_(s32) = G_FMUL %0, %180...81