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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbanklegalize %s -verify-machineinstrs -o - | FileCheck %s3 4---5name: uniform_in_vgpr6legalized: true7body: |8 bb.0:9 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr110 11 ; CHECK-LABEL: name: uniform_in_vgpr12 ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr116 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr017 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr118 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)19 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)20 ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:vgpr(s32) = G_FPTOUI [[COPY4]](s32)21 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOUI]]22 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[AMDGPU_READANYLANE]], [[COPY1]]23 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)24 ; CHECK-NEXT: G_STORE [[COPY5]](s32), [[MV]](p1) :: (store (s32), addrspace 1)25 ; CHECK-NEXT: S_ENDPGM 026 %0:sgpr(s32) = COPY $sgpr027 %1:sgpr(s32) = COPY $sgpr128 %2:vgpr(s32) = COPY $vgpr029 %3:vgpr(s32) = COPY $vgpr130 %4:vgpr(p1) = G_MERGE_VALUES %2(s32), %3(s32)31 %5:sgpr(s32) = G_FPTOUI %0(s32)32 %6:sgpr(s32) = G_ADD %5, %133 G_STORE %6(s32), %4(p1) :: (store (s32), addrspace 1)34 S_ENDPGM 035...36 37---38name: back_to_back_uniform_in_vgpr39legalized: true40body: |41 bb.0:42 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr143 44 ; CHECK-LABEL: name: back_to_back_uniform_in_vgpr45 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr146 ; CHECK-NEXT: {{ $}}47 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr048 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr149 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr250 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr051 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr152 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)53 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)54 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)55 ; CHECK-NEXT: [[FADD:%[0-9]+]]:vgpr(s32) = G_FADD [[COPY5]], [[COPY6]]56 ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:vgpr(s32) = G_FPTOUI [[FADD]](s32)57 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[FPTOUI]]58 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[AMDGPU_READANYLANE]], [[COPY2]]59 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)60 ; CHECK-NEXT: G_STORE [[COPY7]](s32), [[MV]](p1) :: (store (s32), addrspace 1)61 ; CHECK-NEXT: S_ENDPGM 062 %0:sgpr(s32) = COPY $sgpr063 %1:sgpr(s32) = COPY $sgpr164 %2:sgpr(s32) = COPY $sgpr265 %3:vgpr(s32) = COPY $vgpr066 %4:vgpr(s32) = COPY $vgpr167 %5:vgpr(p1) = G_MERGE_VALUES %3(s32), %4(s32)68 %6:sgpr(s32) = G_FADD %0, %169 %7:sgpr(s32) = G_FPTOUI %6(s32)70 %8:sgpr(s32) = G_ADD %7, %271 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)72 S_ENDPGM 073...74 75---76name: buffer_load_uniform77legalized: true78body: |79 bb.0:80 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr181 82 ; CHECK-LABEL: name: buffer_load_uniform83 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr184 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr086 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr187 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr288 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr389 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)90 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr491 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr092 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr193 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)94 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 095 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)96 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[COPY4]](s32)97 ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY8]], [[C]], 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)98 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)99 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV]]100 ; CHECK-NEXT: [[AMDGPU_READANYLANE1:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV1]]101 ; CHECK-NEXT: [[AMDGPU_READANYLANE2:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV2]]102 ; CHECK-NEXT: [[AMDGPU_READANYLANE3:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[UV3]]103 ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[AMDGPU_READANYLANE]](s32), [[AMDGPU_READANYLANE1]](s32), [[AMDGPU_READANYLANE2]](s32), [[AMDGPU_READANYLANE3]](s32)104 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1105 ; CHECK-NEXT: [[UV4:%[0-9]+]]:sgpr(s32), [[UV5:%[0-9]+]]:sgpr(s32), [[UV6:%[0-9]+]]:sgpr(s32), [[UV7:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[BUILD_VECTOR1]](<4 x s32>)106 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[UV5]], [[C1]]107 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)108 ; CHECK-NEXT: G_STORE [[COPY9]](s32), [[MV]](p1) :: (store (s32), addrspace 1)109 ; CHECK-NEXT: S_ENDPGM 0110 %0:sgpr(s32) = COPY $sgpr0111 %1:sgpr(s32) = COPY $sgpr1112 %2:sgpr(s32) = COPY $sgpr2113 %3:sgpr(s32) = COPY $sgpr3114 %4:sgpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)115 %5:sgpr(s32) = COPY $sgpr4116 %6:vgpr(s32) = COPY $vgpr0117 %7:vgpr(s32) = COPY $vgpr1118 %8:vgpr(p1) = G_MERGE_VALUES %6(s32), %7(s32)119 %9:sgpr(s32) = G_CONSTANT i32 0120 %10:sgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD %4(<4 x s32>), %9(s32), %5, %9, 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)121 %11:sgpr(s32) = G_CONSTANT i32 1122 %12:sgpr(s32), %13:sgpr(s32), %14:sgpr(s32), %15:sgpr(s32) = G_UNMERGE_VALUES %10(<4 x s32>)123 %16:sgpr(s32) = G_ADD %13, %11124 G_STORE %16(s32), %8(p1) :: (store (s32), addrspace 1)125 S_ENDPGM 0126...127 128---129name: buffer_load_divergent130legalized: true131body: |132 bb.0:133 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2134 135 ; CHECK-LABEL: name: buffer_load_divergent136 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2137 ; CHECK-NEXT: {{ $}}138 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0139 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1140 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2141 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3142 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)143 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0144 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1145 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2146 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)147 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0148 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)149 ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[COPY7]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)150 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1151 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)152 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)153 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[UV1]], [[COPY8]]154 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)155 ; CHECK-NEXT: S_ENDPGM 0156 %0:sgpr(s32) = COPY $sgpr0157 %1:sgpr(s32) = COPY $sgpr1158 %2:sgpr(s32) = COPY $sgpr2159 %3:sgpr(s32) = COPY $sgpr3160 %4:sgpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)161 %5:vgpr(s32) = COPY $vgpr0162 %6:vgpr(s32) = COPY $vgpr1163 %7:vgpr(s32) = COPY $vgpr2164 %8:vgpr(p1) = G_MERGE_VALUES %6(s32), %7(s32)165 %9:sgpr(s32) = G_CONSTANT i32 0166 %10:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD %4(<4 x s32>), %9(s32), %5, %9, 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)167 %11:sgpr(s32) = G_CONSTANT i32 1168 %12:vgpr(s32), %13:vgpr(s32), %14:vgpr(s32), %15:vgpr(s32) = G_UNMERGE_VALUES %10(<4 x s32>)169 %16:vgpr(s32) = G_ADD %13, %11170 G_STORE %16(s32), %8(p1) :: (store (s32), addrspace 1)171 S_ENDPGM 0172...173 174---175name: vgpr_and_i64176legalized: true177body: |178 bb.0:179 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5180 181 ; CHECK-LABEL: name: vgpr_and_i64182 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0185 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1186 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)187 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2188 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3189 ; CHECK-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)190 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4191 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5192 ; CHECK-NEXT: [[MV2:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)193 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV]](s64)194 ; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[MV1]](s64)195 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[UV]], [[UV2]]196 ; CHECK-NEXT: [[AND1:%[0-9]+]]:vgpr(s32) = G_AND [[UV1]], [[UV3]]197 ; CHECK-NEXT: [[MV3:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[AND]](s32), [[AND1]](s32)198 ; CHECK-NEXT: G_STORE [[MV3]](s64), [[MV2]](p1) :: (store (s64), addrspace 1)199 ; CHECK-NEXT: S_ENDPGM 0200 %0:vgpr(s32) = COPY $vgpr0201 %1:vgpr(s32) = COPY $vgpr1202 %2:vgpr(s64) = G_MERGE_VALUES %0(s32), %1(s32)203 %3:vgpr(s32) = COPY $vgpr2204 %4:vgpr(s32) = COPY $vgpr3205 %5:vgpr(s64) = G_MERGE_VALUES %3(s32), %4(s32)206 %6:vgpr(s32) = COPY $vgpr4207 %7:vgpr(s32) = COPY $vgpr5208 %8:vgpr(p1) = G_MERGE_VALUES %6(s32), %7(s32)209 %9:vgpr(s64) = G_AND %2, %5210 G_STORE %9(s64), %8(p1) :: (store (s64), addrspace 1)211 S_ENDPGM 0212...213 214---215name: abs_sgpr_i16216legalized: true217body: |218 bb.0:219 liveins: $sgpr0, $vgpr0, $vgpr1220 221 ; CHECK-LABEL: name: abs_sgpr_i16222 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1223 ; CHECK-NEXT: {{ $}}224 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0225 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)226 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0227 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1228 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)229 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[TRUNC]](s16)230 ; CHECK-NEXT: [[ABS:%[0-9]+]]:sgpr(s32) = G_ABS [[SEXT]]231 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:sgpr(s16) = G_TRUNC [[ABS]](s32)232 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[TRUNC1]](s16)233 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[ANYEXT]](s32)234 ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[MV]](p1) :: (store (s16), addrspace 1)235 ; CHECK-NEXT: S_ENDPGM 0236 %0:sgpr(s32) = COPY $sgpr0237 %1:sgpr(s16) = G_TRUNC %0(s32)238 %2:vgpr(s32) = COPY $vgpr0239 %3:vgpr(s32) = COPY $vgpr1240 %4:vgpr(p1) = G_MERGE_VALUES %2(s32), %3(s32)241 %5:sgpr(s16) = G_ABS %1242 %6:sgpr(s32) = G_ANYEXT %5(s16)243 G_STORE %6(s32), %4(p1) :: (store (s16), addrspace 1)244 S_ENDPGM 0245...246 247---248name: uniform_i1_phi249legalized: true250tracksRegLiveness: true251body: |252 ; CHECK-LABEL: name: uniform_i1_phi253 ; CHECK: bb.0:254 ; CHECK-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)255 ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1256 ; CHECK-NEXT: {{ $}}257 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0258 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1259 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)260 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0261 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr1262 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6263 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]264 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0265 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]266 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1267 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP1]], [[C2]]268 ; CHECK-NEXT: G_BRCOND [[AND]](s32), %bb.2269 ; CHECK-NEXT: G_BR %bb.1270 ; CHECK-NEXT: {{ $}}271 ; CHECK-NEXT: bb.1:272 ; CHECK-NEXT: successors: %bb.2(0x80000000)273 ; CHECK-NEXT: {{ $}}274 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1275 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[COPY2]](s32), [[C3]]276 ; CHECK-NEXT: {{ $}}277 ; CHECK-NEXT: bb.2:278 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI [[ICMP]](s32), %bb.0, [[ICMP2]](s32), %bb.1279 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1280 ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[PHI]], [[C4]]281 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1282 ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0283 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND1]](s32), [[C5]], [[C6]]284 ; CHECK-NEXT: [[C7:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2285 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[SELECT]], [[C7]]286 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)287 ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[MV]](p1) :: (store (s32), addrspace 1)288 ; CHECK-NEXT: S_ENDPGM 0289 bb.0:290 successors: %bb.1(0x30000000), %bb.2(0x50000000)291 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1292 293 %0:vgpr(s32) = COPY $vgpr0294 %1:vgpr(s32) = COPY $vgpr1295 %2:vgpr(p1) = G_MERGE_VALUES %0(s32), %1(s32)296 %3:sgpr(s32) = COPY $sgpr0297 %4:sgpr(s32) = COPY $sgpr1298 %5:sgpr(s32) = G_CONSTANT i32 6299 %6:sgpr(s1) = G_ICMP intpred(uge), %3(s32), %5300 %7:sgpr(s32) = G_CONSTANT i32 0301 %8:sgpr(s1) = G_ICMP intpred(ne), %4(s32), %7302 G_BRCOND %8(s1), %bb.2303 G_BR %bb.1304 305 bb.1:306 successors: %bb.2(0x80000000)307 308 %9:sgpr(s32) = G_CONSTANT i32 1309 %10:sgpr(s1) = G_ICMP intpred(ult), %3(s32), %9310 311 bb.2:312 %11:sgpr(s1) = G_PHI %6(s1), %bb.0, %10(s1), %bb.1313 %12:sgpr(s32) = G_SEXT %11(s1)314 %13:sgpr(s32) = G_CONSTANT i32 2315 %14:sgpr(s32) = G_ADD %12, %13316 G_STORE %14(s32), %2(p1) :: (store (s32), addrspace 1)317 S_ENDPGM 0318...319 320---321name: vcc_to_scc322legalized: true323body: |324 bb.0:325 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1326 327 ; CHECK-LABEL: name: vcc_to_scc328 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1329 ; CHECK-NEXT: {{ $}}330 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0331 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1332 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2333 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0334 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr1335 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)336 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00337 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)338 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)339 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(oeq), [[COPY5]](s32), [[COPY6]]340 ; CHECK-NEXT: [[AMDGPU_COPY_SCC_VCC:%[0-9]+]]:sgpr(s32) = G_AMDGPU_COPY_SCC_VCC [[FCMP]](s1)341 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1342 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[AMDGPU_COPY_SCC_VCC]], [[C1]]343 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND]](s32), [[COPY1]], [[COPY2]]344 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)345 ; CHECK-NEXT: G_STORE [[COPY7]](s32), [[MV]](p1) :: (store (s32), addrspace 1)346 ; CHECK-NEXT: S_ENDPGM 0347 %0:sgpr(s32) = COPY $sgpr0348 %1:sgpr(s32) = COPY $sgpr1349 %2:sgpr(s32) = COPY $sgpr2350 %3:vgpr(s32) = COPY $vgpr0351 %4:vgpr(s32) = COPY $vgpr1352 %5:vgpr(p1) = G_MERGE_VALUES %3(s32), %4(s32)353 %6:sgpr(s32) = G_FCONSTANT float 0.000000e+00354 %7:sgpr(s1) = G_FCMP floatpred(oeq), %0(s32), %6355 %8:sgpr(s32) = G_SELECT %7(s1), %1, %2356 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)357 S_ENDPGM 0358...359 360---361name: scc_to_vcc362legalized: true363body: |364 bb.0:365 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3366 367 ; CHECK-LABEL: name: scc_to_vcc368 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3369 ; CHECK-NEXT: {{ $}}370 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0371 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0372 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1373 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2374 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr3375 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)376 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0377 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]378 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:vcc(s1) = G_AMDGPU_COPY_VCC_SCC [[ICMP]](s32)379 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AMDGPU_COPY_VCC_SCC]](s1), [[COPY1]], [[COPY2]]380 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)381 ; CHECK-NEXT: S_ENDPGM 0382 %0:sgpr(s32) = COPY $sgpr0383 %1:vgpr(s32) = COPY $vgpr0384 %2:vgpr(s32) = COPY $vgpr1385 %3:vgpr(s32) = COPY $vgpr2386 %4:vgpr(s32) = COPY $vgpr3387 %5:vgpr(p1) = G_MERGE_VALUES %3(s32), %4(s32)388 %6:sgpr(s32) = G_CONSTANT i32 0389 %7:sgpr(s1) = G_ICMP intpred(eq), %0(s32), %6390 %8:vgpr(s32) = G_SELECT %7(s1), %1, %2391 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)392 S_ENDPGM 0393...394 395---396name: vgpr_to_vcc_trunc397legalized: true398body: |399 bb.0:400 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4401 402 ; CHECK-LABEL: name: vgpr_to_vcc_trunc403 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4404 ; CHECK-NEXT: {{ $}}405 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0406 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1407 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2408 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3409 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4410 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)411 ; CHECK-NEXT: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 1412 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s32) = G_AND [[COPY]], [[C]]413 ; CHECK-NEXT: [[C1:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0414 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[AND]](s32), [[C1]]415 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]416 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)417 ; CHECK-NEXT: S_ENDPGM 0418 %0:vgpr(s32) = COPY $vgpr0419 %1:vgpr(s32) = COPY $vgpr1420 %2:vgpr(s32) = COPY $vgpr2421 %3:vgpr(s32) = COPY $vgpr3422 %4:vgpr(s32) = COPY $vgpr4423 %5:vgpr(p1) = G_MERGE_VALUES %3(s32), %4(s32)424 %6:vcc(s1) = G_TRUNC %0(s32)425 %7:vgpr(s32) = G_SELECT %6(s1), %1, %2426 G_STORE %7(s32), %5(p1) :: (store (s32), addrspace 1)427 S_ENDPGM 0428...429 430---431name: zext432legalized: true433body: |434 bb.0:435 liveins: $sgpr0, $vgpr0, $vgpr1436 437 ; CHECK-LABEL: name: zext438 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1439 ; CHECK-NEXT: {{ $}}440 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0441 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0442 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1443 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)444 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10445 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]446 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1447 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C1]]448 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0449 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND]](s32), [[C1]], [[C2]]450 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)451 ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[MV]](p1) :: (store (s32), addrspace 1)452 ; CHECK-NEXT: S_ENDPGM 0453 %0:sgpr(s32) = COPY $sgpr0454 %1:vgpr(s32) = COPY $vgpr0455 %2:vgpr(s32) = COPY $vgpr1456 %3:vgpr(p1) = G_MERGE_VALUES %1(s32), %2(s32)457 %4:sgpr(s32) = G_CONSTANT i32 10458 %5:sgpr(s1) = G_ICMP intpred(eq), %0(s32), %4459 %6:sgpr(s32) = G_ZEXT %5(s1)460 G_STORE %6(s32), %3(p1) :: (store (s32), addrspace 1)461 S_ENDPGM 0462...463 464---465name: sext466legalized: true467body: |468 bb.0:469 liveins: $sgpr0, $vgpr0, $vgpr1470 471 ; CHECK-LABEL: name: sext472 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1473 ; CHECK-NEXT: {{ $}}474 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0475 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0476 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1477 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)478 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10479 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]480 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1481 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[C1]]482 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1483 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0484 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND]](s32), [[C2]], [[C3]]485 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)486 ; CHECK-NEXT: G_STORE [[COPY3]](s32), [[MV]](p1) :: (store (s32), addrspace 1)487 ; CHECK-NEXT: S_ENDPGM 0488 %0:sgpr(s32) = COPY $sgpr0489 %1:vgpr(s32) = COPY $vgpr0490 %2:vgpr(s32) = COPY $vgpr1491 %3:vgpr(p1) = G_MERGE_VALUES %1(s32), %2(s32)492 %4:sgpr(s32) = G_CONSTANT i32 10493 %5:sgpr(s1) = G_ICMP intpred(eq), %0(s32), %4494 %6:sgpr(s32) = G_SEXT %5(s1)495 G_STORE %6(s32), %3(p1) :: (store (s32), addrspace 1)496 S_ENDPGM 0497...498 499---500name: and_i1_vcc501legalized: true502body: |503 bb.0:504 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3505 506 ; CHECK-LABEL: name: and_i1_vcc507 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3508 ; CHECK-NEXT: {{ $}}509 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0510 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1511 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2512 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3513 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)514 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10515 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)516 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(uge), [[COPY]](s32), [[COPY4]]517 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 20518 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)519 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(uge), [[COPY1]](s32), [[COPY5]]520 ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]521 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AND]](s1), [[COPY]], [[COPY1]]522 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)523 ; CHECK-NEXT: S_ENDPGM 0524 %0:vgpr(s32) = COPY $vgpr0525 %1:vgpr(s32) = COPY $vgpr1526 %2:vgpr(s32) = COPY $vgpr2527 %3:vgpr(s32) = COPY $vgpr3528 %4:vgpr(p1) = G_MERGE_VALUES %2(s32), %3(s32)529 %5:sgpr(s32) = G_CONSTANT i32 10530 %6:vcc(s1) = G_ICMP intpred(uge), %0(s32), %5531 %7:sgpr(s32) = G_CONSTANT i32 20532 %8:vcc(s1) = G_ICMP intpred(uge), %1(s32), %7533 %9:vcc(s1) = G_AND %6, %8534 %10:vgpr(s32) = G_SELECT %9(s1), %0, %1535 G_STORE %10(s32), %4(p1) :: (store (s32), addrspace 1)536 S_ENDPGM 0537...538 539---540name: and_i1_scc541legalized: true542body: |543 bb.0:544 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1545 546 ; CHECK-LABEL: name: and_i1_scc547 ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1548 ; CHECK-NEXT: {{ $}}549 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0550 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1551 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0552 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1553 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)554 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10555 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(uge), [[COPY]](s32), [[C]]556 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 20557 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(uge), [[COPY1]](s32), [[C1]]558 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP]], [[ICMP1]]559 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1560 ; CHECK-NEXT: [[AND1:%[0-9]+]]:sgpr(s32) = G_AND [[AND]], [[C2]]561 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND1]](s32), [[COPY]], [[COPY1]]562 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[SELECT]](s32)563 ; CHECK-NEXT: G_STORE [[COPY4]](s32), [[MV]](p1) :: (store (s32), addrspace 1)564 ; CHECK-NEXT: S_ENDPGM 0565 %0:sgpr(s32) = COPY $sgpr0566 %1:sgpr(s32) = COPY $sgpr1567 %2:vgpr(s32) = COPY $vgpr0568 %3:vgpr(s32) = COPY $vgpr1569 %4:vgpr(p1) = G_MERGE_VALUES %2(s32), %3(s32)570 %5:sgpr(s32) = G_CONSTANT i32 10571 %6:sgpr(s1) = G_ICMP intpred(uge), %0(s32), %5572 %7:sgpr(s32) = G_CONSTANT i32 20573 %8:sgpr(s1) = G_ICMP intpred(uge), %1(s32), %7574 %9:sgpr(s1) = G_AND %6, %8575 %10:sgpr(s32) = G_SELECT %9(s1), %0, %1576 G_STORE %10(s32), %4(p1) :: (store (s32), addrspace 1)577 S_ENDPGM 0578...579 580---581name: divergent_phi_with_uniform_inputs582legalized: true583tracksRegLiveness: true584body: |585 ; CHECK-LABEL: name: divergent_phi_with_uniform_inputs586 ; CHECK: bb.0:587 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)588 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0591 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1592 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2593 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)594 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0595 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)596 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY3]]597 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)598 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY4]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec599 ; CHECK-NEXT: G_BR %bb.1600 ; CHECK-NEXT: {{ $}}601 ; CHECK-NEXT: bb.1:602 ; CHECK-NEXT: successors: %bb.2(0x80000000)603 ; CHECK-NEXT: {{ $}}604 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1605 ; CHECK-NEXT: {{ $}}606 ; CHECK-NEXT: bb.2:607 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[C]](s32), %bb.0, [[C1]](s32), %bb.1608 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF]](s32)609 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY5]](s32)610 ; CHECK-NEXT: G_STORE [[PHI]](s32), [[MV]](p1) :: (store (s32), addrspace 1)611 ; CHECK-NEXT: S_ENDPGM 0612 bb.0:613 successors: %bb.1(0x40000000), %bb.2(0x40000000)614 liveins: $vgpr0, $vgpr1, $vgpr2615 616 %0:vgpr(s32) = COPY $vgpr0617 %1:vgpr(s32) = COPY $vgpr1618 %2:vgpr(s32) = COPY $vgpr2619 %3:vgpr(p1) = G_MERGE_VALUES %1(s32), %2(s32)620 %4:sgpr(s32) = G_CONSTANT i32 0621 %9:vcc(s1) = G_ICMP intpred(eq), %0(s32), %4622 %5:sreg_32_xm0_xexec(s1) = COPY %9(s1)623 %6:sreg_32_xm0_xexec(s32) = SI_IF %5(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec624 G_BR %bb.1625 626 bb.1:627 successors: %bb.2(0x80000000)628 629 %7:sgpr(s32) = G_CONSTANT i32 1630 631 bb.2:632 %8:vgpr(s32) = G_PHI %4(s32), %bb.0, %7(s32), %bb.1633 %10:sgpr(s32) = COPY %6(s32)634 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %10(s32)635 G_STORE %8(s32), %3(p1) :: (store (s32), addrspace 1)636 S_ENDPGM 0637...638 639---640name: divergent_because_of_temporal_divergent_use641legalized: true642tracksRegLiveness: true643body: |644 ; CHECK-LABEL: name: divergent_because_of_temporal_divergent_use645 ; CHECK: bb.0:646 ; CHECK-NEXT: successors: %bb.1(0x80000000)647 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2648 ; CHECK-NEXT: {{ $}}649 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0650 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1651 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2652 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)653 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1654 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0655 ; CHECK-NEXT: {{ $}}656 ; CHECK-NEXT: bb.1:657 ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)658 ; CHECK-NEXT: {{ $}}659 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI %7(s32), %bb.1, [[C1]](s32), %bb.0660 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sgpr(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.1661 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1662 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[PHI1]], [[C2]]663 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[ADD]](s32)664 ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:vgpr(s32) = G_UITOFP [[COPY3]](s32)665 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]666 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32)667 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32_xm0_xexec(s32) = COPY [[INT]](s32)668 ; CHECK-NEXT: SI_LOOP [[COPY4]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec669 ; CHECK-NEXT: G_BR %bb.2670 ; CHECK-NEXT: {{ $}}671 ; CHECK-NEXT: bb.2:672 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vgpr(s32) = G_PHI [[ADD]](s32), %bb.1673 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sgpr(s32) = G_PHI [[INT]](s32), %bb.1674 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI3]](s32)675 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10676 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY [[C3]](s32)677 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[PHI2]], [[COPY5]]678 ; CHECK-NEXT: G_STORE [[MUL]](s32), [[MV]](p1) :: (store (s32), addrspace 1)679 ; CHECK-NEXT: S_ENDPGM 0680 bb.0:681 successors: %bb.1(0x80000000)682 liveins: $vgpr0, $vgpr1, $vgpr2683 684 %0:vgpr(s32) = COPY $vgpr0685 %1:vgpr(s32) = COPY $vgpr1686 %2:vgpr(s32) = COPY $vgpr2687 %3:vgpr(p1) = G_MERGE_VALUES %1(s32), %2(s32)688 %4:sgpr(s32) = G_CONSTANT i32 -1689 %5:sgpr(s32) = G_CONSTANT i32 0690 691 bb.1:692 successors: %bb.2(0x04000000), %bb.1(0x7c000000)693 694 %6:sgpr(s32) = G_PHI %17(s32), %bb.1, %5(s32), %bb.0695 %8:sgpr(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.1696 %10:sgpr(s32) = G_CONSTANT i32 1697 %9:sgpr(s32) = G_ADD %8, %10698 %11:sgpr(s32) = G_UITOFP %9(s32)699 %12:vcc(s1) = G_FCMP floatpred(ogt), %11(s32), %0700 %17:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %12(s1), %6(s32)701 %7:sreg_32_xm0_xexec(s32) = COPY %17(s32)702 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec703 G_BR %bb.2704 705 bb.2:706 %13:vgpr(s32) = G_PHI %9(s32), %bb.1707 %14:sgpr(s32) = G_PHI %17(s32), %bb.1708 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %14(s32)709 %15:sgpr(s32) = G_CONSTANT i32 10710 %16:vgpr(s32) = G_MUL %13, %15711 G_STORE %16(s32), %3(p1) :: (store (s32), addrspace 1)712 S_ENDPGM 0713...714 715---716name: loop_with_2breaks717legalized: true718tracksRegLiveness: true719body: |720 ; CHECK-LABEL: name: loop_with_2breaks721 ; CHECK: bb.0:722 ; CHECK-NEXT: successors: %bb.1(0x80000000)723 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5724 ; CHECK-NEXT: {{ $}}725 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0726 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1727 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)728 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2729 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3730 ; CHECK-NEXT: [[MV1:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)731 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4732 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5733 ; CHECK-NEXT: [[MV2:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)734 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF735 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0736 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF737 ; CHECK-NEXT: {{ $}}738 ; CHECK-NEXT: bb.1:739 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)740 ; CHECK-NEXT: {{ $}}741 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %13(s1), %bb.3742 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sgpr(s32) = G_PHI %15(s32), %bb.3, [[C]](s32), %bb.0743 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sgpr(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3744 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)745 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31746 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:sgpr(s32) = G_ASHR [[PHI2]], [[C1]](s32)747 ; CHECK-NEXT: [[MV3:%[0-9]+]]:sgpr(s64) = G_MERGE_VALUES [[PHI2]](s32), [[ASHR]](s32)748 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2749 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[MV3]], [[C2]](s32)750 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr(s64) = COPY [[SHL]](s64)751 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV1]], [[COPY7]](s64)752 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)753 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0754 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr(s32) = COPY [[C3]](s32)755 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[COPY8]]756 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)757 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1758 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC:%[0-9]+]]:sreg_32(s1) = G_AMDGPU_COPY_VCC_SCC [[C4]](s32)759 ; CHECK-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc760 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[AMDGPU_COPY_VCC_SCC]](s1), implicit-def $scc761 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc762 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)763 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY9]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec764 ; CHECK-NEXT: G_BR %bb.2765 ; CHECK-NEXT: {{ $}}766 ; CHECK-NEXT: bb.2:767 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)768 ; CHECK-NEXT: {{ $}}769 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2770 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:sgpr(s64) = G_SHL [[MV3]], [[C5]](s32)771 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr(s64) = COPY [[SHL1]](s64)772 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV2]], [[COPY11]](s64)773 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)774 ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0775 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr(s32) = COPY [[C6]](s32)776 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[COPY12]]777 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP1]](s1)778 ; CHECK-NEXT: [[C7:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1779 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC1:%[0-9]+]]:sreg_32(s1) = G_AMDGPU_COPY_VCC_SCC [[C7]](s32)780 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sreg_32(s1) = COPY [[AMDGPU_COPY_VCC_SCC1]](s1)781 ; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY13]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec782 ; CHECK-NEXT: G_BR %bb.4783 ; CHECK-NEXT: {{ $}}784 ; CHECK-NEXT: bb.3:785 ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)786 ; CHECK-NEXT: {{ $}}787 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %45(s1), %bb.5788 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sgpr(s32) = G_PHI %46(s32), %bb.5, [[DEF]](s32), %bb.1789 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)790 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF]](s32)791 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY16]](s32)792 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:vcc(s1) = COPY [[COPY15]](s1)793 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY17]](s1), [[PHI1]](s32)794 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sreg_32_xm0_xexec(s32) = COPY [[INT]](s32)795 ; CHECK-NEXT: SI_LOOP [[COPY18]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec796 ; CHECK-NEXT: G_BR %bb.6797 ; CHECK-NEXT: {{ $}}798 ; CHECK-NEXT: bb.4:799 ; CHECK-NEXT: successors: %bb.5(0x80000000)800 ; CHECK-NEXT: {{ $}}801 ; CHECK-NEXT: [[C8:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2802 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:sgpr(s64) = G_SHL [[MV3]], [[C8]](s32)803 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:vgpr(s64) = COPY [[SHL2]](s64)804 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV]], [[COPY19]](s64)805 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)806 ; CHECK-NEXT: [[C9:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1807 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:vgpr(s32) = COPY [[C9]](s32)808 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[LOAD2]], [[COPY20]]809 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1)810 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[PHI2]], [[C9]]811 ; CHECK-NEXT: [[C10:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 100812 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s32) = G_ICMP intpred(ult), [[PHI2]](s32), [[C10]]813 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[ICMP2]], [[C9]]814 ; CHECK-NEXT: [[AMDGPU_COPY_VCC_SCC2:%[0-9]+]]:sreg_32(s1) = G_AMDGPU_COPY_VCC_SCC [[AND]](s32)815 ; CHECK-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY14]](s1), $exec_lo, implicit-def $scc816 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[AMDGPU_COPY_VCC_SCC2]](s1), implicit-def $scc817 ; CHECK-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc818 ; CHECK-NEXT: {{ $}}819 ; CHECK-NEXT: bb.5:820 ; CHECK-NEXT: successors: %bb.3(0x80000000)821 ; CHECK-NEXT: {{ $}}822 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[AMDGPU_COPY_VCC_SCC1]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.4823 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:sgpr(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2824 ; CHECK-NEXT: [[COPY21:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)825 ; CHECK-NEXT: [[COPY22:%[0-9]+]]:sreg_32(s1) = COPY [[COPY21]](s1)826 ; CHECK-NEXT: [[COPY23:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF1]](s32)827 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY23]](s32)828 ; CHECK-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY10]](s1), $exec_lo, implicit-def $scc829 ; CHECK-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY22]](s1), implicit-def $scc830 ; CHECK-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc831 ; CHECK-NEXT: G_BR %bb.3832 ; CHECK-NEXT: {{ $}}833 ; CHECK-NEXT: bb.6:834 ; CHECK-NEXT: [[PHI7:%[0-9]+]]:sgpr(s32) = G_PHI [[INT]](s32), %bb.3835 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[PHI7]](s32)836 ; CHECK-NEXT: S_ENDPGM 0837 bb.0:838 successors: %bb.1(0x80000000)839 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5840 841 %0:vgpr(s32) = COPY $vgpr0842 %1:vgpr(s32) = COPY $vgpr1843 %2:vgpr(p1) = G_MERGE_VALUES %0(s32), %1(s32)844 %3:vgpr(s32) = COPY $vgpr2845 %4:vgpr(s32) = COPY $vgpr3846 %5:vgpr(p1) = G_MERGE_VALUES %3(s32), %4(s32)847 %6:vgpr(s32) = COPY $vgpr4848 %7:vgpr(s32) = COPY $vgpr5849 %8:vgpr(p1) = G_MERGE_VALUES %6(s32), %7(s32)850 %9:sgpr(s32) = G_IMPLICIT_DEF851 %10:sgpr(s32) = G_CONSTANT i32 0852 %11:sreg_32(s1) = IMPLICIT_DEF853 854 bb.1:855 successors: %bb.2(0x40000000), %bb.3(0x40000000)856 857 %12:sreg_32(s1) = PHI %11(s1), %bb.0, %13(s1), %bb.3858 %14:sgpr(s32) = G_PHI %15(s32), %bb.3, %10(s32), %bb.0859 %16:sgpr(s32) = G_PHI %10(s32), %bb.0, %17(s32), %bb.3860 %18:sreg_32(s1) = COPY %12(s1)861 %19:sgpr(s64) = G_SEXT %16(s32)862 %20:sgpr(s32) = G_CONSTANT i32 2863 %21:sgpr(s64) = G_SHL %19, %20(s32)864 %22:vgpr(p1) = G_PTR_ADD %5, %21(s64)865 %23:vgpr(s32) = G_LOAD %22(p1) :: (load (s32), addrspace 1)866 %24:sgpr(s32) = G_CONSTANT i32 0867 %25:vcc(s1) = G_ICMP intpred(ne), %23(s32), %24868 %26:sreg_32_xm0_xexec(s1) = COPY %25(s1)869 %27:sgpr(s1) = G_CONSTANT i1 true870 %28:sreg_32(s1) = COPY %27(s1)871 %29:sreg_32(s1) = S_ANDN2_B32 %18(s1), $exec_lo, implicit-def $scc872 %30:sreg_32(s1) = S_AND_B32 $exec_lo, %28(s1), implicit-def $scc873 %31:sreg_32(s1) = S_OR_B32 %29(s1), %30(s1), implicit-def $scc874 %32:sreg_32(s1) = COPY %31(s1)875 %33:sreg_32_xm0_xexec(s32) = SI_IF %26(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec876 G_BR %bb.2877 878 bb.2:879 successors: %bb.4(0x40000000), %bb.5(0x40000000)880 881 %34:sgpr(s32) = G_CONSTANT i32 2882 %35:sgpr(s64) = G_SHL %19, %34(s32)883 %36:vgpr(p1) = G_PTR_ADD %8, %35(s64)884 %37:vgpr(s32) = G_LOAD %36(p1) :: (load (s32), addrspace 1)885 %38:sgpr(s32) = G_CONSTANT i32 0886 %39:vcc(s1) = G_ICMP intpred(ne), %37(s32), %38887 %40:sreg_32_xm0_xexec(s1) = COPY %39(s1)888 %41:sgpr(s1) = G_CONSTANT i1 true889 %42:sreg_32(s1) = COPY %41(s1)890 %43:sreg_32(s1) = COPY %42(s1)891 %44:sreg_32_xm0_xexec(s32) = SI_IF %40(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec892 G_BR %bb.4893 894 bb.3:895 successors: %bb.6(0x04000000), %bb.1(0x7c000000)896 897 %13:sreg_32(s1) = PHI %31(s1), %bb.1, %45(s1), %bb.5898 %17:sgpr(s32) = G_PHI %46(s32), %bb.5, %9(s32), %bb.1899 %47:sreg_32(s1) = COPY %13(s1)900 %48:sgpr(s32) = COPY %33(s32)901 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %48(s32)902 %49:vcc(s1) = COPY %47(s1)903 %15:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %49(s1), %14(s32)904 %50:sreg_32_xm0_xexec(s32) = COPY %15(s32)905 SI_LOOP %50(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec906 G_BR %bb.6907 908 bb.4:909 successors: %bb.5(0x80000000)910 911 %51:sgpr(s32) = G_CONSTANT i32 2912 %52:sgpr(s64) = G_SHL %19, %51(s32)913 %53:vgpr(p1) = G_PTR_ADD %2, %52(s64)914 %54:vgpr(s32) = G_LOAD %53(p1) :: (load (s32), addrspace 1)915 %55:sgpr(s32) = G_CONSTANT i32 1916 %56:vgpr(s32) = G_ADD %54, %55917 G_STORE %56(s32), %53(p1) :: (store (s32), addrspace 1)918 %57:sgpr(s32) = G_ADD %16, %55919 %58:sgpr(s32) = G_CONSTANT i32 100920 %59:sgpr(s1) = G_ICMP intpred(ult), %16(s32), %58921 %60:sreg_32(s1) = COPY %59(s1)922 %61:sreg_32(s1) = S_ANDN2_B32 %43(s1), $exec_lo, implicit-def $scc923 %62:sreg_32(s1) = S_AND_B32 $exec_lo, %60(s1), implicit-def $scc924 %63:sreg_32(s1) = S_OR_B32 %61(s1), %62(s1), implicit-def $scc925 926 bb.5:927 successors: %bb.3(0x80000000)928 929 %64:sreg_32(s1) = PHI %42(s1), %bb.2, %63(s1), %bb.4930 %46:sgpr(s32) = G_PHI %57(s32), %bb.4, %9(s32), %bb.2931 %65:sreg_32(s1) = COPY %64(s1)932 %66:sreg_32(s1) = COPY %65(s1)933 %67:sgpr(s32) = COPY %44(s32)934 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %67(s32)935 %68:sreg_32(s1) = S_ANDN2_B32 %32(s1), $exec_lo, implicit-def $scc936 %69:sreg_32(s1) = S_AND_B32 $exec_lo, %66(s1), implicit-def $scc937 %45:sreg_32(s1) = S_OR_B32 %68(s1), %69(s1), implicit-def $scc938 G_BR %bb.3939 940 bb.6:941 %70:sgpr(s32) = G_PHI %15(s32), %bb.3942 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %70(s32)943 S_ENDPGM 0944...945