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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=amdgpu-regbankselect %s -verify-machineinstrs -o - | FileCheck %s3 4---5name: uniform_in_vgpr6legalized: true7body: |8 bb.0:9 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr110 11 ; CHECK-LABEL: name: uniform_in_vgpr12 ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr116 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr017 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr118 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)19 ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:sgpr(s32) = G_FPTOUI [[COPY]](s32)20 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[FPTOUI]], [[COPY1]]21 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)22 ; CHECK-NEXT: S_ENDPGM 023 %0:_(s32) = COPY $sgpr024 %1:_(s32) = COPY $sgpr125 %2:_(s32) = COPY $vgpr026 %3:_(s32) = COPY $vgpr127 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)28 %5:_(s32) = G_FPTOUI %0(s32)29 %6:_(s32) = G_ADD %5, %130 G_STORE %6(s32), %4(p1) :: (store (s32), addrspace 1)31 S_ENDPGM 032...33 34---35name: back_to_back_uniform_in_vgpr36legalized: true37body: |38 bb.0:39 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr140 41 ; CHECK-LABEL: name: back_to_back_uniform_in_vgpr42 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr143 ; CHECK-NEXT: {{ $}}44 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr045 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr146 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr247 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr048 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr149 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)50 ; CHECK-NEXT: [[FADD:%[0-9]+]]:sgpr(s32) = G_FADD [[COPY]], [[COPY1]]51 ; CHECK-NEXT: [[FPTOUI:%[0-9]+]]:sgpr(s32) = G_FPTOUI [[FADD]](s32)52 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[FPTOUI]], [[COPY2]]53 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)54 ; CHECK-NEXT: S_ENDPGM 055 %0:_(s32) = COPY $sgpr056 %1:_(s32) = COPY $sgpr157 %2:_(s32) = COPY $sgpr258 %3:_(s32) = COPY $vgpr059 %4:_(s32) = COPY $vgpr160 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)61 %6:_(s32) = G_FADD %0, %162 %7:_(s32) = G_FPTOUI %6(s32)63 %8:_(s32) = G_ADD %7, %264 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)65 S_ENDPGM 066...67 68---69name: buffer_load_uniform70legalized: true71body: |72 bb.0:73 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr174 75 ; CHECK-LABEL: name: buffer_load_uniform76 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr177 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr079 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr180 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr281 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr382 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)83 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY $sgpr484 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr085 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr186 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)87 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 088 ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:sgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)89 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 190 ; CHECK-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32), [[UV2:%[0-9]+]]:sgpr(s32), [[UV3:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)91 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[UV1]], [[C1]]92 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)93 ; CHECK-NEXT: S_ENDPGM 094 %0:_(s32) = COPY $sgpr095 %1:_(s32) = COPY $sgpr196 %2:_(s32) = COPY $sgpr297 %3:_(s32) = COPY $sgpr398 %4:_(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)99 %5:_(s32) = COPY $sgpr4100 %6:_(s32) = COPY $vgpr0101 %7:_(s32) = COPY $vgpr1102 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)103 %9:_(s32) = G_CONSTANT i32 0104 %10:_(<4 x s32>) = G_AMDGPU_BUFFER_LOAD %4(<4 x s32>), %9(s32), %5, %9, 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)105 %11:_(s32) = G_CONSTANT i32 1106 %12:_(s32), %13:_(s32), %14:_(s32), %15:_(s32) = G_UNMERGE_VALUES %10(<4 x s32>)107 %16:_(s32) = G_ADD %13, %11108 G_STORE %16(s32), %8(p1) :: (store (s32), addrspace 1)109 S_ENDPGM 0110...111 112---113name: buffer_load_divergent114legalized: true115body: |116 bb.0:117 liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2118 119 ; CHECK-LABEL: name: buffer_load_divergent120 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2121 ; CHECK-NEXT: {{ $}}122 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0123 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1124 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2125 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr3126 ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x s32>) = G_BUILD_VECTOR [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32), [[COPY3]](s32)127 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr0128 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr1129 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr(s32) = COPY $vgpr2130 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY5]](s32), [[COPY6]](s32)131 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0132 ; CHECK-NEXT: [[AMDGPU_BUFFER_LOAD:%[0-9]+]]:vgpr(<4 x s32>) = G_AMDGPU_BUFFER_LOAD [[BUILD_VECTOR]](<4 x s32>), [[C]](s32), [[COPY4]], [[C]], 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)133 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1134 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32), [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[AMDGPU_BUFFER_LOAD]](<4 x s32>)135 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[UV1]], [[C1]]136 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)137 ; CHECK-NEXT: S_ENDPGM 0138 %0:_(s32) = COPY $sgpr0139 %1:_(s32) = COPY $sgpr1140 %2:_(s32) = COPY $sgpr2141 %3:_(s32) = COPY $sgpr3142 %4:_(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32)143 %5:_(s32) = COPY $vgpr0144 %6:_(s32) = COPY $vgpr1145 %7:_(s32) = COPY $vgpr2146 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)147 %9:_(s32) = G_CONSTANT i32 0148 %10:_(<4 x s32>) = G_AMDGPU_BUFFER_LOAD %4(<4 x s32>), %9(s32), %5, %9, 0, 0, 0 :: (dereferenceable load (<4 x s32>), align 1, addrspace 8)149 %11:_(s32) = G_CONSTANT i32 1150 %12:_(s32), %13:_(s32), %14:_(s32), %15:_(s32) = G_UNMERGE_VALUES %10(<4 x s32>)151 %16:_(s32) = G_ADD %13, %11152 G_STORE %16(s32), %8(p1) :: (store (s32), addrspace 1)153 S_ENDPGM 0154...155 156---157name: vgpr_and_i64158legalized: true159body: |160 bb.0:161 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5162 163 ; CHECK-LABEL: name: vgpr_and_i64164 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5165 ; CHECK-NEXT: {{ $}}166 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0167 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1168 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)169 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2170 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3171 ; CHECK-NEXT: [[MV1:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)172 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4173 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5174 ; CHECK-NEXT: [[MV2:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)175 ; CHECK-NEXT: [[AND:%[0-9]+]]:vgpr(s64) = G_AND [[MV]], [[MV1]]176 ; CHECK-NEXT: G_STORE [[AND]](s64), [[MV2]](p1) :: (store (s64), addrspace 1)177 ; CHECK-NEXT: S_ENDPGM 0178 %0:_(s32) = COPY $vgpr0179 %1:_(s32) = COPY $vgpr1180 %2:_(s64) = G_MERGE_VALUES %0(s32), %1(s32)181 %3:_(s32) = COPY $vgpr2182 %4:_(s32) = COPY $vgpr3183 %5:_(s64) = G_MERGE_VALUES %3(s32), %4(s32)184 %6:_(s32) = COPY $vgpr4185 %7:_(s32) = COPY $vgpr5186 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)187 %9:_(s64) = G_AND %2, %5188 G_STORE %9(s64), %8(p1) :: (store (s64), addrspace 1)189 S_ENDPGM 0190...191 192---193name: abs_sgpr_i16194legalized: true195body: |196 bb.0:197 liveins: $sgpr0, $vgpr0, $vgpr1198 199 ; CHECK-LABEL: name: abs_sgpr_i16200 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1201 ; CHECK-NEXT: {{ $}}202 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0203 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:sgpr(s16) = G_TRUNC [[COPY]](s32)204 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0205 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1206 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)207 ; CHECK-NEXT: [[ABS:%[0-9]+]]:sgpr(s16) = G_ABS [[TRUNC]]208 ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:sgpr(s32) = G_ANYEXT [[ABS]](s16)209 ; CHECK-NEXT: G_STORE [[ANYEXT]](s32), [[MV]](p1) :: (store (s16), addrspace 1)210 ; CHECK-NEXT: S_ENDPGM 0211 %0:_(s32) = COPY $sgpr0212 %1:_(s16) = G_TRUNC %0(s32)213 %2:_(s32) = COPY $vgpr0214 %3:_(s32) = COPY $vgpr1215 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)216 %5:_(s16) = G_ABS %1217 %6:_(s32) = G_ANYEXT %5(s16)218 G_STORE %6(s32), %4(p1) :: (store (s16), addrspace 1)219 S_ENDPGM 0220...221 222---223name: uniform_i1_phi224legalized: true225tracksRegLiveness: true226body: |227 ; CHECK-LABEL: name: uniform_i1_phi228 ; CHECK: bb.0:229 ; CHECK-NEXT: successors: %bb.1(0x30000000), %bb.2(0x50000000)230 ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1231 ; CHECK-NEXT: {{ $}}232 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0233 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1234 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)235 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr0236 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY $sgpr1237 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6238 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(uge), [[COPY2]](s32), [[C]]239 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0240 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ne), [[COPY3]](s32), [[C1]]241 ; CHECK-NEXT: G_BRCOND [[ICMP1]](s1), %bb.2242 ; CHECK-NEXT: G_BR %bb.1243 ; CHECK-NEXT: {{ $}}244 ; CHECK-NEXT: bb.1:245 ; CHECK-NEXT: successors: %bb.2(0x80000000)246 ; CHECK-NEXT: {{ $}}247 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1248 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ult), [[COPY2]](s32), [[C2]]249 ; CHECK-NEXT: {{ $}}250 ; CHECK-NEXT: bb.2:251 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr(s1) = G_PHI [[ICMP]](s1), %bb.0, [[ICMP2]](s1), %bb.1252 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[PHI]](s1)253 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2254 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[SEXT]], [[C3]]255 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[MV]](p1) :: (store (s32), addrspace 1)256 ; CHECK-NEXT: S_ENDPGM 0257 bb.0:258 successors: %bb.1(0x30000000), %bb.2(0x50000000)259 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1260 261 %0:_(s32) = COPY $vgpr0262 %1:_(s32) = COPY $vgpr1263 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)264 %3:_(s32) = COPY $sgpr0265 %4:_(s32) = COPY $sgpr1266 %5:_(s32) = G_CONSTANT i32 6267 %6:_(s1) = G_ICMP intpred(uge), %3(s32), %5268 %7:_(s32) = G_CONSTANT i32 0269 %8:_(s1) = G_ICMP intpred(ne), %4(s32), %7270 G_BRCOND %8(s1), %bb.2271 G_BR %bb.1272 273 bb.1:274 successors: %bb.2(0x80000000)275 276 %9:_(s32) = G_CONSTANT i32 1277 %10:_(s1) = G_ICMP intpred(ult), %3(s32), %9278 279 bb.2:280 %11:_(s1) = G_PHI %6(s1), %bb.0, %10(s1), %bb.1281 %12:_(s32) = G_SEXT %11(s1)282 %13:_(s32) = G_CONSTANT i32 2283 %14:_(s32) = G_ADD %12, %13284 G_STORE %14(s32), %2(p1) :: (store (s32), addrspace 1)285 S_ENDPGM 0286...287 288---289name: vcc_to_scc290legalized: true291body: |292 bb.0:293 liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1294 295 ; CHECK-LABEL: name: vcc_to_scc296 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1297 ; CHECK-NEXT: {{ $}}298 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0299 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1300 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2301 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr0302 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr1303 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)304 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_FCONSTANT float 0.000000e+00305 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:sgpr(s1) = G_FCMP floatpred(oeq), [[COPY]](s32), [[C]]306 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[FCMP]](s1), [[COPY1]], [[COPY2]]307 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)308 ; CHECK-NEXT: S_ENDPGM 0309 %0:_(s32) = COPY $sgpr0310 %1:_(s32) = COPY $sgpr1311 %2:_(s32) = COPY $sgpr2312 %3:_(s32) = COPY $vgpr0313 %4:_(s32) = COPY $vgpr1314 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)315 %6:_(s32) = G_FCONSTANT float 0.000000e+00316 %7:_(s1) = G_FCMP floatpred(oeq), %0(s32), %6317 %8:_(s32) = G_SELECT %7(s1), %1, %2318 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)319 S_ENDPGM 0320...321 322---323name: scc_to_vcc324legalized: true325body: |326 bb.0:327 liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3328 329 ; CHECK-LABEL: name: scc_to_vcc330 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3331 ; CHECK-NEXT: {{ $}}332 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0333 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0334 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1335 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr2336 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr3337 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)338 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0339 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]340 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[ICMP]](s1), [[COPY1]], [[COPY2]]341 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)342 ; CHECK-NEXT: S_ENDPGM 0343 %0:_(s32) = COPY $sgpr0344 %1:_(s32) = COPY $vgpr0345 %2:_(s32) = COPY $vgpr1346 %3:_(s32) = COPY $vgpr2347 %4:_(s32) = COPY $vgpr3348 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)349 %6:_(s32) = G_CONSTANT i32 0350 %7:_(s1) = G_ICMP intpred(eq), %0(s32), %6351 %8:_(s32) = G_SELECT %7(s1), %1, %2352 G_STORE %8(s32), %5(p1) :: (store (s32), addrspace 1)353 S_ENDPGM 0354...355 356---357name: vgpr_to_vcc_trunc358legalized: true359body: |360 bb.0:361 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4362 363 ; CHECK-LABEL: name: vgpr_to_vcc_trunc364 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4365 ; CHECK-NEXT: {{ $}}366 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0367 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1368 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2369 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3370 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4371 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY3]](s32), [[COPY4]](s32)372 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vcc(s1) = G_TRUNC [[COPY]](s32)373 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[TRUNC]](s1), [[COPY1]], [[COPY2]]374 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)375 ; CHECK-NEXT: S_ENDPGM 0376 %0:_(s32) = COPY $vgpr0377 %1:_(s32) = COPY $vgpr1378 %2:_(s32) = COPY $vgpr2379 %3:_(s32) = COPY $vgpr3380 %4:_(s32) = COPY $vgpr4381 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)382 %6:_(s1) = G_TRUNC %0(s32)383 %7:_(s32) = G_SELECT %6(s1), %1, %2384 G_STORE %7(s32), %5(p1) :: (store (s32), addrspace 1)385 S_ENDPGM 0386...387 388---389name: zext390legalized: true391body: |392 bb.0:393 liveins: $sgpr0, $vgpr0, $vgpr1394 395 ; CHECK-LABEL: name: zext396 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1397 ; CHECK-NEXT: {{ $}}398 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0399 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0400 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1401 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)402 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10403 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]404 ; CHECK-NEXT: [[ZEXT:%[0-9]+]]:sgpr(s32) = G_ZEXT [[ICMP]](s1)405 ; CHECK-NEXT: G_STORE [[ZEXT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)406 ; CHECK-NEXT: S_ENDPGM 0407 %0:_(s32) = COPY $sgpr0408 %1:_(s32) = COPY $vgpr0409 %2:_(s32) = COPY $vgpr1410 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)411 %4:_(s32) = G_CONSTANT i32 10412 %5:_(s1) = G_ICMP intpred(eq), %0(s32), %4413 %6:_(s32) = G_ZEXT %5(s1)414 G_STORE %6(s32), %3(p1) :: (store (s32), addrspace 1)415 S_ENDPGM 0416...417 418---419name: sext420legalized: true421body: |422 bb.0:423 liveins: $sgpr0, $vgpr0, $vgpr1424 425 ; CHECK-LABEL: name: sext426 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1427 ; CHECK-NEXT: {{ $}}428 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0429 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0430 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1431 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)432 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10433 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]434 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s32) = G_SEXT [[ICMP]](s1)435 ; CHECK-NEXT: G_STORE [[SEXT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)436 ; CHECK-NEXT: S_ENDPGM 0437 %0:_(s32) = COPY $sgpr0438 %1:_(s32) = COPY $vgpr0439 %2:_(s32) = COPY $vgpr1440 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)441 %4:_(s32) = G_CONSTANT i32 10442 %5:_(s1) = G_ICMP intpred(eq), %0(s32), %4443 %6:_(s32) = G_SEXT %5(s1)444 G_STORE %6(s32), %3(p1) :: (store (s32), addrspace 1)445 S_ENDPGM 0446...447 448---449name: and_i1_vcc450legalized: true451body: |452 bb.0:453 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3454 455 ; CHECK-LABEL: name: and_i1_vcc456 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3457 ; CHECK-NEXT: {{ $}}458 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0459 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1460 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2461 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3462 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)463 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10464 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(uge), [[COPY]](s32), [[C]]465 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 20466 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(uge), [[COPY1]](s32), [[C1]]467 ; CHECK-NEXT: [[AND:%[0-9]+]]:vcc(s1) = G_AND [[ICMP]], [[ICMP1]]468 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:vgpr(s32) = G_SELECT [[AND]](s1), [[COPY]], [[COPY1]]469 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)470 ; CHECK-NEXT: S_ENDPGM 0471 %0:_(s32) = COPY $vgpr0472 %1:_(s32) = COPY $vgpr1473 %2:_(s32) = COPY $vgpr2474 %3:_(s32) = COPY $vgpr3475 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)476 %5:_(s32) = G_CONSTANT i32 10477 %6:_(s1) = G_ICMP intpred(uge), %0(s32), %5478 %7:_(s32) = G_CONSTANT i32 20479 %8:_(s1) = G_ICMP intpred(uge), %1(s32), %7480 %9:_(s1) = G_AND %6, %8481 %10:_(s32) = G_SELECT %9(s1), %0, %1482 G_STORE %10(s32), %4(p1) :: (store (s32), addrspace 1)483 S_ENDPGM 0484...485 486---487name: and_i1_scc488legalized: true489body: |490 bb.0:491 liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1492 493 ; CHECK-LABEL: name: and_i1_scc494 ; CHECK: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1495 ; CHECK-NEXT: {{ $}}496 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0497 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1498 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr0499 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr1500 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)501 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10502 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(uge), [[COPY]](s32), [[C]]503 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 20504 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(uge), [[COPY1]](s32), [[C1]]505 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s1) = G_AND [[ICMP]], [[ICMP1]]506 ; CHECK-NEXT: [[SELECT:%[0-9]+]]:sgpr(s32) = G_SELECT [[AND]](s1), [[COPY]], [[COPY1]]507 ; CHECK-NEXT: G_STORE [[SELECT]](s32), [[MV]](p1) :: (store (s32), addrspace 1)508 ; CHECK-NEXT: S_ENDPGM 0509 %0:_(s32) = COPY $sgpr0510 %1:_(s32) = COPY $sgpr1511 %2:_(s32) = COPY $vgpr0512 %3:_(s32) = COPY $vgpr1513 %4:_(p1) = G_MERGE_VALUES %2(s32), %3(s32)514 %5:_(s32) = G_CONSTANT i32 10515 %6:_(s1) = G_ICMP intpred(uge), %0(s32), %5516 %7:_(s32) = G_CONSTANT i32 20517 %8:_(s1) = G_ICMP intpred(uge), %1(s32), %7518 %9:_(s1) = G_AND %6, %8519 %10:_(s32) = G_SELECT %9(s1), %0, %1520 G_STORE %10(s32), %4(p1) :: (store (s32), addrspace 1)521 S_ENDPGM 0522...523 524---525name: divergent_phi_with_uniform_inputs526legalized: true527tracksRegLiveness: true528body: |529 ; CHECK-LABEL: name: divergent_phi_with_uniform_inputs530 ; CHECK: bb.0:531 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)532 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2533 ; CHECK-NEXT: {{ $}}534 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0535 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1536 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2537 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)538 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0539 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[C]]540 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)541 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY3]](s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec542 ; CHECK-NEXT: G_BR %bb.1543 ; CHECK-NEXT: {{ $}}544 ; CHECK-NEXT: bb.1:545 ; CHECK-NEXT: successors: %bb.2(0x80000000)546 ; CHECK-NEXT: {{ $}}547 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1548 ; CHECK-NEXT: {{ $}}549 ; CHECK-NEXT: bb.2:550 ; CHECK-NEXT: [[PHI:%[0-9]+]]:vgpr(s32) = G_PHI [[C]](s32), %bb.0, [[C1]](s32), %bb.1551 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF]](s32)552 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY4]](s32)553 ; CHECK-NEXT: G_STORE [[PHI]](s32), [[MV]](p1) :: (store (s32), addrspace 1)554 ; CHECK-NEXT: S_ENDPGM 0555 bb.0:556 successors: %bb.1(0x40000000), %bb.2(0x40000000)557 liveins: $vgpr0, $vgpr1, $vgpr2558 559 %0:_(s32) = COPY $vgpr0560 %1:_(s32) = COPY $vgpr1561 %2:_(s32) = COPY $vgpr2562 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)563 %4:_(s32) = G_CONSTANT i32 0564 %5:sreg_32_xm0_xexec(s1) = G_ICMP intpred(eq), %0(s32), %4565 %6:sreg_32_xm0_xexec(s32) = SI_IF %5(s1), %bb.2, implicit-def $exec, implicit-def $scc, implicit $exec566 G_BR %bb.1567 568 bb.1:569 successors: %bb.2(0x80000000)570 571 %7:_(s32) = G_CONSTANT i32 1572 573 bb.2:574 %8:_(s32) = G_PHI %4(s32), %bb.0, %7(s32), %bb.1575 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %6(s32)576 G_STORE %8(s32), %3(p1) :: (store (s32), addrspace 1)577 S_ENDPGM 0578...579 580---581name: divergent_because_of_temporal_divergent_use582legalized: true583tracksRegLiveness: true584body: |585 ; CHECK-LABEL: name: divergent_because_of_temporal_divergent_use586 ; CHECK: bb.0:587 ; CHECK-NEXT: successors: %bb.1(0x80000000)588 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2589 ; CHECK-NEXT: {{ $}}590 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0591 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1592 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2593 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY1]](s32), [[COPY2]](s32)594 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -1595 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0596 ; CHECK-NEXT: {{ $}}597 ; CHECK-NEXT: bb.1:598 ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000)599 ; CHECK-NEXT: {{ $}}600 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sgpr(s32) = G_PHI %15(s32), %bb.1, [[C1]](s32), %bb.0601 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sgpr(s32) = G_PHI [[C]](s32), %bb.0, %9(s32), %bb.1602 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1603 ; CHECK-NEXT: [[ADD:%[0-9]+]]:sgpr(s32) = G_ADD [[PHI1]], [[C2]]604 ; CHECK-NEXT: [[UITOFP:%[0-9]+]]:sgpr(s32) = G_UITOFP [[ADD]](s32)605 ; CHECK-NEXT: [[FCMP:%[0-9]+]]:vcc(s1) = G_FCMP floatpred(ogt), [[UITOFP]](s32), [[COPY]]606 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[FCMP]](s1), [[PHI]](s32)607 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32_xm0_xexec(s32) = COPY [[INT]](s32)608 ; CHECK-NEXT: SI_LOOP [[COPY3]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec609 ; CHECK-NEXT: G_BR %bb.2610 ; CHECK-NEXT: {{ $}}611 ; CHECK-NEXT: bb.2:612 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)613 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10614 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[ADD]], [[C3]]615 ; CHECK-NEXT: G_STORE [[MUL]](s32), [[MV]](p1) :: (store (s32), addrspace 1)616 ; CHECK-NEXT: S_ENDPGM 0617 bb.0:618 successors: %bb.1(0x80000000)619 liveins: $vgpr0, $vgpr1, $vgpr2620 621 %0:_(s32) = COPY $vgpr0622 %1:_(s32) = COPY $vgpr1623 %2:_(s32) = COPY $vgpr2624 %3:_(p1) = G_MERGE_VALUES %1(s32), %2(s32)625 %4:_(s32) = G_CONSTANT i32 -1626 %5:_(s32) = G_CONSTANT i32 0627 628 bb.1:629 successors: %bb.2(0x04000000), %bb.1(0x7c000000)630 631 %6:_(s32) = G_PHI %7(s32), %bb.1, %5(s32), %bb.0632 %8:_(s32) = G_PHI %4(s32), %bb.0, %9(s32), %bb.1633 %10:_(s32) = G_CONSTANT i32 1634 %9:_(s32) = G_ADD %8, %10635 %11:_(s32) = G_UITOFP %9(s32)636 %12:_(s1) = G_FCMP floatpred(ogt), %11(s32), %0637 %7:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %12(s1), %6(s32)638 SI_LOOP %7(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec639 G_BR %bb.2640 641 bb.2:642 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %7(s32)643 %13:_(s32) = G_CONSTANT i32 10644 %14:_(s32) = G_MUL %9, %13645 G_STORE %14(s32), %3(p1) :: (store (s32), addrspace 1)646 S_ENDPGM 0647...648 649---650name: loop_with_2breaks651legalized: true652tracksRegLiveness: true653body: |654 ; CHECK-LABEL: name: loop_with_2breaks655 ; CHECK: bb.0:656 ; CHECK-NEXT: successors: %bb.1(0x80000000)657 ; CHECK-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5658 ; CHECK-NEXT: {{ $}}659 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0660 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr1661 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY]](s32), [[COPY1]](s32)662 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr2663 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY $vgpr3664 ; CHECK-NEXT: [[MV1:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY2]](s32), [[COPY3]](s32)665 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY $vgpr4666 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr(s32) = COPY $vgpr5667 ; CHECK-NEXT: [[MV2:%[0-9]+]]:vgpr(p1) = G_MERGE_VALUES [[COPY4]](s32), [[COPY5]](s32)668 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr(s32) = G_IMPLICIT_DEF669 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0670 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_32(s1) = IMPLICIT_DEF671 ; CHECK-NEXT: {{ $}}672 ; CHECK-NEXT: bb.1:673 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)674 ; CHECK-NEXT: {{ $}}675 ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_32(s1) = PHI [[DEF1]](s1), %bb.0, %13(s1), %bb.3676 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sgpr(s32) = G_PHI %67(s32), %bb.3, [[C]](s32), %bb.0677 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sgpr(s32) = G_PHI [[C]](s32), %bb.0, %17(s32), %bb.3678 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32(s1) = COPY [[PHI]](s1)679 ; CHECK-NEXT: [[SEXT:%[0-9]+]]:sgpr(s64) = G_SEXT [[PHI2]](s32)680 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2681 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s64) = G_SHL [[SEXT]], [[C1]](s32)682 ; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV1]], [[SHL]](s64)683 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD]](p1) :: (load (s32), addrspace 1)684 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0685 ; CHECK-NEXT: [[ICMP:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[LOAD]](s32), [[C2]]686 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP]](s1)687 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true688 ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_32(s1) = COPY [[C3]](s1)689 ; CHECK-NEXT: [[S_ANDN2_B32_:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY6]](s1), $exec_lo, implicit-def $scc690 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY8]](s1), implicit-def $scc691 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_]](s1), [[S_AND_B32_]](s1), implicit-def $scc692 ; CHECK-NEXT: [[COPY9:%[0-9]+]]:sreg_32(s1) = COPY [[S_OR_B32_]](s1)693 ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY7]](s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec694 ; CHECK-NEXT: G_BR %bb.2695 ; CHECK-NEXT: {{ $}}696 ; CHECK-NEXT: bb.2:697 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000)698 ; CHECK-NEXT: {{ $}}699 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2700 ; CHECK-NEXT: [[SHL1:%[0-9]+]]:sgpr(s64) = G_SHL [[SEXT]], [[C4]](s32)701 ; CHECK-NEXT: [[PTR_ADD1:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV2]], [[SHL1]](s64)702 ; CHECK-NEXT: [[LOAD1:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD1]](p1) :: (load (s32), addrspace 1)703 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 0704 ; CHECK-NEXT: [[ICMP1:%[0-9]+]]:vcc(s1) = G_ICMP intpred(ne), [[LOAD1]](s32), [[C5]]705 ; CHECK-NEXT: [[COPY10:%[0-9]+]]:sreg_32_xm0_xexec(s1) = COPY [[ICMP1]](s1)706 ; CHECK-NEXT: [[C6:%[0-9]+]]:sgpr(s1) = G_CONSTANT i1 true707 ; CHECK-NEXT: [[COPY11:%[0-9]+]]:sreg_32(s1) = COPY [[C6]](s1)708 ; CHECK-NEXT: [[COPY12:%[0-9]+]]:sreg_32(s1) = COPY [[COPY11]](s1)709 ; CHECK-NEXT: [[SI_IF1:%[0-9]+]]:sreg_32_xm0_xexec(s32) = SI_IF [[COPY10]](s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec710 ; CHECK-NEXT: G_BR %bb.4711 ; CHECK-NEXT: {{ $}}712 ; CHECK-NEXT: bb.3:713 ; CHECK-NEXT: successors: %bb.6(0x04000000), %bb.1(0x7c000000)714 ; CHECK-NEXT: {{ $}}715 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_32(s1) = PHI [[S_OR_B32_]](s1), %bb.1, %43(s1), %bb.5716 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sgpr(s32) = G_PHI %44(s32), %bb.5, [[DEF]](s32), %bb.1717 ; CHECK-NEXT: [[COPY13:%[0-9]+]]:sreg_32(s1) = COPY [[PHI3]](s1)718 ; CHECK-NEXT: [[COPY14:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF]](s32)719 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY14]](s32)720 ; CHECK-NEXT: [[COPY15:%[0-9]+]]:vcc(s1) = COPY [[COPY13]](s1)721 ; CHECK-NEXT: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), [[COPY15]](s1), [[PHI1]](s32)722 ; CHECK-NEXT: [[COPY16:%[0-9]+]]:sreg_32_xm0_xexec(s32) = COPY [[INT]](s32)723 ; CHECK-NEXT: SI_LOOP [[COPY16]](s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec724 ; CHECK-NEXT: G_BR %bb.6725 ; CHECK-NEXT: {{ $}}726 ; CHECK-NEXT: bb.4:727 ; CHECK-NEXT: successors: %bb.5(0x80000000)728 ; CHECK-NEXT: {{ $}}729 ; CHECK-NEXT: [[C7:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 2730 ; CHECK-NEXT: [[SHL2:%[0-9]+]]:sgpr(s64) = G_SHL [[SEXT]], [[C7]](s32)731 ; CHECK-NEXT: [[PTR_ADD2:%[0-9]+]]:vgpr(p1) = G_PTR_ADD [[MV]], [[SHL2]](s64)732 ; CHECK-NEXT: [[LOAD2:%[0-9]+]]:vgpr(s32) = G_LOAD [[PTR_ADD2]](p1) :: (load (s32), addrspace 1)733 ; CHECK-NEXT: [[C8:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1734 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[LOAD2]], [[C8]]735 ; CHECK-NEXT: G_STORE [[ADD]](s32), [[PTR_ADD2]](p1) :: (store (s32), addrspace 1)736 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:sgpr(s32) = G_ADD [[PHI2]], [[C8]]737 ; CHECK-NEXT: [[C9:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 100738 ; CHECK-NEXT: [[ICMP2:%[0-9]+]]:sgpr(s1) = G_ICMP intpred(ult), [[PHI2]](s32), [[C9]]739 ; CHECK-NEXT: [[COPY17:%[0-9]+]]:sreg_32(s1) = COPY [[ICMP2]](s1)740 ; CHECK-NEXT: [[S_ANDN2_B32_1:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY12]](s1), $exec_lo, implicit-def $scc741 ; CHECK-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY17]](s1), implicit-def $scc742 ; CHECK-NEXT: [[S_OR_B32_1:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_1]](s1), [[S_AND_B32_1]](s1), implicit-def $scc743 ; CHECK-NEXT: {{ $}}744 ; CHECK-NEXT: bb.5:745 ; CHECK-NEXT: successors: %bb.3(0x80000000)746 ; CHECK-NEXT: {{ $}}747 ; CHECK-NEXT: [[PHI5:%[0-9]+]]:sreg_32(s1) = PHI [[COPY11]](s1), %bb.2, [[S_OR_B32_1]](s1), %bb.4748 ; CHECK-NEXT: [[PHI6:%[0-9]+]]:sgpr(s32) = G_PHI [[ADD1]](s32), %bb.4, [[DEF]](s32), %bb.2749 ; CHECK-NEXT: [[COPY18:%[0-9]+]]:sreg_32(s1) = COPY [[PHI5]](s1)750 ; CHECK-NEXT: [[COPY19:%[0-9]+]]:sreg_32(s1) = COPY [[COPY18]](s1)751 ; CHECK-NEXT: [[COPY20:%[0-9]+]]:sgpr(s32) = COPY [[SI_IF1]](s32)752 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[COPY20]](s32)753 ; CHECK-NEXT: [[S_ANDN2_B32_2:%[0-9]+]]:sreg_32(s1) = S_ANDN2_B32 [[COPY9]](s1), $exec_lo, implicit-def $scc754 ; CHECK-NEXT: [[S_AND_B32_2:%[0-9]+]]:sreg_32(s1) = S_AND_B32 $exec_lo, [[COPY19]](s1), implicit-def $scc755 ; CHECK-NEXT: [[S_OR_B32_2:%[0-9]+]]:sreg_32(s1) = S_OR_B32 [[S_ANDN2_B32_2]](s1), [[S_AND_B32_2]](s1), implicit-def $scc756 ; CHECK-NEXT: G_BR %bb.3757 ; CHECK-NEXT: {{ $}}758 ; CHECK-NEXT: bb.6:759 ; CHECK-NEXT: G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), [[INT]](s32)760 ; CHECK-NEXT: S_ENDPGM 0761 bb.0:762 successors: %bb.1(0x80000000)763 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5764 765 %0:_(s32) = COPY $vgpr0766 %1:_(s32) = COPY $vgpr1767 %2:_(p1) = G_MERGE_VALUES %0(s32), %1(s32)768 %3:_(s32) = COPY $vgpr2769 %4:_(s32) = COPY $vgpr3770 %5:_(p1) = G_MERGE_VALUES %3(s32), %4(s32)771 %6:_(s32) = COPY $vgpr4772 %7:_(s32) = COPY $vgpr5773 %8:_(p1) = G_MERGE_VALUES %6(s32), %7(s32)774 %9:_(s32) = G_IMPLICIT_DEF775 %10:_(s32) = G_CONSTANT i32 0776 %11:sreg_32(s1) = IMPLICIT_DEF777 778 bb.1:779 successors: %bb.2(0x40000000), %bb.3(0x40000000)780 781 %12:sreg_32(s1) = PHI %11(s1), %bb.0, %13(s1), %bb.3782 %14:_(s32) = G_PHI %15(s32), %bb.3, %10(s32), %bb.0783 %16:_(s32) = G_PHI %10(s32), %bb.0, %17(s32), %bb.3784 %18:sreg_32(s1) = COPY %12(s1)785 %19:_(s64) = G_SEXT %16(s32)786 %20:_(s32) = G_CONSTANT i32 2787 %21:_(s64) = G_SHL %19, %20(s32)788 %22:_(p1) = G_PTR_ADD %5, %21(s64)789 %23:_(s32) = G_LOAD %22(p1) :: (load (s32), addrspace 1)790 %24:_(s32) = G_CONSTANT i32 0791 %25:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %23(s32), %24792 %26:_(s1) = G_CONSTANT i1 true793 %27:sreg_32(s1) = COPY %26(s1)794 %28:sreg_32(s1) = S_ANDN2_B32 %18(s1), $exec_lo, implicit-def $scc795 %29:sreg_32(s1) = S_AND_B32 $exec_lo, %27(s1), implicit-def $scc796 %30:sreg_32(s1) = S_OR_B32 %28(s1), %29(s1), implicit-def $scc797 %31:sreg_32(s1) = COPY %30(s1)798 %32:sreg_32_xm0_xexec(s32) = SI_IF %25(s1), %bb.3, implicit-def $exec, implicit-def $scc, implicit $exec799 G_BR %bb.2800 801 bb.2:802 successors: %bb.4(0x40000000), %bb.5(0x40000000)803 804 %33:_(s32) = G_CONSTANT i32 2805 %34:_(s64) = G_SHL %19, %33(s32)806 %35:_(p1) = G_PTR_ADD %8, %34(s64)807 %36:_(s32) = G_LOAD %35(p1) :: (load (s32), addrspace 1)808 %37:_(s32) = G_CONSTANT i32 0809 %38:sreg_32_xm0_xexec(s1) = G_ICMP intpred(ne), %36(s32), %37810 %39:_(s1) = G_CONSTANT i1 true811 %40:sreg_32(s1) = COPY %39(s1)812 %41:sreg_32(s1) = COPY %40(s1)813 %42:sreg_32_xm0_xexec(s32) = SI_IF %38(s1), %bb.5, implicit-def $exec, implicit-def $scc, implicit $exec814 G_BR %bb.4815 816 bb.3:817 successors: %bb.6(0x04000000), %bb.1(0x7c000000)818 819 %13:sreg_32(s1) = PHI %30(s1), %bb.1, %43(s1), %bb.5820 %17:_(s32) = G_PHI %44(s32), %bb.5, %9(s32), %bb.1821 %45:sreg_32(s1) = COPY %13(s1)822 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %32(s32)823 %15:sreg_32_xm0_xexec(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.if.break), %45(s1), %14(s32)824 SI_LOOP %15(s32), %bb.1, implicit-def $exec, implicit-def $scc, implicit $exec825 G_BR %bb.6826 827 bb.4:828 successors: %bb.5(0x80000000)829 830 %46:_(s32) = G_CONSTANT i32 2831 %47:_(s64) = G_SHL %19, %46(s32)832 %48:_(p1) = G_PTR_ADD %2, %47(s64)833 %49:_(s32) = G_LOAD %48(p1) :: (load (s32), addrspace 1)834 %50:_(s32) = G_CONSTANT i32 1835 %51:_(s32) = G_ADD %49, %50836 G_STORE %51(s32), %48(p1) :: (store (s32), addrspace 1)837 %52:_(s32) = G_ADD %16, %50838 %53:_(s32) = G_CONSTANT i32 100839 %54:_(s1) = G_ICMP intpred(ult), %16(s32), %53840 %55:sreg_32(s1) = COPY %54(s1)841 %56:sreg_32(s1) = S_ANDN2_B32 %41(s1), $exec_lo, implicit-def $scc842 %57:sreg_32(s1) = S_AND_B32 $exec_lo, %55(s1), implicit-def $scc843 %58:sreg_32(s1) = S_OR_B32 %56(s1), %57(s1), implicit-def $scc844 845 bb.5:846 successors: %bb.3(0x80000000)847 848 %59:sreg_32(s1) = PHI %40(s1), %bb.2, %58(s1), %bb.4849 %44:_(s32) = G_PHI %52(s32), %bb.4, %9(s32), %bb.2850 %60:sreg_32(s1) = COPY %59(s1)851 %61:sreg_32(s1) = COPY %60(s1)852 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %42(s32)853 %62:sreg_32(s1) = S_ANDN2_B32 %31(s1), $exec_lo, implicit-def $scc854 %63:sreg_32(s1) = S_AND_B32 $exec_lo, %61(s1), implicit-def $scc855 %43:sreg_32(s1) = S_OR_B32 %62(s1), %63(s1), implicit-def $scc856 G_BR %bb.3857 858 bb.6:859 G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.amdgcn.end.cf), %15(s32)860 S_ENDPGM 0861...862