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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=OLD_RBS_GFX10 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 < %s | FileCheck -check-prefix=OLD_RBS_GFX12 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck -check-prefix=NEW_RBS_GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -new-reg-bank-select < %s | FileCheck -check-prefix=NEW_RBS_GFX12 %s6 7define amdgpu_ps void @salu_float(float inreg %a, float inreg %b, i32 inreg %c, ptr addrspace(1) %ptr) {8; OLD_RBS_GFX10-LABEL: salu_float:9; OLD_RBS_GFX10: ; %bb.0:10; OLD_RBS_GFX10-NEXT: v_add_f32_e64 v2, s0, s111; OLD_RBS_GFX10-NEXT: v_cvt_u32_f32_e32 v2, v212; OLD_RBS_GFX10-NEXT: v_add_nc_u32_e32 v2, s2, v213; OLD_RBS_GFX10-NEXT: global_store_dword v[0:1], v2, off14; OLD_RBS_GFX10-NEXT: s_endpgm15;16; OLD_RBS_GFX12-LABEL: salu_float:17; OLD_RBS_GFX12: ; %bb.0:18; OLD_RBS_GFX12-NEXT: s_add_f32 s0, s0, s119; OLD_RBS_GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)20; OLD_RBS_GFX12-NEXT: s_cvt_u32_f32 s0, s021; OLD_RBS_GFX12-NEXT: s_add_co_i32 s0, s0, s222; OLD_RBS_GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)23; OLD_RBS_GFX12-NEXT: v_mov_b32_e32 v2, s024; OLD_RBS_GFX12-NEXT: global_store_b32 v[0:1], v2, off25; OLD_RBS_GFX12-NEXT: s_endpgm26;27; NEW_RBS_GFX10-LABEL: salu_float:28; NEW_RBS_GFX10: ; %bb.0:29; NEW_RBS_GFX10-NEXT: v_add_f32_e64 v2, s0, s130; NEW_RBS_GFX10-NEXT: v_cvt_u32_f32_e32 v2, v231; NEW_RBS_GFX10-NEXT: v_readfirstlane_b32 s0, v232; NEW_RBS_GFX10-NEXT: s_add_i32 s0, s0, s233; NEW_RBS_GFX10-NEXT: v_mov_b32_e32 v2, s034; NEW_RBS_GFX10-NEXT: global_store_dword v[0:1], v2, off35; NEW_RBS_GFX10-NEXT: s_endpgm36;37; NEW_RBS_GFX12-LABEL: salu_float:38; NEW_RBS_GFX12: ; %bb.0:39; NEW_RBS_GFX12-NEXT: s_add_f32 s0, s0, s140; NEW_RBS_GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3)41; NEW_RBS_GFX12-NEXT: s_cvt_u32_f32 s0, s042; NEW_RBS_GFX12-NEXT: s_add_co_i32 s0, s0, s243; NEW_RBS_GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)44; NEW_RBS_GFX12-NEXT: v_mov_b32_e32 v2, s045; NEW_RBS_GFX12-NEXT: global_store_b32 v[0:1], v2, off46; NEW_RBS_GFX12-NEXT: s_endpgm47 %add = fadd float %a, %b48 %add.i32 = fptoui float %add to i3249 %res = add i32 %add.i32, %c50 store i32 %res, ptr addrspace(1) %ptr51 ret void52}53