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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=OLD_RBS %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -new-reg-bank-select < %s | FileCheck -check-prefix=NEW_RBS %s4 5; if instruction is uniform and there is available instruction, select SALU instruction6define amdgpu_ps void @uniform_in_vgpr(float inreg %a, i32 inreg %b, ptr addrspace(1) %ptr) {7; OLD_RBS-LABEL: uniform_in_vgpr:8; OLD_RBS: ; %bb.0:9; OLD_RBS-NEXT: v_cvt_u32_f32_e32 v2, s010; OLD_RBS-NEXT: v_add_nc_u32_e32 v2, s1, v211; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off12; OLD_RBS-NEXT: s_endpgm13;14; NEW_RBS-LABEL: uniform_in_vgpr:15; NEW_RBS: ; %bb.0:16; NEW_RBS-NEXT: v_cvt_u32_f32_e32 v2, s017; NEW_RBS-NEXT: v_readfirstlane_b32 s0, v218; NEW_RBS-NEXT: s_add_i32 s0, s0, s119; NEW_RBS-NEXT: v_mov_b32_e32 v2, s020; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off21; NEW_RBS-NEXT: s_endpgm22 %a.i32 = fptoui float %a to i3223 %res = add i32 %a.i32, %b24 store i32 %res, ptr addrspace(1) %ptr25 ret void26}27 28; copy sgpr to vgpr + readfirstlane vgpr to sgpr combine from rb-legalize29define amdgpu_ps void @back_to_back_uniform_in_vgpr(float inreg %a, float inreg %b, i32 inreg %c, ptr addrspace(1) %ptr) {30; OLD_RBS-LABEL: back_to_back_uniform_in_vgpr:31; OLD_RBS: ; %bb.0:32; OLD_RBS-NEXT: v_add_f32_e64 v2, s0, s133; OLD_RBS-NEXT: v_cvt_u32_f32_e32 v2, v234; OLD_RBS-NEXT: v_add_nc_u32_e32 v2, s2, v235; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off36; OLD_RBS-NEXT: s_endpgm37;38; NEW_RBS-LABEL: back_to_back_uniform_in_vgpr:39; NEW_RBS: ; %bb.0:40; NEW_RBS-NEXT: v_add_f32_e64 v2, s0, s141; NEW_RBS-NEXT: v_cvt_u32_f32_e32 v2, v242; NEW_RBS-NEXT: v_readfirstlane_b32 s0, v243; NEW_RBS-NEXT: s_add_i32 s0, s0, s244; NEW_RBS-NEXT: v_mov_b32_e32 v2, s045; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off46; NEW_RBS-NEXT: s_endpgm47 %add = fadd float %a, %b48 %add.i32 = fptoui float %add to i3249 %res = add i32 %add.i32, %c50 store i32 %res, ptr addrspace(1) %ptr51 ret void52}53 54; fast rules for vector instructions55define amdgpu_cs void @buffer_load_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, ptr addrspace(1) %ptr) {56; OLD_RBS-LABEL: buffer_load_uniform:57; OLD_RBS: ; %bb.0: ; %.entry58; OLD_RBS-NEXT: v_mov_b32_e32 v2, s459; OLD_RBS-NEXT: buffer_load_dwordx4 v[2:5], v2, s[0:3], 0 offen60; OLD_RBS-NEXT: s_waitcnt vmcnt(0)61; OLD_RBS-NEXT: v_add_nc_u32_e32 v2, 1, v362; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off63; OLD_RBS-NEXT: s_endpgm64;65; NEW_RBS-LABEL: buffer_load_uniform:66; NEW_RBS: ; %bb.0: ; %.entry67; NEW_RBS-NEXT: v_mov_b32_e32 v2, s468; NEW_RBS-NEXT: buffer_load_dwordx4 v[2:5], v2, s[0:3], 0 offen69; NEW_RBS-NEXT: s_waitcnt vmcnt(0)70; NEW_RBS-NEXT: v_readfirstlane_b32 s0, v371; NEW_RBS-NEXT: s_add_i32 s0, s0, 172; NEW_RBS-NEXT: v_mov_b32_e32 v2, s073; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off74; NEW_RBS-NEXT: s_endpgm75.entry:76 %vec = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)77 %el1 = extractelement <4 x i32> %vec, i64 178 %res = add i32 %el1, 179 store i32 %res, ptr addrspace(1) %ptr80 ret void81}82 83define amdgpu_cs void @buffer_load_divergent(<4 x i32> inreg %rsrc, i32 %voffset, ptr addrspace(1) %ptr) {84; OLD_RBS-LABEL: buffer_load_divergent:85; OLD_RBS: ; %bb.0: ; %.entry86; OLD_RBS-NEXT: buffer_load_dwordx4 v[3:6], v0, s[0:3], 0 offen87; OLD_RBS-NEXT: s_waitcnt vmcnt(0)88; OLD_RBS-NEXT: v_add_nc_u32_e32 v0, 1, v489; OLD_RBS-NEXT: global_store_dword v[1:2], v0, off90; OLD_RBS-NEXT: s_endpgm91;92; NEW_RBS-LABEL: buffer_load_divergent:93; NEW_RBS: ; %bb.0: ; %.entry94; NEW_RBS-NEXT: buffer_load_dwordx4 v[3:6], v0, s[0:3], 0 offen95; NEW_RBS-NEXT: s_waitcnt vmcnt(0)96; NEW_RBS-NEXT: v_add_nc_u32_e32 v0, 1, v497; NEW_RBS-NEXT: global_store_dword v[1:2], v0, off98; NEW_RBS-NEXT: s_endpgm99.entry:100 %vec = call <4 x i32> @llvm.amdgcn.raw.buffer.load.v4f32(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)101 %el1 = extractelement <4 x i32> %vec, i64 1102 %res = add i32 %el1, 1103 store i32 %res, ptr addrspace(1) %ptr104 ret void105}106 107;lowering in rb-legalize (sgpr S64 is legal, vgpr has to be split to S32)108define amdgpu_ps void @vgpr_and_i64(i64 %a, i64 %b, ptr addrspace(1) %ptr) {109; OLD_RBS-LABEL: vgpr_and_i64:110; OLD_RBS: ; %bb.0:111; OLD_RBS-NEXT: v_and_b32_e32 v0, v0, v2112; OLD_RBS-NEXT: v_and_b32_e32 v1, v1, v3113; OLD_RBS-NEXT: global_store_dwordx2 v[4:5], v[0:1], off114; OLD_RBS-NEXT: s_endpgm115;116; NEW_RBS-LABEL: vgpr_and_i64:117; NEW_RBS: ; %bb.0:118; NEW_RBS-NEXT: v_and_b32_e32 v0, v0, v2119; NEW_RBS-NEXT: v_and_b32_e32 v1, v1, v3120; NEW_RBS-NEXT: global_store_dwordx2 v[4:5], v[0:1], off121; NEW_RBS-NEXT: s_endpgm122 %res = and i64 %a, %b123 store i64 %res, ptr addrspace(1) %ptr124 ret void125}126 127; It is up to user instruction to deal with potential truncated bits in reg.128; Here G_ABS needs to sign extend S16 in reg to S32 and then do S32 G_ABS.129define amdgpu_ps void @abs_sgpr_i16(i16 inreg %arg, ptr addrspace(1) %ptr) {130; OLD_RBS-LABEL: abs_sgpr_i16:131; OLD_RBS: ; %bb.0:132; OLD_RBS-NEXT: s_sext_i32_i16 s0, s0133; OLD_RBS-NEXT: s_abs_i32 s0, s0134; OLD_RBS-NEXT: v_mov_b32_e32 v2, s0135; OLD_RBS-NEXT: global_store_short v[0:1], v2, off136; OLD_RBS-NEXT: s_endpgm137;138; NEW_RBS-LABEL: abs_sgpr_i16:139; NEW_RBS: ; %bb.0:140; NEW_RBS-NEXT: s_sext_i32_i16 s0, s0141; NEW_RBS-NEXT: s_abs_i32 s0, s0142; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0143; NEW_RBS-NEXT: global_store_short v[0:1], v2, off144; NEW_RBS-NEXT: s_endpgm145 %res = call i16 @llvm.abs.i16(i16 %arg, i1 false)146 store i16 %res, ptr addrspace(1) %ptr147 ret void148}149 150define amdgpu_ps void @uniform_i1_phi(ptr addrspace(1) %out, i32 inreg %tid, i32 inreg %cond) {151; OLD_RBS-LABEL: uniform_i1_phi:152; OLD_RBS: ; %bb.0: ; %A153; OLD_RBS-NEXT: s_cmp_ge_u32 s0, 6154; OLD_RBS-NEXT: s_cselect_b32 s2, 1, 0155; OLD_RBS-NEXT: s_cmp_lg_u32 s1, 0156; OLD_RBS-NEXT: s_cbranch_scc1 .LBB6_2157; OLD_RBS-NEXT: ; %bb.1: ; %B158; OLD_RBS-NEXT: s_cmp_lt_u32 s0, 1159; OLD_RBS-NEXT: s_cselect_b32 s2, 1, 0160; OLD_RBS-NEXT: .LBB6_2: ; %exit161; OLD_RBS-NEXT: s_bfe_i32 s0, s2, 0x10000162; OLD_RBS-NEXT: s_add_i32 s0, s0, 2163; OLD_RBS-NEXT: v_mov_b32_e32 v2, s0164; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off165; OLD_RBS-NEXT: s_endpgm166;167; NEW_RBS-LABEL: uniform_i1_phi:168; NEW_RBS: ; %bb.0: ; %A169; NEW_RBS-NEXT: s_cmp_ge_u32 s0, 6170; NEW_RBS-NEXT: s_cselect_b32 s2, 1, 0171; NEW_RBS-NEXT: s_cmp_lg_u32 s1, 0172; NEW_RBS-NEXT: s_cbranch_scc1 .LBB6_2173; NEW_RBS-NEXT: ; %bb.1: ; %B174; NEW_RBS-NEXT: s_cmp_lt_u32 s0, 1175; NEW_RBS-NEXT: s_cselect_b32 s2, 1, 0176; NEW_RBS-NEXT: .LBB6_2: ; %exit177; NEW_RBS-NEXT: s_cmp_lg_u32 s2, 0178; NEW_RBS-NEXT: s_cselect_b32 s0, -1, 0179; NEW_RBS-NEXT: s_add_i32 s0, s0, 2180; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0181; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off182; NEW_RBS-NEXT: s_endpgm183A:184 %val_A = icmp uge i32 %tid, 6185 %cmp = icmp eq i32 %cond, 0186 br i1 %cmp, label %B, label %exit187 188B:189 %val_B = icmp ult i32 %tid, 1190 br label %exit191 192exit:193 %phi = phi i1 [ %val_A, %A ], [ %val_B, %B ]194 %sel = select i1 %phi, i32 1, i32 2195 store i32 %sel, ptr addrspace(1) %out196 ret void197}198 199; this is kind of i1 readfirstlane200; uniform i1 result on instruction that is only available on VALU201define amdgpu_ps void @vcc_to_scc(float inreg %a, i32 inreg %b, i32 inreg %c, ptr addrspace(1) %ptr) {202; OLD_RBS-LABEL: vcc_to_scc:203; OLD_RBS: ; %bb.0:204; OLD_RBS-NEXT: v_mov_b32_e32 v2, s2205; OLD_RBS-NEXT: v_cmp_eq_f32_e64 s0, s0, 0206; OLD_RBS-NEXT: v_cndmask_b32_e64 v2, v2, s1, s0207; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off208; OLD_RBS-NEXT: s_endpgm209;210; NEW_RBS-LABEL: vcc_to_scc:211; NEW_RBS: ; %bb.0:212; NEW_RBS-NEXT: v_cmp_eq_f32_e64 s0, s0, 0213; NEW_RBS-NEXT: s_cmp_lg_u32 s0, 0214; NEW_RBS-NEXT: s_cselect_b32 s0, 1, 0215; NEW_RBS-NEXT: s_and_b32 s0, s0, 1216; NEW_RBS-NEXT: s_cmp_lg_u32 s0, 0217; NEW_RBS-NEXT: s_cselect_b32 s0, s1, s2218; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0219; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off220; NEW_RBS-NEXT: s_endpgm221 %vcc_to_scc = fcmp oeq float %a, 0.0222 %select = select i1 %vcc_to_scc, i32 %b, i32 %c223 store i32 %select, ptr addrspace(1) %ptr224 ret void225}226 227; combiner in rb-legalize recognizes sgpr S1 to vcc copy228define amdgpu_ps void @scc_to_vcc(i32 inreg %a, i32 %b, i32 %c, ptr addrspace(1) %ptr) {229; OLD_RBS-LABEL: scc_to_vcc:230; OLD_RBS: ; %bb.0:231; OLD_RBS-NEXT: s_cmp_eq_u32 s0, 0232; OLD_RBS-NEXT: s_cselect_b32 s0, 1, 0233; OLD_RBS-NEXT: s_and_b32 s0, 1, s0234; OLD_RBS-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0235; OLD_RBS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo236; OLD_RBS-NEXT: global_store_dword v[2:3], v0, off237; OLD_RBS-NEXT: s_endpgm238;239; NEW_RBS-LABEL: scc_to_vcc:240; NEW_RBS: ; %bb.0:241; NEW_RBS-NEXT: s_cmp_eq_u32 s0, 0242; NEW_RBS-NEXT: s_cselect_b32 vcc_lo, exec_lo, 0243; NEW_RBS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo244; NEW_RBS-NEXT: global_store_dword v[2:3], v0, off245; NEW_RBS-NEXT: s_endpgm246 %scc_to_vcc = icmp eq i32 %a, 0247 %select = select i1 %scc_to_vcc, i32 %b, i32 %c248 store i32 %select, ptr addrspace(1) %ptr249 ret void250}251 252; this is only G_TRUNC that is not no-op in global-isel for AMDGPU253define amdgpu_ps void @vgpr_to_vcc_trunc(i32 %a, i32 %b, i32 %c, ptr addrspace(1) %ptr) {254; OLD_RBS-LABEL: vgpr_to_vcc_trunc:255; OLD_RBS: ; %bb.0:256; OLD_RBS-NEXT: v_and_b32_e32 v0, 1, v0257; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0258; OLD_RBS-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo259; OLD_RBS-NEXT: global_store_dword v[3:4], v0, off260; OLD_RBS-NEXT: s_endpgm261;262; NEW_RBS-LABEL: vgpr_to_vcc_trunc:263; NEW_RBS: ; %bb.0:264; NEW_RBS-NEXT: v_and_b32_e32 v0, 1, v0265; NEW_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0266; NEW_RBS-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc_lo267; NEW_RBS-NEXT: global_store_dword v[3:4], v0, off268; NEW_RBS-NEXT: s_endpgm269 %vcc = trunc i32 %a to i1270 %select = select i1 %vcc, i32 %b, i32 %c271 store i32 %select, ptr addrspace(1) %ptr272 ret void273}274 275; i1 input to zext and sext is something that survived legalizer (not trunc)276; lower to select277define amdgpu_ps void @zext(i32 inreg %a, ptr addrspace(1) %ptr) {278; OLD_RBS-LABEL: zext:279; OLD_RBS: ; %bb.0:280; OLD_RBS-NEXT: s_cmp_eq_u32 s0, 10281; OLD_RBS-NEXT: s_cselect_b32 s0, 1, 0282; OLD_RBS-NEXT: v_mov_b32_e32 v2, s0283; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off284; OLD_RBS-NEXT: s_endpgm285;286; NEW_RBS-LABEL: zext:287; NEW_RBS: ; %bb.0:288; NEW_RBS-NEXT: s_cmp_eq_u32 s0, 10289; NEW_RBS-NEXT: s_cselect_b32 s0, 1, 0290; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0291; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off292; NEW_RBS-NEXT: s_endpgm293 %bool = icmp eq i32 %a, 10294 %zext = zext i1 %bool to i32295 store i32 %zext, ptr addrspace(1) %ptr296 ret void297}298 299define amdgpu_ps void @sext(i32 inreg %a, ptr addrspace(1) %ptr) {300; OLD_RBS-LABEL: sext:301; OLD_RBS: ; %bb.0:302; OLD_RBS-NEXT: s_cmp_eq_u32 s0, 10303; OLD_RBS-NEXT: s_cselect_b32 s0, 1, 0304; OLD_RBS-NEXT: s_bfe_i32 s0, s0, 0x10000305; OLD_RBS-NEXT: v_mov_b32_e32 v2, s0306; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off307; OLD_RBS-NEXT: s_endpgm308;309; NEW_RBS-LABEL: sext:310; NEW_RBS: ; %bb.0:311; NEW_RBS-NEXT: s_cmp_eq_u32 s0, 10312; NEW_RBS-NEXT: s_cselect_b32 s0, -1, 0313; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0314; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off315; NEW_RBS-NEXT: s_endpgm316 %bool = icmp eq i32 %a, 10317 %sext = sext i1 %bool to i32318 store i32 %sext, ptr addrspace(1) %ptr319 ret void320}321 322; divergent i1 bitwise, i1 vcc.323; inst selected into s_and_b32 on wave32 or s_and_b64 on wave64.324define amdgpu_ps void @and_i1_vcc(i32 %a, i32 %b, ptr addrspace(1) %ptr) {325; OLD_RBS-LABEL: and_i1_vcc:326; OLD_RBS: ; %bb.0:327; OLD_RBS-NEXT: v_cmp_le_u32_e32 vcc_lo, 10, v0328; OLD_RBS-NEXT: v_cmp_le_u32_e64 s0, 20, v1329; OLD_RBS-NEXT: s_and_b32 vcc_lo, vcc_lo, s0330; OLD_RBS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo331; OLD_RBS-NEXT: global_store_dword v[2:3], v0, off332; OLD_RBS-NEXT: s_endpgm333;334; NEW_RBS-LABEL: and_i1_vcc:335; NEW_RBS: ; %bb.0:336; NEW_RBS-NEXT: v_cmp_le_u32_e32 vcc_lo, 10, v0337; NEW_RBS-NEXT: v_cmp_le_u32_e64 s0, 20, v1338; NEW_RBS-NEXT: s_and_b32 vcc_lo, vcc_lo, s0339; NEW_RBS-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo340; NEW_RBS-NEXT: global_store_dword v[2:3], v0, off341; NEW_RBS-NEXT: s_endpgm342 %cmp_a = icmp uge i32 %a, 10343 %cmp_b = icmp uge i32 %b, 20344 %cc = and i1 %cmp_a, %cmp_b345 %res = select i1 %cc, i32 %a, i32 %b346 store i32 %res, ptr addrspace(1) %ptr347 ret void348}349 350; uniform i1 bitwise, i32 sgpr. inst selected into s_and_b32.351define amdgpu_ps void @and_i1_scc(i32 inreg %a, i32 inreg %b, ptr addrspace(1) %ptr) {352; OLD_RBS-LABEL: and_i1_scc:353; OLD_RBS: ; %bb.0:354; OLD_RBS-NEXT: s_cmp_ge_u32 s0, 10355; OLD_RBS-NEXT: s_cselect_b32 s2, 1, 0356; OLD_RBS-NEXT: s_cmp_ge_u32 s1, 20357; OLD_RBS-NEXT: s_cselect_b32 s3, 1, 0358; OLD_RBS-NEXT: s_and_b32 s2, s2, s3359; OLD_RBS-NEXT: s_cmp_lg_u32 s2, 0360; OLD_RBS-NEXT: s_cselect_b32 s0, s0, s1361; OLD_RBS-NEXT: v_mov_b32_e32 v2, s0362; OLD_RBS-NEXT: global_store_dword v[0:1], v2, off363; OLD_RBS-NEXT: s_endpgm364;365; NEW_RBS-LABEL: and_i1_scc:366; NEW_RBS: ; %bb.0:367; NEW_RBS-NEXT: s_cmp_ge_u32 s0, 10368; NEW_RBS-NEXT: s_cselect_b32 s2, 1, 0369; NEW_RBS-NEXT: s_cmp_ge_u32 s1, 20370; NEW_RBS-NEXT: s_cselect_b32 s3, 1, 0371; NEW_RBS-NEXT: s_and_b32 s2, s2, s3372; NEW_RBS-NEXT: s_cmp_lg_u32 s2, 0373; NEW_RBS-NEXT: s_cselect_b32 s0, s0, s1374; NEW_RBS-NEXT: v_mov_b32_e32 v2, s0375; NEW_RBS-NEXT: global_store_dword v[0:1], v2, off376; NEW_RBS-NEXT: s_endpgm377 %cmp_a = icmp uge i32 %a, 10378 %cmp_b = icmp uge i32 %b, 20379 %cc = and i1 %cmp_a, %cmp_b380 %res = select i1 %cc, i32 %a, i32 %b381 store i32 %res, ptr addrspace(1) %ptr382 ret void383}384 385; old RBS selects sgpr phi because it had sgpr inputs.386define amdgpu_ps void @divergent_phi_with_uniform_inputs(i32 %a, ptr addrspace(1) %out) {387; OLD_RBS-LABEL: divergent_phi_with_uniform_inputs:388; OLD_RBS: ; %bb.0: ; %A389; OLD_RBS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0390; OLD_RBS-NEXT: s_mov_b32 s0, 0391; OLD_RBS-NEXT: s_and_saveexec_b32 s1, vcc_lo392; OLD_RBS-NEXT: ; %bb.1: ; %B393; OLD_RBS-NEXT: s_mov_b32 s0, 1394; OLD_RBS-NEXT: ; %bb.2: ; %exit395; OLD_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s1396; OLD_RBS-NEXT: v_mov_b32_e32 v0, s0397; OLD_RBS-NEXT: global_store_dword v[1:2], v0, off398; OLD_RBS-NEXT: s_endpgm399;400; NEW_RBS-LABEL: divergent_phi_with_uniform_inputs:401; NEW_RBS: ; %bb.0: ; %A402; NEW_RBS-NEXT: s_mov_b32 s0, 0403; NEW_RBS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0404; NEW_RBS-NEXT: v_mov_b32_e32 v0, s0405; NEW_RBS-NEXT: s_and_saveexec_b32 s0, vcc_lo406; NEW_RBS-NEXT: ; %bb.1: ; %B407; NEW_RBS-NEXT: s_mov_b32 s1, 1408; NEW_RBS-NEXT: v_mov_b32_e32 v0, s1409; NEW_RBS-NEXT: ; %bb.2: ; %exit410; NEW_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s0411; NEW_RBS-NEXT: global_store_dword v[1:2], v0, off412; NEW_RBS-NEXT: s_endpgm413A:414 %cmp = icmp eq i32 %a, 0415 br i1 %cmp, label %B, label %exit416 417B:418 br label %exit419 420exit:421 %phi = phi i32 [ 0, %A ], [ 1, %B ]422 store i32 %phi, ptr addrspace(1) %out423 ret void424}425 426; old RBS assigned vgpr to uniform phi (because one input had undetermined bank)427; and it propagated to mul, which was not wrong.428; new RBS assigns vgpr to destination of mul even though both inputs are sgpr.429; TODO: implement temporal divergence lowering430define amdgpu_ps void @divergent_because_of_temporal_divergent_use(float %val, ptr addrspace(1) %addr) {431; OLD_RBS-LABEL: divergent_because_of_temporal_divergent_use:432; OLD_RBS: ; %bb.0: ; %entry433; OLD_RBS-NEXT: s_mov_b32 s0, -1434; OLD_RBS-NEXT: v_mov_b32_e32 v3, s0435; OLD_RBS-NEXT: s_mov_b32 s0, 0436; OLD_RBS-NEXT: .LBB15_1: ; %loop437; OLD_RBS-NEXT: ; =>This Inner Loop Header: Depth=1438; OLD_RBS-NEXT: v_add_nc_u32_e32 v3, 1, v3439; OLD_RBS-NEXT: v_cvt_f32_u32_e32 v4, v3440; OLD_RBS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v4, v0441; OLD_RBS-NEXT: s_or_b32 s0, vcc_lo, s0442; OLD_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s0443; OLD_RBS-NEXT: s_cbranch_execnz .LBB15_1444; OLD_RBS-NEXT: ; %bb.2: ; %exit445; OLD_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s0446; OLD_RBS-NEXT: v_mul_lo_u32 v0, v3, 10447; OLD_RBS-NEXT: global_store_dword v[1:2], v0, off448; OLD_RBS-NEXT: s_endpgm449;450; NEW_RBS-LABEL: divergent_because_of_temporal_divergent_use:451; NEW_RBS: ; %bb.0: ; %entry452; NEW_RBS-NEXT: s_mov_b32 s1, -1453; NEW_RBS-NEXT: s_mov_b32 s0, 0454; NEW_RBS-NEXT: .LBB15_1: ; %loop455; NEW_RBS-NEXT: ; =>This Inner Loop Header: Depth=1456; NEW_RBS-NEXT: s_add_i32 s1, s1, 1457; NEW_RBS-NEXT: v_cvt_f32_u32_e32 v3, s1458; NEW_RBS-NEXT: v_cmp_gt_f32_e32 vcc_lo, v3, v0459; NEW_RBS-NEXT: v_mov_b32_e32 v3, s1460; NEW_RBS-NEXT: s_or_b32 s0, vcc_lo, s0461; NEW_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s0462; NEW_RBS-NEXT: s_cbranch_execnz .LBB15_1463; NEW_RBS-NEXT: ; %bb.2: ; %exit464; NEW_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s0465; NEW_RBS-NEXT: v_mul_lo_u32 v0, v3, 10466; NEW_RBS-NEXT: global_store_dword v[1:2], v0, off467; NEW_RBS-NEXT: s_endpgm468entry:469 br label %loop470 471loop:472 %counter = phi i32 [ 0, %entry ], [ %counter.plus.1, %loop ]473 %f.counter = uitofp i32 %counter to float474 %cond = fcmp ogt float %f.counter, %val475 %counter.plus.1 = add i32 %counter, 1476 br i1 %cond, label %exit, label %loop477 478exit:479 %ceilx10 = mul i32 %counter, 10480 store i32 %ceilx10, ptr addrspace(1) %addr481 ret void482}483 484; Variables that hande counter can be allocated to sgprs.485define amdgpu_cs void @loop_with_2breaks(ptr addrspace(1) %x, ptr addrspace(1) %a, ptr addrspace(1) %b) {486; OLD_RBS-LABEL: loop_with_2breaks:487; OLD_RBS: ; %bb.0: ; %entry488; OLD_RBS-NEXT: s_mov_b32 s0, 0489; OLD_RBS-NEXT: ; implicit-def: $sgpr1490; OLD_RBS-NEXT: v_mov_b32_e32 v6, s0491; OLD_RBS-NEXT: s_branch .LBB16_3492; OLD_RBS-NEXT: .LBB16_1: ; %Flow3493; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1494; OLD_RBS-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)495; OLD_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s3496; OLD_RBS-NEXT: s_andn2_b32 s1, s1, exec_lo497; OLD_RBS-NEXT: s_and_b32 s3, exec_lo, s4498; OLD_RBS-NEXT: s_or_b32 s1, s1, s3499; OLD_RBS-NEXT: .LBB16_2: ; %Flow500; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1501; OLD_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s2502; OLD_RBS-NEXT: s_and_b32 s2, exec_lo, s1503; OLD_RBS-NEXT: s_or_b32 s0, s2, s0504; OLD_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s0505; OLD_RBS-NEXT: s_cbranch_execz .LBB16_6506; OLD_RBS-NEXT: .LBB16_3: ; %A507; OLD_RBS-NEXT: ; =>This Inner Loop Header: Depth=1508; OLD_RBS-NEXT: v_ashrrev_i32_e32 v7, 31, v6509; OLD_RBS-NEXT: s_andn2_b32 s1, s1, exec_lo510; OLD_RBS-NEXT: s_and_b32 s2, exec_lo, -1511; OLD_RBS-NEXT: s_or_b32 s1, s1, s2512; OLD_RBS-NEXT: v_lshlrev_b64 v[7:8], 2, v[6:7]513; OLD_RBS-NEXT: v_add_co_u32 v9, vcc_lo, v2, v7514; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v3, v8, vcc_lo515; OLD_RBS-NEXT: global_load_dword v9, v[9:10], off516; OLD_RBS-NEXT: s_waitcnt vmcnt(0)517; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9518; OLD_RBS-NEXT: s_and_saveexec_b32 s2, vcc_lo519; OLD_RBS-NEXT: s_cbranch_execz .LBB16_2520; OLD_RBS-NEXT: ; %bb.4: ; %B521; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1522; OLD_RBS-NEXT: v_add_co_u32 v9, vcc_lo, v4, v7523; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v10, vcc_lo, v5, v8, vcc_lo524; OLD_RBS-NEXT: s_mov_b32 s4, -1525; OLD_RBS-NEXT: global_load_dword v9, v[9:10], off526; OLD_RBS-NEXT: s_waitcnt vmcnt(0)527; OLD_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v9528; OLD_RBS-NEXT: s_and_saveexec_b32 s3, vcc_lo529; OLD_RBS-NEXT: s_cbranch_execz .LBB16_1530; OLD_RBS-NEXT: ; %bb.5: ; %loop.body531; OLD_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1532; OLD_RBS-NEXT: v_add_co_u32 v7, vcc_lo, v0, v7533; OLD_RBS-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, v1, v8, vcc_lo534; OLD_RBS-NEXT: v_add_nc_u32_e32 v10, 1, v6535; OLD_RBS-NEXT: v_cmp_gt_u32_e32 vcc_lo, 0x64, v6536; OLD_RBS-NEXT: s_andn2_b32 s4, -1, exec_lo537; OLD_RBS-NEXT: global_load_dword v9, v[7:8], off538; OLD_RBS-NEXT: v_mov_b32_e32 v6, v10539; OLD_RBS-NEXT: s_and_b32 s5, exec_lo, vcc_lo540; OLD_RBS-NEXT: s_or_b32 s4, s4, s5541; OLD_RBS-NEXT: s_waitcnt vmcnt(0)542; OLD_RBS-NEXT: v_add_nc_u32_e32 v9, 1, v9543; OLD_RBS-NEXT: global_store_dword v[7:8], v9, off544; OLD_RBS-NEXT: s_branch .LBB16_1545; OLD_RBS-NEXT: .LBB16_6: ; %exit546; OLD_RBS-NEXT: s_endpgm547;548; NEW_RBS-LABEL: loop_with_2breaks:549; NEW_RBS: ; %bb.0: ; %entry550; NEW_RBS-NEXT: s_mov_b32 s0, 0551; NEW_RBS-NEXT: s_mov_b32 s4, 0552; NEW_RBS-NEXT: ; implicit-def: $sgpr5553; NEW_RBS-NEXT: s_branch .LBB16_3554; NEW_RBS-NEXT: .LBB16_1: ; %Flow3555; NEW_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1556; NEW_RBS-NEXT: s_waitcnt_depctr depctr_vm_vsrc(0)557; NEW_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s7558; NEW_RBS-NEXT: s_andn2_b32 s2, s5, exec_lo559; NEW_RBS-NEXT: s_and_b32 s3, exec_lo, s6560; NEW_RBS-NEXT: s_or_b32 s5, s2, s3561; NEW_RBS-NEXT: .LBB16_2: ; %Flow562; NEW_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1563; NEW_RBS-NEXT: s_or_b32 exec_lo, exec_lo, s1564; NEW_RBS-NEXT: s_and_b32 s1, exec_lo, s5565; NEW_RBS-NEXT: s_or_b32 s4, s1, s4566; NEW_RBS-NEXT: s_andn2_b32 exec_lo, exec_lo, s4567; NEW_RBS-NEXT: s_cbranch_execz .LBB16_6568; NEW_RBS-NEXT: .LBB16_3: ; %A569; NEW_RBS-NEXT: ; =>This Inner Loop Header: Depth=1570; NEW_RBS-NEXT: s_ashr_i32 s1, s0, 31571; NEW_RBS-NEXT: s_lshl_b64 s[2:3], s[0:1], 2572; NEW_RBS-NEXT: s_andn2_b32 s1, s5, exec_lo573; NEW_RBS-NEXT: v_mov_b32_e32 v7, s3574; NEW_RBS-NEXT: v_mov_b32_e32 v6, s2575; NEW_RBS-NEXT: s_and_b32 s5, exec_lo, exec_lo576; NEW_RBS-NEXT: s_or_b32 s5, s1, s5577; NEW_RBS-NEXT: v_add_co_u32 v6, vcc_lo, v2, v6578; NEW_RBS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v3, v7, vcc_lo579; NEW_RBS-NEXT: global_load_dword v6, v[6:7], off580; NEW_RBS-NEXT: s_waitcnt vmcnt(0)581; NEW_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6582; NEW_RBS-NEXT: s_and_saveexec_b32 s1, vcc_lo583; NEW_RBS-NEXT: s_cbranch_execz .LBB16_2584; NEW_RBS-NEXT: ; %bb.4: ; %B585; NEW_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1586; NEW_RBS-NEXT: v_mov_b32_e32 v7, s3587; NEW_RBS-NEXT: v_mov_b32_e32 v6, s2588; NEW_RBS-NEXT: s_mov_b32 s6, exec_lo589; NEW_RBS-NEXT: v_add_co_u32 v6, vcc_lo, v4, v6590; NEW_RBS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v5, v7, vcc_lo591; NEW_RBS-NEXT: global_load_dword v6, v[6:7], off592; NEW_RBS-NEXT: s_waitcnt vmcnt(0)593; NEW_RBS-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v6594; NEW_RBS-NEXT: s_and_saveexec_b32 s7, vcc_lo595; NEW_RBS-NEXT: s_cbranch_execz .LBB16_1596; NEW_RBS-NEXT: ; %bb.5: ; %loop.body597; NEW_RBS-NEXT: ; in Loop: Header=BB16_3 Depth=1598; NEW_RBS-NEXT: v_mov_b32_e32 v7, s3599; NEW_RBS-NEXT: v_mov_b32_e32 v6, s2600; NEW_RBS-NEXT: s_add_i32 s2, s0, 1601; NEW_RBS-NEXT: s_cmpk_lt_u32 s0, 0x64602; NEW_RBS-NEXT: s_cselect_b32 s0, exec_lo, 0603; NEW_RBS-NEXT: v_add_co_u32 v6, vcc_lo, v0, v6604; NEW_RBS-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, v1, v7, vcc_lo605; NEW_RBS-NEXT: s_andn2_b32 s3, s6, exec_lo606; NEW_RBS-NEXT: s_and_b32 s0, exec_lo, s0607; NEW_RBS-NEXT: s_or_b32 s6, s3, s0608; NEW_RBS-NEXT: global_load_dword v8, v[6:7], off609; NEW_RBS-NEXT: s_mov_b32 s0, s2610; NEW_RBS-NEXT: s_waitcnt vmcnt(0)611; NEW_RBS-NEXT: v_add_nc_u32_e32 v8, 1, v8612; NEW_RBS-NEXT: global_store_dword v[6:7], v8, off613; NEW_RBS-NEXT: s_branch .LBB16_1614; NEW_RBS-NEXT: .LBB16_6: ; %exit615; NEW_RBS-NEXT: s_endpgm616entry:617 br label %A618 619A:620 %counter = phi i32 [ %counter.plus.1, %loop.body ], [ 0, %entry ]621 %a.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %a, i32 %counter622 %a.val = load i32, ptr addrspace(1) %a.plus.counter623 %a.cond = icmp eq i32 %a.val, 0624 br i1 %a.cond, label %exit, label %B625 626B:627 %b.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %b, i32 %counter628 %b.val = load i32, ptr addrspace(1) %b.plus.counter629 %b.cond = icmp eq i32 %b.val, 0630 br i1 %b.cond, label %exit, label %loop.body631 632loop.body:633 %x.plus.counter = getelementptr inbounds i32, ptr addrspace(1) %x, i32 %counter634 %x.val = load i32, ptr addrspace(1) %x.plus.counter635 %x.val.plus.1 = add i32 %x.val, 1636 store i32 %x.val.plus.1, ptr addrspace(1) %x.plus.counter637 %counter.plus.1 = add i32 %counter, 1638 %x.cond = icmp ult i32 %counter, 100639 br i1 %x.cond, label %exit, label %A640 641exit:642 ret void643}644 645declare i16 @llvm.abs.i16(i16, i1)646declare <4 x i32> @llvm.amdgcn.raw.buffer.load.v4i32(<4 x i32>, i32, i32, i32 immarg)647