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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s3 4---5name: mul_s32_ss6legalized: true7 8body: |9 bb.0:10 liveins: $sgpr0, $sgpr111 ; CHECK-LABEL: name: mul_s32_ss12 ; CHECK: liveins: $sgpr0, $sgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr015 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr116 ; CHECK-NEXT: [[MUL:%[0-9]+]]:sgpr(s32) = G_MUL [[COPY]], [[COPY1]]17 %0:_(s32) = COPY $sgpr018 %1:_(s32) = COPY $sgpr119 %2:_(s32) = G_MUL %0, %120...21 22---23name: mul_s32_sv24legalized: true25 26body: |27 bb.0:28 liveins: $sgpr0, $vgpr029 ; CHECK-LABEL: name: mul_s32_sv30 ; CHECK: liveins: $sgpr0, $vgpr031 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr033 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr034 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)35 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY2]], [[COPY1]]36 %0:_(s32) = COPY $sgpr037 %1:_(s32) = COPY $vgpr038 %2:_(s32) = G_MUL %0, %139...40 41---42name: mul_s32_vs43legalized: true44 45body: |46 bb.0:47 liveins: $sgpr0, $vgpr048 ; CHECK-LABEL: name: mul_s32_vs49 ; CHECK: liveins: $sgpr0, $vgpr050 ; CHECK-NEXT: {{ $}}51 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr052 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr053 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)54 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY]], [[COPY2]]55 %0:_(s32) = COPY $vgpr056 %1:_(s32) = COPY $sgpr057 %2:_(s32) = G_MUL %0, %158...59 60---61name: mul_s32_vv62legalized: true63 64body: |65 bb.0:66 liveins: $vgpr0, $vgpr167 ; CHECK-LABEL: name: mul_s32_vv68 ; CHECK: liveins: $vgpr0, $vgpr169 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr071 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr172 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[COPY]], [[COPY1]]73 %0:_(s32) = COPY $vgpr074 %1:_(s32) = COPY $vgpr175 %2:_(s32) = G_MUL %0, %176...77 78---79name: mul_s64_ss80legalized: true81 82body: |83 bb.0:84 liveins: $sgpr0_sgpr1, $sgpr2_sgpr385 ; CHECK-LABEL: name: mul_s64_ss86 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr387 ; CHECK-NEXT: {{ $}}88 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr189 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s64) = COPY $sgpr2_sgpr390 ; CHECK-NEXT: [[MUL:%[0-9]+]]:sgpr(s64) = G_MUL [[COPY]], [[COPY1]]91 %0:_(s64) = COPY $sgpr0_sgpr192 %1:_(s64) = COPY $sgpr2_sgpr393 %2:_(s64) = G_MUL %0, %194...95 96---97name: mul_s64_vv98legalized: true99 100body: |101 bb.0:102 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3103 ; CHECK-LABEL: name: mul_s64_vv104 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3105 ; CHECK-NEXT: {{ $}}106 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1107 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3108 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)109 ; CHECK-NEXT: [[UV2:%[0-9]+]]:vgpr(s32), [[UV3:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY1]](s64)110 ; CHECK-NEXT: [[UMULH:%[0-9]+]]:vgpr(s32) = G_UMULH [[UV]], [[UV2]]111 ; CHECK-NEXT: [[MUL:%[0-9]+]]:vgpr(s32) = G_MUL [[UV]], [[UV3]]112 ; CHECK-NEXT: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[UMULH]], [[MUL]]113 ; CHECK-NEXT: [[MUL1:%[0-9]+]]:vgpr(s32) = G_MUL [[UV1]], [[UV2]]114 ; CHECK-NEXT: [[ADD1:%[0-9]+]]:vgpr(s32) = G_ADD [[ADD]], [[MUL1]]115 ; CHECK-NEXT: [[MUL2:%[0-9]+]]:vgpr(s32) = G_MUL [[UV]], [[UV2]]116 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[MUL2]](s32), [[ADD1]](s32)117 %0:_(s64) = COPY $vgpr0_vgpr1118 %1:_(s64) = COPY $vgpr2_vgpr3119 %2:_(s64) = G_MUL %0, %1120...121 122---123name: mul_s64_zext_ss124legalized: true125 126body: |127 bb.0:128 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3129 ; CHECK-LABEL: name: mul_s64_zext_ss130 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3131 ; CHECK-NEXT: {{ $}}132 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr0_sgpr1133 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr2_sgpr3134 ; CHECK-NEXT: [[S_MUL_U64_:%[0-9]+]]:sgpr_64(s64) = S_MUL_U64 [[COPY]](s64), [[COPY1]](s64)135 %0:_(s64) = COPY $sgpr0_sgpr1136 %1:_(s64) = COPY $sgpr2_sgpr3137 %2:_(s64) = G_AMDGPU_S_MUL_U64_U32 %0, %1138...139 140---141name: mul_s64_zext_vv142legalized: true143 144body: |145 bb.0:146 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3147 ; CHECK-LABEL: name: mul_s64_zext_vv148 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1151 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3152 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY]](s64)153 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY1]](s64)154 ; CHECK-NEXT: [[C:%[0-9]+]]:vreg_64(s64) = G_CONSTANT i64 0155 ; CHECK-NEXT: [[AMDGPU_MAD_U64_U32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_U64_U32_1:%[0-9]+]]:vreg_64 = G_AMDGPU_MAD_U64_U32 [[TRUNC]](s32), [[TRUNC1]], [[C]]156 %0:_(s64) = COPY $vgpr0_vgpr1157 %1:_(s64) = COPY $vgpr2_vgpr3158 %2:_(s64) = G_AMDGPU_S_MUL_U64_U32 %0, %1159...160 161---162name: mul_s64_sext_ss163legalized: true164 165body: |166 bb.0:167 liveins: $sgpr0_sgpr1, $sgpr2_sgpr3168 ; CHECK-LABEL: name: mul_s64_sext_ss169 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2_sgpr3170 ; CHECK-NEXT: {{ $}}171 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr0_sgpr1172 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_64(s64) = COPY $sgpr2_sgpr3173 ; CHECK-NEXT: [[S_MUL_U64_:%[0-9]+]]:sgpr_64(s64) = S_MUL_U64 [[COPY]](s64), [[COPY1]](s64)174 %0:_(s64) = COPY $sgpr0_sgpr1175 %1:_(s64) = COPY $sgpr2_sgpr3176 %2:_(s64) = G_AMDGPU_S_MUL_I64_I32 %0, %1177...178 179---180name: mul_s64_sext_vv181legalized: true182 183body: |184 bb.0:185 liveins: $vgpr0_vgpr1, $vgpr2_vgpr3186 ; CHECK-LABEL: name: mul_s64_sext_vv187 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1190 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s64) = COPY $vgpr2_vgpr3191 ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY]](s64)192 ; CHECK-NEXT: [[TRUNC1:%[0-9]+]]:vgpr_32(s32) = G_TRUNC [[COPY1]](s64)193 ; CHECK-NEXT: [[C:%[0-9]+]]:vreg_64(s64) = G_CONSTANT i64 0194 ; CHECK-NEXT: [[AMDGPU_MAD_I64_I32_:%[0-9]+]]:vgpr(s64), [[AMDGPU_MAD_I64_I32_1:%[0-9]+]]:vreg_64 = G_AMDGPU_MAD_I64_I32 [[TRUNC]](s32), [[TRUNC1]], [[C]]195 %0:_(s64) = COPY $vgpr0_vgpr1196 %1:_(s64) = COPY $vgpr2_vgpr3197 %2:_(s64) = G_AMDGPU_S_MUL_I64_I32 %0, %1198...199