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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s3 4...5 6# Generate the 3 operand vector bitfield extract instructions for 32-bit7# operations only.8---9name: test_sbfx_s32_vvv10legalized: true11 12body: |13 bb.0.entry:14 liveins: $vgpr0, $vgpr1, $vgpr215 16 ; CHECK-LABEL: name: test_sbfx_s32_vvv17 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr218 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr121 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr222 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY1]](s32), [[COPY2]]23 ; CHECK-NEXT: $vgpr0 = COPY [[SBFX]](s32)24 %0:_(s32) = COPY $vgpr025 %1:_(s32) = COPY $vgpr126 %2:_(s32) = COPY $vgpr227 %3:_(s32) = G_SBFX %0, %1(s32), %228 $vgpr0 = COPY %3(s32)29...30 31---32name: test_sbfx_s32_vii33legalized: true34 35body: |36 bb.0.entry:37 liveins: $vgpr038 39 ; CHECK-LABEL: name: test_sbfx_s32_vii40 ; CHECK: liveins: $vgpr041 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr043 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1044 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 445 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)46 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)47 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY1]](s32), [[COPY2]]48 ; CHECK-NEXT: $vgpr0 = COPY [[SBFX]](s32)49 %0:_(s32) = COPY $vgpr050 %1:_(s32) = G_CONSTANT i32 1051 %2:_(s32) = G_CONSTANT i32 452 %3:_(s32) = G_SBFX %0, %1(s32), %253 $vgpr0 = COPY %3(s32)54...55 56---57name: test_sbfx_s32_vss58legalized: true59 60body: |61 bb.0.entry:62 liveins: $vgpr0, $sgpr0, $sgpr163 64 ; CHECK-LABEL: name: test_sbfx_s32_vss65 ; CHECK: liveins: $vgpr0, $sgpr0, $sgpr166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr068 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr069 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr170 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)71 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)72 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY]], [[COPY3]](s32), [[COPY4]]73 ; CHECK-NEXT: $vgpr0 = COPY [[SBFX]](s32)74 %0:_(s32) = COPY $vgpr075 %1:_(s32) = COPY $sgpr076 %2:_(s32) = COPY $sgpr177 %3:_(s32) = G_SBFX %0, %1(s32), %278 $vgpr0 = COPY %3(s32)79...80 81# Expand to a sequence that implements the 64-bit bitfield extract using82# shifts and masks.83---84name: test_sbfx_s64_vvv85legalized: true86 87body: |88 bb.0.entry:89 liveins: $vgpr0_vgpr1, $vgpr2, $vgpr390 91 ; CHECK-LABEL: name: test_sbfx_s64_vvv92 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr393 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr195 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr296 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr397 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)98 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6499 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]100 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)101 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)102 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR1]](s64)103 %0:_(s64) = COPY $vgpr0_vgpr1104 %1:_(s32) = COPY $vgpr2105 %2:_(s32) = COPY $vgpr3106 %3:_(s64) = G_SBFX %0, %1(s32), %2107 $vgpr0_vgpr1 = COPY %3(s64)108...109 110---111name: test_sbfx_s64_vss112legalized: true113 114body: |115 bb.0.entry:116 liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1117 118 ; CHECK-LABEL: name: test_sbfx_s64_vss119 ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0123 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1124 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)125 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64126 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]127 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)128 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)129 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR1]](s64)130 %0:_(s64) = COPY $vgpr0_vgpr1131 %1:_(s32) = COPY $vgpr0132 %2:_(s32) = COPY $vgpr1133 %3:_(s64) = G_SBFX %0, %1(s32), %2134 $vgpr0_vgpr1 = COPY %3(s64)135...136 137# If the offset and width are constants, use the 32-bit bitfield extract,138# and merge to create a 64-bit result.139---140name: test_sbfx_s64_vii_small141legalized: true142 143body: |144 bb.0.entry:145 liveins: $vgpr0_vgpr1146 147 ; CHECK-LABEL: name: test_sbfx_s64_vii_small148 ; CHECK: liveins: $vgpr0_vgpr1149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1151 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31152 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4153 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)154 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)155 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)156 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)157 ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0158 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[UV]], [[C2]](s32), [[COPY2]]159 ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 31160 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:vgpr(s32) = G_ASHR [[SBFX]], [[C3]](s32)161 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[SBFX]](s32), [[ASHR1]](s32)162 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)163 %0:_(s64) = COPY $vgpr0_vgpr1164 %1:_(s32) = G_CONSTANT i32 31165 %2:_(s32) = G_CONSTANT i32 4166 %3:_(s64) = G_SBFX %0, %1(s32), %2167 $vgpr0_vgpr1 = COPY %3(s64)168...169 170---171name: test_sbfx_s64_vii_big172legalized: true173 174body: |175 bb.0.entry:176 liveins: $vgpr0_vgpr1177 178 ; CHECK-LABEL: name: test_sbfx_s64_vii_big179 ; CHECK: liveins: $vgpr0_vgpr1180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1182 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 8183 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 40184 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)185 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)186 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY]], [[COPY1]](s32)187 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[ASHR]](s64)188 ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0189 ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 8190 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[UV1]], [[C2]](s32), [[C3]]191 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[SBFX]](s32)192 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)193 %0:_(s64) = COPY $vgpr0_vgpr1194 %1:_(s32) = G_CONSTANT i32 8195 %2:_(s32) = G_CONSTANT i32 40196 %3:_(s64) = G_SBFX %0, %1(s32), %2197 $vgpr0_vgpr1 = COPY %3(s64)198...199 200---201name: test_sbfx_s64_svv202legalized: true203 204body: |205 bb.0.entry:206 liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1207 208 ; CHECK-LABEL: name: test_sbfx_s64_svv209 ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1210 ; CHECK-NEXT: {{ $}}211 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1212 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0213 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1214 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)215 ; CHECK-NEXT: [[ASHR:%[0-9]+]]:vgpr(s64) = G_ASHR [[COPY3]], [[COPY1]](s32)216 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64217 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]218 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[ASHR]], [[SUB]](s32)219 ; CHECK-NEXT: [[ASHR1:%[0-9]+]]:vgpr(s64) = G_ASHR [[SHL]], [[SUB]](s32)220 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[ASHR1]](s64)221 %0:_(s64) = COPY $sgpr0_sgpr1222 %1:_(s32) = COPY $vgpr0223 %2:_(s32) = COPY $vgpr1224 %3:_(s64) = G_SBFX %0, %1(s32), %2225 $vgpr0_vgpr1 = COPY %3(s64)226...227 228# Expand to a sequence that combines the offset and width for the two operand229# version of the 32-bit instruction.230---231name: test_sbfx_s32_svv232legalized: true233 234body: |235 bb.0.entry:236 liveins: $sgpr0, $vgpr0, $vgpr1237 238 ; CHECK-LABEL: name: test_sbfx_s32_svv239 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1240 ; CHECK-NEXT: {{ $}}241 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0242 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0243 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1244 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)245 ; CHECK-NEXT: [[SBFX:%[0-9]+]]:vgpr(s32) = G_SBFX [[COPY3]], [[COPY1]](s32), [[COPY2]]246 ; CHECK-NEXT: $vgpr0 = COPY [[SBFX]](s32)247 %0:_(s32) = COPY $sgpr0248 %1:_(s32) = COPY $vgpr0249 %2:_(s32) = COPY $vgpr1250 %3:_(s32) = G_SBFX %0, %1(s32), %2251 $vgpr0 = COPY %3(s32)252...253 254---255name: test_sbfx_s32_sss256legalized: true257 258body: |259 bb.0.entry:260 liveins: $sgpr0, $sgpr1, $sgpr3261 262 ; CHECK-LABEL: name: test_sbfx_s32_sss263 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr3264 ; CHECK-NEXT: {{ $}}265 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0266 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1267 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2268 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63269 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]270 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16271 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)272 ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[AND]], [[SHL]]273 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)274 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s32) = COPY [[OR]](s32)275 ; CHECK-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY3]](s32), [[COPY4]](s32), implicit-def $scc276 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_I32_]](s32)277 ; CHECK-NEXT: $sgpr0 = COPY [[COPY5]](s32)278 %0:_(s32) = COPY $sgpr0279 %1:_(s32) = COPY $sgpr1280 %2:_(s32) = COPY $sgpr2281 %3:_(s32) = G_SBFX %0, %1(s32), %2282 $sgpr0 = COPY %3(s32)283...284 285---286name: test_sbfx_s32_sii287legalized: true288 289body: |290 bb.0.entry:291 liveins: $sgpr0292 293 ; CHECK-LABEL: name: test_sbfx_s32_sii294 ; CHECK: liveins: $sgpr0295 ; CHECK-NEXT: {{ $}}296 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0297 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1298 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10299 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63300 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16301 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655360302 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655361303 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)304 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(s32) = COPY [[C5]](s32)305 ; CHECK-NEXT: [[S_BFE_I32_:%[0-9]+]]:sreg_32(s32) = S_BFE_I32 [[COPY1]](s32), [[COPY2]](s32), implicit-def $scc306 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_I32_]](s32)307 ; CHECK-NEXT: $sgpr0 = COPY [[COPY3]](s32)308 %0:_(s32) = COPY $sgpr0309 %1:_(s32) = G_CONSTANT i32 1310 %2:_(s32) = G_CONSTANT i32 10311 %3:_(s32) = G_SBFX %0, %1(s32), %2312 $sgpr0 = COPY %3(s32)313...314 315# Expand to a sequence that combines the offset and width for the two operand316# version of the 64-bit scalar instruction.317---318name: test_sbfx_s64_sss319legalized: true320 321body: |322 bb.0.entry:323 liveins: $sgpr0_sgpr1, $sgpr0, $sgpr1324 325 ; CHECK-LABEL: name: test_sbfx_s64_sss326 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr0, $sgpr1327 ; CHECK-NEXT: {{ $}}328 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1329 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr0330 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr1331 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63332 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]333 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16334 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)335 ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[AND]], [[SHL]]336 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)337 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s32) = COPY [[OR]](s32)338 ; CHECK-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY3]](s64), [[COPY4]](s32), implicit-def $scc339 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_I64_]](s64)340 ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[COPY5]](s64)341 %0:_(s64) = COPY $sgpr0_sgpr1342 %1:_(s32) = COPY $sgpr0343 %2:_(s32) = COPY $sgpr1344 %3:_(s64) = G_SBFX %0, %1(s32), %2345 $sgpr0_sgpr1 = COPY %3(s64)346...347 348---349name: test_sbfx_s64_sii350legalized: true351 352body: |353 bb.0.entry:354 liveins: $sgpr0_sgpr1355 356 ; CHECK-LABEL: name: test_sbfx_s64_sii357 ; CHECK: liveins: $sgpr0_sgpr1358 ; CHECK-NEXT: {{ $}}359 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1360 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1361 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10362 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63363 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16364 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655360365 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655361366 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)367 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(s32) = COPY [[C5]](s32)368 ; CHECK-NEXT: [[S_BFE_I64_:%[0-9]+]]:sreg_64(s64) = S_BFE_I64 [[COPY1]](s64), [[COPY2]](s32), implicit-def $scc369 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_I64_]](s64)370 %0:_(s64) = COPY $sgpr0_sgpr1371 %1:_(s32) = G_CONSTANT i32 1372 %2:_(s32) = G_CONSTANT i32 10373 %3:_(s64) = G_SBFX %0, %1(s32), %2374...375