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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -o - %s | FileCheck %s3 4---5name: sextload_constant_i8_to_i32_uniform6legalized: true7 8body: |9 bb.0:10 liveins: $sgpr0_sgpr111 ; CHECK-LABEL: name: sextload_constant_i8_to_i32_uniform12 ; CHECK: liveins: $sgpr0_sgpr113 ; CHECK-NEXT: {{ $}}14 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr115 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 4)16 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]17 %0:_(p4) = COPY $sgpr0_sgpr118 %1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 4, align 1)19...20 21---22name: sextload_global_i8_to_i32_uniform23legalized: true24 25body: |26 bb.0:27 liveins: $sgpr0_sgpr128 29 ; CHECK-LABEL: name: sextload_global_i8_to_i32_uniform30 ; CHECK: liveins: $sgpr0_sgpr131 ; CHECK-NEXT: {{ $}}32 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr133 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY]](p4) :: (load (s8), addrspace 1)34 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]35 %0:_(p4) = COPY $sgpr0_sgpr136 %1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 1, align 1)37...38 39---40name: sextload_constant_i16_to_i32_uniform41legalized: true42 43body: |44 bb.0:45 liveins: $sgpr0_sgpr146 47 ; CHECK-LABEL: name: sextload_constant_i16_to_i32_uniform48 ; CHECK: liveins: $sgpr0_sgpr149 ; CHECK-NEXT: {{ $}}50 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr151 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY]](p4) :: (load (s16), addrspace 4)52 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]53 %0:_(p4) = COPY $sgpr0_sgpr154 %1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 4, align 2)55...56 57---58name: sextload_global_i16_to_i32_uniform59legalized: true60 61body: |62 bb.0:63 liveins: $sgpr0_sgpr164 65 ; CHECK-LABEL: name: sextload_global_i16_to_i32_uniform66 ; CHECK: liveins: $sgpr0_sgpr167 ; CHECK-NEXT: {{ $}}68 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr169 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY]](p4) :: (load (s16), addrspace 1)70 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]71 %0:_(p4) = COPY $sgpr0_sgpr172 %1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 1, align 2)73...74 75---76name: sextload_local_i8_to_i32_uniform77legalized: true78 79body: |80 bb.0:81 liveins: $sgpr082 ; CHECK-LABEL: name: sextload_local_i8_to_i32_uniform83 ; CHECK: liveins: $sgpr084 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr086 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)87 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load (s8), addrspace 3)88 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]89 %0:_(p3) = COPY $sgpr090 %1:_(s32) = G_SEXTLOAD %0 :: (load (s8), addrspace 3, align 1)91...92 93---94name: sextload_local_i16_to_i32_uniform95legalized: true96 97body: |98 bb.0:99 liveins: $sgpr0100 101 ; CHECK-LABEL: name: sextload_local_i16_to_i32_uniform102 ; CHECK: liveins: $sgpr0103 ; CHECK-NEXT: {{ $}}104 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p3) = COPY $sgpr0105 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(p3) = COPY [[COPY]](p3)106 ; CHECK-NEXT: [[SEXTLOAD:%[0-9]+]]:vgpr(s32) = G_SEXTLOAD [[COPY1]](p3) :: (load (s16), addrspace 3)107 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[SEXTLOAD]]108 %0:_(p3) = COPY $sgpr0109 %1:_(s32) = G_SEXTLOAD %0 :: (load (s16), addrspace 3, align 2)110...111