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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=hawaii -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX7 %s3# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s4# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck -check-prefix=GFX12 %s5 6--- |7 8 define amdgpu_ps i96 @split_smrd_load_range(ptr addrspace(4) %ptr) {9 %load = load i96, ptr addrspace(4) %ptr, !range !010 ret i96 %load11 }12 13 define amdgpu_ps <3 x i32> @split_smrd_load_tbaa(ptr addrspace(4) %ptr) {14 %load = load <3 x i32>, ptr addrspace(4) %ptr, !tbaa !115 ret <3 x i32> %load16 }17 18 !0 = !{i96 0, i96 9223372036854775808}19 !1 = !{!"omnipotent char", !2}20 !2 = !{!"Simple C/C++ TBAA"}21 !3 = !{i32 0, i32 2147483646}22...23 24# Make sure range metadata is not preserved when widening loads, but25# tbaa is.26 27---28name: split_smrd_load_range29legalized: true30body: |31 bb.0:32 liveins: $sgpr0_sgpr133 34 ; GFX7-LABEL: name: split_smrd_load_range35 ; GFX7: liveins: $sgpr0_sgpr136 ; GFX7-NEXT: {{ $}}37 ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr138 ; GFX7-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), addrspace 4)39 ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 840 ; GFX7-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)41 ; GFX7-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from unknown-address + 8, align 8, addrspace 4)42 ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)43 ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)44 ; GFX7-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)45 ;46 ; GFX12-LABEL: name: split_smrd_load_range47 ; GFX12: liveins: $sgpr0_sgpr148 ; GFX12-NEXT: {{ $}}49 ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr150 ; GFX12-NEXT: [[LOAD:%[0-9]+]]:sgpr(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 851 ; GFX12-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>)52 %0:_(p4) = COPY $sgpr0_sgpr153 %1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>), align 8, addrspace 4, !range !3)54 $sgpr0_sgpr1_sgpr2 = COPY %155 56...57 58---59name: split_smrd_load_tbaa60legalized: true61body: |62 bb.0:63 liveins: $sgpr0_sgpr164 65 ; GFX7-LABEL: name: split_smrd_load_tbaa66 ; GFX7: liveins: $sgpr0_sgpr167 ; GFX7-NEXT: {{ $}}68 ; GFX7-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr169 ; GFX7-NEXT: [[LOAD:%[0-9]+]]:sgpr(<2 x s32>) = G_LOAD [[COPY]](p4) :: (load (<2 x s32>), !tbaa !2, addrspace 4)70 ; GFX7-NEXT: [[C:%[0-9]+]]:sgpr(s64) = G_CONSTANT i64 871 ; GFX7-NEXT: [[PTR_ADD:%[0-9]+]]:sgpr(p4) = nuw inbounds G_PTR_ADD [[COPY]], [[C]](s64)72 ; GFX7-NEXT: [[LOAD1:%[0-9]+]]:sgpr(s32) = G_LOAD [[PTR_ADD]](p4) :: (load (s32) from unknown-address + 8, align 8, !tbaa !2, addrspace 4)73 ; GFX7-NEXT: [[UV:%[0-9]+]]:sgpr(s32), [[UV1:%[0-9]+]]:sgpr(s32) = G_UNMERGE_VALUES [[LOAD]](<2 x s32>)74 ; GFX7-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<3 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[LOAD1]](s32)75 ; GFX7-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[BUILD_VECTOR]](<3 x s32>)76 ;77 ; GFX12-LABEL: name: split_smrd_load_tbaa78 ; GFX12: liveins: $sgpr0_sgpr179 ; GFX12-NEXT: {{ $}}80 ; GFX12-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr181 ; GFX12-NEXT: [[LOAD:%[0-9]+]]:sgpr(<3 x s32>) = G_LOAD [[COPY]](p4) :: (load (<3 x s32>), align 8, !tbaa !2, addrspace 4)82 ; GFX12-NEXT: $sgpr0_sgpr1_sgpr2 = COPY [[LOAD]](<3 x s32>)83 %0:_(p4) = COPY $sgpr0_sgpr184 %1:_(<3 x s32>) = G_LOAD %0 :: (load (<3 x s32>), align 8, addrspace 4, !tbaa !1)85 $sgpr0_sgpr1_sgpr2 = COPY %186 87...88