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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=fiji -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" -verify-machineinstrs -o - %s | FileCheck %s3 4...5 6# Generate the 3 operand vector bitfield extract instructions for 32-bit7# operations only.8---9name: test_ubfx_s32_vvv10legalized: true11 12body: |13 bb.0.entry:14 liveins: $vgpr0, $vgpr1, $vgpr215 16 ; CHECK-LABEL: name: test_ubfx_s32_vvv17 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr218 ; CHECK-NEXT: {{ $}}19 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr020 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr121 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr222 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[COPY]], [[COPY1]](s32), [[COPY2]]23 ; CHECK-NEXT: $vgpr0 = COPY [[UBFX]](s32)24 %0:_(s32) = COPY $vgpr025 %1:_(s32) = COPY $vgpr126 %2:_(s32) = COPY $vgpr227 %3:_(s32) = G_UBFX %0, %1(s32), %228 $vgpr0 = COPY %3(s32)29...30 31---32name: test_ubfx_s32_vii33legalized: true34 35body: |36 bb.0.entry:37 liveins: $vgpr038 39 ; CHECK-LABEL: name: test_ubfx_s32_vii40 ; CHECK: liveins: $vgpr041 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr043 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1044 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 445 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)46 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)47 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[COPY]], [[COPY1]](s32), [[COPY2]]48 ; CHECK-NEXT: $vgpr0 = COPY [[UBFX]](s32)49 %0:_(s32) = COPY $vgpr050 %1:_(s32) = G_CONSTANT i32 1051 %2:_(s32) = G_CONSTANT i32 452 %3:_(s32) = G_UBFX %0, %1(s32), %253 $vgpr0 = COPY %3(s32)54...55 56---57name: test_ubfx_s32_vss58legalized: true59 60body: |61 bb.0.entry:62 liveins: $vgpr0, $sgpr0, $sgpr163 64 ; CHECK-LABEL: name: test_ubfx_s32_vss65 ; CHECK: liveins: $vgpr0, $sgpr0, $sgpr166 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr068 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr069 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr170 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY1]](s32)71 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr(s32) = COPY [[COPY2]](s32)72 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[COPY]], [[COPY3]](s32), [[COPY4]]73 ; CHECK-NEXT: $vgpr0 = COPY [[UBFX]](s32)74 %0:_(s32) = COPY $vgpr075 %1:_(s32) = COPY $sgpr076 %2:_(s32) = COPY $sgpr177 %3:_(s32) = G_UBFX %0, %1(s32), %278 $vgpr0 = COPY %3(s32)79...80 81# Expand to a sequence that implements the 64-bit bitfield extract using82# shifts and masks.83---84name: test_ubfx_s64_vvv85legalized: true86 87body: |88 bb.0.entry:89 liveins: $vgpr0_vgpr1, $vgpr2, $vgpr390 91 ; CHECK-LABEL: name: test_ubfx_s64_vvv92 ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2, $vgpr393 ; CHECK-NEXT: {{ $}}94 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr195 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr296 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr397 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY]], [[COPY1]](s32)98 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 6499 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]100 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[LSHR]], [[SUB]](s32)101 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:vgpr(s64) = G_LSHR [[SHL]], [[SUB]](s32)102 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR1]](s64)103 %0:_(s64) = COPY $vgpr0_vgpr1104 %1:_(s32) = COPY $vgpr2105 %2:_(s32) = COPY $vgpr3106 %3:_(s64) = G_UBFX %0, %1(s32), %2107 $vgpr0_vgpr1 = COPY %3(s64)108...109 110---111name: test_ubfx_s64_vss112legalized: true113 114body: |115 bb.0.entry:116 liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1117 118 ; CHECK-LABEL: name: test_ubfx_s64_vss119 ; CHECK: liveins: $vgpr0_vgpr1, $sgpr0, $sgpr1120 ; CHECK-NEXT: {{ $}}121 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1122 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0123 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1124 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY]], [[COPY1]](s32)125 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64126 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]127 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[LSHR]], [[SUB]](s32)128 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:vgpr(s64) = G_LSHR [[SHL]], [[SUB]](s32)129 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR1]](s64)130 %0:_(s64) = COPY $vgpr0_vgpr1131 %1:_(s32) = COPY $vgpr0132 %2:_(s32) = COPY $vgpr1133 %3:_(s64) = G_UBFX %0, %1(s32), %2134 $vgpr0_vgpr1 = COPY %3(s64)135...136 137# If the offset and width are constants, use the 32-bit bitfield extract,138# and merge to create a 64-bit result.139---140name: test_ubfx_s64_vii_small141legalized: true142 143body: |144 bb.0.entry:145 liveins: $vgpr0_vgpr1146 147 ; CHECK-LABEL: name: test_ubfx_s64_vii_small148 ; CHECK: liveins: $vgpr0_vgpr1149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1151 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 31152 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 4153 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)154 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)155 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY]], [[COPY1]](s32)156 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[LSHR]](s64)157 ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0158 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[UV]], [[C2]](s32), [[COPY2]]159 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UBFX]](s32), [[C2]](s32)160 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)161 %0:_(s64) = COPY $vgpr0_vgpr1162 %1:_(s32) = G_CONSTANT i32 31163 %2:_(s32) = G_CONSTANT i32 4164 %3:_(s64) = G_UBFX %0, %1(s32), %2165 $vgpr0_vgpr1 = COPY %3(s64)166...167 168---169name: test_ubfx_s64_vii_big170legalized: true171 172body: |173 bb.0.entry:174 liveins: $vgpr0_vgpr1175 176 ; CHECK-LABEL: name: test_ubfx_s64_vii_big177 ; CHECK: liveins: $vgpr0_vgpr1178 ; CHECK-NEXT: {{ $}}179 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1180 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 8181 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 40182 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[C]](s32)183 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY [[C1]](s32)184 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY]], [[COPY1]](s32)185 ; CHECK-NEXT: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[LSHR]](s64)186 ; CHECK-NEXT: [[C2:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 0187 ; CHECK-NEXT: [[C3:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 8188 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[UV1]], [[C2]](s32), [[C3]]189 ; CHECK-NEXT: [[MV:%[0-9]+]]:vgpr(s64) = G_MERGE_VALUES [[UV]](s32), [[UBFX]](s32)190 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[MV]](s64)191 %0:_(s64) = COPY $vgpr0_vgpr1192 %1:_(s32) = G_CONSTANT i32 8193 %2:_(s32) = G_CONSTANT i32 40194 %3:_(s64) = G_UBFX %0, %1(s32), %2195 $vgpr0_vgpr1 = COPY %3(s64)196...197 198---199name: test_ubfx_s64_svv200legalized: true201 202body: |203 bb.0.entry:204 liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1205 206 ; CHECK-LABEL: name: test_ubfx_s64_svv207 ; CHECK: liveins: $sgpr0_sgpr1, $vgpr0, $vgpr1208 ; CHECK-NEXT: {{ $}}209 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1210 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0211 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1212 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s64) = COPY [[COPY]](s64)213 ; CHECK-NEXT: [[LSHR:%[0-9]+]]:vgpr(s64) = G_LSHR [[COPY3]], [[COPY1]](s32)214 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 64215 ; CHECK-NEXT: [[SUB:%[0-9]+]]:vgpr(s32) = G_SUB [[C]], [[COPY2]]216 ; CHECK-NEXT: [[SHL:%[0-9]+]]:vgpr(s64) = G_SHL [[LSHR]], [[SUB]](s32)217 ; CHECK-NEXT: [[LSHR1:%[0-9]+]]:vgpr(s64) = G_LSHR [[SHL]], [[SUB]](s32)218 ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[LSHR1]](s64)219 %0:_(s64) = COPY $sgpr0_sgpr1220 %1:_(s32) = COPY $vgpr0221 %2:_(s32) = COPY $vgpr1222 %3:_(s64) = G_UBFX %0, %1(s32), %2223 $vgpr0_vgpr1 = COPY %3(s64)224...225 226# Expand to a sequence that combines the offset and width for the two operand227# version of the 32-bit instruction.228---229name: test_ubfx_s32_svv230legalized: true231 232body: |233 bb.0.entry:234 liveins: $sgpr0, $vgpr0, $vgpr1235 236 ; CHECK-LABEL: name: test_ubfx_s32_svv237 ; CHECK: liveins: $sgpr0, $vgpr0, $vgpr1238 ; CHECK-NEXT: {{ $}}239 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0240 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY $vgpr0241 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr(s32) = COPY $vgpr1242 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr(s32) = COPY [[COPY]](s32)243 ; CHECK-NEXT: [[UBFX:%[0-9]+]]:vgpr(s32) = G_UBFX [[COPY3]], [[COPY1]](s32), [[COPY2]]244 ; CHECK-NEXT: $vgpr0 = COPY [[UBFX]](s32)245 %0:_(s32) = COPY $sgpr0246 %1:_(s32) = COPY $vgpr0247 %2:_(s32) = COPY $vgpr1248 %3:_(s32) = G_UBFX %0, %1(s32), %2249 $vgpr0 = COPY %3(s32)250...251 252---253name: test_ubfx_s32_sss254legalized: true255 256body: |257 bb.0.entry:258 liveins: $sgpr0, $sgpr1, $sgpr2259 260 ; CHECK-LABEL: name: test_ubfx_s32_sss261 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0264 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1265 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr2266 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63267 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]268 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16269 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)270 ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[AND]], [[SHL]]271 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)272 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s32) = COPY [[OR]](s32)273 ; CHECK-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32(s32) = S_BFE_U32 [[COPY3]](s32), [[COPY4]](s32), implicit-def $scc274 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_U32_]](s32)275 ; CHECK-NEXT: $sgpr0 = COPY [[COPY5]](s32)276 %0:_(s32) = COPY $sgpr0277 %1:_(s32) = COPY $sgpr1278 %2:_(s32) = COPY $sgpr2279 %3:_(s32) = G_UBFX %0, %1(s32), %2280 $sgpr0 = COPY %3(s32)281...282 283---284name: test_ubfx_s32_sii285legalized: true286 287body: |288 bb.0.entry:289 liveins: $sgpr0, $sgpr1, $sgpr2290 291 ; CHECK-LABEL: name: test_ubfx_s32_sii292 ; CHECK: liveins: $sgpr0, $sgpr1, $sgpr2293 ; CHECK-NEXT: {{ $}}294 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0295 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1296 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10297 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63298 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16299 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655360300 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655361301 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32(s32) = COPY [[COPY]](s32)302 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(s32) = COPY [[C5]](s32)303 ; CHECK-NEXT: [[S_BFE_U32_:%[0-9]+]]:sreg_32(s32) = S_BFE_U32 [[COPY1]](s32), [[COPY2]](s32), implicit-def $scc304 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s32) = COPY [[S_BFE_U32_]](s32)305 ; CHECK-NEXT: $sgpr0 = COPY [[COPY3]](s32)306 %0:_(s32) = COPY $sgpr0307 %1:_(s32) = G_CONSTANT i32 1308 %2:_(s32) = G_CONSTANT i32 10309 %3:_(s32) = G_UBFX %0, %1(s32), %2310 $sgpr0 = COPY %3(s32)311...312 313# Expand to a sequence that combines the offset and width for the two operand314# version of the 64-bit scalar instruction.315---316name: test_ubfx_s64_sss317legalized: true318 319body: |320 bb.0.entry:321 liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3322 323 ; CHECK-LABEL: name: test_ubfx_s64_sss324 ; CHECK: liveins: $sgpr0_sgpr1, $sgpr2, $sgpr3325 ; CHECK-NEXT: {{ $}}326 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1327 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr2328 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr(s32) = COPY $sgpr3329 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63330 ; CHECK-NEXT: [[AND:%[0-9]+]]:sgpr(s32) = G_AND [[COPY1]], [[C]]331 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16332 ; CHECK-NEXT: [[SHL:%[0-9]+]]:sgpr(s32) = G_SHL [[COPY2]], [[C1]](s32)333 ; CHECK-NEXT: [[OR:%[0-9]+]]:sgpr(s32) = G_OR [[AND]], [[SHL]]334 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)335 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32(s32) = COPY [[OR]](s32)336 ; CHECK-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64(s64) = S_BFE_U64 [[COPY3]](s64), [[COPY4]](s32), implicit-def $scc337 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_U64_]](s64)338 ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[COPY5]](s64)339 %0:_(s64) = COPY $sgpr0_sgpr1340 %1:_(s32) = COPY $sgpr2341 %2:_(s32) = COPY $sgpr3342 %3:_(s64) = G_UBFX %0, %1(s32), %2343 $sgpr0_sgpr1 = COPY %3(s64)344...345 346---347name: test_ubfx_s64_sii348legalized: true349 350body: |351 bb.0.entry:352 liveins: $sgpr0_sgpr1353 354 ; CHECK-LABEL: name: test_ubfx_s64_sii355 ; CHECK: liveins: $sgpr0_sgpr1356 ; CHECK-NEXT: {{ $}}357 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1358 ; CHECK-NEXT: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 1359 ; CHECK-NEXT: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 10360 ; CHECK-NEXT: [[C2:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 63361 ; CHECK-NEXT: [[C3:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 16362 ; CHECK-NEXT: [[C4:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655360363 ; CHECK-NEXT: [[C5:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 655361364 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_64(s64) = COPY [[COPY]](s64)365 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32(s32) = COPY [[C5]](s32)366 ; CHECK-NEXT: [[S_BFE_U64_:%[0-9]+]]:sreg_64(s64) = S_BFE_U64 [[COPY1]](s64), [[COPY2]](s32), implicit-def $scc367 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr(s64) = COPY [[S_BFE_U64_]](s64)368 ; CHECK-NEXT: $sgpr0_sgpr1 = COPY [[COPY3]](s64)369 %0:_(s64) = COPY $sgpr0_sgpr1370 %1:_(s32) = G_CONSTANT i32 1371 %2:_(s32) = G_CONSTANT i32 10372 %3:_(s64) = G_UBFX %0, %1(s32), %2373 $sgpr0_sgpr1 = COPY %3(s64)374...375