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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=hawaii -mattr=+flat-for-global -run-pass="amdgpu-regbankselect,amdgpu-regbanklegalize" %s -o - | FileCheck %s3 4--- |5 define amdgpu_kernel void @load_constant(ptr addrspace(4) %ptr0) {6 ret void7 }8 9 define amdgpu_kernel void @load_constant_volatile(ptr addrspace(4) %ptr0) {10 ret void11 }12 13 define amdgpu_kernel void @load_global_uniform_invariant(ptr addrspace(1) %ptr1) {14 %tmp0 = load i32, ptr addrspace(1) %ptr115 ret void16 }17 18 define amdgpu_kernel void @load_global_uniform_noclobber(ptr addrspace(1) %ptr1) {19 %tmp0 = load i32, ptr addrspace(1) %ptr1, !amdgpu.noclobber !020 ret void21 }22 23 define amdgpu_kernel void @load_global_uniform_variant(ptr addrspace(1) %ptr1) {24 %tmp0 = load i32, ptr addrspace(1) %ptr125 ret void26 }27 28 define amdgpu_kernel void @load_global_uniform_volatile_invariant(ptr addrspace(1) %ptr1) {29 %tmp0 = load i32, ptr addrspace(1) %ptr130 ret void31 }32 33 define amdgpu_kernel void @load_global_uniform_atomic_invariant(ptr addrspace(1) %ptr1) {34 %tmp0 = load i32, ptr addrspace(1) %ptr135 ret void36 }37 38 define amdgpu_kernel void @load_global_non_uniform(ptr addrspace(1) %ptr2) {39 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x() #040 %tmp1 = getelementptr i32, ptr addrspace(1) %ptr2, i32 %tmp041 %tmp2 = load i32, ptr addrspace(1) %tmp142 ret void43 }44 45 define amdgpu_kernel void @load_constant_v4i16_from_8_align8(ptr addrspace(4) %ptr0) {46 ret void47 }48 49 declare i32 @llvm.amdgcn.workitem.id.x() #050 attributes #0 = { nounwind readnone }51 !0 = !{}52 53...54---55name: load_constant56legalized: true57 58body: |59 bb.0:60 liveins: $sgpr0_sgpr161 ; CHECK-LABEL: name: load_constant62 ; CHECK: liveins: $sgpr0_sgpr163 ; CHECK-NEXT: {{ $}}64 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr165 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:sgpr(s32) = G_LOAD [[COPY]](p4) :: (load (s32) from %ir.ptr0, addrspace 4)66 %0:_(p4) = COPY $sgpr0_sgpr167 %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.ptr0)68...69 70---71name: load_constant_volatile72legalized: true73 74body: |75 bb.0:76 liveins: $sgpr0_sgpr177 ; CHECK-LABEL: name: load_constant_volatile78 ; CHECK: liveins: $sgpr0_sgpr179 ; CHECK-NEXT: {{ $}}80 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr181 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:sgpr(s32) = G_LOAD [[COPY]](p4) :: (volatile load (s32) from %ir.ptr0, addrspace 4)82 %0:_(p4) = COPY $sgpr0_sgpr183 %1:_(s32) = G_LOAD %0 :: (volatile load (s32) from %ir.ptr0)84...85 86---87name: load_global_uniform_invariant88legalized: true89 90body: |91 bb.0:92 liveins: $sgpr0_sgpr193 ; CHECK-LABEL: name: load_global_uniform_invariant94 ; CHECK: liveins: $sgpr0_sgpr195 ; CHECK-NEXT: {{ $}}96 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr197 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:sgpr(s32) = G_LOAD [[COPY]](p1) :: (invariant load (s32) from %ir.ptr1, addrspace 1)98 %0:_(p1) = COPY $sgpr0_sgpr199 %1:_(s32) = G_LOAD %0 :: (invariant load (s32) from %ir.ptr1)100...101 102---103name: load_global_uniform_noclobber104legalized: true105 106body: |107 bb.0:108 liveins: $sgpr0_sgpr1109 ; CHECK-LABEL: name: load_global_uniform_noclobber110 ; CHECK: liveins: $sgpr0_sgpr1111 ; CHECK-NEXT: {{ $}}112 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1113 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY]](p1) :: (load (s32) from %ir.ptr1, addrspace 1)114 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[LOAD]]115 %0:_(p1) = COPY $sgpr0_sgpr1116 %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.ptr1)117...118 119---120name: load_global_uniform_variant121legalized: true122 123body: |124 bb.0:125 liveins: $sgpr0_sgpr1126 ; CHECK-LABEL: name: load_global_uniform_variant127 ; CHECK: liveins: $sgpr0_sgpr1128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1130 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY]](p1) :: (load (s32) from %ir.ptr1, addrspace 1)131 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[LOAD]]132 %0:_(p1) = COPY $sgpr0_sgpr1133 %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.ptr1)134...135 136---137name: load_global_uniform_volatile_invariant138legalized: true139 140body: |141 bb.0:142 liveins: $sgpr0_sgpr1143 ; CHECK-LABEL: name: load_global_uniform_volatile_invariant144 ; CHECK: liveins: $sgpr0_sgpr1145 ; CHECK-NEXT: {{ $}}146 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1147 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY]](p1) :: (volatile invariant load (s32) from %ir.ptr1, addrspace 1)148 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[LOAD]]149 %0:_(p1) = COPY $sgpr0_sgpr1150 %1:_(s32) = G_LOAD %0 :: (volatile invariant load (s32) from %ir.ptr1)151...152 153---154name: load_global_uniform_atomic_invariant155legalized: true156 157body: |158 bb.0:159 liveins: $sgpr0_sgpr1160 ; CHECK-LABEL: name: load_global_uniform_atomic_invariant161 ; CHECK: liveins: $sgpr0_sgpr1162 ; CHECK-NEXT: {{ $}}163 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1164 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY]](p1) :: (invariant load acquire (s32) from %ir.ptr1, addrspace 1)165 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[LOAD]]166 %0:_(p1) = COPY $sgpr0_sgpr1167 %1:_(s32) = G_LOAD %0 :: (invariant load acquire (s32) from %ir.ptr1)168...169 170---171name: load_global_non_uniform172legalized: true173 174body: |175 bb.0:176 liveins: $sgpr0_sgpr1177 ; CHECK-LABEL: name: load_global_non_uniform178 ; CHECK: liveins: $sgpr0_sgpr1179 ; CHECK-NEXT: {{ $}}180 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr(p1) = COPY $sgpr0_sgpr1181 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:vgpr(s32) = G_LOAD [[COPY]](p1) :: (load (s32) from %ir.tmp1, addrspace 1)182 ; CHECK-NEXT: [[AMDGPU_READANYLANE:%[0-9]+]]:sgpr(s32) = G_AMDGPU_READANYLANE [[LOAD]]183 %0:_(p1) = COPY $sgpr0_sgpr1184 %1:_(s32) = G_LOAD %0 :: (load (s32) from %ir.tmp1)185...186 187---188name: load_constant_v4i16_from_8_align8189legalized: true190 191body: |192 bb.0:193 ; CHECK-LABEL: name: load_constant_v4i16_from_8_align8194 ; CHECK: [[COPY:%[0-9]+]]:sgpr(p4) = COPY $sgpr0_sgpr1195 ; CHECK-NEXT: [[LOAD:%[0-9]+]]:sgpr(<4 x s16>) = G_LOAD [[COPY]](p4) :: (load (<4 x s16>) from %ir.ptr0, addrspace 4)196 %0:_(p4) = COPY $sgpr0_sgpr1197 %1:_(<4 x s16>) = G_LOAD %0 :: (load (<4 x s16>) from %ir.ptr0, align 8, addrspace 4)198 199...200