132 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN %s5 6; Test vector signed bitfield extract.7define signext i8 @v_ashr_i8_i32(i32 %value) {8; GCN-LABEL: v_ashr_i8_i32:9; GCN: ; %bb.0:10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GCN-NEXT: v_bfe_i32 v0, v0, 4, 812; GCN-NEXT: s_setpc_b64 s[30:31]13 %1 = ashr i32 %value, 414 %2 = trunc i32 %1 to i815 ret i8 %216}17 18define signext i16 @v_ashr_i16_i32(i32 %value) {19; GCN-LABEL: v_ashr_i16_i32:20; GCN: ; %bb.0:21; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)22; GCN-NEXT: v_bfe_i32 v0, v0, 9, 1623; GCN-NEXT: s_setpc_b64 s[30:31]24 %1 = ashr i32 %value, 925 %2 = trunc i32 %1 to i1626 ret i16 %227}28 29define signext i8 @v_lshr_i8_i32(i32 %value) {30; GCN-LABEL: v_lshr_i8_i32:31; GCN: ; %bb.0:32; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GCN-NEXT: v_bfe_i32 v0, v0, 4, 834; GCN-NEXT: s_setpc_b64 s[30:31]35 %1 = lshr i32 %value, 436 %2 = trunc i32 %1 to i837 ret i8 %238}39 40define signext i16 @v_lshr_i16_i32(i32 %value) {41; GCN-LABEL: v_lshr_i16_i32:42; GCN: ; %bb.0:43; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; GCN-NEXT: v_bfe_i32 v0, v0, 9, 1645; GCN-NEXT: s_setpc_b64 s[30:31]46 %1 = lshr i32 %value, 947 %2 = trunc i32 %1 to i1648 ret i16 %249}50 51; Test vector bitfield extract for 64-bits.52define i64 @v_ashr_i64(i64 %value) {53; GCN-LABEL: v_ashr_i64:54; GCN: ; %bb.0:55; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]57; GCN-NEXT: v_bfe_i32 v0, v0, 0, 458; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v059; GCN-NEXT: s_setpc_b64 s[30:31]60 %1 = ashr i64 %value, 1061 %2 = shl i64 %1, 6062 %3 = ashr i64 %2, 6063 ret i64 %364}65 66define i64 @v_lshr_i64(i64 %value) {67; GCN-LABEL: v_lshr_i64:68; GCN: ; %bb.0:69; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GCN-NEXT: v_ashrrev_i64 v[0:1], 10, v[0:1]71; GCN-NEXT: v_bfe_i32 v0, v0, 0, 472; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v073; GCN-NEXT: s_setpc_b64 s[30:31]74 %1 = lshr i64 %value, 1075 %2 = shl i64 %1, 6076 %3 = ashr i64 %2, 6077 ret i64 %378}79 80; Test scalar signed bitfield extract.81define amdgpu_ps signext i8 @s_ashr_i8_i32(i32 inreg %value) {82; GCN-LABEL: s_ashr_i8_i32:83; GCN: ; %bb.0:84; GCN-NEXT: s_bfe_i32 s0, s0, 0x8000485; GCN-NEXT: ; return to shader part epilog86 %1 = ashr i32 %value, 487 %2 = trunc i32 %1 to i888 ret i8 %289}90 91define amdgpu_ps signext i16 @s_ashr_i16_i32(i32 inreg %value) {92; GCN-LABEL: s_ashr_i16_i32:93; GCN: ; %bb.0:94; GCN-NEXT: s_bfe_i32 s0, s0, 0x10000995; GCN-NEXT: ; return to shader part epilog96 %1 = ashr i32 %value, 997 %2 = trunc i32 %1 to i1698 ret i16 %299}100 101define amdgpu_ps signext i8 @s_lshr_i8_i32(i32 inreg %value) {102; GCN-LABEL: s_lshr_i8_i32:103; GCN: ; %bb.0:104; GCN-NEXT: s_bfe_i32 s0, s0, 0x80004105; GCN-NEXT: ; return to shader part epilog106 %1 = lshr i32 %value, 4107 %2 = trunc i32 %1 to i8108 ret i8 %2109}110 111define amdgpu_ps signext i16 @s_lshr_i16_i32(i32 inreg %value) {112; GCN-LABEL: s_lshr_i16_i32:113; GCN: ; %bb.0:114; GCN-NEXT: s_bfe_i32 s0, s0, 0x100009115; GCN-NEXT: ; return to shader part epilog116 %1 = lshr i32 %value, 9117 %2 = trunc i32 %1 to i16118 ret i16 %2119}120 121; Test scalar bitfield extract for 64-bits.122define amdgpu_ps i64 @s_ashr_i64(i64 inreg %value) {123; GCN-LABEL: s_ashr_i64:124; GCN: ; %bb.0:125; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x40001126; GCN-NEXT: ; return to shader part epilog127 %1 = ashr i64 %value, 1128 %2 = shl i64 %1, 60129 %3 = ashr i64 %2, 60130 ret i64 %3131}132