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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s4 5; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.6 7define i32 @v_sdiv_i32(i32 %num, i32 %den) {8; GISEL-LABEL: v_sdiv_i32:9; GISEL: ; %bb.0:10; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v012; GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v113; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v214; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v315; GISEL-NEXT: v_xor_b32_e32 v0, v0, v216; GISEL-NEXT: v_xor_b32_e32 v1, v1, v317; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v118; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v119; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v420; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v421; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v422; GISEL-NEXT: v_mul_lo_u32 v5, v5, v423; GISEL-NEXT: v_mul_hi_u32 v5, v4, v524; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v525; GISEL-NEXT: v_mul_hi_u32 v4, v0, v426; GISEL-NEXT: v_mul_lo_u32 v5, v4, v127; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v428; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v529; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v130; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc31; GISEL-NEXT: v_sub_i32_e64 v5, s[4:5], v0, v132; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc33; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v434; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v135; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc36; GISEL-NEXT: v_xor_b32_e32 v1, v2, v337; GISEL-NEXT: v_xor_b32_e32 v0, v0, v138; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v139; GISEL-NEXT: s_setpc_b64 s[30:31]40;41; CGP-LABEL: v_sdiv_i32:42; CGP: ; %bb.0:43; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)44; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v045; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v146; CGP-NEXT: v_xor_b32_e32 v4, v2, v347; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v248; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v349; CGP-NEXT: v_xor_b32_e32 v0, v0, v250; CGP-NEXT: v_xor_b32_e32 v1, v1, v351; CGP-NEXT: v_cvt_f32_u32_e32 v2, v152; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v153; CGP-NEXT: v_rcp_f32_e32 v2, v254; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v255; CGP-NEXT: v_cvt_u32_f32_e32 v2, v256; CGP-NEXT: v_mul_lo_u32 v3, v3, v257; CGP-NEXT: v_mul_hi_u32 v3, v2, v358; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v359; CGP-NEXT: v_mul_hi_u32 v2, v0, v260; CGP-NEXT: v_mul_lo_u32 v3, v2, v161; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v262; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v363; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v164; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc65; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v166; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc67; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v268; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v169; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc70; CGP-NEXT: v_xor_b32_e32 v0, v0, v471; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v472; CGP-NEXT: s_setpc_b64 s[30:31]73 %result = sdiv i32 %num, %den74 ret i32 %result75}76 77; FIXME: This is a workaround for not handling uniform VGPR case.78declare i32 @llvm.amdgcn.readfirstlane(i32)79 80define amdgpu_ps i32 @s_sdiv_i32(i32 inreg %num, i32 inreg %den) {81; GISEL-LABEL: s_sdiv_i32:82; GISEL: ; %bb.0:83; GISEL-NEXT: s_ashr_i32 s2, s0, 3184; GISEL-NEXT: s_ashr_i32 s3, s1, 3185; GISEL-NEXT: s_add_i32 s0, s0, s286; GISEL-NEXT: s_add_i32 s1, s1, s387; GISEL-NEXT: s_xor_b32 s0, s0, s288; GISEL-NEXT: s_xor_b32 s4, s1, s389; GISEL-NEXT: v_cvt_f32_u32_e32 v0, s490; GISEL-NEXT: s_sub_i32 s1, 0, s491; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v092; GISEL-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v093; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v094; GISEL-NEXT: v_mul_lo_u32 v1, s1, v095; GISEL-NEXT: v_mul_hi_u32 v1, v0, v196; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v197; GISEL-NEXT: v_mul_hi_u32 v0, s0, v098; GISEL-NEXT: v_mul_lo_u32 v1, v0, s499; GISEL-NEXT: v_add_i32_e32 v2, vcc, 1, v0100; GISEL-NEXT: v_sub_i32_e32 v1, vcc, s0, v1101; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1102; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc103; GISEL-NEXT: v_subrev_i32_e64 v2, s[0:1], s4, v1104; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc105; GISEL-NEXT: v_add_i32_e32 v2, vcc, 1, v0106; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s4, v1107; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc108; GISEL-NEXT: s_xor_b32 s0, s2, s3109; GISEL-NEXT: v_xor_b32_e32 v0, s0, v0110; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s0, v0111; GISEL-NEXT: v_readfirstlane_b32 s0, v0112; GISEL-NEXT: ; return to shader part epilog113;114; CGP-LABEL: s_sdiv_i32:115; CGP: ; %bb.0:116; CGP-NEXT: s_ashr_i32 s2, s0, 31117; CGP-NEXT: s_ashr_i32 s3, s1, 31118; CGP-NEXT: s_xor_b32 s4, s2, s3119; CGP-NEXT: s_add_i32 s0, s0, s2120; CGP-NEXT: s_add_i32 s1, s1, s3121; CGP-NEXT: s_xor_b32 s0, s0, s2122; CGP-NEXT: s_xor_b32 s2, s1, s3123; CGP-NEXT: v_cvt_f32_u32_e32 v0, s2124; CGP-NEXT: s_sub_i32 s1, 0, s2125; CGP-NEXT: v_rcp_f32_e32 v0, v0126; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0127; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0128; CGP-NEXT: v_mul_lo_u32 v1, s1, v0129; CGP-NEXT: v_mul_hi_u32 v1, v0, v1130; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1131; CGP-NEXT: v_mul_hi_u32 v0, s0, v0132; CGP-NEXT: v_mul_lo_u32 v1, v0, s2133; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0134; CGP-NEXT: v_sub_i32_e32 v1, vcc, s0, v1135; CGP-NEXT: v_cmp_le_u32_e32 vcc, s2, v1136; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc137; CGP-NEXT: v_subrev_i32_e64 v2, s[0:1], s2, v1138; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc139; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0140; CGP-NEXT: v_cmp_le_u32_e32 vcc, s2, v1141; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc142; CGP-NEXT: v_xor_b32_e32 v0, s4, v0143; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s4, v0144; CGP-NEXT: v_readfirstlane_b32 s0, v0145; CGP-NEXT: ; return to shader part epilog146 %result = sdiv i32 %num, %den147 %readlane = call i32 @llvm.amdgcn.readfirstlane(i32 %result)148 ret i32 %readlane149}150 151define <2 x i32> @v_sdiv_v2i32(<2 x i32> %num, <2 x i32> %den) {152; GISEL-LABEL: v_sdiv_v2i32:153; GISEL: ; %bb.0:154; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0156; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2157; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1158; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3159; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4160; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5161; GISEL-NEXT: v_xor_b32_e32 v8, v4, v5162; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6163; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7164; GISEL-NEXT: v_xor_b32_e32 v9, v6, v7165; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4166; GISEL-NEXT: v_xor_b32_e32 v2, v2, v5167; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6168; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7169; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2170; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2171; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3172; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3173; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4174; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6175; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4176; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6177; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4178; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6179; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4180; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6181; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5182; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7183; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5184; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7185; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4186; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5187; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2188; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4189; GISEL-NEXT: v_mul_lo_u32 v10, v5, v3190; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v5191; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6192; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v10193; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2194; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc195; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2196; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3197; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5]198; GISEL-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3199; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc200; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4201; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]202; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5203; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2204; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc205; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3206; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc207; GISEL-NEXT: v_xor_b32_e32 v0, v0, v8208; GISEL-NEXT: v_xor_b32_e32 v1, v1, v9209; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8210; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v9211; GISEL-NEXT: s_setpc_b64 s[30:31]212;213; CGP-LABEL: v_sdiv_v2i32:214; CGP: ; %bb.0:215; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)216; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0217; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v2218; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1219; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3220; CGP-NEXT: v_xor_b32_e32 v8, v4, v5221; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4222; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5223; CGP-NEXT: v_xor_b32_e32 v9, v6, v7224; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6225; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7226; CGP-NEXT: v_xor_b32_e32 v0, v0, v4227; CGP-NEXT: v_xor_b32_e32 v2, v2, v5228; CGP-NEXT: v_xor_b32_e32 v1, v1, v6229; CGP-NEXT: v_xor_b32_e32 v3, v3, v7230; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2231; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2232; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3233; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3234; CGP-NEXT: v_rcp_f32_e32 v4, v4235; CGP-NEXT: v_rcp_f32_e32 v6, v6236; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4237; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6238; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4239; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6240; CGP-NEXT: v_mul_lo_u32 v5, v5, v4241; CGP-NEXT: v_mul_lo_u32 v7, v7, v6242; CGP-NEXT: v_mul_hi_u32 v5, v4, v5243; CGP-NEXT: v_mul_hi_u32 v7, v6, v7244; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5245; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7246; CGP-NEXT: v_mul_hi_u32 v4, v0, v4247; CGP-NEXT: v_mul_hi_u32 v5, v1, v5248; CGP-NEXT: v_mul_lo_u32 v6, v4, v2249; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4250; CGP-NEXT: v_mul_lo_u32 v10, v5, v3251; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v5252; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6253; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v10254; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2255; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc256; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2257; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3258; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v11, s[4:5]259; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3260; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc261; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4262; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]263; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5264; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2265; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc266; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3267; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc268; CGP-NEXT: v_xor_b32_e32 v0, v0, v8269; CGP-NEXT: v_xor_b32_e32 v1, v1, v9270; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v8271; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v9272; CGP-NEXT: s_setpc_b64 s[30:31]273 %result = sdiv <2 x i32> %num, %den274 ret <2 x i32> %result275}276 277define i32 @v_sdiv_i32_pow2k_denom(i32 %num) {278; CHECK-LABEL: v_sdiv_i32_pow2k_denom:279; CHECK: ; %bb.0:280; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)281; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v0282; CHECK-NEXT: v_lshrrev_b32_e32 v1, 20, v1283; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1284; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0285; CHECK-NEXT: s_setpc_b64 s[30:31]286 %result = sdiv i32 %num, 4096287 ret i32 %result288}289 290define <2 x i32> @v_sdiv_v2i32_pow2k_denom(<2 x i32> %num) {291; CHECK-LABEL: v_sdiv_v2i32_pow2k_denom:292; CHECK: ; %bb.0:293; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)294; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v0295; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1296; CHECK-NEXT: v_lshrrev_b32_e32 v2, 20, v2297; CHECK-NEXT: v_lshrrev_b32_e32 v3, 20, v3298; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2299; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3300; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0301; CHECK-NEXT: v_ashrrev_i32_e32 v1, 12, v1302; CHECK-NEXT: s_setpc_b64 s[30:31]303 %result = sdiv <2 x i32> %num, <i32 4096, i32 4096>304 ret <2 x i32> %result305}306 307define i32 @v_sdiv_i32_oddk_denom(i32 %num) {308; CHECK-LABEL: v_sdiv_i32_oddk_denom:309; CHECK: ; %bb.0:310; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)311; CHECK-NEXT: v_mov_b32_e32 v1, 0xd9528441312; CHECK-NEXT: v_mul_hi_i32 v1, v0, v1313; CHECK-NEXT: v_add_i32_e32 v0, vcc, v1, v0314; CHECK-NEXT: v_ashrrev_i32_e32 v0, 20, v0315; CHECK-NEXT: v_lshrrev_b32_e32 v1, 31, v0316; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1317; CHECK-NEXT: s_setpc_b64 s[30:31]318 %result = sdiv i32 %num, 1235195319 ret i32 %result320}321 322define <2 x i32> @v_sdiv_v2i32_oddk_denom(<2 x i32> %num) {323; GISEL-LABEL: v_sdiv_v2i32_oddk_denom:324; GISEL: ; %bb.0:325; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)326; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0327; GISEL-NEXT: v_mov_b32_e32 v3, 0x12d8fb328; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb329; GISEL-NEXT: v_mov_b32_e32 v5, 0xffed2705330; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1331; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2332; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4333; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6334; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2335; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4336; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6337; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4338; GISEL-NEXT: v_mul_lo_u32 v7, v4, v5339; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7340; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7341; GISEL-NEXT: v_mul_hi_u32 v7, v0, v4342; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4343; GISEL-NEXT: v_mul_lo_u32 v8, v7, v3344; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v7345; GISEL-NEXT: v_mul_lo_u32 v10, v4, v3346; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v4347; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8348; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v10349; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v3350; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]351; GISEL-NEXT: v_add_i32_e32 v5, vcc, v0, v5352; GISEL-NEXT: v_cmp_ge_u32_e64 s[6:7], v1, v3353; GISEL-NEXT: v_cndmask_b32_e64 v4, v4, v11, s[6:7]354; GISEL-NEXT: v_add_i32_e32 v8, vcc, 0xffed2705, v1355; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v5, s[4:5]356; GISEL-NEXT: v_add_i32_e32 v5, vcc, 1, v7357; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v8, s[6:7]358; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v4359; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3360; GISEL-NEXT: v_cndmask_b32_e32 v0, v7, v5, vcc361; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3362; GISEL-NEXT: v_cndmask_b32_e32 v1, v4, v8, vcc363; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2364; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6365; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2366; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6367; GISEL-NEXT: s_setpc_b64 s[30:31]368;369; CGP-LABEL: v_sdiv_v2i32_oddk_denom:370; CGP: ; %bb.0:371; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)372; CGP-NEXT: v_mov_b32_e32 v2, 0xd9528441373; CGP-NEXT: v_mul_hi_i32 v3, v0, v2374; CGP-NEXT: v_mul_hi_i32 v2, v1, v2375; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0376; CGP-NEXT: v_add_i32_e32 v1, vcc, v2, v1377; CGP-NEXT: v_ashrrev_i32_e32 v0, 20, v0378; CGP-NEXT: v_ashrrev_i32_e32 v1, 20, v1379; CGP-NEXT: v_lshrrev_b32_e32 v2, 31, v0380; CGP-NEXT: v_lshrrev_b32_e32 v3, 31, v1381; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v2382; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3383; CGP-NEXT: s_setpc_b64 s[30:31]384 %result = sdiv <2 x i32> %num, <i32 1235195, i32 1235195>385 ret <2 x i32> %result386}387 388define i32 @v_sdiv_i32_pow2_shl_denom(i32 %x, i32 %y) {389; CHECK-LABEL: v_sdiv_i32_pow2_shl_denom:390; CHECK: ; %bb.0:391; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)392; CHECK-NEXT: v_lshl_b32_e32 v1, 0x1000, v1393; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v0394; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1395; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2396; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3397; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2398; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3399; CHECK-NEXT: v_cvt_f32_u32_e32 v4, v1400; CHECK-NEXT: v_sub_i32_e32 v5, vcc, 0, v1401; CHECK-NEXT: v_rcp_iflag_f32_e32 v4, v4402; CHECK-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4403; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4404; CHECK-NEXT: v_mul_lo_u32 v5, v5, v4405; CHECK-NEXT: v_mul_hi_u32 v5, v4, v5406; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v5407; CHECK-NEXT: v_mul_hi_u32 v4, v0, v4408; CHECK-NEXT: v_mul_lo_u32 v5, v4, v1409; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v4410; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5411; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1412; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc413; CHECK-NEXT: v_sub_i32_e64 v5, s[4:5], v0, v1414; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc415; CHECK-NEXT: v_add_i32_e32 v5, vcc, 1, v4416; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1417; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc418; CHECK-NEXT: v_xor_b32_e32 v1, v2, v3419; CHECK-NEXT: v_xor_b32_e32 v0, v0, v1420; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1421; CHECK-NEXT: s_setpc_b64 s[30:31]422 %shl.y = shl i32 4096, %y423 %r = sdiv i32 %x, %shl.y424 ret i32 %r425}426 427define <2 x i32> @v_sdiv_v2i32_pow2_shl_denom(<2 x i32> %x, <2 x i32> %y) {428; GISEL-LABEL: v_sdiv_v2i32_pow2_shl_denom:429; GISEL: ; %bb.0:430; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)431; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2432; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3433; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0434; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v1435; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v2436; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4437; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3438; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5439; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6440; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4441; GISEL-NEXT: v_xor_b32_e32 v4, v4, v6442; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7443; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5444; GISEL-NEXT: v_xor_b32_e32 v5, v5, v7445; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6446; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7447; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v2448; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v2449; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v3450; GISEL-NEXT: v_sub_i32_e32 v9, vcc, 0, v3451; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6452; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8453; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6454; GISEL-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8455; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6456; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8457; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6458; GISEL-NEXT: v_mul_lo_u32 v9, v9, v8459; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7460; GISEL-NEXT: v_mul_hi_u32 v9, v8, v9461; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7462; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v9463; GISEL-NEXT: v_mul_hi_u32 v6, v0, v6464; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7465; GISEL-NEXT: v_mul_lo_u32 v8, v6, v2466; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v6467; GISEL-NEXT: v_mul_lo_u32 v10, v7, v3468; GISEL-NEXT: v_add_i32_e32 v11, vcc, 1, v7469; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v8470; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v10471; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2472; GISEL-NEXT: v_cndmask_b32_e32 v6, v6, v9, vcc473; GISEL-NEXT: v_sub_i32_e64 v8, s[4:5], v0, v2474; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3475; GISEL-NEXT: v_cndmask_b32_e64 v7, v7, v11, s[4:5]476; GISEL-NEXT: v_sub_i32_e64 v9, s[6:7], v1, v3477; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v8, vcc478; GISEL-NEXT: v_add_i32_e32 v8, vcc, 1, v6479; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[4:5]480; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v7481; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2482; GISEL-NEXT: v_cndmask_b32_e32 v0, v6, v8, vcc483; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3484; GISEL-NEXT: v_cndmask_b32_e32 v1, v7, v9, vcc485; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4486; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5487; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4488; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5489; GISEL-NEXT: s_setpc_b64 s[30:31]490;491; CGP-LABEL: v_sdiv_v2i32_pow2_shl_denom:492; CGP: ; %bb.0:493; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)494; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2495; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3496; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0497; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1498; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v2499; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4500; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3501; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5502; CGP-NEXT: v_xor_b32_e32 v8, v4, v6503; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6504; CGP-NEXT: v_xor_b32_e32 v0, v0, v4505; CGP-NEXT: v_xor_b32_e32 v4, v5, v7506; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7507; CGP-NEXT: v_xor_b32_e32 v1, v1, v5508; CGP-NEXT: v_xor_b32_e32 v2, v2, v6509; CGP-NEXT: v_xor_b32_e32 v3, v3, v7510; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2511; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v2512; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3513; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3514; CGP-NEXT: v_rcp_f32_e32 v5, v5515; CGP-NEXT: v_rcp_f32_e32 v7, v7516; CGP-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5517; CGP-NEXT: v_mul_f32_e32 v7, 0x4f7ffffe, v7518; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5519; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7520; CGP-NEXT: v_mul_lo_u32 v6, v6, v5521; CGP-NEXT: v_mul_lo_u32 v9, v9, v7522; CGP-NEXT: v_mul_hi_u32 v6, v5, v6523; CGP-NEXT: v_mul_hi_u32 v9, v7, v9524; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v6525; CGP-NEXT: v_add_i32_e32 v6, vcc, v7, v9526; CGP-NEXT: v_mul_hi_u32 v5, v0, v5527; CGP-NEXT: v_mul_hi_u32 v6, v1, v6528; CGP-NEXT: v_mul_lo_u32 v7, v5, v2529; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5530; CGP-NEXT: v_mul_lo_u32 v10, v6, v3531; CGP-NEXT: v_add_i32_e32 v11, vcc, 1, v6532; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v7533; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v10534; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2535; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc536; CGP-NEXT: v_sub_i32_e64 v7, s[4:5], v0, v2537; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3538; CGP-NEXT: v_cndmask_b32_e64 v6, v6, v11, s[4:5]539; CGP-NEXT: v_sub_i32_e64 v9, s[6:7], v1, v3540; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v7, vcc541; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5542; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v9, s[4:5]543; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v6544; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2545; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc546; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3547; CGP-NEXT: v_cndmask_b32_e32 v1, v6, v9, vcc548; CGP-NEXT: v_xor_b32_e32 v0, v0, v8549; CGP-NEXT: v_xor_b32_e32 v1, v1, v4550; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v8551; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v4552; CGP-NEXT: s_setpc_b64 s[30:31]553 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y554 %r = sdiv <2 x i32> %x, %shl.y555 ret <2 x i32> %r556}557 558define i32 @v_sdiv_i32_24bit(i32 %num, i32 %den) {559; GISEL-LABEL: v_sdiv_i32_24bit:560; GISEL: ; %bb.0:561; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)562; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0563; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1564; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1565; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1566; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2567; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2568; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2569; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2570; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3571; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3572; GISEL-NEXT: v_mul_hi_u32 v2, v0, v2573; GISEL-NEXT: v_mul_lo_u32 v3, v2, v1574; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v2575; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3576; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1577; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc578; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1579; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc580; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v2581; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1582; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc583; GISEL-NEXT: s_setpc_b64 s[30:31]584;585; CGP-LABEL: v_sdiv_i32_24bit:586; CGP: ; %bb.0:587; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)588; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0589; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1590; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1591; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1592; CGP-NEXT: v_rcp_f32_e32 v2, v2593; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2594; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2595; CGP-NEXT: v_mul_lo_u32 v3, v3, v2596; CGP-NEXT: v_mul_hi_u32 v3, v2, v3597; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3598; CGP-NEXT: v_mul_hi_u32 v2, v0, v2599; CGP-NEXT: v_mul_lo_u32 v3, v2, v1600; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2601; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3602; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1603; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc604; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1605; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc606; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2607; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1608; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc609; CGP-NEXT: s_setpc_b64 s[30:31]610 %num.mask = and i32 %num, 16777215611 %den.mask = and i32 %den, 16777215612 %result = sdiv i32 %num.mask, %den.mask613 ret i32 %result614}615 616define <2 x i32> @v_sdiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {617; GISEL-LABEL: v_sdiv_v2i32_24bit:618; GISEL: ; %bb.0:619; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)620; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0621; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1622; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2623; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3624; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2625; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2626; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3627; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3628; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4629; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6630; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4631; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6632; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4633; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6634; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4635; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6636; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5637; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7638; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5639; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7640; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4641; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5642; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2643; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4644; GISEL-NEXT: v_mul_lo_u32 v8, v5, v3645; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v5646; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6647; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8648; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2649; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc650; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2651; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3652; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]653; GISEL-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3654; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc655; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4656; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]657; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5658; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2659; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc660; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3661; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc662; GISEL-NEXT: s_setpc_b64 s[30:31]663;664; CGP-LABEL: v_sdiv_v2i32_24bit:665; CGP: ; %bb.0:666; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0668; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1669; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2670; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3671; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2672; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2673; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3674; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3675; CGP-NEXT: v_rcp_f32_e32 v4, v4676; CGP-NEXT: v_rcp_f32_e32 v6, v6677; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4678; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6679; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4680; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6681; CGP-NEXT: v_mul_lo_u32 v5, v5, v4682; CGP-NEXT: v_mul_lo_u32 v7, v7, v6683; CGP-NEXT: v_mul_hi_u32 v5, v4, v5684; CGP-NEXT: v_mul_hi_u32 v7, v6, v7685; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5686; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7687; CGP-NEXT: v_mul_hi_u32 v4, v0, v4688; CGP-NEXT: v_mul_hi_u32 v5, v1, v5689; CGP-NEXT: v_mul_lo_u32 v6, v4, v2690; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4691; CGP-NEXT: v_mul_lo_u32 v8, v5, v3692; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5693; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6694; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8695; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2696; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc697; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2698; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3699; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]700; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3701; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc702; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4703; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]704; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5705; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2706; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc707; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3708; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc709; CGP-NEXT: s_setpc_b64 s[30:31]710 %num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>711 %den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>712 %result = sdiv <2 x i32> %num.mask, %den.mask713 ret <2 x i32> %result714}715 716define i32 @v_sdiv_i32_exact(i32 %num) {717; CHECK-LABEL: v_sdiv_i32_exact:718; CHECK: ; %bb.0:719; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)720; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0721; CHECK-NEXT: s_setpc_b64 s[30:31]722 %result = sdiv exact i32 %num, 4096723 ret i32 %result724}725 726define <2 x i32> @v_sdiv_v2i32_exact(<2 x i32> %num) {727; CHECK-LABEL: v_sdiv_v2i32_exact:728; CHECK: ; %bb.0:729; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)730; CHECK-NEXT: v_ashrrev_i32_e32 v0, 12, v0731; CHECK-NEXT: v_ashrrev_i32_e32 v1, 10, v1732; CHECK-NEXT: s_setpc_b64 s[30:31]733 %result = sdiv exact <2 x i32> %num, <i32 4096, i32 1024>734 ret <2 x i32> %result735}736