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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5 6define amdgpu_kernel void @sdivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %x, i32 %y) {7; GFX8-LABEL: sdivrem_i32:8; GFX8:       ; %bb.0:9; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x1010; GFX8-NEXT:    s_add_i32 s12, s12, s1711; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s1312; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 813; GFX8-NEXT:    s_waitcnt lgkmcnt(0)14; GFX8-NEXT:    s_ashr_i32 s6, s5, 3115; GFX8-NEXT:    s_add_i32 s0, s5, s616; GFX8-NEXT:    s_xor_b32 s5, s0, s617; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s518; GFX8-NEXT:    s_sub_i32 s0, 0, s519; GFX8-NEXT:    s_ashr_i32 s7, s4, 3120; GFX8-NEXT:    s_add_i32 s4, s4, s721; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v022; GFX8-NEXT:    s_xor_b32 s4, s4, s723; GFX8-NEXT:    s_xor_b32 s6, s7, s624; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v025; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v026; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v027; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x028; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v129; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v130; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v031; GFX8-NEXT:    s_waitcnt lgkmcnt(0)32; GFX8-NEXT:    v_mov_b32_e32 v0, s033; GFX8-NEXT:    v_mov_b32_e32 v1, s134; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s535; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v236; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v337; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v338; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc39; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v340; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc41; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v242; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v343; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc44; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v345; GFX8-NEXT:    v_xor_b32_e32 v2, s6, v246; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc47; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s6, v248; GFX8-NEXT:    v_xor_b32_e32 v3, s7, v349; GFX8-NEXT:    flat_store_dword v[0:1], v250; GFX8-NEXT:    v_mov_b32_e32 v0, s251; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s7, v352; GFX8-NEXT:    v_mov_b32_e32 v1, s353; GFX8-NEXT:    flat_store_dword v[0:1], v354; GFX8-NEXT:    s_endpgm55;56; GFX9-LABEL: sdivrem_i32:57; GFX9:       ; %bb.0:58; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x1059; GFX9-NEXT:    v_mov_b32_e32 v2, 060; GFX9-NEXT:    s_waitcnt lgkmcnt(0)61; GFX9-NEXT:    s_ashr_i32 s4, s1, 3162; GFX9-NEXT:    s_add_i32 s1, s1, s463; GFX9-NEXT:    s_xor_b32 s5, s1, s464; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s565; GFX9-NEXT:    s_sub_i32 s1, 0, s566; GFX9-NEXT:    s_ashr_i32 s6, s0, 3167; GFX9-NEXT:    s_add_i32 s0, s0, s668; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v069; GFX9-NEXT:    s_xor_b32 s7, s0, s670; GFX9-NEXT:    s_xor_b32 s4, s6, s471; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v072; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v073; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v074; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x075; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v176; GFX9-NEXT:    v_add_u32_e32 v0, v0, v177; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v078; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s579; GFX9-NEXT:    v_add_u32_e32 v3, 1, v080; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v181; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v182; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc83; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v184; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc85; GFX9-NEXT:    v_add_u32_e32 v3, 1, v086; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v187; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc88; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v189; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc90; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v091; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v092; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v193; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v194; GFX9-NEXT:    s_waitcnt lgkmcnt(0)95; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]96; GFX9-NEXT:    global_store_dword v2, v1, s[2:3]97; GFX9-NEXT:    s_endpgm98;99; GFX10-LABEL: sdivrem_i32:100; GFX10:       ; %bb.0:101; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x10102; GFX10-NEXT:    s_waitcnt lgkmcnt(0)103; GFX10-NEXT:    s_ashr_i32 s4, s1, 31104; GFX10-NEXT:    s_ashr_i32 s6, s0, 31105; GFX10-NEXT:    s_add_i32 s1, s1, s4106; GFX10-NEXT:    s_add_i32 s0, s0, s6107; GFX10-NEXT:    s_xor_b32 s5, s1, s4108; GFX10-NEXT:    s_xor_b32 s0, s0, s6109; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s5110; GFX10-NEXT:    s_sub_i32 s1, 0, s5111; GFX10-NEXT:    s_xor_b32 s4, s6, s4112; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0113; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0114; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0115; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v0116; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v1117; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v1118; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0119; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s5120; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0121; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v1122; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x0123; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v1124; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v1125; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo126; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo127; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v0128; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v1129; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v1130; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo131; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo132; GFX10-NEXT:    v_mov_b32_e32 v2, 0133; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v0134; GFX10-NEXT:    v_xor_b32_e32 v1, s6, v1135; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v0136; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s6, v1137; GFX10-NEXT:    s_waitcnt lgkmcnt(0)138; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]139; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]140; GFX10-NEXT:    s_endpgm141  %div = sdiv i32 %x, %y142  store i32 %div, ptr addrspace(1) %out0143  %rem = srem i32 %x, %y144  store i32 %rem, ptr addrspace(1) %out1145  ret void146}147 148define amdgpu_kernel void @sdivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i64 %x, i64 %y) {149; GFX8-LABEL: sdivrem_i64:150; GFX8:       ; %bb.0:151; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[8:9], 0x0152; GFX8-NEXT:    s_add_i32 s12, s12, s17153; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8154; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13155; GFX8-NEXT:    s_waitcnt lgkmcnt(0)156; GFX8-NEXT:    s_ashr_i32 s2, s9, 31157; GFX8-NEXT:    s_ashr_i32 s12, s11, 31158; GFX8-NEXT:    s_add_u32 s0, s8, s2159; GFX8-NEXT:    s_addc_u32 s1, s9, s2160; GFX8-NEXT:    s_add_u32 s8, s10, s12161; GFX8-NEXT:    s_mov_b32 s13, s12162; GFX8-NEXT:    s_addc_u32 s9, s11, s12163; GFX8-NEXT:    s_xor_b64 s[8:9], s[8:9], s[12:13]164; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s9165; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s8166; GFX8-NEXT:    s_mov_b32 s3, s2167; GFX8-NEXT:    s_xor_b64 s[10:11], s[0:1], s[2:3]168; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0169; GFX8-NEXT:    v_add_f32_e32 v0, v0, v1170; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0171; GFX8-NEXT:    s_sub_u32 s14, 0, s8172; GFX8-NEXT:    s_subb_u32 s15, 0, s9173; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0174; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0175; GFX8-NEXT:    v_trunc_f32_e32 v1, v1176; GFX8-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v1177; GFX8-NEXT:    v_add_f32_e32 v0, v2, v0178; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v0179; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v1180; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v6, 0181; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s14, v7, v[1:2]182; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v0183; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s15, v6, v[2:3]184; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v0185; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v0186; GFX8-NEXT:    v_mul_lo_u32 v3, v6, v4187; GFX8-NEXT:    v_mul_lo_u32 v5, v7, v4188; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v4189; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3190; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc191; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v5, v0192; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc193; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2194; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc195; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1196; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v8197; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc198; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2199; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v4200; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1201; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc202; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1203; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1204; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v0205; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc206; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s14, v6, 0207; GFX8-NEXT:    v_mov_b32_e32 v8, s11208; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s14, v7, v[1:2]209; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v0210; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s15, v6, v[2:3]211; GFX8-NEXT:    v_mul_hi_u32 v3, v6, v0212; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v0213; GFX8-NEXT:    v_mul_lo_u32 v2, v6, v4214; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2215; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc216; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3217; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc218; GFX8-NEXT:    v_mul_lo_u32 v3, v7, v4219; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1220; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v4221; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0222; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc223; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2224; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc225; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2226; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v4227; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1228; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc229; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1230; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1231; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v0232; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc233; GFX8-NEXT:    v_mul_lo_u32 v2, s11, v0234; GFX8-NEXT:    v_mul_lo_u32 v3, s10, v1235; GFX8-NEXT:    v_mul_hi_u32 v4, s10, v0236; GFX8-NEXT:    v_mul_hi_u32 v0, s11, v0237; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v3238; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc239; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4240; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc241; GFX8-NEXT:    v_mul_lo_u32 v4, s11, v1242; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2243; GFX8-NEXT:    v_mul_hi_u32 v3, s10, v1244; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v0245; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc246; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v3247; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc248; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3249; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v0, v2250; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc251; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v0252; GFX8-NEXT:    v_mul_hi_u32 v3, s11, v1253; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s8, v6, 0254; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v3, v2255; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s8, v7, v[1:2]256; GFX8-NEXT:    v_sub_u32_e32 v0, vcc, s10, v0257; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s9, v6, v[2:3]258; GFX8-NEXT:    v_mov_b32_e32 v1, s9259; GFX8-NEXT:    v_subb_u32_e64 v2, s[0:1], v8, v4, vcc260; GFX8-NEXT:    v_sub_u32_e64 v3, s[0:1], s11, v4261; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v2262; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]263; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v0264; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s[0:1]265; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v2266; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v3, v1, vcc267; GFX8-NEXT:    v_cndmask_b32_e64 v4, v4, v5, s[0:1]268; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s8, v0269; GFX8-NEXT:    v_subbrev_u32_e64 v8, s[0:1], 0, v3, vcc270; GFX8-NEXT:    v_add_u32_e64 v9, s[0:1], 1, v6271; GFX8-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v7, s[0:1]272; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v8273; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]274; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v5275; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v3, v1, vcc276; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]277; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v8278; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s8, v5279; GFX8-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]280; GFX8-NEXT:    v_add_u32_e64 v12, s[0:1], 1, v9281; GFX8-NEXT:    v_subbrev_u32_e32 v1, vcc, 0, v1, vcc282; GFX8-NEXT:    v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]283; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11284; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v12, vcc285; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc286; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v4287; GFX8-NEXT:    v_cndmask_b32_e32 v3, v5, v3, vcc288; GFX8-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc289; GFX8-NEXT:    v_cndmask_b32_e64 v4, v6, v9, s[0:1]290; GFX8-NEXT:    v_cndmask_b32_e64 v6, v7, v10, s[0:1]291; GFX8-NEXT:    v_cndmask_b32_e64 v3, v0, v3, s[0:1]292; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v1, s[0:1]293; GFX8-NEXT:    s_xor_b64 s[0:1], s[2:3], s[12:13]294; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v4295; GFX8-NEXT:    v_xor_b32_e32 v1, s1, v6296; GFX8-NEXT:    v_mov_b32_e32 v4, s1297; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0298; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v4, vcc299; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v3300; GFX8-NEXT:    v_xor_b32_e32 v4, s2, v2301; GFX8-NEXT:    v_mov_b32_e32 v5, s2302; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s2, v3303; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v4, v5, vcc304; GFX8-NEXT:    v_mov_b32_e32 v4, s4305; GFX8-NEXT:    v_mov_b32_e32 v5, s5306; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]307; GFX8-NEXT:    v_mov_b32_e32 v0, s6308; GFX8-NEXT:    v_mov_b32_e32 v1, s7309; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]310; GFX8-NEXT:    s_endpgm311;312; GFX9-LABEL: sdivrem_i64:313; GFX9:       ; %bb.0:314; GFX9-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0315; GFX9-NEXT:    v_mov_b32_e32 v9, 0316; GFX9-NEXT:    s_waitcnt lgkmcnt(0)317; GFX9-NEXT:    s_ashr_i32 s2, s17, 31318; GFX9-NEXT:    s_ashr_i32 s4, s19, 31319; GFX9-NEXT:    s_add_u32 s0, s16, s2320; GFX9-NEXT:    s_addc_u32 s1, s17, s2321; GFX9-NEXT:    s_add_u32 s6, s18, s4322; GFX9-NEXT:    s_mov_b32 s5, s4323; GFX9-NEXT:    s_addc_u32 s7, s19, s4324; GFX9-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]325; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s7326; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s6327; GFX9-NEXT:    s_mov_b32 s3, s2328; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[2:3]329; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0330; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1331; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0332; GFX9-NEXT:    s_sub_u32 s10, 0, s6333; GFX9-NEXT:    s_subb_u32 s11, 0, s7334; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0335; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0336; GFX9-NEXT:    v_trunc_f32_e32 v1, v1337; GFX9-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v1338; GFX9-NEXT:    v_add_f32_e32 v0, v2, v0339; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v0340; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v1341; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s10, v6, 0342; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s10, v7, v[1:2]343; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v0344; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s11, v6, v[2:3]345; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v0346; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v0347; GFX9-NEXT:    v_mul_lo_u32 v3, v6, v4348; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v4349; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v4350; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v3351; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc352; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v5, v0353; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc354; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v2355; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc356; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1357; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v4358; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v8359; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc360; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1361; GFX9-NEXT:    v_add_u32_e32 v2, v5, v2362; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc363; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v3364; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0365; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v1, vcc366; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s10, v6, 0367; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s10, v7, v[1:2]368; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v0369; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s11, v6, v[2:3]370; GFX9-NEXT:    v_mul_hi_u32 v3, v6, v0371; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v0372; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v4373; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v2374; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc375; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v3376; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc377; GFX9-NEXT:    v_mul_lo_u32 v3, v7, v4378; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1379; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v4380; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0381; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc382; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2383; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc384; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2385; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v4386; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1387; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc388; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v3389; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v0390; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v1, vcc391; GFX9-NEXT:    v_mul_lo_u32 v2, s9, v0392; GFX9-NEXT:    v_mul_lo_u32 v3, s8, v1393; GFX9-NEXT:    v_mul_hi_u32 v4, s8, v0394; GFX9-NEXT:    v_mul_hi_u32 v0, s9, v0395; GFX9-NEXT:    v_mul_hi_u32 v5, s9, v1396; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3397; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc398; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4399; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc400; GFX9-NEXT:    v_mul_lo_u32 v4, s9, v1401; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2402; GFX9-NEXT:    v_mul_hi_u32 v3, s8, v1403; GFX9-NEXT:    v_mov_b32_e32 v6, s7404; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0405; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc406; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3407; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc408; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v0, v2409; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s6, v7, 0410; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc411; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3412; GFX9-NEXT:    v_add3_u32 v8, v3, v2, v5413; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s6, v8, v[1:2]414; GFX9-NEXT:    v_mov_b32_e32 v1, s9415; GFX9-NEXT:    v_sub_co_u32_e32 v0, vcc, s8, v0416; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s7, v7, v[2:3]417; GFX9-NEXT:    v_subb_co_u32_e64 v1, s[0:1], v1, v4, vcc418; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v1419; GFX9-NEXT:    v_sub_u32_e32 v2, s9, v4420; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]421; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v0422; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]423; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v1424; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v6, vcc425; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]426; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s6, v0427; GFX9-NEXT:    v_subbrev_co_u32_e64 v5, s[0:1], 0, v2, vcc428; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], 1, v7429; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], 0, v8, s[0:1]430; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v5431; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]432; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v4433; GFX9-NEXT:    v_subb_co_u32_e32 v2, vcc, v2, v6, vcc434; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]435; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v5436; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s6, v4437; GFX9-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[0:1]438; GFX9-NEXT:    v_add_co_u32_e64 v13, s[0:1], 1, v10439; GFX9-NEXT:    v_subbrev_co_u32_e32 v2, vcc, 0, v2, vcc440; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1]441; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12442; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc443; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v14, vcc444; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v3445; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v6, vcc446; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc447; GFX9-NEXT:    v_cndmask_b32_e64 v3, v7, v10, s[0:1]448; GFX9-NEXT:    v_cndmask_b32_e64 v7, v8, v11, s[0:1]449; GFX9-NEXT:    v_cndmask_b32_e64 v4, v0, v4, s[0:1]450; GFX9-NEXT:    v_cndmask_b32_e64 v2, v1, v2, s[0:1]451; GFX9-NEXT:    s_xor_b64 s[0:1], s[2:3], s[4:5]452; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v3453; GFX9-NEXT:    v_xor_b32_e32 v1, s1, v7454; GFX9-NEXT:    v_mov_b32_e32 v3, s1455; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s0, v0456; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v3, vcc457; GFX9-NEXT:    v_xor_b32_e32 v3, s2, v4458; GFX9-NEXT:    v_xor_b32_e32 v4, s2, v2459; GFX9-NEXT:    v_mov_b32_e32 v5, s2460; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s2, v3461; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v4, v5, vcc462; GFX9-NEXT:    global_store_dwordx2 v9, v[0:1], s[12:13]463; GFX9-NEXT:    global_store_dwordx2 v9, v[2:3], s[14:15]464; GFX9-NEXT:    s_endpgm465;466; GFX10-LABEL: sdivrem_i64:467; GFX10:       ; %bb.0:468; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0469; GFX10-NEXT:    s_waitcnt lgkmcnt(0)470; GFX10-NEXT:    s_ashr_i32 s2, s17, 31471; GFX10-NEXT:    s_ashr_i32 s4, s19, 31472; GFX10-NEXT:    s_add_u32 s0, s16, s2473; GFX10-NEXT:    s_addc_u32 s1, s17, s2474; GFX10-NEXT:    s_add_u32 s6, s18, s4475; GFX10-NEXT:    s_mov_b32 s5, s4476; GFX10-NEXT:    s_addc_u32 s7, s19, s4477; GFX10-NEXT:    s_mov_b32 s3, s2478; GFX10-NEXT:    s_xor_b64 s[6:7], s[6:7], s[4:5]479; GFX10-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]480; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s7481; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s6482; GFX10-NEXT:    s_sub_u32 s8, 0, s6483; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0484; GFX10-NEXT:    v_add_f32_e32 v0, v0, v1485; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0486; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0487; GFX10-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0488; GFX10-NEXT:    v_trunc_f32_e32 v2, v1489; GFX10-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2490; GFX10-NEXT:    v_cvt_u32_f32_e32 v4, v2491; GFX10-NEXT:    v_add_f32_e32 v0, v1, v0492; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v0493; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s9, s8, v3, 0494; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s9, s8, v4, v[1:2]495; GFX10-NEXT:    s_subb_u32 s9, 0, s7496; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v0497; GFX10-NEXT:    s_xor_b64 s[4:5], s[2:3], s[4:5]498; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s10, s9, v3, v[1:2]499; GFX10-NEXT:    v_mul_lo_u32 v2, v4, v0500; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0501; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1502; GFX10-NEXT:    v_mul_lo_u32 v7, v4, v1503; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1504; GFX10-NEXT:    v_mul_hi_u32 v1, v4, v1505; GFX10-NEXT:    v_add_co_u32 v2, s10, v2, v5506; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s10507; GFX10-NEXT:    v_add_co_u32 v6, s10, v7, v6508; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s10509; GFX10-NEXT:    v_add_co_u32 v0, s10, v2, v0510; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s10511; GFX10-NEXT:    v_add_co_u32 v2, s10, v6, v8512; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s10513; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0514; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6515; GFX10-NEXT:    v_add_co_u32 v0, s10, v2, v0516; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s10517; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v3, v0518; GFX10-NEXT:    v_add3_u32 v1, v5, v2, v1519; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo520; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s10, s8, v3, 0521; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s8, s8, v4, v[1:2]522; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v0523; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s8, s9, v3, v[1:2]524; GFX10-NEXT:    v_mul_lo_u32 v2, v4, v0525; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0526; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1527; GFX10-NEXT:    v_mul_lo_u32 v7, v4, v1528; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1529; GFX10-NEXT:    v_mul_hi_u32 v1, v4, v1530; GFX10-NEXT:    v_add_co_u32 v2, s8, v2, v5531; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s8532; GFX10-NEXT:    v_add_co_u32 v6, s8, v7, v6533; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s8534; GFX10-NEXT:    v_add_co_u32 v0, s8, v2, v0535; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s8536; GFX10-NEXT:    v_add_co_u32 v2, s8, v6, v8537; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s8538; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0539; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6540; GFX10-NEXT:    v_add_co_u32 v0, s8, v2, v0541; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s8542; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v3, v0543; GFX10-NEXT:    v_add3_u32 v1, v5, v2, v1544; GFX10-NEXT:    v_mul_lo_u32 v2, s1, v0545; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo546; GFX10-NEXT:    v_mul_hi_u32 v4, s0, v0547; GFX10-NEXT:    v_mul_hi_u32 v0, s1, v0548; GFX10-NEXT:    v_mul_lo_u32 v3, s0, v1549; GFX10-NEXT:    v_mul_lo_u32 v5, s1, v1550; GFX10-NEXT:    v_add_co_u32 v2, s8, v2, v3551; GFX10-NEXT:    v_mul_hi_u32 v3, s0, v1552; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s8553; GFX10-NEXT:    v_add_co_u32 v2, s8, v2, v4554; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s8555; GFX10-NEXT:    v_add_co_u32 v0, s8, v5, v0556; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s8557; GFX10-NEXT:    v_mul_hi_u32 v5, s1, v1558; GFX10-NEXT:    v_add_nc_u32_e32 v2, v6, v2559; GFX10-NEXT:    v_add_co_u32 v0, s8, v0, v3560; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s8561; GFX10-NEXT:    v_add_co_u32 v6, s8, v0, v2562; GFX10-NEXT:    v_add_nc_u32_e32 v2, v4, v3563; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s8564; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s8, s6, v6, 0565; GFX10-NEXT:    v_add3_u32 v3, v2, v3, v5566; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s8, s6, v3, v[1:2]567; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s8, s7, v6, v[1:2]568; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v6, 1569; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, 0, v3, vcc_lo570; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, s0, v0571; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s1, v1572; GFX10-NEXT:    v_sub_co_ci_u32_e64 v1, s0, s1, v1, vcc_lo573; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo574; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s6, v0575; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, -1, vcc_lo576; GFX10-NEXT:    v_sub_co_u32 v8, vcc_lo, v0, s6577; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v9, s0, 0, v5, vcc_lo578; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s7, v1579; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s7, v5, vcc_lo580; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s0581; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s6, v8582; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s0583; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s7, v9584; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s0585; GFX10-NEXT:    v_add_co_u32 v13, s0, v2, 1586; GFX10-NEXT:    v_add_co_ci_u32_e64 v14, s0, 0, v4, s0587; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s7, v9588; GFX10-NEXT:    v_cndmask_b32_e64 v11, v12, v11, s0589; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s7, v1590; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11591; GFX10-NEXT:    v_cndmask_b32_e64 v7, v10, v7, s0592; GFX10-NEXT:    v_sub_co_u32 v10, s0, v8, s6593; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v5, s0, 0, v5, s0594; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v13, vcc_lo595; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v7596; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v14, vcc_lo597; GFX10-NEXT:    v_cndmask_b32_e32 v7, v8, v10, vcc_lo598; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v5, vcc_lo599; GFX10-NEXT:    v_cndmask_b32_e64 v2, v6, v2, s0600; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s0601; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, v7, s0602; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0603; GFX10-NEXT:    v_mov_b32_e32 v4, 0604; GFX10-NEXT:    v_xor_b32_e32 v2, s4, v2605; GFX10-NEXT:    v_xor_b32_e32 v3, s5, v3606; GFX10-NEXT:    v_xor_b32_e32 v5, s2, v0607; GFX10-NEXT:    v_xor_b32_e32 v6, s2, v1608; GFX10-NEXT:    v_sub_co_u32 v0, vcc_lo, v2, s4609; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v1, vcc_lo, s5, v3, vcc_lo610; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v5, s2611; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s2, v6, vcc_lo612; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[12:13]613; GFX10-NEXT:    global_store_dwordx2 v4, v[2:3], s[14:15]614; GFX10-NEXT:    s_endpgm615  %div = sdiv i64 %x, %y616  store i64 %div, ptr addrspace(1) %out0617  %rem = srem i64 %x, %y618  store i64 %rem, ptr addrspace(1) %out1619  ret void620}621 622define amdgpu_kernel void @sdivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i32> %x, <2 x i32> %y) {623; GFX8-LABEL: sdivrem_v2i32:624; GFX8:       ; %bb.0:625; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[8:9], 0x0626; GFX8-NEXT:    s_add_i32 s12, s12, s17627; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8628; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13629; GFX8-NEXT:    s_waitcnt lgkmcnt(0)630; GFX8-NEXT:    s_ashr_i32 s2, s10, 31631; GFX8-NEXT:    s_add_i32 s0, s10, s2632; GFX8-NEXT:    s_xor_b32 s3, s0, s2633; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s3634; GFX8-NEXT:    s_ashr_i32 s10, s11, 31635; GFX8-NEXT:    s_add_i32 s0, s11, s10636; GFX8-NEXT:    s_xor_b32 s11, s0, s10637; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0638; GFX8-NEXT:    s_sub_i32 s0, 0, s3639; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s11640; GFX8-NEXT:    s_ashr_i32 s12, s8, 31641; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0642; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0643; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1644; GFX8-NEXT:    s_sub_i32 s1, 0, s11645; GFX8-NEXT:    v_mul_lo_u32 v2, s0, v0646; GFX8-NEXT:    s_add_i32 s0, s8, s12647; GFX8-NEXT:    s_xor_b32 s0, s0, s12648; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1649; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2650; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1651; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2652; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0653; GFX8-NEXT:    v_mul_lo_u32 v2, s1, v1654; GFX8-NEXT:    v_mul_lo_u32 v3, v0, s3655; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v0656; GFX8-NEXT:    v_mul_hi_u32 v2, v1, v2657; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s0, v3658; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3659; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc660; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v3661; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc662; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v0663; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v3664; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc665; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v3666; GFX8-NEXT:    s_xor_b32 s0, s12, s2667; GFX8-NEXT:    s_ashr_i32 s2, s9, 31668; GFX8-NEXT:    s_add_i32 s1, s9, s2669; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc670; GFX8-NEXT:    s_xor_b32 s1, s1, s2671; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2672; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1673; GFX8-NEXT:    v_xor_b32_e32 v2, s12, v3674; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0675; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0676; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s11677; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s12, v2678; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1679; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v3680; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3681; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc682; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3683; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc684; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1685; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3686; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc687; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3688; GFX8-NEXT:    s_xor_b32 s0, s2, s10689; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc690; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1691; GFX8-NEXT:    v_mov_b32_e32 v4, s4692; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1693; GFX8-NEXT:    v_mov_b32_e32 v5, s5694; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v3695; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]696; GFX8-NEXT:    v_mov_b32_e32 v0, s6697; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v3698; GFX8-NEXT:    v_mov_b32_e32 v1, s7699; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]700; GFX8-NEXT:    s_endpgm701;702; GFX9-LABEL: sdivrem_v2i32:703; GFX9:       ; %bb.0:704; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[8:9], 0x0705; GFX9-NEXT:    s_waitcnt lgkmcnt(0)706; GFX9-NEXT:    s_ashr_i32 s8, s6, 31707; GFX9-NEXT:    s_add_i32 s6, s6, s8708; GFX9-NEXT:    s_xor_b32 s6, s6, s8709; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s6710; GFX9-NEXT:    s_ashr_i32 s9, s7, 31711; GFX9-NEXT:    s_add_i32 s7, s7, s9712; GFX9-NEXT:    s_xor_b32 s7, s7, s9713; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0714; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s7715; GFX9-NEXT:    s_sub_i32 s12, 0, s6716; GFX9-NEXT:    s_ashr_i32 s10, s4, 31717; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0718; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0719; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1720; GFX9-NEXT:    s_add_i32 s4, s4, s10721; GFX9-NEXT:    s_xor_b32 s4, s4, s10722; GFX9-NEXT:    v_mul_lo_u32 v2, s12, v0723; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1724; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1725; GFX9-NEXT:    s_sub_i32 s12, 0, s7726; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2727; GFX9-NEXT:    s_ashr_i32 s11, s5, 31728; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v1729; GFX9-NEXT:    s_add_i32 s5, s5, s11730; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2731; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v0732; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v3733; GFX9-NEXT:    s_xor_b32 s5, s5, s11734; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s6735; GFX9-NEXT:    v_add_u32_e32 v1, v1, v2736; GFX9-NEXT:    v_add_u32_e32 v2, 1, v0737; GFX9-NEXT:    v_mul_hi_u32 v1, s5, v1738; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v3739; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v3740; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc741; GFX9-NEXT:    v_subrev_u32_e32 v2, s6, v3742; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc743; GFX9-NEXT:    v_add_u32_e32 v3, 1, v0744; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v2745; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc746; GFX9-NEXT:    v_subrev_u32_e32 v3, s6, v2747; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc748; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s7749; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1750; GFX9-NEXT:    s_xor_b32 s4, s10, s8751; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v0752; GFX9-NEXT:    v_sub_u32_e32 v3, s5, v3753; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3754; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc755; GFX9-NEXT:    v_subrev_u32_e32 v4, s7, v3756; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc757; GFX9-NEXT:    v_add_u32_e32 v4, 1, v1758; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v3759; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v0760; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc761; GFX9-NEXT:    v_subrev_u32_e32 v4, s7, v3762; GFX9-NEXT:    s_xor_b32 s4, s11, s9763; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc764; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v1765; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v2766; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v1767; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v3768; GFX9-NEXT:    v_mov_b32_e32 v4, 0769; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v2770; GFX9-NEXT:    v_subrev_u32_e32 v3, s11, v3771; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[0:1]772; GFX9-NEXT:    global_store_dwordx2 v4, v[2:3], s[2:3]773; GFX9-NEXT:    s_endpgm774;775; GFX10-LABEL: sdivrem_v2i32:776; GFX10:       ; %bb.0:777; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0778; GFX10-NEXT:    s_waitcnt lgkmcnt(0)779; GFX10-NEXT:    s_ashr_i32 s1, s18, 31780; GFX10-NEXT:    s_ashr_i32 s2, s19, 31781; GFX10-NEXT:    s_add_i32 s0, s18, s1782; GFX10-NEXT:    s_add_i32 s3, s19, s2783; GFX10-NEXT:    s_xor_b32 s4, s0, s1784; GFX10-NEXT:    s_xor_b32 s3, s3, s2785; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s4786; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s3787; GFX10-NEXT:    s_sub_i32 s0, 0, s4788; GFX10-NEXT:    s_sub_i32 s5, 0, s3789; GFX10-NEXT:    s_ashr_i32 s6, s17, 31790; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0791; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1792; GFX10-NEXT:    s_add_i32 s7, s17, s6793; GFX10-NEXT:    s_xor_b32 s7, s7, s6794; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0795; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1796; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0797; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1798; GFX10-NEXT:    v_mul_lo_u32 v2, s0, v0799; GFX10-NEXT:    v_mul_lo_u32 v3, s5, v1800; GFX10-NEXT:    s_ashr_i32 s5, s16, 31801; GFX10-NEXT:    s_add_i32 s0, s16, s5802; GFX10-NEXT:    s_xor_b32 s1, s5, s1803; GFX10-NEXT:    s_xor_b32 s0, s0, s5804; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2805; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3806; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2807; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3808; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0809; GFX10-NEXT:    v_mul_hi_u32 v1, s7, v1810; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s4811; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s3812; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0813; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1814; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s0, v2815; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s7, v3816; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v2817; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s4, v2818; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v3819; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s3, v3820; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo821; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo822; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0823; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0824; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0825; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v2826; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1827; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v3828; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s4, v2829; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s3, v3830; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo831; GFX10-NEXT:    v_mov_b32_e32 v4, 0832; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0833; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo834; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0835; GFX10-NEXT:    s_xor_b32 s0, s6, s2836; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v0837; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v1838; GFX10-NEXT:    v_xor_b32_e32 v2, s5, v2839; GFX10-NEXT:    v_xor_b32_e32 v3, s6, v3840; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v0841; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s0, v1842; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s5, v2843; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s6, v3844; GFX10-NEXT:    global_store_dwordx2 v4, v[0:1], s[12:13]845; GFX10-NEXT:    global_store_dwordx2 v4, v[2:3], s[14:15]846; GFX10-NEXT:    s_endpgm847  %div = sdiv <2 x i32> %x, %y848  store <2 x i32> %div, ptr addrspace(1) %out0849  %rem = srem <2 x i32> %x, %y850  store <2 x i32> %rem, ptr addrspace(1) %out1851  ret void852}853 854define amdgpu_kernel void @sdivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <4 x i32> %x, <4 x i32> %y) {855; GFX8-LABEL: sdivrem_v4i32:856; GFX8:       ; %bb.0:857; GFX8-NEXT:    s_add_i32 s12, s12, s17858; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13859; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8860; GFX8-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x10861; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x0862; GFX8-NEXT:    s_waitcnt lgkmcnt(0)863; GFX8-NEXT:    s_ashr_i32 s2, s16, 31864; GFX8-NEXT:    s_add_i32 s0, s16, s2865; GFX8-NEXT:    s_xor_b32 s3, s0, s2866; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s3867; GFX8-NEXT:    s_sub_i32 s1, 0, s3868; GFX8-NEXT:    s_ashr_i32 s9, s17, 31869; GFX8-NEXT:    s_add_i32 s0, s17, s9870; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0871; GFX8-NEXT:    s_xor_b32 s10, s0, s9872; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s10873; GFX8-NEXT:    s_ashr_i32 s8, s12, 31874; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0875; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0876; GFX8-NEXT:    s_add_i32 s0, s12, s8877; GFX8-NEXT:    s_xor_b32 s0, s0, s8878; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v2879; GFX8-NEXT:    v_mul_lo_u32 v1, s1, v0880; GFX8-NEXT:    s_sub_i32 s11, 0, s10881; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v1882; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1883; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v0884; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v2885; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1886; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s3887; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0888; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v2889; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2890; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc891; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2892; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc893; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0894; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v2895; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc896; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s3, v2897; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc898; GFX8-NEXT:    v_mul_lo_u32 v3, s11, v1899; GFX8-NEXT:    s_xor_b32 s0, s8, s2900; GFX8-NEXT:    s_ashr_i32 s2, s13, 31901; GFX8-NEXT:    s_add_i32 s1, s13, s2902; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3903; GFX8-NEXT:    s_xor_b32 s1, s1, s2904; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v0905; GFX8-NEXT:    v_xor_b32_e32 v2, s8, v2906; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3907; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v1908; GFX8-NEXT:    s_ashr_i32 s3, s18, 31909; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v0910; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s10911; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, s8, v2912; GFX8-NEXT:    s_add_i32 s0, s18, s3913; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s1, v3914; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v1915; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2916; GFX8-NEXT:    s_xor_b32 s8, s0, s3917; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc918; GFX8-NEXT:    v_cvt_f32_u32_e32 v3, s8919; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s10, v2920; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc921; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v3922; GFX8-NEXT:    v_add_u32_e32 v5, vcc, 1, v1923; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2924; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3925; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3926; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc927; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s10, v2928; GFX8-NEXT:    s_sub_i32 s0, 0, s8929; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc930; GFX8-NEXT:    v_mul_lo_u32 v5, s0, v3931; GFX8-NEXT:    s_xor_b32 s0, s2, s9932; GFX8-NEXT:    s_ashr_i32 s9, s14, 31933; GFX8-NEXT:    s_add_i32 s1, s14, s9934; GFX8-NEXT:    v_mul_hi_u32 v5, v3, v5935; GFX8-NEXT:    s_xor_b32 s1, s1, s9936; GFX8-NEXT:    v_xor_b32_e32 v2, s2, v2937; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v1938; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v3, v5939; GFX8-NEXT:    v_mul_hi_u32 v3, s1, v3940; GFX8-NEXT:    v_subrev_u32_e32 v5, vcc, s2, v2941; GFX8-NEXT:    s_ashr_i32 s2, s19, 31942; GFX8-NEXT:    v_mul_lo_u32 v6, v3, s8943; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v1944; GFX8-NEXT:    s_add_i32 s0, s19, s2945; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s1, v6946; GFX8-NEXT:    v_add_u32_e32 v6, vcc, 1, v3947; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2948; GFX8-NEXT:    s_xor_b32 s10, s0, s2949; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc950; GFX8-NEXT:    v_cvt_f32_u32_e32 v6, s10951; GFX8-NEXT:    v_subrev_u32_e64 v7, s[0:1], s8, v2952; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc953; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v6954; GFX8-NEXT:    v_add_u32_e32 v7, vcc, 1, v3955; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s8, v2956; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6957; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6958; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc959; GFX8-NEXT:    v_subrev_u32_e64 v7, s[0:1], s8, v2960; GFX8-NEXT:    s_sub_i32 s0, 0, s10961; GFX8-NEXT:    v_cndmask_b32_e32 v7, v2, v7, vcc962; GFX8-NEXT:    v_mul_lo_u32 v2, s0, v6963; GFX8-NEXT:    s_xor_b32 s0, s9, s3964; GFX8-NEXT:    s_ashr_i32 s3, s15, 31965; GFX8-NEXT:    s_add_i32 s1, s15, s3966; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v2967; GFX8-NEXT:    s_xor_b32 s1, s1, s3968; GFX8-NEXT:    v_xor_b32_e32 v3, s0, v3969; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v6, v2970; GFX8-NEXT:    v_mul_hi_u32 v8, s1, v2971; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s0, v3972; GFX8-NEXT:    v_xor_b32_e32 v3, s9, v7973; GFX8-NEXT:    v_mul_lo_u32 v7, v8, s10974; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, s9, v3975; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v7976; GFX8-NEXT:    v_add_u32_e32 v7, vcc, 1, v8977; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3978; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc979; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s10, v3980; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc981; GFX8-NEXT:    v_add_u32_e32 v8, vcc, 1, v7982; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v3983; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc984; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s10, v3985; GFX8-NEXT:    v_cndmask_b32_e32 v8, v3, v8, vcc986; GFX8-NEXT:    s_xor_b32 s0, s3, s2987; GFX8-NEXT:    v_xor_b32_e32 v3, s0, v7988; GFX8-NEXT:    v_xor_b32_e32 v7, s3, v8989; GFX8-NEXT:    v_mov_b32_e32 v9, s5990; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s0, v3991; GFX8-NEXT:    v_mov_b32_e32 v8, s4992; GFX8-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]993; GFX8-NEXT:    v_subrev_u32_e32 v7, vcc, s3, v7994; GFX8-NEXT:    v_mov_b32_e32 v0, s6995; GFX8-NEXT:    v_mov_b32_e32 v1, s7996; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[4:7]997; GFX8-NEXT:    s_endpgm998;999; GFX9-LABEL: sdivrem_v4i32:1000; GFX9:       ; %bb.0:1001; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[8:9], 0x101002; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1003; GFX9-NEXT:    s_ashr_i32 s12, s4, 311004; GFX9-NEXT:    s_add_i32 s4, s4, s121005; GFX9-NEXT:    s_xor_b32 s4, s4, s121006; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s41007; GFX9-NEXT:    s_ashr_i32 s13, s5, 311008; GFX9-NEXT:    s_add_i32 s5, s5, s131009; GFX9-NEXT:    s_xor_b32 s5, s5, s131010; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01011; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s51012; GFX9-NEXT:    s_sub_i32 s15, 0, s41013; GFX9-NEXT:    s_ashr_i32 s14, s0, 311014; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01015; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v01016; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v11017; GFX9-NEXT:    s_add_i32 s0, s0, s141018; GFX9-NEXT:    s_xor_b32 s0, s0, s141019; GFX9-NEXT:    v_mul_lo_u32 v2, s15, v01020; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v11021; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v11022; GFX9-NEXT:    s_sub_i32 s15, 0, s51023; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v21024; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x01025; GFX9-NEXT:    v_mul_lo_u32 v3, s15, v11026; GFX9-NEXT:    s_ashr_i32 s15, s1, 311027; GFX9-NEXT:    v_add_u32_e32 v0, v0, v21028; GFX9-NEXT:    v_mul_hi_u32 v0, s0, v01029; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v31030; GFX9-NEXT:    s_add_i32 s1, s1, s151031; GFX9-NEXT:    s_xor_b32 s1, s1, s151032; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s41033; GFX9-NEXT:    v_add_u32_e32 v1, v1, v21034; GFX9-NEXT:    v_add_u32_e32 v2, 1, v01035; GFX9-NEXT:    v_mul_hi_u32 v1, s1, v11036; GFX9-NEXT:    v_sub_u32_e32 v3, s0, v31037; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v31038; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc1039; GFX9-NEXT:    v_subrev_u32_e32 v2, s4, v31040; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc1041; GFX9-NEXT:    v_add_u32_e32 v3, 1, v01042; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v21043; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc1044; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v21045; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1046; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s51047; GFX9-NEXT:    s_xor_b32 s0, s14, s121048; GFX9-NEXT:    v_xor_b32_e32 v0, s0, v01049; GFX9-NEXT:    v_subrev_u32_e32 v0, s0, v01050; GFX9-NEXT:    v_xor_b32_e32 v2, s14, v21051; GFX9-NEXT:    s_ashr_i32 s0, s6, 311052; GFX9-NEXT:    v_subrev_u32_e32 v4, s14, v21053; GFX9-NEXT:    v_sub_u32_e32 v2, s1, v31054; GFX9-NEXT:    s_add_i32 s1, s6, s01055; GFX9-NEXT:    s_xor_b32 s1, s1, s01056; GFX9-NEXT:    v_cvt_f32_u32_e32 v3, s11057; GFX9-NEXT:    v_add_u32_e32 v5, 1, v11058; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v21059; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc1060; GFX9-NEXT:    v_rcp_iflag_f32_e32 v3, v31061; GFX9-NEXT:    v_subrev_u32_e32 v5, s5, v21062; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc1063; GFX9-NEXT:    v_add_u32_e32 v5, 1, v11064; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v31065; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v31066; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v21067; GFX9-NEXT:    s_sub_i32 s4, 0, s11068; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc1069; GFX9-NEXT:    v_mul_lo_u32 v5, s4, v31070; GFX9-NEXT:    s_xor_b32 s4, s15, s131071; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v11072; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v11073; GFX9-NEXT:    s_ashr_i32 s4, s7, 311074; GFX9-NEXT:    s_add_i32 s6, s7, s41075; GFX9-NEXT:    v_mul_hi_u32 v5, v3, v51076; GFX9-NEXT:    s_xor_b32 s6, s6, s41077; GFX9-NEXT:    v_cvt_f32_u32_e32 v7, s61078; GFX9-NEXT:    v_subrev_u32_e32 v6, s5, v21079; GFX9-NEXT:    s_ashr_i32 s5, s2, 311080; GFX9-NEXT:    s_add_i32 s2, s2, s51081; GFX9-NEXT:    s_xor_b32 s2, s2, s51082; GFX9-NEXT:    v_add_u32_e32 v3, v3, v51083; GFX9-NEXT:    v_mul_hi_u32 v3, s2, v31084; GFX9-NEXT:    v_rcp_iflag_f32_e32 v7, v71085; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc1086; GFX9-NEXT:    v_xor_b32_e32 v2, s15, v21087; GFX9-NEXT:    v_mul_lo_u32 v6, v3, s11088; GFX9-NEXT:    v_mul_f32_e32 v7, 0x4f7ffffe, v71089; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v71090; GFX9-NEXT:    v_subrev_u32_e32 v5, s15, v21091; GFX9-NEXT:    v_sub_u32_e32 v2, s2, v61092; GFX9-NEXT:    s_sub_i32 s2, 0, s61093; GFX9-NEXT:    v_mul_lo_u32 v8, s2, v71094; GFX9-NEXT:    v_add_u32_e32 v6, 1, v31095; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v21096; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc1097; GFX9-NEXT:    v_subrev_u32_e32 v6, s1, v21098; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc1099; GFX9-NEXT:    v_mul_hi_u32 v8, v7, v81100; GFX9-NEXT:    v_add_u32_e32 v6, 1, v31101; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s1, v21102; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v6, vcc1103; GFX9-NEXT:    v_subrev_u32_e32 v6, s1, v21104; GFX9-NEXT:    s_ashr_i32 s1, s3, 311105; GFX9-NEXT:    s_add_i32 s2, s3, s11106; GFX9-NEXT:    s_xor_b32 s2, s2, s11107; GFX9-NEXT:    v_add_u32_e32 v7, v7, v81108; GFX9-NEXT:    v_mul_hi_u32 v7, s2, v71109; GFX9-NEXT:    s_xor_b32 s0, s5, s01110; GFX9-NEXT:    v_cndmask_b32_e32 v6, v2, v6, vcc1111; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v31112; GFX9-NEXT:    v_mul_lo_u32 v3, v7, s61113; GFX9-NEXT:    v_add_u32_e32 v8, 1, v71114; GFX9-NEXT:    v_subrev_u32_e32 v2, s0, v21115; GFX9-NEXT:    s_xor_b32 s0, s1, s41116; GFX9-NEXT:    v_sub_u32_e32 v3, s2, v31117; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v31118; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc1119; GFX9-NEXT:    v_subrev_u32_e32 v8, s6, v31120; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc1121; GFX9-NEXT:    v_add_u32_e32 v8, 1, v71122; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v31123; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc1124; GFX9-NEXT:    v_subrev_u32_e32 v8, s6, v31125; GFX9-NEXT:    v_cndmask_b32_e32 v8, v3, v8, vcc1126; GFX9-NEXT:    v_xor_b32_e32 v3, s0, v71127; GFX9-NEXT:    v_xor_b32_e32 v6, s5, v61128; GFX9-NEXT:    v_subrev_u32_e32 v3, s0, v31129; GFX9-NEXT:    v_xor_b32_e32 v7, s1, v81130; GFX9-NEXT:    v_mov_b32_e32 v8, 01131; GFX9-NEXT:    v_subrev_u32_e32 v6, s5, v61132; GFX9-NEXT:    v_subrev_u32_e32 v7, s1, v71133; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1134; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[8:9]1135; GFX9-NEXT:    global_store_dwordx4 v8, v[4:7], s[10:11]1136; GFX9-NEXT:    s_endpgm1137;1138; GFX10-LABEL: sdivrem_v4i32:1139; GFX10:       ; %bb.0:1140; GFX10-NEXT:    s_load_dwordx8 s[0:7], s[8:9], 0x101141; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1142; GFX10-NEXT:    s_ashr_i32 s10, s4, 311143; GFX10-NEXT:    s_ashr_i32 s11, s5, 311144; GFX10-NEXT:    s_ashr_i32 s12, s6, 311145; GFX10-NEXT:    s_ashr_i32 s13, s7, 311146; GFX10-NEXT:    s_add_i32 s4, s4, s101147; GFX10-NEXT:    s_add_i32 s5, s5, s111148; GFX10-NEXT:    s_add_i32 s6, s6, s121149; GFX10-NEXT:    s_add_i32 s7, s7, s131150; GFX10-NEXT:    s_xor_b32 s14, s4, s101151; GFX10-NEXT:    s_xor_b32 s15, s5, s111152; GFX10-NEXT:    s_xor_b32 s16, s6, s121153; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s141154; GFX10-NEXT:    s_xor_b32 s17, s7, s131155; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s151156; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s161157; GFX10-NEXT:    v_cvt_f32_u32_e32 v3, s171158; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v01159; GFX10-NEXT:    s_sub_i32 s4, 0, s141160; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v11161; GFX10-NEXT:    v_rcp_iflag_f32_e32 v2, v21162; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v31163; GFX10-NEXT:    s_sub_i32 s5, 0, s151164; GFX10-NEXT:    s_sub_i32 s6, 0, s161165; GFX10-NEXT:    s_ashr_i32 s18, s0, 311166; GFX10-NEXT:    s_ashr_i32 s19, s1, 311167; GFX10-NEXT:    s_ashr_i32 s20, s2, 311168; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01169; GFX10-NEXT:    s_ashr_i32 s21, s3, 311170; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v11171; GFX10-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v21172; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v31173; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v01174; GFX10-NEXT:    s_add_i32 s0, s0, s181175; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v11176; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v21177; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v31178; GFX10-NEXT:    v_mul_lo_u32 v4, s4, v01179; GFX10-NEXT:    s_sub_i32 s4, 0, s171180; GFX10-NEXT:    v_mul_lo_u32 v5, s5, v11181; GFX10-NEXT:    v_mul_lo_u32 v6, s6, v21182; GFX10-NEXT:    v_mul_lo_u32 v7, s4, v31183; GFX10-NEXT:    s_add_i32 s1, s1, s191184; GFX10-NEXT:    s_add_i32 s2, s2, s201185; GFX10-NEXT:    s_add_i32 s3, s3, s211186; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v41187; GFX10-NEXT:    s_xor_b32 s0, s0, s181188; GFX10-NEXT:    v_mul_hi_u32 v5, v1, v51189; GFX10-NEXT:    v_mul_hi_u32 v6, v2, v61190; GFX10-NEXT:    v_mul_hi_u32 v7, v3, v71191; GFX10-NEXT:    s_xor_b32 s1, s1, s191192; GFX10-NEXT:    s_xor_b32 s2, s2, s201193; GFX10-NEXT:    s_xor_b32 s3, s3, s211194; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v41195; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x01196; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v51197; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v61198; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v71199; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v01200; GFX10-NEXT:    s_xor_b32 s8, s18, s101201; GFX10-NEXT:    v_mul_hi_u32 v1, s1, v11202; GFX10-NEXT:    v_mul_hi_u32 v2, s2, v21203; GFX10-NEXT:    v_mul_hi_u32 v3, s3, v31204; GFX10-NEXT:    s_xor_b32 s9, s19, s111205; GFX10-NEXT:    s_xor_b32 s10, s20, s121206; GFX10-NEXT:    v_mul_lo_u32 v4, v0, s141207; GFX10-NEXT:    v_add_nc_u32_e32 v8, 1, v01208; GFX10-NEXT:    v_mul_lo_u32 v5, v1, s151209; GFX10-NEXT:    v_mul_lo_u32 v6, v2, s161210; GFX10-NEXT:    v_mul_lo_u32 v7, v3, s171211; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v11212; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v21213; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v31214; GFX10-NEXT:    v_sub_nc_u32_e32 v4, s0, v41215; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s1, v51216; GFX10-NEXT:    v_sub_nc_u32_e32 v6, s2, v61217; GFX10-NEXT:    v_sub_nc_u32_e32 v7, s3, v71218; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s14, v41219; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s15, v51220; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s16, v61221; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s17, v71222; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo1223; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, s14, v41224; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s01225; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s15, v51226; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v10, s11227; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s16, v61228; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v11, s21229; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s17, v71230; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo1231; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s01232; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s11233; GFX10-NEXT:    v_add_nc_u32_e32 v8, 1, v01234; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s21235; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v11236; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v21237; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v31238; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s14, v41239; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s15, v51240; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s16, v61241; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s17, v71242; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo1243; GFX10-NEXT:    v_subrev_nc_u32_e32 v8, s14, v41244; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v9, s01245; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s15, v51246; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v10, s11247; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s16, v61248; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v11, s21249; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s17, v71250; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v8, vcc_lo1251; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v9, s01252; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v10, s11253; GFX10-NEXT:    s_xor_b32 s0, s21, s131254; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v11, s21255; GFX10-NEXT:    v_xor_b32_e32 v0, s8, v01256; GFX10-NEXT:    v_xor_b32_e32 v1, s9, v11257; GFX10-NEXT:    v_xor_b32_e32 v2, s10, v21258; GFX10-NEXT:    v_xor_b32_e32 v3, s0, v31259; GFX10-NEXT:    v_xor_b32_e32 v4, s18, v41260; GFX10-NEXT:    v_xor_b32_e32 v5, s19, v51261; GFX10-NEXT:    v_xor_b32_e32 v6, s20, v61262; GFX10-NEXT:    v_xor_b32_e32 v7, s21, v71263; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s8, v01264; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s9, v11265; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s10, v21266; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s0, v31267; GFX10-NEXT:    v_mov_b32_e32 v8, 01268; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s18, v41269; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s19, v51270; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s20, v61271; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s21, v71272; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1273; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[4:5]1274; GFX10-NEXT:    global_store_dwordx4 v8, v[4:7], s[6:7]1275; GFX10-NEXT:    s_endpgm1276  %div = sdiv <4 x i32> %x, %y1277  store <4 x i32> %div, ptr addrspace(1) %out01278  %rem = srem <4 x i32> %x, %y1279  store <4 x i32> %rem, ptr addrspace(1) %out11280  ret void1281}1282 1283define amdgpu_kernel void @sdivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i64> %x, <2 x i64> %y) {1284; GFX8-LABEL: sdivrem_v2i64:1285; GFX8:       ; %bb.0:1286; GFX8-NEXT:    s_add_i32 s12, s12, s171287; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s131288; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81289; GFX8-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x01290; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x201291; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1292; GFX8-NEXT:    s_ashr_i32 s4, s17, 311293; GFX8-NEXT:    s_ashr_i32 s6, s1, 311294; GFX8-NEXT:    s_add_u32 s10, s16, s41295; GFX8-NEXT:    s_addc_u32 s11, s17, s41296; GFX8-NEXT:    s_add_u32 s0, s0, s61297; GFX8-NEXT:    s_mov_b32 s7, s61298; GFX8-NEXT:    s_addc_u32 s1, s1, s61299; GFX8-NEXT:    s_xor_b64 s[8:9], s[0:1], s[6:7]1300; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s91301; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s81302; GFX8-NEXT:    s_mov_b32 s5, s41303; GFX8-NEXT:    s_xor_b64 s[10:11], s[10:11], s[4:5]1304; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v01305; GFX8-NEXT:    v_add_f32_e32 v0, v0, v11306; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v01307; GFX8-NEXT:    s_sub_u32 s16, 0, s81308; GFX8-NEXT:    s_subb_u32 s17, 0, s91309; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01310; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01311; GFX8-NEXT:    v_trunc_f32_e32 v1, v11312; GFX8-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11313; GFX8-NEXT:    v_add_f32_e32 v0, v2, v01314; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v01315; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v11316; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s16, v6, 01317; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s16, v7, v[1:2]1318; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v01319; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s17, v6, v[2:3]1320; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v01321; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v01322; GFX8-NEXT:    v_mul_lo_u32 v3, v6, v41323; GFX8-NEXT:    v_mul_lo_u32 v5, v7, v41324; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v41325; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31326; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1327; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v5, v01328; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc1329; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v21330; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1331; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11332; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v81333; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1334; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v21335; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v41336; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11337; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1338; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11339; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11340; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v01341; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc1342; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s16, v6, 01343; GFX8-NEXT:    v_mov_b32_e32 v8, s111344; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s16, v7, v[1:2]1345; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v01346; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s17, v6, v[2:3]1347; GFX8-NEXT:    v_mul_hi_u32 v3, v6, v01348; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v01349; GFX8-NEXT:    v_mul_lo_u32 v2, v6, v41350; GFX8-NEXT:    s_xor_b64 s[16:17], s[4:5], s[6:7]1351; GFX8-NEXT:    s_ashr_i32 s6, s19, 311352; GFX8-NEXT:    s_mov_b32 s7, s61353; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v21354; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1355; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31356; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1357; GFX8-NEXT:    v_mul_lo_u32 v3, v7, v41358; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11359; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v41360; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v01361; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1362; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v21363; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1364; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v21365; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v41366; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11367; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1368; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11369; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11370; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v01371; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc1372; GFX8-NEXT:    v_mul_lo_u32 v2, s11, v01373; GFX8-NEXT:    v_mul_lo_u32 v3, s10, v11374; GFX8-NEXT:    v_mul_hi_u32 v4, s10, v01375; GFX8-NEXT:    v_mul_hi_u32 v0, s11, v01376; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v31377; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1378; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v41379; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1380; GFX8-NEXT:    v_mul_lo_u32 v4, s11, v11381; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v21382; GFX8-NEXT:    v_mul_hi_u32 v3, s10, v11383; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v01384; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1385; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v31386; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1387; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v31388; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v0, v21389; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc1390; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v01391; GFX8-NEXT:    v_mul_hi_u32 v3, s11, v11392; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s8, v6, 01393; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v3, v21394; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s8, v7, v[1:2]1395; GFX8-NEXT:    v_sub_u32_e32 v9, vcc, s10, v01396; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s9, v6, v[2:3]1397; GFX8-NEXT:    v_mov_b32_e32 v1, s91398; GFX8-NEXT:    v_subb_u32_e64 v8, s[0:1], v8, v4, vcc1399; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], s11, v41400; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v81401; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]1402; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v91403; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1404; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v81405; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v1, vcc1406; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]1407; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s8, v91408; GFX8-NEXT:    v_subbrev_u32_e64 v4, s[0:1], 0, v0, vcc1409; GFX8-NEXT:    v_add_u32_e64 v5, s[0:1], 1, v61410; GFX8-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v7, s[0:1]1411; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v41412; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]1413; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v31414; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v1, vcc1415; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]1416; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v41417; GFX8-NEXT:    v_subrev_u32_e32 v14, vcc, s8, v31418; GFX8-NEXT:    s_ashr_i32 s8, s3, 311419; GFX8-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]1420; GFX8-NEXT:    v_add_u32_e64 v12, s[0:1], 1, v51421; GFX8-NEXT:    s_add_u32 s10, s18, s61422; GFX8-NEXT:    v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]1423; GFX8-NEXT:    s_addc_u32 s11, s19, s61424; GFX8-NEXT:    s_add_u32 s0, s2, s81425; GFX8-NEXT:    s_mov_b32 s9, s81426; GFX8-NEXT:    s_addc_u32 s1, s3, s81427; GFX8-NEXT:    s_xor_b64 s[2:3], s[0:1], s[8:9]1428; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s31429; GFX8-NEXT:    v_subbrev_u32_e32 v15, vcc, 0, v0, vcc1430; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s21431; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v11432; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v21433; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111434; GFX8-NEXT:    v_add_f32_e32 v0, v1, v01435; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v01436; GFX8-NEXT:    s_xor_b64 s[10:11], s[10:11], s[6:7]1437; GFX8-NEXT:    s_sub_u32 s5, 0, s21438; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc1439; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01440; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01441; GFX8-NEXT:    v_trunc_f32_e32 v1, v11442; GFX8-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11443; GFX8-NEXT:    v_add_f32_e32 v0, v2, v01444; GFX8-NEXT:    v_cvt_u32_f32_e32 v11, v01445; GFX8-NEXT:    v_cvt_u32_f32_e32 v12, v11446; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc1447; GFX8-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[0:1]1448; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[18:19], s5, v11, 01449; GFX8-NEXT:    v_cndmask_b32_e32 v10, v3, v14, vcc1450; GFX8-NEXT:    s_subb_u32 s20, 0, s31451; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[18:19], s5, v12, v[1:2]1452; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, v5, s[0:1]1453; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v15, vcc1454; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[18:19], s20, v11, v[2:3]1455; GFX8-NEXT:    v_cndmask_b32_e64 v8, v8, v1, s[0:1]1456; GFX8-NEXT:    v_mul_lo_u32 v1, v12, v01457; GFX8-NEXT:    v_mul_lo_u32 v2, v11, v41458; GFX8-NEXT:    v_mul_hi_u32 v3, v11, v01459; GFX8-NEXT:    v_mul_hi_u32 v0, v12, v01460; GFX8-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[0:1]1461; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v21462; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1463; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31464; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1465; GFX8-NEXT:    v_mul_lo_u32 v3, v12, v41466; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11467; GFX8-NEXT:    v_mul_hi_u32 v2, v11, v41468; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v01469; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1470; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v21471; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1472; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v21473; GFX8-NEXT:    v_mul_hi_u32 v3, v12, v41474; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11475; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1476; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11477; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11478; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v11, v01479; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s5, v10, 01480; GFX8-NEXT:    v_addc_u32_e32 v11, vcc, v12, v1, vcc1481; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s5, v11, v[3:4]1482; GFX8-NEXT:    v_xor_b32_e32 v6, s16, v61483; GFX8-NEXT:    v_xor_b32_e32 v1, s17, v71484; GFX8-NEXT:    v_mov_b32_e32 v7, s171485; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s16, v61486; GFX8-NEXT:    v_subb_u32_e32 v1, vcc, v1, v7, vcc1487; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s20, v10, v[4:5]1488; GFX8-NEXT:    v_mul_lo_u32 v4, v11, v21489; GFX8-NEXT:    v_xor_b32_e32 v3, s4, v91490; GFX8-NEXT:    v_mul_lo_u32 v7, v10, v61491; GFX8-NEXT:    v_mul_hi_u32 v9, v10, v21492; GFX8-NEXT:    v_mul_hi_u32 v2, v11, v21493; GFX8-NEXT:    v_xor_b32_e32 v5, s4, v81494; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v71495; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1496; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v91497; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1498; GFX8-NEXT:    v_mul_lo_u32 v9, v11, v61499; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v7, v41500; GFX8-NEXT:    v_mul_hi_u32 v7, v10, v61501; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v9, v21502; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1503; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v71504; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1505; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v9, v71506; GFX8-NEXT:    v_mul_hi_u32 v6, v11, v61507; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v41508; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1509; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v7, v41510; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v6, v41511; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v10, v21512; GFX8-NEXT:    v_addc_u32_e32 v6, vcc, v11, v4, vcc1513; GFX8-NEXT:    v_mul_lo_u32 v7, s11, v21514; GFX8-NEXT:    v_mul_lo_u32 v9, s10, v61515; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, s4, v31516; GFX8-NEXT:    v_mul_hi_u32 v3, s10, v21517; GFX8-NEXT:    v_mov_b32_e32 v8, s41518; GFX8-NEXT:    v_subb_u32_e32 v5, vcc, v5, v8, vcc1519; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v91520; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1521; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v7, v31522; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1523; GFX8-NEXT:    v_mul_lo_u32 v7, s11, v61524; GFX8-NEXT:    v_mul_hi_u32 v2, s11, v21525; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v8, v31526; GFX8-NEXT:    v_mul_hi_u32 v8, s10, v61527; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v7, v21528; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1529; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v81530; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1531; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v81532; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v2, v31533; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1534; GFX8-NEXT:    v_mul_hi_u32 v6, s11, v61535; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v7, v21536; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v10, 01537; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v6, v71538; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s2, v11, v[3:4]1539; GFX8-NEXT:    v_mov_b32_e32 v12, s111540; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s10, v21541; GFX8-NEXT:    v_mad_u64_u32 v[8:9], s[0:1], s3, v10, v[6:7]1542; GFX8-NEXT:    v_mov_b32_e32 v3, s31543; GFX8-NEXT:    v_subb_u32_e64 v6, s[0:1], v12, v8, vcc1544; GFX8-NEXT:    v_sub_u32_e64 v7, s[0:1], s11, v81545; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v61546; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]1547; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v21548; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]1549; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v61550; GFX8-NEXT:    v_subb_u32_e32 v7, vcc, v7, v3, vcc1551; GFX8-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]1552; GFX8-NEXT:    v_subrev_u32_e32 v9, vcc, s2, v21553; GFX8-NEXT:    v_subbrev_u32_e64 v12, s[0:1], 0, v7, vcc1554; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v121555; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]1556; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v91557; GFX8-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]1558; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v121559; GFX8-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]1560; GFX8-NEXT:    v_add_u32_e64 v14, s[0:1], 1, v101561; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v7, v3, vcc1562; GFX8-NEXT:    v_addc_u32_e64 v15, s[0:1], 0, v11, s[0:1]1563; GFX8-NEXT:    v_add_u32_e32 v7, vcc, 1, v141564; GFX8-NEXT:    v_addc_u32_e32 v16, vcc, 0, v15, vcc1565; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v131566; GFX8-NEXT:    v_subrev_u32_e64 v13, s[0:1], s2, v91567; GFX8-NEXT:    v_subbrev_u32_e64 v3, s[0:1], 0, v3, s[0:1]1568; GFX8-NEXT:    v_cndmask_b32_e32 v7, v14, v7, vcc1569; GFX8-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc1570; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v81571; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v13, vcc1572; GFX8-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc1573; GFX8-NEXT:    v_cndmask_b32_e64 v7, v10, v7, s[0:1]1574; GFX8-NEXT:    v_cndmask_b32_e64 v8, v11, v14, s[0:1]1575; GFX8-NEXT:    v_cndmask_b32_e64 v9, v2, v9, s[0:1]1576; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, v3, s[0:1]1577; GFX8-NEXT:    s_xor_b64 s[0:1], s[6:7], s[8:9]1578; GFX8-NEXT:    v_xor_b32_e32 v2, s0, v71579; GFX8-NEXT:    v_xor_b32_e32 v3, s1, v81580; GFX8-NEXT:    v_mov_b32_e32 v7, s11581; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s0, v21582; GFX8-NEXT:    v_subb_u32_e32 v3, vcc, v3, v7, vcc1583; GFX8-NEXT:    v_xor_b32_e32 v7, s6, v91584; GFX8-NEXT:    v_xor_b32_e32 v8, s6, v61585; GFX8-NEXT:    v_mov_b32_e32 v9, s61586; GFX8-NEXT:    v_subrev_u32_e32 v6, vcc, s6, v71587; GFX8-NEXT:    v_subb_u32_e32 v7, vcc, v8, v9, vcc1588; GFX8-NEXT:    v_mov_b32_e32 v8, s121589; GFX8-NEXT:    v_mov_b32_e32 v9, s131590; GFX8-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]1591; GFX8-NEXT:    s_nop 01592; GFX8-NEXT:    v_mov_b32_e32 v0, s141593; GFX8-NEXT:    v_mov_b32_e32 v1, s151594; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[4:7]1595; GFX8-NEXT:    s_endpgm1596;1597; GFX9-LABEL: sdivrem_v2i64:1598; GFX9:       ; %bb.0:1599; GFX9-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x01600; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x201601; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1602; GFX9-NEXT:    s_ashr_i32 s4, s17, 311603; GFX9-NEXT:    s_ashr_i32 s6, s1, 311604; GFX9-NEXT:    s_add_u32 s10, s16, s41605; GFX9-NEXT:    s_addc_u32 s11, s17, s41606; GFX9-NEXT:    s_add_u32 s0, s0, s61607; GFX9-NEXT:    s_mov_b32 s7, s61608; GFX9-NEXT:    s_addc_u32 s1, s1, s61609; GFX9-NEXT:    s_xor_b64 s[8:9], s[0:1], s[6:7]1610; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s91611; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s81612; GFX9-NEXT:    s_mov_b32 s5, s41613; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[4:5]1614; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v01615; GFX9-NEXT:    v_add_f32_e32 v0, v0, v11616; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01617; GFX9-NEXT:    s_sub_u32 s16, 0, s81618; GFX9-NEXT:    s_subb_u32 s17, 0, s91619; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01620; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01621; GFX9-NEXT:    v_trunc_f32_e32 v1, v11622; GFX9-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11623; GFX9-NEXT:    v_add_f32_e32 v0, v2, v01624; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v01625; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v11626; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s16, v6, 01627; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s16, v7, v[1:2]1628; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v01629; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s17, v6, v[2:3]1630; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v01631; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v01632; GFX9-NEXT:    v_mul_lo_u32 v3, v6, v41633; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v41634; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v41635; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v31636; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1637; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v5, v01638; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc1639; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v21640; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1641; GFX9-NEXT:    v_add_u32_e32 v1, v3, v11642; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v41643; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v81644; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1645; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v11646; GFX9-NEXT:    v_add_u32_e32 v2, v5, v21647; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1648; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v31649; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v01650; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v1, vcc1651; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s16, v6, 01652; GFX9-NEXT:    v_mov_b32_e32 v8, s111653; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s16, v7, v[1:2]1654; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v01655; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s17, v6, v[2:3]1656; GFX9-NEXT:    v_mul_hi_u32 v3, v6, v01657; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v01658; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v41659; GFX9-NEXT:    s_xor_b64 s[16:17], s[4:5], s[6:7]1660; GFX9-NEXT:    s_ashr_i32 s6, s19, 311661; GFX9-NEXT:    s_mov_b32 s7, s61662; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v21663; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1664; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v31665; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1666; GFX9-NEXT:    v_mul_lo_u32 v3, v7, v41667; GFX9-NEXT:    v_add_u32_e32 v1, v2, v11668; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v41669; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v01670; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1671; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v21672; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1673; GFX9-NEXT:    v_add_u32_e32 v2, v3, v21674; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v41675; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v11676; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1677; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v31678; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v01679; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v1, vcc1680; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v01681; GFX9-NEXT:    v_mul_lo_u32 v3, s10, v11682; GFX9-NEXT:    v_mul_hi_u32 v4, s10, v01683; GFX9-NEXT:    v_mul_hi_u32 v0, s11, v01684; GFX9-NEXT:    v_mul_hi_u32 v5, s11, v11685; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v31686; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1687; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v41688; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1689; GFX9-NEXT:    v_mul_lo_u32 v4, s11, v11690; GFX9-NEXT:    v_add_u32_e32 v2, v3, v21691; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v11692; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v01693; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1694; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v31695; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1696; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v0, v21697; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s8, v6, 01698; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1699; GFX9-NEXT:    v_add_u32_e32 v3, v4, v31700; GFX9-NEXT:    v_add3_u32 v7, v3, v2, v51701; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s8, v7, v[1:2]1702; GFX9-NEXT:    v_sub_co_u32_e32 v9, vcc, s10, v01703; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s9, v6, v[2:3]1704; GFX9-NEXT:    v_mov_b32_e32 v1, s91705; GFX9-NEXT:    v_subb_co_u32_e64 v8, s[0:1], v8, v4, vcc1706; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v81707; GFX9-NEXT:    v_sub_u32_e32 v0, s11, v41708; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]1709; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v91710; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1711; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v81712; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v1, vcc1713; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v3, s[0:1]1714; GFX9-NEXT:    v_subrev_co_u32_e32 v3, vcc, s8, v91715; GFX9-NEXT:    v_subbrev_co_u32_e64 v4, s[0:1], 0, v0, vcc1716; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], 1, v61717; GFX9-NEXT:    v_addc_co_u32_e64 v10, s[0:1], 0, v7, s[0:1]1718; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s9, v41719; GFX9-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]1720; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s8, v31721; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v1, vcc1722; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]1723; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s9, v41724; GFX9-NEXT:    v_subrev_co_u32_e32 v14, vcc, s8, v31725; GFX9-NEXT:    s_ashr_i32 s8, s3, 311726; GFX9-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]1727; GFX9-NEXT:    v_add_co_u32_e64 v12, s[0:1], 1, v51728; GFX9-NEXT:    s_add_u32 s10, s18, s61729; GFX9-NEXT:    v_addc_co_u32_e64 v13, s[0:1], 0, v10, s[0:1]1730; GFX9-NEXT:    s_addc_u32 s11, s19, s61731; GFX9-NEXT:    s_add_u32 s0, s2, s81732; GFX9-NEXT:    s_mov_b32 s9, s81733; GFX9-NEXT:    s_addc_u32 s1, s3, s81734; GFX9-NEXT:    s_xor_b64 s[2:3], s[0:1], s[8:9]1735; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s31736; GFX9-NEXT:    v_subbrev_co_u32_e32 v15, vcc, 0, v0, vcc1737; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s21738; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v11739; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v21740; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v111741; GFX9-NEXT:    v_add_f32_e32 v0, v1, v01742; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01743; GFX9-NEXT:    s_xor_b64 s[10:11], s[10:11], s[6:7]1744; GFX9-NEXT:    s_sub_u32 s5, 0, s21745; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v12, vcc1746; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01747; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01748; GFX9-NEXT:    v_trunc_f32_e32 v1, v11749; GFX9-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11750; GFX9-NEXT:    v_add_f32_e32 v0, v2, v01751; GFX9-NEXT:    v_cvt_u32_f32_e32 v11, v01752; GFX9-NEXT:    v_cvt_u32_f32_e32 v12, v11753; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v13, vcc1754; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, v10, s[0:1]1755; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[18:19], s5, v11, 01756; GFX9-NEXT:    v_cndmask_b32_e32 v10, v3, v14, vcc1757; GFX9-NEXT:    s_subb_u32 s20, 0, s31758; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[18:19], s5, v12, v[1:2]1759; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, v5, s[0:1]1760; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v15, vcc1761; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[18:19], s20, v11, v[2:3]1762; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v1, s[0:1]1763; GFX9-NEXT:    v_mul_lo_u32 v1, v12, v01764; GFX9-NEXT:    v_mul_lo_u32 v2, v11, v41765; GFX9-NEXT:    v_mul_hi_u32 v3, v11, v01766; GFX9-NEXT:    v_mul_hi_u32 v0, v12, v01767; GFX9-NEXT:    v_cndmask_b32_e64 v9, v9, v10, s[0:1]1768; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v21769; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1770; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v31771; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1772; GFX9-NEXT:    v_mul_lo_u32 v3, v12, v41773; GFX9-NEXT:    v_add_u32_e32 v1, v2, v11774; GFX9-NEXT:    v_mul_hi_u32 v2, v11, v41775; GFX9-NEXT:    v_xor_b32_e32 v6, s16, v61776; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v01777; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1778; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v21779; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1780; GFX9-NEXT:    v_add_u32_e32 v2, v3, v21781; GFX9-NEXT:    v_mul_hi_u32 v3, v12, v41782; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v11783; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1784; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v11, v01785; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v31786; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s5, v10, 01787; GFX9-NEXT:    v_addc_co_u32_e32 v11, vcc, v12, v1, vcc1788; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s5, v11, v[3:4]1789; GFX9-NEXT:    v_xor_b32_e32 v1, s17, v71790; GFX9-NEXT:    v_mov_b32_e32 v7, s171791; GFX9-NEXT:    v_subrev_co_u32_e32 v0, vcc, s16, v61792; GFX9-NEXT:    v_subb_co_u32_e32 v1, vcc, v1, v7, vcc1793; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s20, v10, v[4:5]1794; GFX9-NEXT:    v_mul_lo_u32 v4, v11, v21795; GFX9-NEXT:    v_xor_b32_e32 v3, s4, v91796; GFX9-NEXT:    v_mul_lo_u32 v7, v10, v61797; GFX9-NEXT:    v_mul_hi_u32 v9, v10, v21798; GFX9-NEXT:    v_mul_hi_u32 v2, v11, v21799; GFX9-NEXT:    v_xor_b32_e32 v5, s4, v81800; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v71801; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1802; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v91803; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1804; GFX9-NEXT:    v_mul_lo_u32 v9, v11, v61805; GFX9-NEXT:    v_add_u32_e32 v4, v7, v41806; GFX9-NEXT:    v_mul_hi_u32 v7, v10, v61807; GFX9-NEXT:    v_mul_hi_u32 v6, v11, v61808; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v9, v21809; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1810; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v71811; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1812; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v41813; GFX9-NEXT:    v_add_u32_e32 v7, v9, v71814; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1815; GFX9-NEXT:    v_add3_u32 v4, v7, v4, v61816; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v10, v21817; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v11, v4, vcc1818; GFX9-NEXT:    v_mul_lo_u32 v7, s11, v21819; GFX9-NEXT:    v_mul_lo_u32 v9, s10, v61820; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s4, v31821; GFX9-NEXT:    v_mul_hi_u32 v3, s10, v21822; GFX9-NEXT:    v_mov_b32_e32 v8, s41823; GFX9-NEXT:    v_subb_co_u32_e32 v5, vcc, v5, v8, vcc1824; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, v7, v91825; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1826; GFX9-NEXT:    v_add_co_u32_e32 v3, vcc, v7, v31827; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1828; GFX9-NEXT:    v_mul_lo_u32 v7, s11, v61829; GFX9-NEXT:    v_mul_hi_u32 v2, s11, v21830; GFX9-NEXT:    v_add_u32_e32 v3, v8, v31831; GFX9-NEXT:    v_mul_hi_u32 v8, s10, v61832; GFX9-NEXT:    v_mul_hi_u32 v6, s11, v61833; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v7, v21834; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1835; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v81836; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1837; GFX9-NEXT:    v_add_co_u32_e32 v10, vcc, v2, v31838; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v10, 01839; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1840; GFX9-NEXT:    v_add_u32_e32 v7, v7, v81841; GFX9-NEXT:    v_add3_u32 v11, v7, v9, v61842; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s2, v11, v[3:4]1843; GFX9-NEXT:    v_mov_b32_e32 v12, s111844; GFX9-NEXT:    v_sub_co_u32_e32 v2, vcc, s10, v21845; GFX9-NEXT:    v_mad_u64_u32 v[8:9], s[0:1], s3, v10, v[6:7]1846; GFX9-NEXT:    v_mov_b32_e32 v3, s31847; GFX9-NEXT:    v_subb_co_u32_e64 v6, s[0:1], v12, v8, vcc1848; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v61849; GFX9-NEXT:    v_sub_u32_e32 v7, s11, v81850; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, -1, s[0:1]1851; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v21852; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]1853; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v61854; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, v7, v3, vcc1855; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]1856; GFX9-NEXT:    v_subrev_co_u32_e32 v9, vcc, s2, v21857; GFX9-NEXT:    v_subbrev_co_u32_e64 v12, s[0:1], 0, v7, vcc1858; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s3, v121859; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]1860; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v91861; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]1862; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s3, v121863; GFX9-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]1864; GFX9-NEXT:    v_add_co_u32_e64 v14, s[0:1], 1, v101865; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v7, v3, vcc1866; GFX9-NEXT:    v_addc_co_u32_e64 v15, s[0:1], 0, v11, s[0:1]1867; GFX9-NEXT:    v_add_co_u32_e32 v7, vcc, 1, v141868; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, 0, v15, vcc1869; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v131870; GFX9-NEXT:    v_cndmask_b32_e32 v7, v14, v7, vcc1871; GFX9-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc1872; GFX9-NEXT:    v_subrev_co_u32_e64 v15, s[0:1], s2, v91873; GFX9-NEXT:    v_subbrev_co_u32_e64 v3, s[0:1], 0, v3, s[0:1]1874; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v81875; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc1876; GFX9-NEXT:    v_cndmask_b32_e32 v3, v12, v3, vcc1877; GFX9-NEXT:    v_cndmask_b32_e64 v7, v10, v7, s[0:1]1878; GFX9-NEXT:    v_cndmask_b32_e64 v8, v11, v14, s[0:1]1879; GFX9-NEXT:    v_cndmask_b32_e64 v9, v2, v9, s[0:1]1880; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, v3, s[0:1]1881; GFX9-NEXT:    s_xor_b64 s[0:1], s[6:7], s[8:9]1882; GFX9-NEXT:    v_xor_b32_e32 v2, s0, v71883; GFX9-NEXT:    v_xor_b32_e32 v3, s1, v81884; GFX9-NEXT:    v_mov_b32_e32 v7, s11885; GFX9-NEXT:    v_subrev_co_u32_e32 v2, vcc, s0, v21886; GFX9-NEXT:    v_subb_co_u32_e32 v3, vcc, v3, v7, vcc1887; GFX9-NEXT:    v_xor_b32_e32 v7, s6, v91888; GFX9-NEXT:    v_mov_b32_e32 v13, 01889; GFX9-NEXT:    v_xor_b32_e32 v8, s6, v61890; GFX9-NEXT:    v_mov_b32_e32 v9, s61891; GFX9-NEXT:    v_subrev_co_u32_e32 v6, vcc, s6, v71892; GFX9-NEXT:    v_subb_co_u32_e32 v7, vcc, v8, v9, vcc1893; GFX9-NEXT:    global_store_dwordx4 v13, v[0:3], s[12:13]1894; GFX9-NEXT:    global_store_dwordx4 v13, v[4:7], s[14:15]1895; GFX9-NEXT:    s_endpgm1896;1897; GFX10-LABEL: sdivrem_v2i64:1898; GFX10:       ; %bb.0:1899; GFX10-NEXT:    s_clause 0x11900; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x201901; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x01902; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1903; GFX10-NEXT:    s_ashr_i32 s8, s1, 311904; GFX10-NEXT:    s_ashr_i32 s4, s17, 311905; GFX10-NEXT:    s_mov_b32 s9, s81906; GFX10-NEXT:    s_add_u32 s10, s16, s41907; GFX10-NEXT:    s_addc_u32 s11, s17, s41908; GFX10-NEXT:    s_add_u32 s0, s0, s81909; GFX10-NEXT:    s_addc_u32 s1, s1, s81910; GFX10-NEXT:    s_mov_b32 s5, s41911; GFX10-NEXT:    s_xor_b64 s[6:7], s[0:1], s[8:9]1912; GFX10-NEXT:    s_xor_b64 s[0:1], s[10:11], s[4:5]1913; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s71914; GFX10-NEXT:    s_sub_u32 s21, 0, s61915; GFX10-NEXT:    s_subb_u32 s20, 0, s71916; GFX10-NEXT:    s_xor_b64 s[16:17], s[4:5], s[8:9]1917; GFX10-NEXT:    s_ashr_i32 s8, s19, 311918; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s61919; GFX10-NEXT:    s_ashr_i32 s10, s3, 311920; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v11921; GFX10-NEXT:    s_add_u32 s18, s18, s81922; GFX10-NEXT:    s_addc_u32 s19, s19, s81923; GFX10-NEXT:    s_add_u32 s2, s2, s101924; GFX10-NEXT:    s_mov_b32 s11, s101925; GFX10-NEXT:    s_addc_u32 s3, s3, s101926; GFX10-NEXT:    v_add_f32_e32 v0, v1, v01927; GFX10-NEXT:    s_xor_b64 s[2:3], s[2:3], s[10:11]1928; GFX10-NEXT:    s_mov_b32 s9, s81929; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s31930; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s21931; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v01932; GFX10-NEXT:    s_xor_b64 s[18:19], s[18:19], s[8:9]1933; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v11934; GFX10-NEXT:    v_add_f32_e32 v1, v1, v21935; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01936; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v11937; GFX10-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v01938; GFX10-NEXT:    v_trunc_f32_e32 v2, v21939; GFX10-NEXT:    v_mul_f32_e32 v3, 0x5f7ffffc, v11940; GFX10-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v21941; GFX10-NEXT:    v_cvt_u32_f32_e32 v7, v21942; GFX10-NEXT:    v_mul_f32_e32 v4, 0x2f800000, v31943; GFX10-NEXT:    v_add_f32_e32 v0, v1, v01944; GFX10-NEXT:    v_trunc_f32_e32 v5, v41945; GFX10-NEXT:    v_cvt_u32_f32_e32 v6, v01946; GFX10-NEXT:    v_mul_f32_e32 v4, 0xcf800000, v51947; GFX10-NEXT:    v_cvt_u32_f32_e32 v9, v51948; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s5, s21, v6, 01949; GFX10-NEXT:    v_add_f32_e32 v3, v4, v31950; GFX10-NEXT:    v_cvt_u32_f32_e32 v8, v31951; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s5, s21, v7, v[1:2]1952; GFX10-NEXT:    s_sub_u32 s5, 0, s21953; GFX10-NEXT:    v_mul_lo_u32 v10, v7, v01954; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s23, s5, v8, 01955; GFX10-NEXT:    s_subb_u32 s22, 0, s31956; GFX10-NEXT:    v_mul_hi_u32 v12, v7, v01957; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s23, s20, v6, v[3:4]1958; GFX10-NEXT:    v_mul_hi_u32 v11, v6, v01959; GFX10-NEXT:    v_mul_hi_u32 v14, v9, v11960; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s23, s5, v9, v[2:3]1961; GFX10-NEXT:    v_mul_hi_u32 v5, v8, v11962; GFX10-NEXT:    v_mul_lo_u32 v13, v6, v31963; GFX10-NEXT:    v_mul_lo_u32 v15, v7, v31964; GFX10-NEXT:    v_mul_lo_u32 v2, v9, v11965; GFX10-NEXT:    v_mul_hi_u32 v16, v6, v31966; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s23, s22, v8, v[4:5]1967; GFX10-NEXT:    v_mul_hi_u32 v1, v7, v31968; GFX10-NEXT:    v_add_co_u32 v3, s23, v10, v131969; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s231970; GFX10-NEXT:    v_add_co_u32 v10, s23, v15, v121971; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s231972; GFX10-NEXT:    v_mul_lo_u32 v13, v8, v01973; GFX10-NEXT:    v_add_co_u32 v3, s23, v3, v111974; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s231975; GFX10-NEXT:    v_mul_lo_u32 v15, v9, v01976; GFX10-NEXT:    v_add_co_u32 v10, s23, v10, v161977; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s231978; GFX10-NEXT:    v_mul_hi_u32 v16, v8, v01979; GFX10-NEXT:    v_mul_hi_u32 v17, v9, v01980; GFX10-NEXT:    v_add_nc_u32_e32 v0, v4, v31981; GFX10-NEXT:    v_add_co_u32 v2, s23, v2, v131982; GFX10-NEXT:    v_add_nc_u32_e32 v3, v12, v111983; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s231984; GFX10-NEXT:    v_add_co_u32 v11, s23, v15, v141985; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s231986; GFX10-NEXT:    v_add_co_u32 v0, s23, v10, v01987; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s231988; GFX10-NEXT:    v_add_co_u32 v2, s23, v2, v51989; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s231990; GFX10-NEXT:    v_add_co_u32 v6, vcc_lo, v6, v01991; GFX10-NEXT:    v_add3_u32 v1, v3, v10, v11992; GFX10-NEXT:    v_add_co_u32 v5, s23, v11, v161993; GFX10-NEXT:    v_add_nc_u32_e32 v2, v4, v21994; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s231995; GFX10-NEXT:    v_add_co_ci_u32_e32 v7, vcc_lo, v7, v1, vcc_lo1996; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s23, s21, v6, 01997; GFX10-NEXT:    v_add_co_u32 v2, s23, v5, v21998; GFX10-NEXT:    v_add_nc_u32_e32 v3, v12, v111999; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s232000; GFX10-NEXT:    v_add_co_u32 v8, vcc_lo, v8, v22001; GFX10-NEXT:    v_mul_lo_u32 v10, v7, v02002; GFX10-NEXT:    v_add3_u32 v5, v3, v4, v172003; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s21, s21, v7, v[1:2]2004; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s21, s5, v8, 02005; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v9, v5, vcc_lo2006; GFX10-NEXT:    v_mul_hi_u32 v12, v7, v02007; GFX10-NEXT:    v_mul_hi_u32 v11, v6, v02008; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s20, s20, v6, v[3:4]2009; GFX10-NEXT:    v_mul_hi_u32 v14, v9, v12010; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s5, s5, v9, v[2:3]2011; GFX10-NEXT:    v_mul_hi_u32 v5, v8, v12012; GFX10-NEXT:    v_mul_lo_u32 v13, v6, v32013; GFX10-NEXT:    v_mul_lo_u32 v15, v7, v32014; GFX10-NEXT:    v_mul_lo_u32 v2, v9, v12015; GFX10-NEXT:    v_mul_hi_u32 v16, v6, v32016; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s5, s22, v8, v[4:5]2017; GFX10-NEXT:    v_mul_hi_u32 v1, v7, v32018; GFX10-NEXT:    v_add_co_u32 v3, s5, v10, v132019; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s52020; GFX10-NEXT:    v_add_co_u32 v10, s5, v15, v122021; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s52022; GFX10-NEXT:    v_mul_lo_u32 v13, v8, v02023; GFX10-NEXT:    v_add_co_u32 v3, s5, v3, v112024; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s52025; GFX10-NEXT:    v_mul_lo_u32 v15, v9, v02026; GFX10-NEXT:    v_add_co_u32 v10, s5, v10, v162027; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s52028; GFX10-NEXT:    v_add_nc_u32_e32 v3, v4, v32029; GFX10-NEXT:    v_add_co_u32 v2, s5, v2, v132030; GFX10-NEXT:    v_mul_hi_u32 v16, v8, v02031; GFX10-NEXT:    v_add_nc_u32_e32 v4, v12, v112032; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s52033; GFX10-NEXT:    v_add_co_u32 v12, s5, v15, v142034; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s52035; GFX10-NEXT:    v_add_co_u32 v3, s5, v10, v32036; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s52037; GFX10-NEXT:    v_add_co_u32 v2, s5, v2, v52038; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s52039; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v6, v32040; GFX10-NEXT:    v_add3_u32 v1, v4, v10, v12041; GFX10-NEXT:    v_add_co_u32 v5, s5, v12, v162042; GFX10-NEXT:    v_add_nc_u32_e32 v2, v11, v22043; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s52044; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v7, v1, vcc_lo2045; GFX10-NEXT:    v_mul_hi_u32 v0, v9, v02046; GFX10-NEXT:    v_mul_lo_u32 v6, s1, v32047; GFX10-NEXT:    v_add_co_u32 v2, s5, v5, v22048; GFX10-NEXT:    v_mul_lo_u32 v10, s0, v12049; GFX10-NEXT:    v_add_nc_u32_e32 v4, v13, v122050; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s52051; GFX10-NEXT:    v_mul_hi_u32 v7, s0, v32052; GFX10-NEXT:    v_mul_hi_u32 v3, s1, v32053; GFX10-NEXT:    v_mul_lo_u32 v11, s1, v12054; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v8, v22055; GFX10-NEXT:    v_add3_u32 v0, v4, v5, v02056; GFX10-NEXT:    v_mul_hi_u32 v4, s0, v12057; GFX10-NEXT:    v_mul_hi_u32 v5, s1, v12058; GFX10-NEXT:    v_add_co_u32 v1, s5, v6, v102059; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s52060; GFX10-NEXT:    v_add_co_u32 v3, s5, v11, v32061; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s52062; GFX10-NEXT:    v_add_co_u32 v1, s5, v1, v72063; GFX10-NEXT:    v_add_co_ci_u32_e32 v8, vcc_lo, v9, v0, vcc_lo2064; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s52065; GFX10-NEXT:    v_mul_lo_u32 v0, s19, v22066; GFX10-NEXT:    v_add_co_u32 v3, s5, v3, v42067; GFX10-NEXT:    v_mul_lo_u32 v7, s18, v82068; GFX10-NEXT:    v_add_nc_u32_e32 v1, v6, v12069; GFX10-NEXT:    v_mul_hi_u32 v9, s18, v22070; GFX10-NEXT:    v_mul_hi_u32 v2, s19, v22071; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s52072; GFX10-NEXT:    v_mul_lo_u32 v6, s19, v82073; GFX10-NEXT:    v_add_co_u32 v3, s5, v3, v12074; GFX10-NEXT:    v_add_co_u32 v7, s20, v0, v72075; GFX10-NEXT:    v_add_nc_u32_e32 v4, v10, v42076; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s52077; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s5, s6, v3, 02078; GFX10-NEXT:    v_mul_hi_u32 v11, s18, v82079; GFX10-NEXT:    v_add_co_u32 v6, s5, v6, v22080; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s52081; GFX10-NEXT:    v_add3_u32 v4, v4, v12, v52082; GFX10-NEXT:    v_add_co_u32 v2, s5, v7, v92083; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s52084; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, 1, s202085; GFX10-NEXT:    v_mul_hi_u32 v7, s19, v82086; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s5, s6, v4, v[1:2]2087; GFX10-NEXT:    v_add_co_u32 v6, s5, v6, v112088; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s52089; GFX10-NEXT:    v_add_nc_u32_e32 v5, v10, v52090; GFX10-NEXT:    v_add_co_u32 v10, vcc_lo, v3, 12091; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, 0, v4, vcc_lo2092; GFX10-NEXT:    v_add_nc_u32_e32 v8, v13, v22093; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s5, s7, v3, v[1:2]2094; GFX10-NEXT:    v_add_co_u32 v5, s5, v6, v52095; GFX10-NEXT:    v_sub_co_u32 v12, vcc_lo, s0, v02096; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s52097; GFX10-NEXT:    v_mov_b32_e32 v9, 02098; GFX10-NEXT:    v_sub_nc_u32_e32 v6, s1, v12099; GFX10-NEXT:    v_sub_co_ci_u32_e64 v13, s0, s1, v1, vcc_lo2100; GFX10-NEXT:    v_add3_u32 v7, v8, v2, v72101; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo2102; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s6, v122103; GFX10-NEXT:    v_cndmask_b32_e64 v14, 0, -1, vcc_lo2104; GFX10-NEXT:    v_sub_co_u32 v15, vcc_lo, v12, s62105; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v16, s0, 0, v6, vcc_lo2106; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s7, v132107; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v6, vcc_lo, s7, v6, vcc_lo2108; GFX10-NEXT:    v_cndmask_b32_e64 v17, 0, -1, s02109; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s6, v152110; GFX10-NEXT:    v_cndmask_b32_e64 v18, 0, -1, s02111; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s7, v162112; GFX10-NEXT:    v_cndmask_b32_e64 v19, 0, -1, s02113; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s2, v5, 02114; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s7, v132115; GFX10-NEXT:    v_cndmask_b32_e64 v14, v17, v14, s02116; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s7, v162117; GFX10-NEXT:    v_cndmask_b32_e64 v17, v19, v18, s02118; GFX10-NEXT:    v_add_co_u32 v18, s0, v10, 12119; GFX10-NEXT:    v_add_co_ci_u32_e64 v19, s0, 0, v11, s02120; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s0, s2, v7, v[1:2]2121; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v172122; GFX10-NEXT:    v_sub_co_u32 v2, s0, v15, s62123; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v6, s0, 0, v6, s02124; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v18, vcc_lo2125; GFX10-NEXT:    v_cndmask_b32_e32 v10, v11, v19, vcc_lo2126; GFX10-NEXT:    v_cndmask_b32_e32 v11, v15, v2, vcc_lo2127; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s1, s3, v5, v[1:2]2128; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v142129; GFX10-NEXT:    v_cndmask_b32_e64 v2, v3, v8, s02130; GFX10-NEXT:    v_cndmask_b32_e64 v3, v4, v10, s02131; GFX10-NEXT:    v_cndmask_b32_e32 v4, v16, v6, vcc_lo2132; GFX10-NEXT:    v_sub_co_u32 v8, vcc_lo, s18, v02133; GFX10-NEXT:    v_sub_co_ci_u32_e64 v10, s1, s19, v1, vcc_lo2134; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s19, v12135; GFX10-NEXT:    v_cndmask_b32_e64 v6, v12, v11, s02136; GFX10-NEXT:    v_cndmask_b32_e64 v4, v13, v4, s02137; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v102138; GFX10-NEXT:    v_xor_b32_e32 v0, s16, v22139; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v11, vcc_lo, s3, v1, vcc_lo2140; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v82141; GFX10-NEXT:    v_xor_b32_e32 v2, s17, v32142; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s02143; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, -1, vcc_lo2144; GFX10-NEXT:    v_sub_co_u32 v13, vcc_lo, v8, s22145; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v14, s0, 0, v11, vcc_lo2146; GFX10-NEXT:    v_sub_co_u32 v0, s0, v0, s162147; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v1, s0, s17, v2, s02148; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s3, v102149; GFX10-NEXT:    v_xor_b32_e32 v2, s4, v62150; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v11, vcc_lo, s3, v11, vcc_lo2151; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v12, s02152; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v142153; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s02154; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s2, v132155; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s02156; GFX10-NEXT:    v_add_co_u32 v15, s0, v5, 12157; GFX10-NEXT:    v_add_co_ci_u32_e64 v16, s0, 0, v7, s02158; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s3, v142159; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v12, s02160; GFX10-NEXT:    v_add_co_u32 v12, s0, v15, 12161; GFX10-NEXT:    v_add_co_ci_u32_e64 v17, s0, 0, v16, s02162; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v62163; GFX10-NEXT:    v_sub_co_u32 v6, s0, v13, s22164; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v11, s0, 0, v11, s02165; GFX10-NEXT:    v_cndmask_b32_e32 v12, v15, v12, vcc_lo2166; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v32167; GFX10-NEXT:    v_cndmask_b32_e32 v15, v16, v17, vcc_lo2168; GFX10-NEXT:    v_cndmask_b32_e32 v3, v13, v6, vcc_lo2169; GFX10-NEXT:    v_cndmask_b32_e32 v6, v14, v11, vcc_lo2170; GFX10-NEXT:    v_xor_b32_e32 v11, s4, v42171; GFX10-NEXT:    v_cndmask_b32_e64 v12, v5, v12, s02172; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v15, s02173; GFX10-NEXT:    v_cndmask_b32_e64 v3, v8, v3, s02174; GFX10-NEXT:    v_cndmask_b32_e64 v6, v10, v6, s02175; GFX10-NEXT:    s_xor_b64 s[0:1], s[8:9], s[10:11]2176; GFX10-NEXT:    v_sub_co_u32 v4, vcc_lo, v2, s42177; GFX10-NEXT:    v_xor_b32_e32 v2, s0, v122178; GFX10-NEXT:    v_xor_b32_e32 v7, s1, v72179; GFX10-NEXT:    v_xor_b32_e32 v8, s8, v32180; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v5, vcc_lo, s4, v11, vcc_lo2181; GFX10-NEXT:    v_xor_b32_e32 v10, s8, v62182; GFX10-NEXT:    v_sub_co_u32 v2, vcc_lo, v2, s02183; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v7, vcc_lo2184; GFX10-NEXT:    v_sub_co_u32 v6, vcc_lo, v8, s82185; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v7, vcc_lo, s8, v10, vcc_lo2186; GFX10-NEXT:    global_store_dwordx4 v9, v[0:3], s[12:13]2187; GFX10-NEXT:    global_store_dwordx4 v9, v[4:7], s[14:15]2188; GFX10-NEXT:    s_endpgm2189  %div = sdiv <2 x i64> %x, %y2190  store <2 x i64> %div, ptr addrspace(1) %out02191  %rem = srem <2 x i64> %x, %y2192  store <2 x i64> %rem, ptr addrspace(1) %out12193  ret void2194}2195 2196define amdgpu_kernel void @sdiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i8 %x, i8 %y) {2197; GFX8-LABEL: sdiv_i8:2198; GFX8:       ; %bb.0:2199; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x102200; GFX8-NEXT:    s_add_i32 s12, s12, s172201; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132202; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82203; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2204; GFX8-NEXT:    s_bfe_i32 s0, s4, 0x800082205; GFX8-NEXT:    s_ashr_i32 s5, s0, 312206; GFX8-NEXT:    s_add_i32 s0, s0, s52207; GFX8-NEXT:    s_xor_b32 s6, s0, s52208; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s62209; GFX8-NEXT:    s_sub_i32 s0, 0, s62210; GFX8-NEXT:    s_sext_i32_i8 s4, s42211; GFX8-NEXT:    s_ashr_i32 s7, s4, 312212; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02213; GFX8-NEXT:    s_add_i32 s4, s4, s72214; GFX8-NEXT:    s_xor_b32 s4, s4, s72215; GFX8-NEXT:    s_xor_b32 s5, s7, s52216; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02217; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02218; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v02219; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02220; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12221; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12222; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v02223; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2224; GFX8-NEXT:    v_mov_b32_e32 v0, s02225; GFX8-NEXT:    v_mov_b32_e32 v1, s12226; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s62227; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22228; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v32229; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32230; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2231; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v32232; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2233; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22234; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32235; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2236; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v32237; GFX8-NEXT:    v_xor_b32_e32 v2, s5, v22238; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2239; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s5, v22240; GFX8-NEXT:    v_xor_b32_e32 v3, s7, v32241; GFX8-NEXT:    flat_store_byte v[0:1], v22242; GFX8-NEXT:    v_mov_b32_e32 v0, s22243; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s7, v32244; GFX8-NEXT:    v_mov_b32_e32 v1, s32245; GFX8-NEXT:    flat_store_byte v[0:1], v32246; GFX8-NEXT:    s_endpgm2247;2248; GFX9-LABEL: sdiv_i8:2249; GFX9:       ; %bb.0:2250; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x102251; GFX9-NEXT:    v_mov_b32_e32 v2, 02252; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2253; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x800082254; GFX9-NEXT:    s_ashr_i32 s4, s1, 312255; GFX9-NEXT:    s_add_i32 s1, s1, s42256; GFX9-NEXT:    s_xor_b32 s5, s1, s42257; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s52258; GFX9-NEXT:    s_sub_i32 s1, 0, s52259; GFX9-NEXT:    s_sext_i32_i8 s0, s02260; GFX9-NEXT:    s_ashr_i32 s6, s0, 312261; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02262; GFX9-NEXT:    s_add_i32 s0, s0, s62263; GFX9-NEXT:    s_xor_b32 s7, s0, s62264; GFX9-NEXT:    s_xor_b32 s4, s6, s42265; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02266; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02267; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v02268; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02269; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v12270; GFX9-NEXT:    v_add_u32_e32 v0, v0, v12271; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v02272; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s52273; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02274; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v12275; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v12276; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2277; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v12278; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2279; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02280; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v12281; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2282; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v12283; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2284; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v02285; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v02286; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v12287; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v12288; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2289; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]2290; GFX9-NEXT:    global_store_byte v2, v1, s[2:3]2291; GFX9-NEXT:    s_endpgm2292;2293; GFX10-LABEL: sdiv_i8:2294; GFX10:       ; %bb.0:2295; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102296; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2297; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x800082298; GFX10-NEXT:    s_sext_i32_i8 s0, s02299; GFX10-NEXT:    s_ashr_i32 s4, s1, 312300; GFX10-NEXT:    s_ashr_i32 s6, s0, 312301; GFX10-NEXT:    s_add_i32 s1, s1, s42302; GFX10-NEXT:    s_add_i32 s0, s0, s62303; GFX10-NEXT:    s_xor_b32 s5, s1, s42304; GFX10-NEXT:    s_xor_b32 s0, s0, s62305; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s52306; GFX10-NEXT:    s_sub_i32 s1, 0, s52307; GFX10-NEXT:    s_xor_b32 s4, s6, s42308; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02309; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02310; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02311; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v02312; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v12313; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v12314; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v02315; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s52316; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02317; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v12318; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02319; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v12320; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v12321; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2322; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2323; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02324; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v12325; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v12326; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2327; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2328; GFX10-NEXT:    v_mov_b32_e32 v2, 02329; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v02330; GFX10-NEXT:    v_xor_b32_e32 v1, s6, v12331; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v02332; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s6, v12333; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2334; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]2335; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]2336; GFX10-NEXT:    s_endpgm2337  %div = sdiv i8 %x, %y2338  store i8 %div, ptr addrspace(1) %out02339  %rem = srem i8 %x, %y2340  store i8 %rem, ptr addrspace(1) %out12341  ret void2342}2343 2344define amdgpu_kernel void @sdivrem_v2i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i8> %x, <2 x i8> %y) {2345; GFX8-LABEL: sdivrem_v2i8:2346; GFX8:       ; %bb.0:2347; GFX8-NEXT:    s_load_dword s2, s[8:9], 0x102348; GFX8-NEXT:    s_add_i32 s12, s12, s172349; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82350; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132351; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2352; GFX8-NEXT:    s_bfe_i32 s0, s2, 0x800102353; GFX8-NEXT:    s_ashr_i32 s3, s0, 312354; GFX8-NEXT:    s_add_i32 s0, s0, s32355; GFX8-NEXT:    s_xor_b32 s10, s0, s32356; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s102357; GFX8-NEXT:    s_sub_i32 s4, 0, s102358; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x800182359; GFX8-NEXT:    s_ashr_i32 s12, s1, 312360; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02361; GFX8-NEXT:    s_add_i32 s1, s1, s122362; GFX8-NEXT:    s_xor_b32 s13, s1, s122363; GFX8-NEXT:    s_sext_i32_i8 s0, s22364; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02365; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02366; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s132367; GFX8-NEXT:    s_ashr_i32 s11, s0, 312368; GFX8-NEXT:    s_add_i32 s0, s0, s112369; GFX8-NEXT:    v_mul_lo_u32 v1, s4, v02370; GFX8-NEXT:    s_xor_b32 s0, s0, s112371; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v22372; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02373; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12374; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12375; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v02376; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v22377; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v12378; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s102379; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02380; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v22381; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v22382; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2383; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s10, v22384; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc2385; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02386; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v22387; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2388; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s10, v22389; GFX8-NEXT:    s_sub_i32 s1, 0, s132390; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc2391; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v12392; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x800082393; GFX8-NEXT:    s_ashr_i32 s2, s1, 312394; GFX8-NEXT:    s_add_i32 s1, s1, s22395; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v32396; GFX8-NEXT:    s_xor_b32 s1, s1, s22397; GFX8-NEXT:    s_xor_b32 s0, s11, s32398; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v02399; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v32400; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v12401; GFX8-NEXT:    v_xor_b32_e32 v2, s11, v22402; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v02403; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s132404; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s11, v22405; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12406; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v32407; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v32408; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2409; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s13, v32410; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2411; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12412; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v32413; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2414; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s13, v32415; GFX8-NEXT:    s_xor_b32 s0, s2, s122416; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v12417; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2418; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v12419; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v12420; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v12421; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v32422; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2423; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2424; GFX8-NEXT:    v_mov_b32_e32 v0, s42425; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v32426; GFX8-NEXT:    v_mov_b32_e32 v1, s52427; GFX8-NEXT:    flat_store_short v[0:1], v42428; GFX8-NEXT:    v_and_b32_e32 v0, 0xff, v32429; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v02430; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2431; GFX8-NEXT:    v_mov_b32_e32 v0, s62432; GFX8-NEXT:    v_mov_b32_e32 v1, s72433; GFX8-NEXT:    flat_store_short v[0:1], v22434; GFX8-NEXT:    s_endpgm2435;2436; GFX9-LABEL: sdivrem_v2i8:2437; GFX9:       ; %bb.0:2438; GFX9-NEXT:    s_load_dword s4, s[8:9], 0x102439; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2440; GFX9-NEXT:    s_bfe_i32 s0, s4, 0x800102441; GFX9-NEXT:    s_ashr_i32 s5, s0, 312442; GFX9-NEXT:    s_add_i32 s0, s0, s52443; GFX9-NEXT:    s_xor_b32 s6, s0, s52444; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s62445; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02446; GFX9-NEXT:    s_bfe_i32 s8, s4, 0x800182447; GFX9-NEXT:    s_ashr_i32 s9, s8, 312448; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02449; GFX9-NEXT:    s_add_i32 s8, s8, s92450; GFX9-NEXT:    s_xor_b32 s8, s8, s92451; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s82452; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02453; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02454; GFX9-NEXT:    s_sub_i32 s10, 0, s62455; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v12456; GFX9-NEXT:    s_sext_i32_i8 s7, s42457; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v02458; GFX9-NEXT:    s_ashr_i32 s10, s7, 312459; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12460; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v12461; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v22462; GFX9-NEXT:    s_add_i32 s7, s7, s102463; GFX9-NEXT:    s_xor_b32 s7, s7, s102464; GFX9-NEXT:    s_sub_i32 s11, 0, s82465; GFX9-NEXT:    v_add_u32_e32 v0, v0, v22466; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v02467; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v12468; GFX9-NEXT:    s_bfe_i32 s4, s4, 0x800082469; GFX9-NEXT:    s_ashr_i32 s11, s4, 312470; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s62471; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v22472; GFX9-NEXT:    s_add_i32 s4, s4, s112473; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02474; GFX9-NEXT:    v_sub_u32_e32 v3, s7, v32475; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32476; GFX9-NEXT:    s_xor_b32 s4, s4, s112477; GFX9-NEXT:    v_add_u32_e32 v1, v1, v22478; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2479; GFX9-NEXT:    v_subrev_u32_e32 v4, s6, v32480; GFX9-NEXT:    v_mul_hi_u32 v1, s4, v12481; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2482; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02483; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32484; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2485; GFX9-NEXT:    v_subrev_u32_e32 v4, s6, v32486; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2487; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s82488; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12489; GFX9-NEXT:    s_xor_b32 s5, s10, s52490; GFX9-NEXT:    v_xor_b32_e32 v0, s5, v02491; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v32492; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v32493; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2494; GFX9-NEXT:    v_subrev_u32_e32 v4, s8, v32495; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2496; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12497; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s8, v32498; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2499; GFX9-NEXT:    s_xor_b32 s4, s11, s92500; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v12501; GFX9-NEXT:    v_subrev_u32_e32 v4, s8, v32502; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v12503; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2504; GFX9-NEXT:    v_and_b32_e32 v1, 0xff, v12505; GFX9-NEXT:    v_subrev_u32_e32 v0, s5, v02506; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v32507; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v12508; GFX9-NEXT:    v_subrev_u32_e32 v3, s11, v32509; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2510; GFX9-NEXT:    v_mov_b32_e32 v1, 02511; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v22512; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2513; GFX9-NEXT:    global_store_short v1, v0, s[0:1]2514; GFX9-NEXT:    v_and_b32_e32 v0, 0xff, v32515; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v22516; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v02517; GFX9-NEXT:    v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2518; GFX9-NEXT:    global_store_short v1, v0, s[2:3]2519; GFX9-NEXT:    s_endpgm2520;2521; GFX10-LABEL: sdivrem_v2i8:2522; GFX10:       ; %bb.0:2523; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102524; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2525; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x800182526; GFX10-NEXT:    s_bfe_i32 s3, s0, 0x800102527; GFX10-NEXT:    s_ashr_i32 s2, s1, 312528; GFX10-NEXT:    s_ashr_i32 s10, s3, 312529; GFX10-NEXT:    s_add_i32 s1, s1, s22530; GFX10-NEXT:    s_add_i32 s3, s3, s102531; GFX10-NEXT:    s_xor_b32 s1, s1, s22532; GFX10-NEXT:    s_xor_b32 s3, s3, s102533; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s12534; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s32535; GFX10-NEXT:    s_sub_i32 s4, 0, s12536; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02537; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v12538; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02539; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12540; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02541; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v12542; GFX10-NEXT:    v_mul_lo_u32 v2, s4, v02543; GFX10-NEXT:    s_sub_i32 s4, 0, s32544; GFX10-NEXT:    v_mul_lo_u32 v3, s4, v12545; GFX10-NEXT:    s_bfe_i32 s4, s0, 0x800082546; GFX10-NEXT:    s_sext_i32_i8 s0, s02547; GFX10-NEXT:    s_ashr_i32 s11, s4, 312548; GFX10-NEXT:    s_ashr_i32 s12, s0, 312549; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v22550; GFX10-NEXT:    s_add_i32 s4, s4, s112551; GFX10-NEXT:    s_add_i32 s0, s0, s122552; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v32553; GFX10-NEXT:    s_xor_b32 s4, s4, s112554; GFX10-NEXT:    s_xor_b32 s0, s0, s122555; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v22556; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v32557; GFX10-NEXT:    v_mul_hi_u32 v0, s4, v02558; GFX10-NEXT:    v_mul_hi_u32 v1, s0, v12559; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s12560; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02561; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s32562; GFX10-NEXT:    v_add_nc_u32_e32 v6, 1, v12563; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s4, v22564; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02565; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s0, v32566; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v22567; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s1, v22568; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v32569; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s3, v32570; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2571; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo2572; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s02573; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s02574; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02575; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v22576; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s1, v22577; GFX10-NEXT:    v_add_nc_u32_e32 v6, 1, v12578; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s3, v32579; GFX10-NEXT:    s_xor_b32 s1, s11, s22580; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2581; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s3, v32582; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo2583; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s02584; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v02585; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s02586; GFX10-NEXT:    v_xor_b32_e32 v2, s11, v22587; GFX10-NEXT:    s_xor_b32 s0, s12, s102588; GFX10-NEXT:    v_mov_b32_e32 v4, 0xff2589; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v12590; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v02591; GFX10-NEXT:    v_xor_b32_e32 v3, s12, v32592; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s11, v22593; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s0, v12594; GFX10-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2595; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s12, v32596; GFX10-NEXT:    v_and_b32_sdwa v2, v2, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2597; GFX10-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2598; GFX10-NEXT:    v_mov_b32_e32 v1, 02599; GFX10-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2600; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2601; GFX10-NEXT:    global_store_short v1, v0, s[4:5]2602; GFX10-NEXT:    global_store_short v1, v2, s[6:7]2603; GFX10-NEXT:    s_endpgm2604  %div = sdiv <2 x i8> %x, %y2605  store <2 x i8> %div, ptr addrspace(1) %out02606  %rem = srem <2 x i8> %x, %y2607  store <2 x i8> %rem, ptr addrspace(1) %out12608  ret void2609}2610 2611define amdgpu_kernel void @sdiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i16 %x, i16 %y) {2612; GFX8-LABEL: sdiv_i16:2613; GFX8:       ; %bb.0:2614; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x102615; GFX8-NEXT:    s_add_i32 s12, s12, s172616; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132617; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82618; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2619; GFX8-NEXT:    s_bfe_i32 s0, s4, 0x1000102620; GFX8-NEXT:    s_ashr_i32 s5, s0, 312621; GFX8-NEXT:    s_add_i32 s0, s0, s52622; GFX8-NEXT:    s_xor_b32 s6, s0, s52623; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s62624; GFX8-NEXT:    s_sub_i32 s0, 0, s62625; GFX8-NEXT:    s_sext_i32_i16 s4, s42626; GFX8-NEXT:    s_ashr_i32 s7, s4, 312627; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02628; GFX8-NEXT:    s_add_i32 s4, s4, s72629; GFX8-NEXT:    s_xor_b32 s4, s4, s72630; GFX8-NEXT:    s_xor_b32 s5, s7, s52631; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02632; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02633; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v02634; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02635; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12636; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12637; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v02638; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2639; GFX8-NEXT:    v_mov_b32_e32 v0, s02640; GFX8-NEXT:    v_mov_b32_e32 v1, s12641; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s62642; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22643; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v32644; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32645; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2646; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v32647; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2648; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22649; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v32650; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2651; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v32652; GFX8-NEXT:    v_xor_b32_e32 v2, s5, v22653; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2654; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s5, v22655; GFX8-NEXT:    v_xor_b32_e32 v3, s7, v32656; GFX8-NEXT:    flat_store_short v[0:1], v22657; GFX8-NEXT:    v_mov_b32_e32 v0, s22658; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s7, v32659; GFX8-NEXT:    v_mov_b32_e32 v1, s32660; GFX8-NEXT:    flat_store_short v[0:1], v32661; GFX8-NEXT:    s_endpgm2662;2663; GFX9-LABEL: sdiv_i16:2664; GFX9:       ; %bb.0:2665; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x102666; GFX9-NEXT:    v_mov_b32_e32 v2, 02667; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2668; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x1000102669; GFX9-NEXT:    s_ashr_i32 s4, s1, 312670; GFX9-NEXT:    s_add_i32 s1, s1, s42671; GFX9-NEXT:    s_xor_b32 s5, s1, s42672; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s52673; GFX9-NEXT:    s_sub_i32 s1, 0, s52674; GFX9-NEXT:    s_sext_i32_i16 s0, s02675; GFX9-NEXT:    s_ashr_i32 s6, s0, 312676; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02677; GFX9-NEXT:    s_add_i32 s0, s0, s62678; GFX9-NEXT:    s_xor_b32 s7, s0, s62679; GFX9-NEXT:    s_xor_b32 s4, s6, s42680; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02681; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02682; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v02683; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02684; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v12685; GFX9-NEXT:    v_add_u32_e32 v0, v0, v12686; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v02687; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s52688; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02689; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v12690; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v12691; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2692; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v12693; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2694; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02695; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v12696; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2697; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v12698; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2699; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v02700; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v02701; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v12702; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v12703; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2704; GFX9-NEXT:    global_store_short v2, v0, s[0:1]2705; GFX9-NEXT:    global_store_short v2, v1, s[2:3]2706; GFX9-NEXT:    s_endpgm2707;2708; GFX10-LABEL: sdiv_i16:2709; GFX10:       ; %bb.0:2710; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102711; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2712; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x1000102713; GFX10-NEXT:    s_sext_i32_i16 s0, s02714; GFX10-NEXT:    s_ashr_i32 s4, s1, 312715; GFX10-NEXT:    s_ashr_i32 s6, s0, 312716; GFX10-NEXT:    s_add_i32 s1, s1, s42717; GFX10-NEXT:    s_add_i32 s0, s0, s62718; GFX10-NEXT:    s_xor_b32 s5, s1, s42719; GFX10-NEXT:    s_xor_b32 s0, s0, s62720; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s52721; GFX10-NEXT:    s_sub_i32 s1, 0, s52722; GFX10-NEXT:    s_xor_b32 s4, s6, s42723; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02724; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02725; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02726; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v02727; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v12728; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v12729; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v02730; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s52731; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02732; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v12733; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02734; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v12735; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v12736; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2737; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2738; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02739; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v12740; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v12741; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2742; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2743; GFX10-NEXT:    v_mov_b32_e32 v2, 02744; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v02745; GFX10-NEXT:    v_xor_b32_e32 v1, s6, v12746; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v02747; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s6, v12748; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2749; GFX10-NEXT:    global_store_short v2, v0, s[0:1]2750; GFX10-NEXT:    global_store_short v2, v1, s[2:3]2751; GFX10-NEXT:    s_endpgm2752  %div = sdiv i16 %x, %y2753  store i16 %div, ptr addrspace(1) %out02754  %rem = srem i16 %x, %y2755  store i16 %rem, ptr addrspace(1) %out12756  ret void2757}2758 2759define amdgpu_kernel void @sdivrem_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i16> %x, <2 x i16> %y) {2760; GFX8-LABEL: sdivrem_v2i16:2761; GFX8:       ; %bb.0:2762; GFX8-NEXT:    s_load_dwordx2 s[2:3], s[8:9], 0x102763; GFX8-NEXT:    s_add_i32 s12, s12, s172764; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82765; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132766; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2767; GFX8-NEXT:    s_sext_i32_i16 s0, s32768; GFX8-NEXT:    s_ashr_i32 s10, s0, 312769; GFX8-NEXT:    s_add_i32 s0, s0, s102770; GFX8-NEXT:    s_xor_b32 s11, s0, s102771; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s112772; GFX8-NEXT:    s_sub_i32 s4, 0, s112773; GFX8-NEXT:    s_bfe_i32 s1, s3, 0x1000102774; GFX8-NEXT:    s_ashr_i32 s12, s1, 312775; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02776; GFX8-NEXT:    s_add_i32 s1, s1, s122777; GFX8-NEXT:    s_xor_b32 s13, s1, s122778; GFX8-NEXT:    s_sext_i32_i16 s0, s22779; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02780; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02781; GFX8-NEXT:    v_cvt_f32_u32_e32 v2, s132782; GFX8-NEXT:    s_ashr_i32 s3, s0, 312783; GFX8-NEXT:    s_add_i32 s0, s0, s32784; GFX8-NEXT:    v_mul_lo_u32 v1, s4, v02785; GFX8-NEXT:    s_xor_b32 s0, s0, s32786; GFX8-NEXT:    v_rcp_iflag_f32_e32 v2, v22787; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02788; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12789; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12790; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v02791; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v22792; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v12793; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s112794; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02795; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v22796; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v22797; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2798; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s11, v22799; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc2800; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02801; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v22802; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2803; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s11, v22804; GFX8-NEXT:    s_sub_i32 s1, 0, s132805; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc2806; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v12807; GFX8-NEXT:    s_bfe_i32 s1, s2, 0x1000102808; GFX8-NEXT:    s_ashr_i32 s2, s1, 312809; GFX8-NEXT:    s_add_i32 s1, s1, s22810; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v32811; GFX8-NEXT:    s_xor_b32 s1, s1, s22812; GFX8-NEXT:    s_xor_b32 s0, s3, s102813; GFX8-NEXT:    v_xor_b32_e32 v0, s0, v02814; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v32815; GFX8-NEXT:    v_mul_hi_u32 v1, s1, v12816; GFX8-NEXT:    v_xor_b32_e32 v2, s3, v22817; GFX8-NEXT:    v_subrev_u32_e32 v0, vcc, s0, v02818; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s132819; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s3, v22820; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12821; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s1, v32822; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v32823; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2824; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s13, v32825; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2826; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12827; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s13, v32828; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2829; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s13, v32830; GFX8-NEXT:    s_xor_b32 s0, s2, s122831; GFX8-NEXT:    v_xor_b32_e32 v1, s0, v12832; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2833; GFX8-NEXT:    v_subrev_u32_e32 v1, vcc, s0, v12834; GFX8-NEXT:    v_xor_b32_e32 v3, s2, v32835; GFX8-NEXT:    v_and_b32_e32 v1, 0xffff, v12836; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s2, v32837; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v12838; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2839; GFX8-NEXT:    v_and_b32_e32 v0, 0xffff, v32840; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 16, v02841; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2842; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2843; GFX8-NEXT:    v_mov_b32_e32 v0, s42844; GFX8-NEXT:    v_mov_b32_e32 v1, s52845; GFX8-NEXT:    flat_store_dword v[0:1], v42846; GFX8-NEXT:    v_mov_b32_e32 v0, s62847; GFX8-NEXT:    v_mov_b32_e32 v1, s72848; GFX8-NEXT:    flat_store_dword v[0:1], v22849; GFX8-NEXT:    s_endpgm2850;2851; GFX9-LABEL: sdivrem_v2i16:2852; GFX9:       ; %bb.0:2853; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x102854; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2855; GFX9-NEXT:    s_sext_i32_i16 s0, s52856; GFX9-NEXT:    s_ashr_i32 s6, s0, 312857; GFX9-NEXT:    s_add_i32 s0, s0, s62858; GFX9-NEXT:    s_xor_b32 s7, s0, s62859; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s72860; GFX9-NEXT:    s_bfe_i32 s5, s5, 0x1000102861; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02862; GFX9-NEXT:    s_ashr_i32 s9, s5, 312863; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02864; GFX9-NEXT:    s_add_i32 s5, s5, s92865; GFX9-NEXT:    s_xor_b32 s5, s5, s92866; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s52867; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02868; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02869; GFX9-NEXT:    s_sub_i32 s10, 0, s72870; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v12871; GFX9-NEXT:    s_sext_i32_i16 s8, s42872; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v02873; GFX9-NEXT:    s_ashr_i32 s10, s8, 312874; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12875; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v12876; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v22877; GFX9-NEXT:    s_add_i32 s8, s8, s102878; GFX9-NEXT:    s_xor_b32 s8, s8, s102879; GFX9-NEXT:    s_sub_i32 s11, 0, s52880; GFX9-NEXT:    v_add_u32_e32 v0, v0, v22881; GFX9-NEXT:    v_mul_hi_u32 v0, s8, v02882; GFX9-NEXT:    v_mul_lo_u32 v2, s11, v12883; GFX9-NEXT:    s_bfe_i32 s4, s4, 0x1000102884; GFX9-NEXT:    s_ashr_i32 s11, s4, 312885; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s72886; GFX9-NEXT:    v_mul_hi_u32 v2, v1, v22887; GFX9-NEXT:    s_add_i32 s4, s4, s112888; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02889; GFX9-NEXT:    v_sub_u32_e32 v3, s8, v32890; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v32891; GFX9-NEXT:    s_xor_b32 s4, s4, s112892; GFX9-NEXT:    v_add_u32_e32 v1, v1, v22893; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2894; GFX9-NEXT:    v_subrev_u32_e32 v4, s7, v32895; GFX9-NEXT:    v_mul_hi_u32 v1, s4, v12896; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2897; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02898; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v32899; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2900; GFX9-NEXT:    v_subrev_u32_e32 v4, s7, v32901; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v4, vcc2902; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s52903; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12904; GFX9-NEXT:    s_xor_b32 s6, s10, s62905; GFX9-NEXT:    v_xor_b32_e32 v0, s6, v02906; GFX9-NEXT:    v_sub_u32_e32 v3, s4, v32907; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32908; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2909; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v32910; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2911; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12912; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32913; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2914; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v32915; GFX9-NEXT:    s_xor_b32 s4, s11, s92916; GFX9-NEXT:    v_subrev_u32_e32 v0, s6, v02917; GFX9-NEXT:    v_xor_b32_e32 v2, s10, v22918; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2919; GFX9-NEXT:    v_xor_b32_e32 v1, s4, v12920; GFX9-NEXT:    v_subrev_u32_e32 v2, s10, v22921; GFX9-NEXT:    v_subrev_u32_e32 v1, s4, v12922; GFX9-NEXT:    v_xor_b32_e32 v3, s11, v32923; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v02924; GFX9-NEXT:    v_subrev_u32_e32 v3, s11, v32925; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v02926; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v22927; GFX9-NEXT:    v_mov_b32_e32 v2, 02928; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v12929; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2930; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]2931; GFX9-NEXT:    global_store_dword v2, v1, s[2:3]2932; GFX9-NEXT:    s_endpgm2933;2934; GFX10-LABEL: sdivrem_v2i16:2935; GFX10:       ; %bb.0:2936; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102937; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2938; GFX10-NEXT:    s_sext_i32_i16 s2, s12939; GFX10-NEXT:    s_bfe_i32 s1, s1, 0x1000102940; GFX10-NEXT:    s_ashr_i32 s3, s2, 312941; GFX10-NEXT:    s_ashr_i32 s10, s1, 312942; GFX10-NEXT:    s_add_i32 s2, s2, s32943; GFX10-NEXT:    s_add_i32 s1, s1, s102944; GFX10-NEXT:    s_xor_b32 s2, s2, s32945; GFX10-NEXT:    s_xor_b32 s1, s1, s102946; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s22947; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s12948; GFX10-NEXT:    s_sub_i32 s4, 0, s22949; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02950; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v12951; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02952; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12953; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02954; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v12955; GFX10-NEXT:    v_mul_lo_u32 v2, s4, v02956; GFX10-NEXT:    s_sub_i32 s4, 0, s12957; GFX10-NEXT:    v_mul_lo_u32 v3, s4, v12958; GFX10-NEXT:    s_sext_i32_i16 s4, s02959; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x1000102960; GFX10-NEXT:    s_ashr_i32 s11, s4, 312961; GFX10-NEXT:    s_ashr_i32 s12, s0, 312962; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v22963; GFX10-NEXT:    s_add_i32 s4, s4, s112964; GFX10-NEXT:    s_add_i32 s0, s0, s122965; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v32966; GFX10-NEXT:    s_xor_b32 s4, s4, s112967; GFX10-NEXT:    s_xor_b32 s0, s0, s122968; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v22969; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v32970; GFX10-NEXT:    v_mul_hi_u32 v0, s4, v02971; GFX10-NEXT:    v_mul_hi_u32 v1, s0, v12972; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s22973; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02974; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s12975; GFX10-NEXT:    v_add_nc_u32_e32 v6, 1, v12976; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s4, v22977; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02978; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s0, v32979; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22980; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s2, v22981; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32982; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2983; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s1, v32984; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo2985; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s02986; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v02987; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s02988; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22989; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s2, v22990; GFX10-NEXT:    v_add_nc_u32_e32 v6, 1, v12991; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32992; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc_lo2993; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s1, v32994; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo2995; GFX10-NEXT:    s_xor_b32 s1, s11, s32996; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s02997; GFX10-NEXT:    v_xor_b32_e32 v0, s1, v02998; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s02999; GFX10-NEXT:    v_xor_b32_e32 v2, s11, v23000; GFX10-NEXT:    s_xor_b32 s0, s12, s103001; GFX10-NEXT:    v_xor_b32_e32 v1, s0, v13002; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s1, v03003; GFX10-NEXT:    v_xor_b32_e32 v3, s12, v33004; GFX10-NEXT:    v_subrev_nc_u32_e32 v2, s11, v23005; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s0, v13006; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v03007; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s12, v33008; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v23009; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v03010; GFX10-NEXT:    v_mov_b32_e32 v1, 03011; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v23012; GFX10-NEXT:    s_waitcnt lgkmcnt(0)3013; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]3014; GFX10-NEXT:    global_store_dword v1, v2, s[6:7]3015; GFX10-NEXT:    s_endpgm3016  %div = sdiv <2 x i16> %x, %y3017  store <2 x i16> %div, ptr addrspace(1) %out03018  %rem = srem <2 x i16> %x, %y3019  store <2 x i16> %rem, ptr addrspace(1) %out13020  ret void3021}3022 3023define amdgpu_kernel void @sdivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i3 %x, i3 %y) {3024; GFX8-LABEL: sdivrem_i3:3025; GFX8:       ; %bb.0:3026; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x103027; GFX8-NEXT:    s_add_i32 s12, s12, s173028; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s133029; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 83030; GFX8-NEXT:    s_waitcnt lgkmcnt(0)3031; GFX8-NEXT:    s_bfe_i32 s0, s4, 0x300083032; GFX8-NEXT:    s_ashr_i32 s5, s0, 313033; GFX8-NEXT:    s_add_i32 s0, s0, s53034; GFX8-NEXT:    s_xor_b32 s6, s0, s53035; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s63036; GFX8-NEXT:    s_sub_i32 s0, 0, s63037; GFX8-NEXT:    s_bfe_i32 s4, s4, 0x300003038; GFX8-NEXT:    s_ashr_i32 s7, s4, 313039; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v03040; GFX8-NEXT:    s_add_i32 s4, s4, s73041; GFX8-NEXT:    s_xor_b32 s4, s4, s73042; GFX8-NEXT:    s_xor_b32 s5, s7, s53043; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03044; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v03045; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v03046; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03047; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v13048; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v13049; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v03050; GFX8-NEXT:    s_waitcnt lgkmcnt(0)3051; GFX8-NEXT:    v_mov_b32_e32 v0, s03052; GFX8-NEXT:    v_mov_b32_e32 v1, s13053; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s63054; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v23055; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v33056; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v33057; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc3058; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v33059; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc3060; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v23061; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v33062; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc3063; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v33064; GFX8-NEXT:    v_xor_b32_e32 v2, s5, v23065; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc3066; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s5, v23067; GFX8-NEXT:    v_xor_b32_e32 v3, s7, v33068; GFX8-NEXT:    v_and_b32_e32 v2, 7, v23069; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s7, v33070; GFX8-NEXT:    flat_store_byte v[0:1], v23071; GFX8-NEXT:    v_mov_b32_e32 v0, s23072; GFX8-NEXT:    v_and_b32_e32 v2, 7, v33073; GFX8-NEXT:    v_mov_b32_e32 v1, s33074; GFX8-NEXT:    flat_store_byte v[0:1], v23075; GFX8-NEXT:    s_endpgm3076;3077; GFX9-LABEL: sdivrem_i3:3078; GFX9:       ; %bb.0:3079; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x103080; GFX9-NEXT:    v_mov_b32_e32 v2, 03081; GFX9-NEXT:    s_waitcnt lgkmcnt(0)3082; GFX9-NEXT:    s_bfe_i32 s1, s0, 0x300083083; GFX9-NEXT:    s_ashr_i32 s4, s1, 313084; GFX9-NEXT:    s_add_i32 s1, s1, s43085; GFX9-NEXT:    s_xor_b32 s5, s1, s43086; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s53087; GFX9-NEXT:    s_sub_i32 s1, 0, s53088; GFX9-NEXT:    s_bfe_i32 s0, s0, 0x300003089; GFX9-NEXT:    s_ashr_i32 s6, s0, 313090; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v03091; GFX9-NEXT:    s_add_i32 s0, s0, s63092; GFX9-NEXT:    s_xor_b32 s7, s0, s63093; GFX9-NEXT:    s_xor_b32 s4, s6, s43094; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03095; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v03096; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v03097; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03098; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v13099; GFX9-NEXT:    v_add_u32_e32 v0, v0, v13100; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v03101; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s53102; GFX9-NEXT:    v_add_u32_e32 v3, 1, v03103; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v13104; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v13105; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3106; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v13107; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc3108; GFX9-NEXT:    v_add_u32_e32 v3, 1, v03109; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v13110; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3111; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v13112; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc3113; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v03114; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v03115; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v13116; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v13117; GFX9-NEXT:    v_and_b32_e32 v0, 7, v03118; GFX9-NEXT:    s_waitcnt lgkmcnt(0)3119; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]3120; GFX9-NEXT:    v_and_b32_e32 v0, 7, v13121; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]3122; GFX9-NEXT:    s_endpgm3123;3124; GFX10-LABEL: sdivrem_i3:3125; GFX10:       ; %bb.0:3126; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x103127; GFX10-NEXT:    s_waitcnt lgkmcnt(0)3128; GFX10-NEXT:    s_bfe_i32 s1, s0, 0x300083129; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x300003130; GFX10-NEXT:    s_ashr_i32 s4, s1, 313131; GFX10-NEXT:    s_ashr_i32 s5, s0, 313132; GFX10-NEXT:    s_add_i32 s1, s1, s43133; GFX10-NEXT:    s_add_i32 s0, s0, s53134; GFX10-NEXT:    s_xor_b32 s1, s1, s43135; GFX10-NEXT:    s_xor_b32 s0, s0, s53136; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s13137; GFX10-NEXT:    s_sub_i32 s2, 0, s13138; GFX10-NEXT:    s_xor_b32 s4, s5, s43139; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v03140; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03141; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v03142; GFX10-NEXT:    v_mul_lo_u32 v1, s2, v03143; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v13144; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v13145; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v03146; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s13147; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v03148; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v13149; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v13150; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v13151; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3152; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo3153; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v03154; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v13155; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v13156; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03157; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3158; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo3159; GFX10-NEXT:    v_mov_b32_e32 v2, 03160; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v03161; GFX10-NEXT:    v_xor_b32_e32 v1, s5, v13162; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v03163; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s5, v13164; GFX10-NEXT:    v_and_b32_e32 v0, 7, v03165; GFX10-NEXT:    v_and_b32_e32 v1, 7, v13166; GFX10-NEXT:    s_waitcnt lgkmcnt(0)3167; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]3168; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]3169; GFX10-NEXT:    s_endpgm3170  %div = sdiv i3 %x, %y3171  store i3 %div, ptr addrspace(1) %out03172  %rem = srem i3 %x, %y3173  store i3 %rem, ptr addrspace(1) %out13174  ret void3175}3176 3177define amdgpu_kernel void @sdivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i27 %x, i27 %y) {3178; GFX8-LABEL: sdivrem_i27:3179; GFX8:       ; %bb.0:3180; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x103181; GFX8-NEXT:    s_add_i32 s12, s12, s173182; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s133183; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 83184; GFX8-NEXT:    s_waitcnt lgkmcnt(0)3185; GFX8-NEXT:    s_bfe_i32 s0, s5, 0x1b00003186; GFX8-NEXT:    s_ashr_i32 s5, s0, 313187; GFX8-NEXT:    s_add_i32 s0, s0, s53188; GFX8-NEXT:    s_xor_b32 s6, s0, s53189; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s63190; GFX8-NEXT:    s_sub_i32 s0, 0, s63191; GFX8-NEXT:    s_bfe_i32 s4, s4, 0x1b00003192; GFX8-NEXT:    s_ashr_i32 s7, s4, 313193; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v03194; GFX8-NEXT:    s_add_i32 s4, s4, s73195; GFX8-NEXT:    s_xor_b32 s4, s4, s73196; GFX8-NEXT:    s_xor_b32 s5, s7, s53197; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03198; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v03199; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v03200; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03201; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v13202; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v13203; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v03204; GFX8-NEXT:    s_waitcnt lgkmcnt(0)3205; GFX8-NEXT:    v_mov_b32_e32 v0, s03206; GFX8-NEXT:    v_mov_b32_e32 v1, s13207; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s63208; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v23209; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v33210; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v33211; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc3212; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v33213; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc3214; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v23215; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s6, v33216; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc3217; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s6, v33218; GFX8-NEXT:    v_xor_b32_e32 v2, s5, v23219; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc3220; GFX8-NEXT:    v_subrev_u32_e32 v2, vcc, s5, v23221; GFX8-NEXT:    v_xor_b32_e32 v3, s7, v33222; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v23223; GFX8-NEXT:    v_subrev_u32_e32 v3, vcc, s7, v33224; GFX8-NEXT:    flat_store_dword v[0:1], v23225; GFX8-NEXT:    v_mov_b32_e32 v0, s23226; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v33227; GFX8-NEXT:    v_mov_b32_e32 v1, s33228; GFX8-NEXT:    flat_store_dword v[0:1], v23229; GFX8-NEXT:    s_endpgm3230;3231; GFX9-LABEL: sdivrem_i27:3232; GFX9:       ; %bb.0:3233; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x103234; GFX9-NEXT:    v_mov_b32_e32 v2, 03235; GFX9-NEXT:    s_waitcnt lgkmcnt(0)3236; GFX9-NEXT:    s_bfe_i32 s1, s1, 0x1b00003237; GFX9-NEXT:    s_ashr_i32 s4, s1, 313238; GFX9-NEXT:    s_add_i32 s1, s1, s43239; GFX9-NEXT:    s_xor_b32 s5, s1, s43240; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s53241; GFX9-NEXT:    s_sub_i32 s1, 0, s53242; GFX9-NEXT:    s_bfe_i32 s0, s0, 0x1b00003243; GFX9-NEXT:    s_ashr_i32 s6, s0, 313244; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v03245; GFX9-NEXT:    s_add_i32 s0, s0, s63246; GFX9-NEXT:    s_xor_b32 s7, s0, s63247; GFX9-NEXT:    s_xor_b32 s4, s6, s43248; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03249; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v03250; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v03251; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03252; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v13253; GFX9-NEXT:    v_add_u32_e32 v0, v0, v13254; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v03255; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s53256; GFX9-NEXT:    v_add_u32_e32 v3, 1, v03257; GFX9-NEXT:    v_sub_u32_e32 v1, s7, v13258; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v13259; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3260; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v13261; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc3262; GFX9-NEXT:    v_add_u32_e32 v3, 1, v03263; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v13264; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc3265; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v13266; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc3267; GFX9-NEXT:    v_xor_b32_e32 v0, s4, v03268; GFX9-NEXT:    v_subrev_u32_e32 v0, s4, v03269; GFX9-NEXT:    v_xor_b32_e32 v1, s6, v13270; GFX9-NEXT:    v_subrev_u32_e32 v1, s6, v13271; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v03272; GFX9-NEXT:    s_waitcnt lgkmcnt(0)3273; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]3274; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v13275; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]3276; GFX9-NEXT:    s_endpgm3277;3278; GFX10-LABEL: sdivrem_i27:3279; GFX10:       ; %bb.0:3280; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x103281; GFX10-NEXT:    s_waitcnt lgkmcnt(0)3282; GFX10-NEXT:    s_bfe_i32 s1, s1, 0x1b00003283; GFX10-NEXT:    s_bfe_i32 s0, s0, 0x1b00003284; GFX10-NEXT:    s_ashr_i32 s4, s1, 313285; GFX10-NEXT:    s_ashr_i32 s5, s0, 313286; GFX10-NEXT:    s_add_i32 s1, s1, s43287; GFX10-NEXT:    s_add_i32 s0, s0, s53288; GFX10-NEXT:    s_xor_b32 s1, s1, s43289; GFX10-NEXT:    s_xor_b32 s0, s0, s53290; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s13291; GFX10-NEXT:    s_sub_i32 s2, 0, s13292; GFX10-NEXT:    s_xor_b32 s4, s5, s43293; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v03294; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v03295; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v03296; GFX10-NEXT:    v_mul_lo_u32 v1, s2, v03297; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v13298; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v13299; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v03300; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s13301; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v03302; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v13303; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v13304; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v13305; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3306; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo3307; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v03308; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s1, v13309; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s1, v13310; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x03311; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo3312; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo3313; GFX10-NEXT:    v_mov_b32_e32 v2, 03314; GFX10-NEXT:    v_xor_b32_e32 v0, s4, v03315; GFX10-NEXT:    v_xor_b32_e32 v1, s5, v13316; GFX10-NEXT:    v_subrev_nc_u32_e32 v0, s4, v03317; GFX10-NEXT:    v_subrev_nc_u32_e32 v1, s5, v13318; GFX10-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v03319; GFX10-NEXT:    v_and_b32_e32 v1, 0x7ffffff, v13320; GFX10-NEXT:    s_waitcnt lgkmcnt(0)3321; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]3322; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]3323; GFX10-NEXT:    s_endpgm3324  %div = sdiv i27 %x, %y3325  store i27 %div, ptr addrspace(1) %out03326  %rem = srem i27 %x, %y3327  store i27 %rem, ptr addrspace(1) %out13328  ret void3329}3330