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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 %s -o - | FileCheck -check-prefixes=GCN %s3 4define half @test_s16(half %a) #0 {5; GCN-LABEL: test_s16:6; GCN: ; %bb.0: ; %entry7; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v09; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc10; GCN-NEXT: s_setpc_b64 s[30:31]11entry:12 %fcmp = fcmp olt half %a, 0.013 %sel = select i1 %fcmp, half 0.0, half %a14 ret half %sel15}16 17define float @test_s32(float %a) #0 {18; GCN-LABEL: test_s32:19; GCN: ; %bb.0: ; %entry20; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v022; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc23; GCN-NEXT: s_setpc_b64 s[30:31]24entry:25 %fcmp = fcmp olt float %a, 0.026 %sel = select i1 %fcmp, float 0.0, float %a27 ret float %sel28}29 30define double @test_s64(double %a) #0 {31; GCN-LABEL: test_s64:32; GCN: ; %bb.0: ; %entry33; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; GCN-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[0:1]35; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc36; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc37; GCN-NEXT: s_setpc_b64 s[30:31]38entry:39 %fcmp = fcmp olt double %a, 0.040 %sel = select i1 %fcmp, double 0.0, double %a41 ret double %sel42}43 44define <4 x half> @test_v4s16(<4 x half> %a) #0 {45; GCN-LABEL: test_v4s16:46; GCN: ; %bb.0: ; %entry47; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GCN-NEXT: v_mov_b32_e32 v4, 049; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v050; GCN-NEXT: v_lshrrev_b32_e32 v2, 16, v051; GCN-NEXT: v_cndmask_b32_e64 v5, v0, 0, vcc52; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v4 src0_sel:WORD_1 src1_sel:DWORD53; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v154; GCN-NEXT: v_lshrrev_b32_e32 v3, 16, v155; GCN-NEXT: v_cndmask_b32_e64 v0, v2, 0, s[4:5]56; GCN-NEXT: v_cndmask_b32_e64 v2, v1, 0, vcc57; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v4 src0_sel:WORD_1 src1_sel:DWORD58; GCN-NEXT: v_cndmask_b32_e64 v1, v3, 0, s[4:5]59; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v560; GCN-NEXT: v_and_b32_e32 v2, 0xffff, v261; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, v362; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v263; GCN-NEXT: s_setpc_b64 s[30:31]64entry:65 %fcmp = fcmp olt <4 x half> %a, zeroinitializer66 %sel = select <4 x i1> %fcmp, <4 x half> zeroinitializer, <4 x half> %a67 ret <4 x half> %sel68}69 70define <8 x half> @test_v8s16(<8 x half> %a) #0 {71; GCN-LABEL: test_v8s16:72; GCN: ; %bb.0: ; %entry73; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; GCN-NEXT: v_mov_b32_e32 v8, 075; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v076; GCN-NEXT: v_lshrrev_b32_e32 v4, 16, v077; GCN-NEXT: v_cndmask_b32_e64 v9, v0, 0, vcc78; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v0, v8 src0_sel:WORD_1 src1_sel:DWORD79; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v180; GCN-NEXT: v_lshrrev_b32_e32 v5, 16, v181; GCN-NEXT: v_cndmask_b32_e64 v0, v4, 0, s[4:5]82; GCN-NEXT: v_cndmask_b32_e64 v4, v1, 0, vcc83; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v8 src0_sel:WORD_1 src1_sel:DWORD84; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v285; GCN-NEXT: v_lshrrev_b32_e32 v6, 16, v286; GCN-NEXT: v_cndmask_b32_e64 v1, v5, 0, s[4:5]87; GCN-NEXT: v_cndmask_b32_e64 v5, v2, 0, vcc88; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v2, v8 src0_sel:WORD_1 src1_sel:DWORD89; GCN-NEXT: v_cmp_gt_f16_e32 vcc, 0, v390; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v491; GCN-NEXT: v_lshrrev_b32_e32 v7, 16, v392; GCN-NEXT: v_cndmask_b32_e64 v2, v6, 0, s[4:5]93; GCN-NEXT: v_cndmask_b32_e64 v6, v3, 0, vcc94; GCN-NEXT: v_cmp_lt_f16_sdwa s[4:5], v3, v8 src0_sel:WORD_1 src1_sel:DWORD95; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v496; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v597; GCN-NEXT: v_cndmask_b32_e64 v3, v7, 0, s[4:5]98; GCN-NEXT: v_and_b32_e32 v7, 0xffff, v999; GCN-NEXT: v_lshl_or_b32 v2, v2, 16, v4100; GCN-NEXT: v_and_b32_e32 v4, 0xffff, v6101; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, v7102; GCN-NEXT: v_lshl_or_b32 v3, v3, 16, v4103; GCN-NEXT: s_setpc_b64 s[30:31]104entry:105 %fcmp = fcmp olt <8 x half> %a, zeroinitializer106 %sel = select <8 x i1> %fcmp, <8 x half> zeroinitializer, <8 x half> %a107 ret <8 x half> %sel108}109 110define <2 x float> @test_v2s32(<2 x float> %a) #0 {111; GCN-LABEL: test_v2s32:112; GCN: ; %bb.0: ; %entry113; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0115; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc116; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1117; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc118; GCN-NEXT: s_setpc_b64 s[30:31]119entry:120 %fcmp = fcmp olt <2 x float> %a, zeroinitializer121 %sel = select <2 x i1> %fcmp, <2 x float> zeroinitializer, <2 x float> %a122 ret <2 x float> %sel123}124 125define <4 x float> @test_v4s32(<4 x float> %a) #0 {126; GCN-LABEL: test_v4s32:127; GCN: ; %bb.0: ; %entry128; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v0130; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc131; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v1132; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc133; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v2134; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc135; GCN-NEXT: v_cmp_gt_f32_e32 vcc, 0, v3136; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc137; GCN-NEXT: s_setpc_b64 s[30:31]138entry:139 %fcmp = fcmp olt <4 x float> %a, zeroinitializer140 %sel = select <4 x i1> %fcmp, <4 x float> zeroinitializer, <4 x float> %a141 ret <4 x float> %sel142}143 144define <2 x double> @test_v2s64(<2 x double> %a) #0 {145; GCN-LABEL: test_v2s64:146; GCN: ; %bb.0: ; %entry147; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; GCN-NEXT: v_cmp_gt_f64_e32 vcc, 0, v[0:1]149; GCN-NEXT: v_cmp_gt_f64_e64 s[4:5], 0, v[2:3]150; GCN-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc151; GCN-NEXT: v_cndmask_b32_e64 v2, v2, 0, s[4:5]152; GCN-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc153; GCN-NEXT: v_cndmask_b32_e64 v3, v3, 0, s[4:5]154; GCN-NEXT: s_setpc_b64 s[30:31]155entry:156 %fcmp = fcmp olt <2 x double> %a, zeroinitializer157 %sel = select <2 x i1> %fcmp, <2 x double> zeroinitializer, <2 x double> %a158 ret <2 x double> %sel159}160 161