1505 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define i8 @v_sext_inreg_i8_4(i8 %value) {9; GCN-LABEL: v_sext_inreg_i8_4:10; GCN: ; %bb.0:11; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GCN-NEXT: v_bfe_i32 v0, v0, 0, 413; GCN-NEXT: s_setpc_b64 s[30:31]14;15; GFX10PLUS-LABEL: v_sext_inreg_i8_4:16; GFX10PLUS: ; %bb.0:17; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 419; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]20 %shl = shl i8 %value, 421 %ashr = ashr i8 %shl, 422 ret i8 %ashr23}24 25define i8 @v_sext_inreg_i8_7(i8 %value) {26; GCN-LABEL: v_sext_inreg_i8_7:27; GCN: ; %bb.0:28; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; GCN-NEXT: v_bfe_i32 v0, v0, 0, 130; GCN-NEXT: s_setpc_b64 s[30:31]31;32; GFX10PLUS-LABEL: v_sext_inreg_i8_7:33; GFX10PLUS: ; %bb.0:34; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 136; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]37 %shl = shl i8 %value, 738 %ashr = ashr i8 %shl, 739 ret i8 %ashr40}41 42define amdgpu_ps i8 @s_sext_inreg_i8(i8 inreg %value) {43; GCN-LABEL: s_sext_inreg_i8:44; GCN: ; %bb.0:45; GCN-NEXT: s_bfe_i32 s0, s0, 0x5000046; GCN-NEXT: ; return to shader part epilog47;48; GFX10PLUS-LABEL: s_sext_inreg_i8:49; GFX10PLUS: ; %bb.0:50; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x5000051; GFX10PLUS-NEXT: ; return to shader part epilog52 %shl = shl i8 %value, 353 %ashr = ashr i8 %shl, 354 ret i8 %ashr55}56 57define amdgpu_ps i8 @s_sext_inreg_i8_6(i8 inreg %value) {58; GCN-LABEL: s_sext_inreg_i8_6:59; GCN: ; %bb.0:60; GCN-NEXT: s_bfe_i32 s0, s0, 0x2000061; GCN-NEXT: ; return to shader part epilog62;63; GFX10PLUS-LABEL: s_sext_inreg_i8_6:64; GFX10PLUS: ; %bb.0:65; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x2000066; GFX10PLUS-NEXT: ; return to shader part epilog67 %shl = shl i8 %value, 668 %ashr = ashr i8 %shl, 669 ret i8 %ashr70}71 72define i24 @v_sext_inreg_i24_12(i24 %value) {73; GCN-LABEL: v_sext_inreg_i24_12:74; GCN: ; %bb.0:75; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GCN-NEXT: v_bfe_i32 v0, v0, 0, 2477; GCN-NEXT: v_ashrrev_i32_e32 v0, 12, v078; GCN-NEXT: s_setpc_b64 s[30:31]79;80; GFX10PLUS-LABEL: v_sext_inreg_i24_12:81; GFX10PLUS: ; %bb.0:82; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 2484; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 12, v085; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]86 %shl = shl i24 %value, 1287 %ashr = ashr i24 %value, 1288 ret i24 %ashr89}90 91define i24 @v_sext_inreg_i24_7(i24 %value) {92; GCN-LABEL: v_sext_inreg_i24_7:93; GCN: ; %bb.0:94; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1796; GCN-NEXT: s_setpc_b64 s[30:31]97;98; GFX10PLUS-LABEL: v_sext_inreg_i24_7:99; GFX10PLUS: ; %bb.0:100; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)101; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 17102; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]103 %shl = shl i24 %value, 7104 %ashr = ashr i24 %shl, 7105 ret i24 %ashr106}107 108define amdgpu_ps i24 @s_sext_inreg_i24_8(i24 inreg %value) {109; GCN-LABEL: s_sext_inreg_i24_8:110; GCN: ; %bb.0:111; GCN-NEXT: s_sext_i32_i16 s0, s0112; GCN-NEXT: ; return to shader part epilog113;114; GFX10PLUS-LABEL: s_sext_inreg_i24_8:115; GFX10PLUS: ; %bb.0:116; GFX10PLUS-NEXT: s_sext_i32_i16 s0, s0117; GFX10PLUS-NEXT: ; return to shader part epilog118 %shl = shl i24 %value, 8119 %ashr = ashr i24 %shl, 8120 ret i24 %ashr121}122 123define amdgpu_ps i24 @s_sext_inreg_i24_7(i24 inreg %value) {124; GCN-LABEL: s_sext_inreg_i24_7:125; GCN: ; %bb.0:126; GCN-NEXT: s_bfe_i32 s0, s0, 0x110000127; GCN-NEXT: ; return to shader part epilog128;129; GFX10PLUS-LABEL: s_sext_inreg_i24_7:130; GFX10PLUS: ; %bb.0:131; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x110000132; GFX10PLUS-NEXT: ; return to shader part epilog133 %shl = shl i24 %value, 7134 %ashr = ashr i24 %shl, 7135 ret i24 %ashr136}137 138define i32 @v_sext_inreg_i32_3(i32 %value) {139; GCN-LABEL: v_sext_inreg_i32_3:140; GCN: ; %bb.0:141; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GCN-NEXT: v_bfe_i32 v0, v0, 0, 29143; GCN-NEXT: s_setpc_b64 s[30:31]144;145; GFX10PLUS-LABEL: v_sext_inreg_i32_3:146; GFX10PLUS: ; %bb.0:147; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)148; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 29149; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]150 %shl = shl i32 %value, 3151 %ashr = ashr i32 %shl, 3152 ret i32 %ashr153}154 155define i32 @v_sext_inreg_i32_31(i32 %value) {156; GCN-LABEL: v_sext_inreg_i32_31:157; GCN: ; %bb.0:158; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; GCN-NEXT: v_ashrrev_i32_e32 v0, 31, v0160; GCN-NEXT: s_setpc_b64 s[30:31]161;162; GFX10PLUS-LABEL: v_sext_inreg_i32_31:163; GFX10PLUS: ; %bb.0:164; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 31, v0166; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]167 %shl = shl i32 %value, 31168 %ashr = ashr i32 %value, 31169 ret i32 %ashr170}171 172define amdgpu_ps i32 @s_sext_inreg_i32_2(i32 inreg %value) {173; GCN-LABEL: s_sext_inreg_i32_2:174; GCN: ; %bb.0:175; GCN-NEXT: s_bfe_i32 s0, s0, 0x1e0000176; GCN-NEXT: ; return to shader part epilog177;178; GFX10PLUS-LABEL: s_sext_inreg_i32_2:179; GFX10PLUS: ; %bb.0:180; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x1e0000181; GFX10PLUS-NEXT: ; return to shader part epilog182 %shl = shl i32 %value, 2183 %ashr = ashr i32 %shl, 2184 ret i32 %ashr185}186 187define amdgpu_ps i32 @s_sext_inreg_i32_31(i32 inreg %value) {188; GCN-LABEL: s_sext_inreg_i32_31:189; GCN: ; %bb.0:190; GCN-NEXT: s_bfe_i32 s0, s0, 0x10000191; GCN-NEXT: ; return to shader part epilog192;193; GFX10PLUS-LABEL: s_sext_inreg_i32_31:194; GFX10PLUS: ; %bb.0:195; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x10000196; GFX10PLUS-NEXT: ; return to shader part epilog197 %shl = shl i32 %value, 31198 %ashr = ashr i32 %shl, 31199 ret i32 %ashr200}201 202define <2 x i32> @v_sext_inreg_v2i32_14(<2 x i32> %value) {203; GCN-LABEL: v_sext_inreg_v2i32_14:204; GCN: ; %bb.0:205; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)206; GCN-NEXT: v_bfe_i32 v0, v0, 0, 18207; GCN-NEXT: v_bfe_i32 v1, v1, 0, 18208; GCN-NEXT: s_setpc_b64 s[30:31]209;210; GFX10PLUS-LABEL: v_sext_inreg_v2i32_14:211; GFX10PLUS: ; %bb.0:212; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)213; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 18214; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 18215; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]216 %shl = shl <2 x i32> %value, <i32 14, i32 14>217 %ashr = ashr <2 x i32> %shl, <i32 14, i32 14>218 ret <2 x i32> %ashr219}220 221define <2 x i32> @v_sext_inreg_v2i32_31(<2 x i32> %value) {222; GCN-LABEL: v_sext_inreg_v2i32_31:223; GCN: ; %bb.0:224; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)225; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1226; GCN-NEXT: v_bfe_i32 v1, v1, 0, 1227; GCN-NEXT: s_setpc_b64 s[30:31]228;229; GFX10PLUS-LABEL: v_sext_inreg_v2i32_31:230; GFX10PLUS: ; %bb.0:231; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 1233; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 1234; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]235 %shl = shl <2 x i32> %value, <i32 31, i32 31>236 %shr = ashr <2 x i32> %shl, <i32 31, i32 31>237 ret <2 x i32> %shr238}239 240define amdgpu_ps <2 x i32> @s_sext_inreg_v2i32_22(<2 x i32> inreg %value) {241; GCN-LABEL: s_sext_inreg_v2i32_22:242; GCN: ; %bb.0:243; GCN-NEXT: s_bfe_i32 s0, s0, 0xa0000244; GCN-NEXT: s_bfe_i32 s1, s1, 0xa0000245; GCN-NEXT: ; return to shader part epilog246;247; GFX10PLUS-LABEL: s_sext_inreg_v2i32_22:248; GFX10PLUS: ; %bb.0:249; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0xa0000250; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0xa0000251; GFX10PLUS-NEXT: ; return to shader part epilog252 %shl = shl <2 x i32> %value, <i32 22, i32 22>253 %ashr = ashr <2 x i32> %shl, <i32 22, i32 22>254 ret <2 x i32> %ashr255}256 257define <3 x i32> @v_sext_inreg_v3i32_16(<3 x i32> %value, <3 x i32> %amount) {258; GCN-LABEL: v_sext_inreg_v3i32_16:259; GCN: ; %bb.0:260; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)261; GCN-NEXT: v_bfe_i32 v0, v0, 0, 16262; GCN-NEXT: v_bfe_i32 v1, v1, 0, 16263; GCN-NEXT: v_bfe_i32 v2, v2, 0, 16264; GCN-NEXT: s_setpc_b64 s[30:31]265;266; GFX10PLUS-LABEL: v_sext_inreg_v3i32_16:267; GFX10PLUS: ; %bb.0:268; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)269; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 16270; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 16271; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 16272; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]273 %shl = shl <3 x i32> %value, <i32 16, i32 16, i32 16>274 %ashr = ashr <3 x i32> %shl, <i32 16, i32 16, i32 16>275 ret <3 x i32> %ashr276}277 278define amdgpu_ps <3 x i32> @s_sext_inreg_v3i32_22(<3 x i32> inreg %value) {279; GCN-LABEL: s_sext_inreg_v3i32_22:280; GCN: ; %bb.0:281; GCN-NEXT: s_bfe_i32 s0, s0, 0xa0000282; GCN-NEXT: s_bfe_i32 s1, s1, 0xa0000283; GCN-NEXT: s_bfe_i32 s2, s2, 0xa0000284; GCN-NEXT: ; return to shader part epilog285;286; GFX10PLUS-LABEL: s_sext_inreg_v3i32_22:287; GFX10PLUS: ; %bb.0:288; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0xa0000289; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0xa0000290; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0xa0000291; GFX10PLUS-NEXT: ; return to shader part epilog292 %shl = shl <3 x i32> %value, <i32 22, i32 22, i32 22>293 %ashr = ashr <3 x i32> %shl, <i32 22, i32 22, i32 22>294 ret <3 x i32> %ashr295}296 297define <4 x i32> @v_sext_inreg_v4i32_6(<4 x i32> %value) {298; GCN-LABEL: v_sext_inreg_v4i32_6:299; GCN: ; %bb.0:300; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)301; GCN-NEXT: v_bfe_i32 v0, v0, 0, 26302; GCN-NEXT: v_bfe_i32 v1, v1, 0, 26303; GCN-NEXT: v_bfe_i32 v2, v2, 0, 26304; GCN-NEXT: v_bfe_i32 v3, v3, 0, 26305; GCN-NEXT: s_setpc_b64 s[30:31]306;307; GFX10PLUS-LABEL: v_sext_inreg_v4i32_6:308; GFX10PLUS: ; %bb.0:309; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)310; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 26311; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 26312; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 26313; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 26314; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]315 %shl = shl <4 x i32> %value, <i32 6, i32 6, i32 6, i32 6>316 %ashr = ashr <4 x i32> %shl, <i32 6, i32 6, i32 6, i32 6>317 ret <4 x i32> %ashr318}319 320define amdgpu_ps <4 x i32> @s_sext_inreg_v4i32_13(<4 x i32> inreg %value) {321; GCN-LABEL: s_sext_inreg_v4i32_13:322; GCN: ; %bb.0:323; GCN-NEXT: s_bfe_i32 s0, s0, 0x130000324; GCN-NEXT: s_bfe_i32 s1, s1, 0x130000325; GCN-NEXT: s_bfe_i32 s2, s2, 0x130000326; GCN-NEXT: s_bfe_i32 s3, s3, 0x130000327; GCN-NEXT: ; return to shader part epilog328;329; GFX10PLUS-LABEL: s_sext_inreg_v4i32_13:330; GFX10PLUS: ; %bb.0:331; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x130000332; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x130000333; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x130000334; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x130000335; GFX10PLUS-NEXT: ; return to shader part epilog336 %shl = shl <4 x i32> %value, <i32 13, i32 13, i32 13, i32 13>337 %ashr = ashr <4 x i32> %shl, <i32 13, i32 13, i32 13, i32 13>338 ret <4 x i32> %ashr339}340 341define <5 x i32> @v_sext_inreg_v5i32_30(<5 x i32> %value) {342; GCN-LABEL: v_sext_inreg_v5i32_30:343; GCN: ; %bb.0:344; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)345; GCN-NEXT: v_bfe_i32 v0, v0, 0, 2346; GCN-NEXT: v_bfe_i32 v1, v1, 0, 2347; GCN-NEXT: v_bfe_i32 v2, v2, 0, 2348; GCN-NEXT: v_bfe_i32 v3, v3, 0, 2349; GCN-NEXT: v_bfe_i32 v4, v4, 0, 2350; GCN-NEXT: s_setpc_b64 s[30:31]351;352; GFX10PLUS-LABEL: v_sext_inreg_v5i32_30:353; GFX10PLUS: ; %bb.0:354; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)355; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 2356; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 2357; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 2358; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 2359; GFX10PLUS-NEXT: v_bfe_i32 v4, v4, 0, 2360; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]361 %shl = shl <5 x i32> %value, <i32 30, i32 30, i32 30, i32 30, i32 30>362 %ashr = ashr <5 x i32> %shl, <i32 30, i32 30, i32 30, i32 30, i32 30>363 ret <5 x i32> %ashr364}365 366define amdgpu_ps <5 x i32> @s_sext_inreg_v5i32_19(<5 x i32> inreg %value) {367; GCN-LABEL: s_sext_inreg_v5i32_19:368; GCN: ; %bb.0:369; GCN-NEXT: s_ashr_i32 s0, s0, 19370; GCN-NEXT: s_ashr_i32 s1, s1, 19371; GCN-NEXT: s_ashr_i32 s2, s2, 19372; GCN-NEXT: s_ashr_i32 s3, s3, 19373; GCN-NEXT: s_ashr_i32 s4, s4, 19374; GCN-NEXT: ; return to shader part epilog375;376; GFX10PLUS-LABEL: s_sext_inreg_v5i32_19:377; GFX10PLUS: ; %bb.0:378; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 19379; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 19380; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 19381; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 19382; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, 19383; GFX10PLUS-NEXT: ; return to shader part epilog384 %shl = shl <5 x i32> %value, <i32 19, i32 19, i32 19, i32 19, i32 19>385 %ashr = ashr <5 x i32> %value, <i32 19, i32 19, i32 19, i32 19, i32 19>386 ret <5 x i32> %ashr387}388 389define <16 x i32> @v_sext_inreg_v16i32_27(<16 x i32> %value) {390; GCN-LABEL: v_sext_inreg_v16i32_27:391; GCN: ; %bb.0:392; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)393; GCN-NEXT: v_bfe_i32 v0, v0, 0, 5394; GCN-NEXT: v_bfe_i32 v1, v1, 0, 5395; GCN-NEXT: v_bfe_i32 v2, v2, 0, 5396; GCN-NEXT: v_bfe_i32 v3, v3, 0, 5397; GCN-NEXT: v_bfe_i32 v4, v4, 0, 5398; GCN-NEXT: v_bfe_i32 v5, v5, 0, 5399; GCN-NEXT: v_bfe_i32 v6, v6, 0, 5400; GCN-NEXT: v_bfe_i32 v7, v7, 0, 5401; GCN-NEXT: v_bfe_i32 v8, v8, 0, 5402; GCN-NEXT: v_bfe_i32 v9, v9, 0, 5403; GCN-NEXT: v_bfe_i32 v10, v10, 0, 5404; GCN-NEXT: v_bfe_i32 v11, v11, 0, 5405; GCN-NEXT: v_bfe_i32 v12, v12, 0, 5406; GCN-NEXT: v_bfe_i32 v13, v13, 0, 5407; GCN-NEXT: v_bfe_i32 v14, v14, 0, 5408; GCN-NEXT: v_bfe_i32 v15, v15, 0, 5409; GCN-NEXT: s_setpc_b64 s[30:31]410;411; GFX10PLUS-LABEL: v_sext_inreg_v16i32_27:412; GFX10PLUS: ; %bb.0:413; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)414; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 5415; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 5416; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 5417; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 5418; GFX10PLUS-NEXT: v_bfe_i32 v4, v4, 0, 5419; GFX10PLUS-NEXT: v_bfe_i32 v5, v5, 0, 5420; GFX10PLUS-NEXT: v_bfe_i32 v6, v6, 0, 5421; GFX10PLUS-NEXT: v_bfe_i32 v7, v7, 0, 5422; GFX10PLUS-NEXT: v_bfe_i32 v8, v8, 0, 5423; GFX10PLUS-NEXT: v_bfe_i32 v9, v9, 0, 5424; GFX10PLUS-NEXT: v_bfe_i32 v10, v10, 0, 5425; GFX10PLUS-NEXT: v_bfe_i32 v11, v11, 0, 5426; GFX10PLUS-NEXT: v_bfe_i32 v12, v12, 0, 5427; GFX10PLUS-NEXT: v_bfe_i32 v13, v13, 0, 5428; GFX10PLUS-NEXT: v_bfe_i32 v14, v14, 0, 5429; GFX10PLUS-NEXT: v_bfe_i32 v15, v15, 0, 5430; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]431 %shl = shl <16 x i32> %value, <i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27>432 %ashr = ashr <16 x i32> %shl, <i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27, i32 27>433 ret <16 x i32> %ashr434}435 436define amdgpu_ps <16 x i32> @s_sext_inreg_v16i32_3(<16 x i32> inreg %value) {437; GCN-LABEL: s_sext_inreg_v16i32_3:438; GCN: ; %bb.0:439; GCN-NEXT: s_bfe_i32 s0, s0, 0x1d0000440; GCN-NEXT: s_bfe_i32 s1, s1, 0x1d0000441; GCN-NEXT: s_bfe_i32 s2, s2, 0x1d0000442; GCN-NEXT: s_bfe_i32 s3, s3, 0x1d0000443; GCN-NEXT: s_bfe_i32 s4, s4, 0x1d0000444; GCN-NEXT: s_bfe_i32 s5, s5, 0x1d0000445; GCN-NEXT: s_bfe_i32 s6, s6, 0x1d0000446; GCN-NEXT: s_bfe_i32 s7, s7, 0x1d0000447; GCN-NEXT: s_bfe_i32 s8, s8, 0x1d0000448; GCN-NEXT: s_bfe_i32 s9, s9, 0x1d0000449; GCN-NEXT: s_bfe_i32 s10, s10, 0x1d0000450; GCN-NEXT: s_bfe_i32 s11, s11, 0x1d0000451; GCN-NEXT: s_bfe_i32 s12, s12, 0x1d0000452; GCN-NEXT: s_bfe_i32 s13, s13, 0x1d0000453; GCN-NEXT: s_bfe_i32 s14, s14, 0x1d0000454; GCN-NEXT: s_bfe_i32 s15, s15, 0x1d0000455; GCN-NEXT: ; return to shader part epilog456;457; GFX10PLUS-LABEL: s_sext_inreg_v16i32_3:458; GFX10PLUS: ; %bb.0:459; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x1d0000460; GFX10PLUS-NEXT: s_bfe_i32 s1, s1, 0x1d0000461; GFX10PLUS-NEXT: s_bfe_i32 s2, s2, 0x1d0000462; GFX10PLUS-NEXT: s_bfe_i32 s3, s3, 0x1d0000463; GFX10PLUS-NEXT: s_bfe_i32 s4, s4, 0x1d0000464; GFX10PLUS-NEXT: s_bfe_i32 s5, s5, 0x1d0000465; GFX10PLUS-NEXT: s_bfe_i32 s6, s6, 0x1d0000466; GFX10PLUS-NEXT: s_bfe_i32 s7, s7, 0x1d0000467; GFX10PLUS-NEXT: s_bfe_i32 s8, s8, 0x1d0000468; GFX10PLUS-NEXT: s_bfe_i32 s9, s9, 0x1d0000469; GFX10PLUS-NEXT: s_bfe_i32 s10, s10, 0x1d0000470; GFX10PLUS-NEXT: s_bfe_i32 s11, s11, 0x1d0000471; GFX10PLUS-NEXT: s_bfe_i32 s12, s12, 0x1d0000472; GFX10PLUS-NEXT: s_bfe_i32 s13, s13, 0x1d0000473; GFX10PLUS-NEXT: s_bfe_i32 s14, s14, 0x1d0000474; GFX10PLUS-NEXT: s_bfe_i32 s15, s15, 0x1d0000475; GFX10PLUS-NEXT: ; return to shader part epilog476 %shl = shl <16 x i32> %value, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>477 %ashr = ashr <16 x i32> %shl, <i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3, i32 3>478 ret <16 x i32> %ashr479}480 481define i16 @v_sext_inreg_i16_4(i16 %value) {482; GCN-LABEL: v_sext_inreg_i16_4:483; GCN: ; %bb.0:484; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)485; GCN-NEXT: v_bfe_i32 v0, v0, 0, 12486; GCN-NEXT: s_setpc_b64 s[30:31]487;488; GFX10PLUS-LABEL: v_sext_inreg_i16_4:489; GFX10PLUS: ; %bb.0:490; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)491; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 12492; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]493 %shl = shl i16 %value, 4494 %ashr = ashr i16 %shl, 4495 ret i16 %ashr496}497 498define i16 @v_sext_inreg_i16_15(i16 %value) {499; GCN-LABEL: v_sext_inreg_i16_15:500; GCN: ; %bb.0:501; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; GCN-NEXT: v_bfe_i32 v0, v0, 0, 1503; GCN-NEXT: s_setpc_b64 s[30:31]504;505; GFX10PLUS-LABEL: v_sext_inreg_i16_15:506; GFX10PLUS: ; %bb.0:507; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)508; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 1509; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]510 %shl = shl i16 %value, 15511 %ashr = ashr i16 %shl, 15512 ret i16 %ashr513}514 515define amdgpu_ps i16 @s_sext_inreg_i16_9(i16 inreg %value) {516; GCN-LABEL: s_sext_inreg_i16_9:517; GCN: ; %bb.0:518; GCN-NEXT: s_bfe_i32 s0, s0, 0x70000519; GCN-NEXT: ; return to shader part epilog520;521; GFX10PLUS-LABEL: s_sext_inreg_i16_9:522; GFX10PLUS: ; %bb.0:523; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x70000524; GFX10PLUS-NEXT: ; return to shader part epilog525 %shl = shl i16 %value, 9526 %ashr = ashr i16 %shl, 9527 ret i16 %ashr528}529 530define amdgpu_ps i16 @s_sext_inreg_i16_15(i16 inreg %value) {531; GCN-LABEL: s_sext_inreg_i16_15:532; GCN: ; %bb.0:533; GCN-NEXT: s_bfe_i32 s0, s0, 0x10000534; GCN-NEXT: ; return to shader part epilog535;536; GFX10PLUS-LABEL: s_sext_inreg_i16_15:537; GFX10PLUS: ; %bb.0:538; GFX10PLUS-NEXT: s_bfe_i32 s0, s0, 0x10000539; GFX10PLUS-NEXT: ; return to shader part epilog540 %shl = shl i16 %value, 15541 %ashr = ashr i16 %shl, 15542 ret i16 %ashr543}544 545define <2 x i16> @v_sext_inreg_v2i16_8(<2 x i16> %value) {546; GFX6-LABEL: v_sext_inreg_v2i16_8:547; GFX6: ; %bb.0:548; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)549; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 8550; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 8551; GFX6-NEXT: s_setpc_b64 s[30:31]552;553; GFX8-LABEL: v_sext_inreg_v2i16_8:554; GFX8: ; %bb.0:555; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)556; GFX8-NEXT: v_mov_b32_e32 v1, 0xffff557; GFX8-NEXT: v_and_b32_sdwa v2, sext(v0), v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD558; GFX8-NEXT: v_and_b32_sdwa v0, sext(v0), v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:DWORD559; GFX8-NEXT: v_or_b32_e32 v0, v2, v0560; GFX8-NEXT: s_setpc_b64 s[30:31]561;562; GFX9-LABEL: v_sext_inreg_v2i16_8:563; GFX9: ; %bb.0:564; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]566; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]567; GFX9-NEXT: s_setpc_b64 s[30:31]568;569; GFX10PLUS-LABEL: v_sext_inreg_v2i16_8:570; GFX10PLUS: ; %bb.0:571; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)572; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]573; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]574; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]575 %shl = shl <2 x i16> %value, <i16 8, i16 8>576 %ashr = ashr <2 x i16> %shl, <i16 8, i16 8>577 ret <2 x i16> %ashr578}579 580define <2 x i16> @v_sext_inreg_v2i16_15(<2 x i16> %value) {581; GFX6-LABEL: v_sext_inreg_v2i16_15:582; GFX6: ; %bb.0:583; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)584; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 1585; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 1586; GFX6-NEXT: s_setpc_b64 s[30:31]587;588; GFX8-LABEL: v_sext_inreg_v2i16_15:589; GFX8: ; %bb.0:590; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)591; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 1592; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 1593; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0594; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0595; GFX8-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD596; GFX8-NEXT: s_setpc_b64 s[30:31]597;598; GFX9-LABEL: v_sext_inreg_v2i16_15:599; GFX9: ; %bb.0:600; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)601; GFX9-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1]602; GFX9-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1]603; GFX9-NEXT: s_setpc_b64 s[30:31]604;605; GFX10PLUS-LABEL: v_sext_inreg_v2i16_15:606; GFX10PLUS: ; %bb.0:607; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)608; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1]609; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 15, v0 op_sel_hi:[0,1]610; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]611 %shl = shl <2 x i16> %value, <i16 15, i16 15>612 %ashr = ashr <2 x i16> %shl, <i16 15, i16 15>613 ret <2 x i16> %ashr614}615 616define amdgpu_ps i32 @s_sext_inreg_v2i16_11(<2 x i16> inreg %value) {617; GFX6-LABEL: s_sext_inreg_v2i16_11:618; GFX6: ; %bb.0:619; GFX6-NEXT: s_bfe_i32 s1, s1, 0x50000620; GFX6-NEXT: s_bfe_i32 s0, s0, 0x50000621; GFX6-NEXT: s_and_b32 s1, s1, 0xffff622; GFX6-NEXT: s_and_b32 s0, s0, 0xffff623; GFX6-NEXT: s_lshl_b32 s1, s1, 16624; GFX6-NEXT: s_or_b32 s0, s0, s1625; GFX6-NEXT: ; return to shader part epilog626;627; GFX8-LABEL: s_sext_inreg_v2i16_11:628; GFX8: ; %bb.0:629; GFX8-NEXT: s_bfe_i32 s1, s0, 0x50000630; GFX8-NEXT: s_bfe_i32 s0, s0, 0x50010631; GFX8-NEXT: s_and_b32 s0, s0, 0xffff632; GFX8-NEXT: s_and_b32 s1, s1, 0xffff633; GFX8-NEXT: s_lshl_b32 s0, s0, 16634; GFX8-NEXT: s_or_b32 s0, s1, s0635; GFX8-NEXT: ; return to shader part epilog636;637; GFX9-LABEL: s_sext_inreg_v2i16_11:638; GFX9: ; %bb.0:639; GFX9-NEXT: s_lshr_b32 s1, s0, 16640; GFX9-NEXT: s_lshl_b32 s0, s0, 0xb000b641; GFX9-NEXT: s_lshl_b32 s1, s1, 11642; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1643; GFX9-NEXT: s_sext_i32_i16 s1, s0644; GFX9-NEXT: s_ashr_i32 s0, s0, 16645; GFX9-NEXT: s_sext_i32_i16 s2, 0xb000b646; GFX9-NEXT: s_ashr_i32 s1, s1, s2647; GFX9-NEXT: s_ashr_i32 s0, s0, 11648; GFX9-NEXT: s_pack_ll_b32_b16 s0, s1, s0649; GFX9-NEXT: ; return to shader part epilog650;651; GFX10PLUS-LABEL: s_sext_inreg_v2i16_11:652; GFX10PLUS: ; %bb.0:653; GFX10PLUS-NEXT: s_lshr_b32 s1, s0, 16654; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 0xb000b655; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 11656; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s1657; GFX10PLUS-NEXT: s_sext_i32_i16 s1, 0xb000b658; GFX10PLUS-NEXT: s_sext_i32_i16 s2, s0659; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16660; GFX10PLUS-NEXT: s_ashr_i32 s1, s2, s1661; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 11662; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s1, s0663; GFX10PLUS-NEXT: ; return to shader part epilog664 %shl = shl <2 x i16> %value, <i16 11, i16 11>665 %ashr = ashr <2 x i16> %shl, <i16 11, i16 11>666 %cast = bitcast <2 x i16> %ashr to i32667 ret i32 %cast668}669 670; FIXME671; define <3 x i16> @v_sext_inreg_v3i16_4(<3 x i16> %value) {672; %shl = shl <3 x i16> %value, <i16 4, i16 4, i16 4>673; %ashr = ashr <3 x i16> %shl, <i16 4, i16 4, i16 4>674; ret <3 x i16> %ashr675; }676 677; define amdgpu_ps <3 x i16> @s_sext_inreg_v3i16_4(<3 x i16> inreg %value) {678; %shl = shl <3 x i16> %value, <i16 4, i16 4, i16 4>679; %ashr = ashr <3 x i16> %shl, <i16 4, i16 4, i16 4>680; ret <3 x i16> %ashr681; }682 683define <2 x float> @v_sext_inreg_v4i16_3(<4 x i16> %value) {684; GFX6-LABEL: v_sext_inreg_v4i16_3:685; GFX6: ; %bb.0:686; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)687; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 13688; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 13689; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1690; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 13691; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 13692; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0693; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1694; GFX6-NEXT: v_or_b32_e32 v0, v0, v1695; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2696; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3697; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2698; GFX6-NEXT: v_or_b32_e32 v1, v1, v2699; GFX6-NEXT: s_setpc_b64 s[30:31]700;701; GFX8-LABEL: v_sext_inreg_v4i16_3:702; GFX8: ; %bb.0:703; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)704; GFX8-NEXT: v_bfe_i32 v2, v0, 0, 13705; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 13706; GFX8-NEXT: v_bfe_i32 v3, v1, 0, 13707; GFX8-NEXT: v_bfe_i32 v1, v1, 16, 13708; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0709; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1710; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0711; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1712; GFX8-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD713; GFX8-NEXT: v_or_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD714; GFX8-NEXT: s_setpc_b64 s[30:31]715;716; GFX9-LABEL: v_sext_inreg_v4i16_3:717; GFX9: ; %bb.0:718; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)719; GFX9-NEXT: v_pk_lshlrev_b16 v0, 3, v0 op_sel_hi:[0,1]720; GFX9-NEXT: v_pk_lshlrev_b16 v1, 3, v1 op_sel_hi:[0,1]721; GFX9-NEXT: v_pk_ashrrev_i16 v0, 3, v0 op_sel_hi:[0,1]722; GFX9-NEXT: v_pk_ashrrev_i16 v1, 3, v1 op_sel_hi:[0,1]723; GFX9-NEXT: s_setpc_b64 s[30:31]724;725; GFX10PLUS-LABEL: v_sext_inreg_v4i16_3:726; GFX10PLUS: ; %bb.0:727; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)728; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 3, v0 op_sel_hi:[0,1]729; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, 3, v1 op_sel_hi:[0,1]730; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 3, v0 op_sel_hi:[0,1]731; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, 3, v1 op_sel_hi:[0,1]732; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]733 %shl = shl <4 x i16> %value, <i16 3, i16 3, i16 3, i16 3>734 %ashr = ashr <4 x i16> %shl, <i16 3, i16 3, i16 3, i16 3>735 %cast = bitcast <4 x i16> %ashr to <2 x float>736 ret <2 x float> %cast737}738 739define amdgpu_ps <2 x i32> @s_sext_inreg_v4i16_14(<4 x i16> inreg %value) {740; GFX6-LABEL: s_sext_inreg_v4i16_14:741; GFX6: ; %bb.0:742; GFX6-NEXT: s_bfe_i32 s1, s1, 0x20000743; GFX6-NEXT: s_bfe_i32 s0, s0, 0x20000744; GFX6-NEXT: s_and_b32 s1, s1, 0xffff745; GFX6-NEXT: s_bfe_i32 s2, s2, 0x20000746; GFX6-NEXT: s_bfe_i32 s3, s3, 0x20000747; GFX6-NEXT: s_and_b32 s0, s0, 0xffff748; GFX6-NEXT: s_lshl_b32 s1, s1, 16749; GFX6-NEXT: s_or_b32 s0, s0, s1750; GFX6-NEXT: s_and_b32 s1, s2, 0xffff751; GFX6-NEXT: s_and_b32 s2, s3, 0xffff752; GFX6-NEXT: s_lshl_b32 s2, s2, 16753; GFX6-NEXT: s_or_b32 s1, s1, s2754; GFX6-NEXT: ; return to shader part epilog755;756; GFX8-LABEL: s_sext_inreg_v4i16_14:757; GFX8: ; %bb.0:758; GFX8-NEXT: s_bfe_i32 s2, s0, 0x20000759; GFX8-NEXT: s_bfe_i32 s0, s0, 0x20010760; GFX8-NEXT: s_bfe_i32 s3, s1, 0x20000761; GFX8-NEXT: s_bfe_i32 s1, s1, 0x20010762; GFX8-NEXT: s_and_b32 s0, s0, 0xffff763; GFX8-NEXT: s_and_b32 s2, s2, 0xffff764; GFX8-NEXT: s_lshl_b32 s0, s0, 16765; GFX8-NEXT: s_and_b32 s1, s1, 0xffff766; GFX8-NEXT: s_or_b32 s0, s2, s0767; GFX8-NEXT: s_and_b32 s2, s3, 0xffff768; GFX8-NEXT: s_lshl_b32 s1, s1, 16769; GFX8-NEXT: s_or_b32 s1, s2, s1770; GFX8-NEXT: ; return to shader part epilog771;772; GFX9-LABEL: s_sext_inreg_v4i16_14:773; GFX9: ; %bb.0:774; GFX9-NEXT: s_lshr_b32 s2, s0, 16775; GFX9-NEXT: s_lshl_b32 s0, s0, 0xe000e776; GFX9-NEXT: s_lshl_b32 s2, s2, 14777; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2778; GFX9-NEXT: s_sext_i32_i16 s2, s0779; GFX9-NEXT: s_ashr_i32 s0, s0, 16780; GFX9-NEXT: s_sext_i32_i16 s3, 0xe000e781; GFX9-NEXT: s_ashr_i32 s2, s2, s3782; GFX9-NEXT: s_ashr_i32 s0, s0, 14783; GFX9-NEXT: s_pack_ll_b32_b16 s0, s2, s0784; GFX9-NEXT: s_lshr_b32 s2, s1, 16785; GFX9-NEXT: s_lshl_b32 s1, s1, 0xe000e786; GFX9-NEXT: s_lshl_b32 s2, s2, 14787; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2788; GFX9-NEXT: s_sext_i32_i16 s2, s1789; GFX9-NEXT: s_ashr_i32 s1, s1, 16790; GFX9-NEXT: s_ashr_i32 s2, s2, s3791; GFX9-NEXT: s_ashr_i32 s1, s1, 14792; GFX9-NEXT: s_pack_ll_b32_b16 s1, s2, s1793; GFX9-NEXT: ; return to shader part epilog794;795; GFX10PLUS-LABEL: s_sext_inreg_v4i16_14:796; GFX10PLUS: ; %bb.0:797; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16798; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 16799; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 0xe000e800; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 14801; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 0xe000e802; GFX10PLUS-NEXT: s_lshl_b32 s4, s4, 14803; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s2804; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s4805; GFX10PLUS-NEXT: s_sext_i32_i16 s2, 0xe000e806; GFX10PLUS-NEXT: s_sext_i32_i16 s3, s0807; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 16808; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s1809; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 16810; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, s2811; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 14812; GFX10PLUS-NEXT: s_ashr_i32 s2, s4, s2813; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 14814; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s3, s0815; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s2, s1816; GFX10PLUS-NEXT: ; return to shader part epilog817 %shl = shl <4 x i16> %value, <i16 14, i16 14, i16 14, i16 14>818 %ashr = ashr <4 x i16> %shl, <i16 14, i16 14, i16 14, i16 14>819 %cast = bitcast <4 x i16> %ashr to <2 x i32>820 ret <2 x i32> %cast821}822 823; FIXME824; define <5 x i16> @v_sext_inreg_v5i16(<5 x i16> %value) {825; %shl = shl <5 x i16> %value, %amount826; ret <5 x i16> %result827; }828 829; define amdgpu_ps <5 x i16> @s_sext_inreg_v5i16(<5 x i16> inreg %value) {830; %shl = shl <5 x i16> %value, %amount831; ret <5 x i16> %result832; }833 834; define <3 x float> @v_sext_inreg_v6i16(<6 x i16> %value) {835; %shl = shl <6 x i16> %value, %amount836; %cast = bitcast <6 x i16> %result to <3 x float>837; ret <3 x float> %cast838; }839 840; define amdgpu_ps <3 x i32> @s_sext_inreg_v6i16(<6 x i16> inreg %value) {841; %shl = shl <6 x i16> %value, %amount842; %cast = bitcast <6 x i16> %result to <3 x i32>843; ret <3 x i32> %cast844; }845 846define <4 x float> @v_sext_inreg_v8i16_11(<8 x i16> %value) {847; GFX6-LABEL: v_sext_inreg_v8i16_11:848; GFX6: ; %bb.0:849; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)850; GFX6-NEXT: v_bfe_i32 v1, v1, 0, 5851; GFX6-NEXT: v_bfe_i32 v0, v0, 0, 5852; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1853; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 5854; GFX6-NEXT: v_bfe_i32 v3, v3, 0, 5855; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0856; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1857; GFX6-NEXT: v_bfe_i32 v5, v5, 0, 5858; GFX6-NEXT: v_or_b32_e32 v0, v0, v1859; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2860; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3861; GFX6-NEXT: v_bfe_i32 v4, v4, 0, 5862; GFX6-NEXT: v_bfe_i32 v7, v7, 0, 5863; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2864; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v5865; GFX6-NEXT: v_bfe_i32 v6, v6, 0, 5866; GFX6-NEXT: v_or_b32_e32 v1, v1, v2867; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v4868; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3869; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7870; GFX6-NEXT: v_or_b32_e32 v2, v2, v3871; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v6872; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4873; GFX6-NEXT: v_or_b32_e32 v3, v3, v4874; GFX6-NEXT: s_setpc_b64 s[30:31]875;876; GFX8-LABEL: v_sext_inreg_v8i16_11:877; GFX8: ; %bb.0:878; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; GFX8-NEXT: v_bfe_i32 v4, v0, 0, 5880; GFX8-NEXT: v_bfe_i32 v0, v0, 16, 5881; GFX8-NEXT: v_bfe_i32 v5, v1, 0, 5882; GFX8-NEXT: v_bfe_i32 v1, v1, 16, 5883; GFX8-NEXT: v_bfe_i32 v6, v2, 0, 5884; GFX8-NEXT: v_bfe_i32 v2, v2, 16, 5885; GFX8-NEXT: v_bfe_i32 v7, v3, 0, 5886; GFX8-NEXT: v_bfe_i32 v3, v3, 16, 5887; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0888; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v1889; GFX8-NEXT: v_and_b32_e32 v2, 0xffff, v2890; GFX8-NEXT: v_and_b32_e32 v3, 0xffff, v3891; GFX8-NEXT: v_lshlrev_b32_e32 v0, 16, v0892; GFX8-NEXT: v_lshlrev_b32_e32 v1, 16, v1893; GFX8-NEXT: v_lshlrev_b32_e32 v2, 16, v2894; GFX8-NEXT: v_lshlrev_b32_e32 v3, 16, v3895; GFX8-NEXT: v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD896; GFX8-NEXT: v_or_b32_sdwa v1, v5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD897; GFX8-NEXT: v_or_b32_sdwa v2, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD898; GFX8-NEXT: v_or_b32_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD899; GFX8-NEXT: s_setpc_b64 s[30:31]900;901; GFX9-LABEL: v_sext_inreg_v8i16_11:902; GFX9: ; %bb.0:903; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)904; GFX9-NEXT: v_pk_lshlrev_b16 v0, 11, v0 op_sel_hi:[0,1]905; GFX9-NEXT: v_pk_lshlrev_b16 v1, 11, v1 op_sel_hi:[0,1]906; GFX9-NEXT: v_pk_lshlrev_b16 v2, 11, v2 op_sel_hi:[0,1]907; GFX9-NEXT: v_pk_lshlrev_b16 v3, 11, v3 op_sel_hi:[0,1]908; GFX9-NEXT: v_pk_ashrrev_i16 v0, 11, v0 op_sel_hi:[0,1]909; GFX9-NEXT: v_pk_ashrrev_i16 v1, 11, v1 op_sel_hi:[0,1]910; GFX9-NEXT: v_pk_ashrrev_i16 v2, 11, v2 op_sel_hi:[0,1]911; GFX9-NEXT: v_pk_ashrrev_i16 v3, 11, v3 op_sel_hi:[0,1]912; GFX9-NEXT: s_setpc_b64 s[30:31]913;914; GFX10PLUS-LABEL: v_sext_inreg_v8i16_11:915; GFX10PLUS: ; %bb.0:916; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)917; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 11, v0 op_sel_hi:[0,1]918; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, 11, v1 op_sel_hi:[0,1]919; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v2, 11, v2 op_sel_hi:[0,1]920; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v3, 11, v3 op_sel_hi:[0,1]921; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v0, 11, v0 op_sel_hi:[0,1]922; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v1, 11, v1 op_sel_hi:[0,1]923; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v2, 11, v2 op_sel_hi:[0,1]924; GFX10PLUS-NEXT: v_pk_ashrrev_i16 v3, 11, v3 op_sel_hi:[0,1]925; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]926 %shl = shl <8 x i16> %value, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>927 %ashr = ashr <8 x i16> %shl, <i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11, i16 11>928 %cast = bitcast <8 x i16> %ashr to <4 x float>929 ret <4 x float> %cast930}931 932define amdgpu_ps <4 x i32> @s_sext_inreg_v8i16_5(<8 x i16> inreg %value) {933; GFX6-LABEL: s_sext_inreg_v8i16_5:934; GFX6: ; %bb.0:935; GFX6-NEXT: s_bfe_i32 s1, s1, 0xb0000936; GFX6-NEXT: s_bfe_i32 s0, s0, 0xb0000937; GFX6-NEXT: s_and_b32 s1, s1, 0xffff938; GFX6-NEXT: s_bfe_i32 s2, s2, 0xb0000939; GFX6-NEXT: s_bfe_i32 s3, s3, 0xb0000940; GFX6-NEXT: s_and_b32 s0, s0, 0xffff941; GFX6-NEXT: s_lshl_b32 s1, s1, 16942; GFX6-NEXT: s_bfe_i32 s5, s5, 0xb0000943; GFX6-NEXT: s_or_b32 s0, s0, s1944; GFX6-NEXT: s_and_b32 s1, s2, 0xffff945; GFX6-NEXT: s_and_b32 s2, s3, 0xffff946; GFX6-NEXT: s_bfe_i32 s4, s4, 0xb0000947; GFX6-NEXT: s_bfe_i32 s7, s7, 0xb0000948; GFX6-NEXT: s_lshl_b32 s2, s2, 16949; GFX6-NEXT: s_and_b32 s3, s5, 0xffff950; GFX6-NEXT: s_bfe_i32 s6, s6, 0xb0000951; GFX6-NEXT: s_or_b32 s1, s1, s2952; GFX6-NEXT: s_and_b32 s2, s4, 0xffff953; GFX6-NEXT: s_lshl_b32 s3, s3, 16954; GFX6-NEXT: s_and_b32 s4, s7, 0xffff955; GFX6-NEXT: s_or_b32 s2, s2, s3956; GFX6-NEXT: s_and_b32 s3, s6, 0xffff957; GFX6-NEXT: s_lshl_b32 s4, s4, 16958; GFX6-NEXT: s_or_b32 s3, s3, s4959; GFX6-NEXT: ; return to shader part epilog960;961; GFX8-LABEL: s_sext_inreg_v8i16_5:962; GFX8: ; %bb.0:963; GFX8-NEXT: s_bfe_i32 s4, s0, 0xb0000964; GFX8-NEXT: s_bfe_i32 s0, s0, 0xb0010965; GFX8-NEXT: s_bfe_i32 s5, s1, 0xb0000966; GFX8-NEXT: s_bfe_i32 s1, s1, 0xb0010967; GFX8-NEXT: s_and_b32 s0, s0, 0xffff968; GFX8-NEXT: s_bfe_i32 s6, s2, 0xb0000969; GFX8-NEXT: s_bfe_i32 s2, s2, 0xb0010970; GFX8-NEXT: s_and_b32 s4, s4, 0xffff971; GFX8-NEXT: s_lshl_b32 s0, s0, 16972; GFX8-NEXT: s_and_b32 s1, s1, 0xffff973; GFX8-NEXT: s_bfe_i32 s7, s3, 0xb0000974; GFX8-NEXT: s_bfe_i32 s3, s3, 0xb0010975; GFX8-NEXT: s_or_b32 s0, s4, s0976; GFX8-NEXT: s_and_b32 s4, s5, 0xffff977; GFX8-NEXT: s_lshl_b32 s1, s1, 16978; GFX8-NEXT: s_and_b32 s2, s2, 0xffff979; GFX8-NEXT: s_or_b32 s1, s4, s1980; GFX8-NEXT: s_and_b32 s4, s6, 0xffff981; GFX8-NEXT: s_lshl_b32 s2, s2, 16982; GFX8-NEXT: s_and_b32 s3, s3, 0xffff983; GFX8-NEXT: s_or_b32 s2, s4, s2984; GFX8-NEXT: s_and_b32 s4, s7, 0xffff985; GFX8-NEXT: s_lshl_b32 s3, s3, 16986; GFX8-NEXT: s_or_b32 s3, s4, s3987; GFX8-NEXT: ; return to shader part epilog988;989; GFX9-LABEL: s_sext_inreg_v8i16_5:990; GFX9: ; %bb.0:991; GFX9-NEXT: s_lshr_b32 s4, s0, 16992; GFX9-NEXT: s_lshl_b32 s0, s0, 0x50005993; GFX9-NEXT: s_lshl_b32 s4, s4, 5994; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4995; GFX9-NEXT: s_sext_i32_i16 s4, s0996; GFX9-NEXT: s_ashr_i32 s0, s0, 16997; GFX9-NEXT: s_sext_i32_i16 s5, 0x50005998; GFX9-NEXT: s_ashr_i32 s4, s4, s5999; GFX9-NEXT: s_ashr_i32 s0, s0, 51000; GFX9-NEXT: s_pack_ll_b32_b16 s0, s4, s01001; GFX9-NEXT: s_lshr_b32 s4, s1, 161002; GFX9-NEXT: s_lshl_b32 s1, s1, 0x500051003; GFX9-NEXT: s_lshl_b32 s4, s4, 51004; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s41005; GFX9-NEXT: s_sext_i32_i16 s4, s11006; GFX9-NEXT: s_ashr_i32 s1, s1, 161007; GFX9-NEXT: s_ashr_i32 s4, s4, s51008; GFX9-NEXT: s_ashr_i32 s1, s1, 51009; GFX9-NEXT: s_pack_ll_b32_b16 s1, s4, s11010; GFX9-NEXT: s_lshr_b32 s4, s2, 161011; GFX9-NEXT: s_lshl_b32 s2, s2, 0x500051012; GFX9-NEXT: s_lshl_b32 s4, s4, 51013; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s41014; GFX9-NEXT: s_sext_i32_i16 s4, s21015; GFX9-NEXT: s_ashr_i32 s2, s2, 161016; GFX9-NEXT: s_ashr_i32 s4, s4, s51017; GFX9-NEXT: s_ashr_i32 s2, s2, 51018; GFX9-NEXT: s_pack_ll_b32_b16 s2, s4, s21019; GFX9-NEXT: s_lshr_b32 s4, s3, 161020; GFX9-NEXT: s_lshl_b32 s3, s3, 0x500051021; GFX9-NEXT: s_lshl_b32 s4, s4, 51022; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s41023; GFX9-NEXT: s_sext_i32_i16 s4, s31024; GFX9-NEXT: s_ashr_i32 s3, s3, 161025; GFX9-NEXT: s_ashr_i32 s4, s4, s51026; GFX9-NEXT: s_ashr_i32 s3, s3, 51027; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s31028; GFX9-NEXT: ; return to shader part epilog1029;1030; GFX10PLUS-LABEL: s_sext_inreg_v8i16_5:1031; GFX10PLUS: ; %bb.0:1032; GFX10PLUS-NEXT: s_lshr_b32 s4, s0, 161033; GFX10PLUS-NEXT: s_lshr_b32 s6, s1, 161034; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 0x500051035; GFX10PLUS-NEXT: s_lshl_b32 s4, s4, 51036; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 0x500051037; GFX10PLUS-NEXT: s_lshl_b32 s6, s6, 51038; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s41039; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s61040; GFX10PLUS-NEXT: s_lshr_b32 s6, s2, 161041; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s01042; GFX10PLUS-NEXT: s_sext_i32_i16 s5, 0x500051043; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 161044; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, 0x500051045; GFX10PLUS-NEXT: s_lshl_b32 s6, s6, 51046; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s51047; GFX10PLUS-NEXT: s_ashr_i32 s0, s0, 51048; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s2, s61049; GFX10PLUS-NEXT: s_lshr_b32 s6, s3, 161050; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s4, s01051; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s11052; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 161053; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, 0x500051054; GFX10PLUS-NEXT: s_lshl_b32 s6, s6, 51055; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s51056; GFX10PLUS-NEXT: s_ashr_i32 s1, s1, 51057; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s3, s61058; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s4, s11059; GFX10PLUS-NEXT: s_sext_i32_i16 s4, s21060; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 161061; GFX10PLUS-NEXT: s_sext_i32_i16 s6, s31062; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 161063; GFX10PLUS-NEXT: s_ashr_i32 s4, s4, s51064; GFX10PLUS-NEXT: s_ashr_i32 s2, s2, 51065; GFX10PLUS-NEXT: s_ashr_i32 s5, s6, s51066; GFX10PLUS-NEXT: s_ashr_i32 s3, s3, 51067; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s4, s21068; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s5, s31069; GFX10PLUS-NEXT: ; return to shader part epilog1070 %shl = shl <8 x i16> %value, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>1071 %ashr = ashr <8 x i16> %shl, <i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5, i16 5>1072 %cast = bitcast <8 x i16> %ashr to <4 x i32>1073 ret <4 x i32> %cast1074}1075 1076define i64 @v_sext_inreg_i64_23(i64 %value) {1077; GCN-LABEL: v_sext_inreg_i64_23:1078; GCN: ; %bb.0:1079; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1080; GCN-NEXT: v_bfe_i32 v1, v1, 0, 91081; GCN-NEXT: s_setpc_b64 s[30:31]1082;1083; GFX10PLUS-LABEL: v_sext_inreg_i64_23:1084; GFX10PLUS: ; %bb.0:1085; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1086; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 91087; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1088 %shl = shl i64 %value, 231089 %ashr = ashr i64 %shl, 231090 ret i64 %ashr1091}1092 1093define i64 @v_sext_inreg_i64_40(i64 %value) {1094; GCN-LABEL: v_sext_inreg_i64_40:1095; GCN: ; %bb.0:1096; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1097; GCN-NEXT: v_bfe_i32 v0, v0, 0, 241098; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01099; GCN-NEXT: s_setpc_b64 s[30:31]1100;1101; GFX10PLUS-LABEL: v_sext_inreg_i64_40:1102; GFX10PLUS: ; %bb.0:1103; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1104; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 241105; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v01106; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1107 %shl = shl i64 %value, 401108 %ashr = ashr i64 %shl, 401109 ret i64 %ashr1110}1111 1112define i64 @v_sext_inreg_i64_63(i64 %value) {1113; GCN-LABEL: v_sext_inreg_i64_63:1114; GCN: ; %bb.0:1115; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1116; GCN-NEXT: v_bfe_i32 v0, v0, 0, 11117; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01118; GCN-NEXT: s_setpc_b64 s[30:31]1119;1120; GFX10PLUS-LABEL: v_sext_inreg_i64_63:1121; GFX10PLUS: ; %bb.0:1122; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1123; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 11124; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v01125; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1126 %shl = shl i64 %value, 631127 %ashr = ashr i64 %shl, 631128 ret i64 %ashr1129}1130 1131define i64 @v_sext_inreg_i64_33(i64 %value) {1132; GCN-LABEL: v_sext_inreg_i64_33:1133; GCN: ; %bb.0:1134; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1135; GCN-NEXT: v_bfe_i32 v0, v0, 0, 311136; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01137; GCN-NEXT: s_setpc_b64 s[30:31]1138;1139; GFX10PLUS-LABEL: v_sext_inreg_i64_33:1140; GFX10PLUS: ; %bb.0:1141; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1142; GFX10PLUS-NEXT: v_bfe_i32 v0, v0, 0, 311143; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v01144; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1145 %shl = shl i64 %value, 331146 %ashr = ashr i64 %shl, 331147 ret i64 %ashr1148}1149 1150define i64 @v_sext_inreg_i64_32(i64 %value) {1151; GCN-LABEL: v_sext_inreg_i64_32:1152; GCN: ; %bb.0:1153; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1154; GCN-NEXT: v_mov_b32_e32 v0, v11155; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v01156; GCN-NEXT: s_setpc_b64 s[30:31]1157;1158; GFX10PLUS-LABEL: v_sext_inreg_i64_32:1159; GFX10PLUS: ; %bb.0:1160; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1161; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v11162; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v01163; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1164 %shl = shl i64 %value, 321165 %ashr = ashr i64 %value, 321166 ret i64 %ashr1167}1168 1169define i64 @v_sext_inreg_i64_31(i64 %value) {1170; GCN-LABEL: v_sext_inreg_i64_31:1171; GCN: ; %bb.0:1172; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1173; GCN-NEXT: v_bfe_i32 v1, v1, 0, 11174; GCN-NEXT: s_setpc_b64 s[30:31]1175;1176; GFX10PLUS-LABEL: v_sext_inreg_i64_31:1177; GFX10PLUS: ; %bb.0:1178; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1179; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 11180; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1181 %shl = shl i64 %value, 311182 %ashr = ashr i64 %shl, 311183 ret i64 %ashr1184}1185 1186define amdgpu_ps i64 @s_sext_inreg_i64_3(i64 inreg %value) {1187; GCN-LABEL: s_sext_inreg_i64_3:1188; GCN: ; %bb.0:1189; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3d00001190; GCN-NEXT: ; return to shader part epilog1191;1192; GFX10PLUS-LABEL: s_sext_inreg_i64_3:1193; GFX10PLUS: ; %bb.0:1194; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3d00001195; GFX10PLUS-NEXT: ; return to shader part epilog1196 %shl = shl i64 %value, 31197 %ashr = ashr i64 %shl, 31198 ret i64 %ashr1199}1200 1201define amdgpu_ps i64 @s_sext_inreg_i64_63(i64 inreg %value) {1202; GCN-LABEL: s_sext_inreg_i64_63:1203; GCN: ; %bb.0:1204; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100001205; GCN-NEXT: ; return to shader part epilog1206;1207; GFX10PLUS-LABEL: s_sext_inreg_i64_63:1208; GFX10PLUS: ; %bb.0:1209; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x100001210; GFX10PLUS-NEXT: ; return to shader part epilog1211 %shl = shl i64 %value, 631212 %ashr = ashr i64 %shl, 631213 ret i64 %ashr1214}1215 1216define amdgpu_ps i64 @s_sext_inreg_i64_33(i64 inreg %value) {1217; GCN-LABEL: s_sext_inreg_i64_33:1218; GCN: ; %bb.0:1219; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x1f00001220; GCN-NEXT: ; return to shader part epilog1221;1222; GFX10PLUS-LABEL: s_sext_inreg_i64_33:1223; GFX10PLUS: ; %bb.0:1224; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x1f00001225; GFX10PLUS-NEXT: ; return to shader part epilog1226 %shl = shl i64 %value, 331227 %ashr = ashr i64 %shl, 331228 ret i64 %ashr1229}1230 1231define amdgpu_ps i64 @s_sext_inreg_i64_32(i64 inreg %value) {1232; GCN-LABEL: s_sext_inreg_i64_32:1233; GCN: ; %bb.0:1234; GCN-NEXT: s_ashr_i32 s1, s0, 311235; GCN-NEXT: ; return to shader part epilog1236;1237; GFX10PLUS-LABEL: s_sext_inreg_i64_32:1238; GFX10PLUS: ; %bb.0:1239; GFX10PLUS-NEXT: s_ashr_i32 s1, s0, 311240; GFX10PLUS-NEXT: ; return to shader part epilog1241 %shl = shl i64 %value, 321242 %ashr = ashr i64 %shl, 321243 ret i64 %ashr1244}1245 1246define amdgpu_ps i64 @s_sext_inreg_i64_31(i64 inreg %value) {1247; GCN-LABEL: s_sext_inreg_i64_31:1248; GCN: ; %bb.0:1249; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x2100001250; GCN-NEXT: ; return to shader part epilog1251;1252; GFX10PLUS-LABEL: s_sext_inreg_i64_31:1253; GFX10PLUS: ; %bb.0:1254; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x2100001255; GFX10PLUS-NEXT: ; return to shader part epilog1256 %shl = shl i64 %value, 311257 %ashr = ashr i64 %shl, 311258 ret i64 %ashr1259}1260 1261define <2 x i64> @v_sext_inreg_v2i64_16(<2 x i64> %value) {1262; GCN-LABEL: v_sext_inreg_v2i64_16:1263; GCN: ; %bb.0:1264; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1265; GCN-NEXT: v_bfe_i32 v1, v1, 0, 161266; GCN-NEXT: v_bfe_i32 v3, v3, 0, 161267; GCN-NEXT: s_setpc_b64 s[30:31]1268;1269; GFX10PLUS-LABEL: v_sext_inreg_v2i64_16:1270; GFX10PLUS: ; %bb.0:1271; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1272; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 161273; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 161274; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1275 %shl = shl <2 x i64> %value, <i64 16, i64 16>1276 %ashr = ashr <2 x i64> %shl, <i64 16, i64 16>1277 ret <2 x i64> %ashr1278}1279 1280define <2 x i64> @v_sext_inreg_v2i64_31(<2 x i64> %value) {1281; GCN-LABEL: v_sext_inreg_v2i64_31:1282; GCN: ; %bb.0:1283; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1284; GCN-NEXT: v_bfe_i32 v1, v1, 0, 11285; GCN-NEXT: v_bfe_i32 v3, v3, 0, 11286; GCN-NEXT: s_setpc_b64 s[30:31]1287;1288; GFX10PLUS-LABEL: v_sext_inreg_v2i64_31:1289; GFX10PLUS: ; %bb.0:1290; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1291; GFX10PLUS-NEXT: v_bfe_i32 v1, v1, 0, 11292; GFX10PLUS-NEXT: v_bfe_i32 v3, v3, 0, 11293; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1294 %shl = shl <2 x i64> %value, <i64 31, i64 31>1295 %ashr = ashr <2 x i64> %shl, <i64 31, i64 31>1296 ret <2 x i64> %ashr1297}1298 1299define amdgpu_ps <2 x i64> @s_sext_inreg_v2i64_30(<2 x i64> inreg %value) {1300; GCN-LABEL: s_sext_inreg_v2i64_30:1301; GCN: ; %bb.0:1302; GCN-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x2200001303; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x2200001304; GCN-NEXT: ; return to shader part epilog1305;1306; GFX10PLUS-LABEL: s_sext_inreg_v2i64_30:1307; GFX10PLUS: ; %bb.0:1308; GFX10PLUS-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x2200001309; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x2200001310; GFX10PLUS-NEXT: ; return to shader part epilog1311 %shl = shl <2 x i64> %value, <i64 30, i64 30>1312 %ashr = ashr <2 x i64> %shl, <i64 30, i64 30>1313 ret <2 x i64> %ashr1314}1315 1316define i65 @v_sext_inreg_i65_22(i65 %value) {1317; GFX6-LABEL: v_sext_inreg_i65_22:1318; GFX6: ; %bb.0:1319; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1320; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 221321; GFX6-NEXT: v_lshrrev_b32_e32 v3, 10, v11322; GFX6-NEXT: v_or_b32_e32 v2, v2, v31323; GFX6-NEXT: v_bfe_i32 v2, v2, 0, 11324; GFX6-NEXT: v_ashrrev_i32_e32 v3, 31, v21325; GFX6-NEXT: v_bfe_u32 v1, v1, 0, 101326; GFX6-NEXT: v_lshlrev_b32_e32 v4, 10, v21327; GFX6-NEXT: v_ashr_i64 v[2:3], v[2:3], 221328; GFX6-NEXT: v_or_b32_e32 v1, v1, v41329; GFX6-NEXT: s_setpc_b64 s[30:31]1330;1331; GFX8-LABEL: v_sext_inreg_i65_22:1332; GFX8: ; %bb.0:1333; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1334; GFX8-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]1335; GFX8-NEXT: v_lshrrev_b32_e32 v3, 10, v11336; GFX8-NEXT: v_or_b32_e32 v2, v2, v31337; GFX8-NEXT: v_bfe_i32 v2, v2, 0, 11338; GFX8-NEXT: v_ashrrev_i32_e32 v3, 31, v21339; GFX8-NEXT: v_bfe_u32 v1, v1, 0, 101340; GFX8-NEXT: v_lshlrev_b32_e32 v4, 10, v21341; GFX8-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]1342; GFX8-NEXT: v_or_b32_e32 v1, v1, v41343; GFX8-NEXT: s_setpc_b64 s[30:31]1344;1345; GFX9-LABEL: v_sext_inreg_i65_22:1346; GFX9: ; %bb.0:1347; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1348; GFX9-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]1349; GFX9-NEXT: v_lshrrev_b32_e32 v3, 10, v11350; GFX9-NEXT: v_or_b32_e32 v2, v2, v31351; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 11352; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v21353; GFX9-NEXT: v_bfe_u32 v1, v1, 0, 101354; GFX9-NEXT: v_lshl_or_b32 v1, v2, 10, v11355; GFX9-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]1356; GFX9-NEXT: s_setpc_b64 s[30:31]1357;1358; GFX10PLUS-LABEL: v_sext_inreg_i65_22:1359; GFX10PLUS: ; %bb.0:1360; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1361; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 22, v[2:3]1362; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 10, v11363; GFX10PLUS-NEXT: v_bfe_u32 v1, v1, 0, 101364; GFX10PLUS-NEXT: v_or_b32_e32 v2, v2, v31365; GFX10PLUS-NEXT: v_bfe_i32 v2, v2, 0, 11366; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v3, 31, v21367; GFX10PLUS-NEXT: v_lshl_or_b32 v1, v2, 10, v11368; GFX10PLUS-NEXT: v_ashrrev_i64 v[2:3], 22, v[2:3]1369; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1370 %shl = shl i65 %value, 221371 %ashr = ashr i65 %shl, 221372 ret i65 %ashr1373}1374 1375define i65 @v_sext_inreg_i65_33(i65 %value) {1376; GFX6-LABEL: v_sext_inreg_i65_33:1377; GFX6: ; %bb.0:1378; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1379; GFX6-NEXT: v_mov_b32_e32 v3, v11380; GFX6-NEXT: v_bfe_i32 v1, v2, 0, 11381; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v11382; GFX6-NEXT: v_lshl_b64 v[0:1], v[1:2], 311383; GFX6-NEXT: v_lshrrev_b32_e32 v3, 1, v31384; GFX6-NEXT: v_or_b32_e32 v0, v0, v31385; GFX6-NEXT: v_ashrrev_i32_e32 v2, 1, v21386; GFX6-NEXT: s_setpc_b64 s[30:31]1387;1388; GFX8-LABEL: v_sext_inreg_i65_33:1389; GFX8: ; %bb.0:1390; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1391; GFX8-NEXT: v_mov_b32_e32 v3, v11392; GFX8-NEXT: v_bfe_i32 v1, v2, 0, 11393; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v11394; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1395; GFX8-NEXT: v_lshrrev_b32_e32 v3, 1, v31396; GFX8-NEXT: v_or_b32_e32 v0, v0, v31397; GFX8-NEXT: v_ashrrev_i32_e32 v2, 1, v21398; GFX8-NEXT: s_setpc_b64 s[30:31]1399;1400; GFX9-LABEL: v_sext_inreg_i65_33:1401; GFX9: ; %bb.0:1402; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1403; GFX9-NEXT: v_mov_b32_e32 v3, v11404; GFX9-NEXT: v_bfe_i32 v1, v2, 0, 11405; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v11406; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1407; GFX9-NEXT: v_lshrrev_b32_e32 v3, 1, v31408; GFX9-NEXT: v_or_b32_e32 v0, v0, v31409; GFX9-NEXT: v_ashrrev_i32_e32 v2, 1, v21410; GFX9-NEXT: s_setpc_b64 s[30:31]1411;1412; GFX10PLUS-LABEL: v_sext_inreg_i65_33:1413; GFX10PLUS: ; %bb.0:1414; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1415; GFX10PLUS-NEXT: v_mov_b32_e32 v3, v11416; GFX10PLUS-NEXT: v_bfe_i32 v1, v2, 0, 11417; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v3, 1, v31418; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 31, v11419; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[1:2]1420; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v2, 1, v21421; GFX10PLUS-NEXT: v_or_b32_e32 v0, v0, v31422; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1423 %shl = shl i65 %value, 331424 %ashr = ashr i65 %value, 331425 ret i65 %ashr1426}1427 1428define amdgpu_ps i65 @s_sext_inreg_i65_18(i65 inreg %value) {1429; GCN-LABEL: s_sext_inreg_i65_18:1430; GCN: ; %bb.0:1431; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], 181432; GCN-NEXT: s_lshr_b32 s3, s1, 141433; GCN-NEXT: s_or_b32 s2, s2, s31434; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001435; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e00001436; GCN-NEXT: s_lshl_b32 s5, s2, 141437; GCN-NEXT: s_mov_b32 s4, 01438; GCN-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1439; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 181440; GCN-NEXT: ; return to shader part epilog1441;1442; GFX10PLUS-LABEL: s_sext_inreg_i65_18:1443; GFX10PLUS: ; %bb.0:1444; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 181445; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 141446; GFX10PLUS-NEXT: s_bfe_u64 s[0:1], s[0:1], 0x2e00001447; GFX10PLUS-NEXT: s_or_b32 s2, s2, s31448; GFX10PLUS-NEXT: s_mov_b32 s4, 01449; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001450; GFX10PLUS-NEXT: s_lshl_b32 s5, s2, 141451; GFX10PLUS-NEXT: s_ashr_i64 s[2:3], s[2:3], 181452; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5]1453; GFX10PLUS-NEXT: ; return to shader part epilog1454 %shl = shl i65 %value, 181455 %ashr = ashr i65 %shl, 181456 ret i65 %ashr1457}1458 1459define amdgpu_ps i65 @s_sext_inreg_i65_33(i65 inreg %value) {1460; GCN-LABEL: s_sext_inreg_i65_33:1461; GCN: ; %bb.0:1462; GCN-NEXT: s_lshl_b32 s3, s2, 11463; GCN-NEXT: s_mov_b32 s2, 01464; GCN-NEXT: s_lshr_b64 s[4:5], s[0:1], 311465; GCN-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]1466; GCN-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001467; GCN-NEXT: s_bfe_u32 s4, s0, 0x1f00001468; GCN-NEXT: s_lshl_b64 s[0:1], s[2:3], 311469; GCN-NEXT: s_or_b32 s0, s0, s41470; GCN-NEXT: s_ashr_i32 s2, s3, 11471; GCN-NEXT: ; return to shader part epilog1472;1473; GFX10PLUS-LABEL: s_sext_inreg_i65_33:1474; GFX10PLUS: ; %bb.0:1475; GFX10PLUS-NEXT: s_lshl_b32 s3, s2, 11476; GFX10PLUS-NEXT: s_mov_b32 s2, 01477; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], 311478; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5]1479; GFX10PLUS-NEXT: s_bfe_u32 s4, s0, 0x1f00001480; GFX10PLUS-NEXT: s_bfe_i64 s[2:3], s[2:3], 0x100001481; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[2:3], 311482; GFX10PLUS-NEXT: s_ashr_i32 s2, s3, 11483; GFX10PLUS-NEXT: s_or_b32 s0, s0, s41484; GFX10PLUS-NEXT: ; return to shader part epilog1485 %shl = shl i65 %value, 331486 %ashr = ashr i65 %shl, 331487 ret i65 %ashr1488}1489 1490; FIXME: Argument lowering asserts1491; define <2 x i65> @v_sext_inreg_v2i65_36(<2 x i65> %value) {1492; %shl = shl <2 x i65> %value, <i65 36, i65 36>1493; %ashr = ashr <2 x i65> %shl, <i65 36, i65 36>1494; ret <2 x i65> %ashr1495; }1496 1497; define amdgpu_ps <2 x i65> @s_sext_inreg_v2i65_36(<2 x i65> inreg %valuex) {1498; %shl = shl <2 x i65> %value, <i65 36, i65 36>1499; %ashr = ashrshl <2 x i65> %shl, <i65 36, i65 36>1500; ret <2 x i65> %ashr1501; }1502;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:1503; GFX10: {{.*}}1504; GFX11: {{.*}}1505