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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8; Test optimization to reduce shifts to narrower sizes.9 10define amdgpu_ps i64 @s_shl_i64_zext_i32(i32 inreg %x) {11; GCN-LABEL: s_shl_i64_zext_i32:12; GCN: ; %bb.0:13; GCN-NEXT: s_andn2_b32 s0, s0, -2.014; GCN-NEXT: s_lshl_b32 s0, s0, 215; GCN-NEXT: s_mov_b32 s1, 016; GCN-NEXT: ; return to shader part epilog17;18; GFX10-LABEL: s_shl_i64_zext_i32:19; GFX10: ; %bb.0:20; GFX10-NEXT: s_andn2_b32 s0, s0, -2.021; GFX10-NEXT: s_mov_b32 s1, 022; GFX10-NEXT: s_lshl_b32 s0, s0, 223; GFX10-NEXT: ; return to shader part epilog24;25; GFX11-LABEL: s_shl_i64_zext_i32:26; GFX11: ; %bb.0:27; GFX11-NEXT: s_and_not1_b32 s0, s0, -2.028; GFX11-NEXT: s_mov_b32 s1, 029; GFX11-NEXT: s_lshl_b32 s0, s0, 230; GFX11-NEXT: ; return to shader part epilog31 %and = and i32 %x, 107374182332 %ext = zext i32 %and to i6433 %shl = shl i64 %ext, 234 ret i64 %shl35}36 37define i64 @v_shl_i64_zext_i32(i32 %x) {38; GCN-LABEL: v_shl_i64_zext_i32:39; GCN: ; %bb.0:40; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GCN-NEXT: v_and_b32_e32 v0, 0x3fffffff, v042; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v043; GCN-NEXT: v_mov_b32_e32 v1, 044; GCN-NEXT: s_setpc_b64 s[30:31]45;46; GFX10-LABEL: v_shl_i64_zext_i32:47; GFX10: ; %bb.0:48; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; GFX10-NEXT: v_and_b32_e32 v0, 0x3fffffff, v050; GFX10-NEXT: v_mov_b32_e32 v1, 051; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v052; GFX10-NEXT: s_setpc_b64 s[30:31]53;54; GFX11-LABEL: v_shl_i64_zext_i32:55; GFX11: ; %bb.0:56; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)57; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x3fffffff, v058; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v059; GFX11-NEXT: s_setpc_b64 s[30:31]60 %and = and i32 %x, 107374182361 %ext = zext i32 %and to i6462 %shl = shl i64 %ext, 263 ret i64 %shl64}65 66define amdgpu_ps i64 @s_shl_i64_sext_i32(i32 inreg %x) {67; GCN-LABEL: s_shl_i64_sext_i32:68; GCN: ; %bb.0:69; GCN-NEXT: s_and_b32 s0, s0, 0x1fffffff70; GCN-NEXT: s_lshl_b32 s0, s0, 271; GCN-NEXT: s_mov_b32 s1, 072; GCN-NEXT: ; return to shader part epilog73;74; GFX10PLUS-LABEL: s_shl_i64_sext_i32:75; GFX10PLUS: ; %bb.0:76; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0x1fffffff77; GFX10PLUS-NEXT: s_mov_b32 s1, 078; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 279; GFX10PLUS-NEXT: ; return to shader part epilog80 %and = and i32 %x, 53687091181 %ext = sext i32 %and to i6482 %shl = shl i64 %ext, 283 ret i64 %shl84}85 86define i64 @v_shl_i64_sext_i32(i32 %x) {87; GCN-LABEL: v_shl_i64_sext_i32:88; GCN: ; %bb.0:89; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)90; GCN-NEXT: v_and_b32_e32 v0, 0x1fffffff, v091; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v092; GCN-NEXT: v_mov_b32_e32 v1, 093; GCN-NEXT: s_setpc_b64 s[30:31]94;95; GFX10-LABEL: v_shl_i64_sext_i32:96; GFX10: ; %bb.0:97; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; GFX10-NEXT: v_and_b32_e32 v0, 0x1fffffff, v099; GFX10-NEXT: v_mov_b32_e32 v1, 0100; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0101; GFX10-NEXT: s_setpc_b64 s[30:31]102;103; GFX11-LABEL: v_shl_i64_sext_i32:104; GFX11: ; %bb.0:105; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)106; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x1fffffff, v0107; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0108; GFX11-NEXT: s_setpc_b64 s[30:31]109 %and = and i32 %x, 536870911110 %ext = sext i32 %and to i64111 %shl = shl i64 %ext, 2112 ret i64 %shl113}114 115define amdgpu_ps i64 @s_shl_i64_zext_i32_overflow(i32 inreg %x) {116; GCN-LABEL: s_shl_i64_zext_i32_overflow:117; GCN: ; %bb.0:118; GCN-NEXT: s_bitset0_b32 s0, 31119; GCN-NEXT: s_mov_b32 s1, 0120; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2121; GCN-NEXT: ; return to shader part epilog122;123; GFX10PLUS-LABEL: s_shl_i64_zext_i32_overflow:124; GFX10PLUS: ; %bb.0:125; GFX10PLUS-NEXT: s_mov_b32 s1, 0126; GFX10PLUS-NEXT: s_bitset0_b32 s0, 31127; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 2128; GFX10PLUS-NEXT: ; return to shader part epilog129 %and = and i32 %x, 2147483647130 %ext = zext i32 %and to i64131 %shl = shl i64 %ext, 2132 ret i64 %shl133}134 135define i64 @v_shl_i64_zext_i32_overflow(i32 %x) {136; GFX7-LABEL: v_shl_i64_zext_i32_overflow:137; GFX7: ; %bb.0:138; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)139; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0140; GFX7-NEXT: v_mov_b32_e32 v1, 0141; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2142; GFX7-NEXT: s_setpc_b64 s[30:31]143;144; GFX8-LABEL: v_shl_i64_zext_i32_overflow:145; GFX8: ; %bb.0:146; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0148; GFX8-NEXT: v_mov_b32_e32 v1, 0149; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]150; GFX8-NEXT: s_setpc_b64 s[30:31]151;152; GFX9-LABEL: v_shl_i64_zext_i32_overflow:153; GFX9: ; %bb.0:154; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)155; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0156; GFX9-NEXT: v_mov_b32_e32 v1, 0157; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]158; GFX9-NEXT: s_setpc_b64 s[30:31]159;160; GFX10-LABEL: v_shl_i64_zext_i32_overflow:161; GFX10: ; %bb.0:162; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)163; GFX10-NEXT: v_mov_b32_e32 v1, 0164; GFX10-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0165; GFX10-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]166; GFX10-NEXT: s_setpc_b64 s[30:31]167;168; GFX11-LABEL: v_shl_i64_zext_i32_overflow:169; GFX11: ; %bb.0:170; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)171; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0x7fffffff, v0172; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]173; GFX11-NEXT: s_setpc_b64 s[30:31]174 %and = and i32 %x, 2147483647175 %ext = zext i32 %and to i64176 %shl = shl i64 %ext, 2177 ret i64 %shl178}179 180define amdgpu_ps i64 @s_shl_i64_sext_i32_overflow(i32 inreg %x) {181; GCN-LABEL: s_shl_i64_sext_i32_overflow:182; GCN: ; %bb.0:183; GCN-NEXT: s_bitset0_b32 s0, 31184; GCN-NEXT: s_ashr_i32 s1, s0, 31185; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 2186; GCN-NEXT: ; return to shader part epilog187;188; GFX10PLUS-LABEL: s_shl_i64_sext_i32_overflow:189; GFX10PLUS: ; %bb.0:190; GFX10PLUS-NEXT: s_bitset0_b32 s0, 31191; GFX10PLUS-NEXT: s_ashr_i32 s1, s0, 31192; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 2193; GFX10PLUS-NEXT: ; return to shader part epilog194 %and = and i32 %x, 2147483647195 %ext = sext i32 %and to i64196 %shl = shl i64 %ext, 2197 ret i64 %shl198}199 200define i64 @v_shl_i64_sext_i32_overflow(i32 %x) {201; GFX7-LABEL: v_shl_i64_sext_i32_overflow:202; GFX7: ; %bb.0:203; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)204; GFX7-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0205; GFX7-NEXT: v_ashrrev_i32_e32 v1, 31, v0206; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 2207; GFX7-NEXT: s_setpc_b64 s[30:31]208;209; GFX8-LABEL: v_shl_i64_sext_i32_overflow:210; GFX8: ; %bb.0:211; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)212; GFX8-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0213; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v0214; GFX8-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]215; GFX8-NEXT: s_setpc_b64 s[30:31]216;217; GFX9-LABEL: v_shl_i64_sext_i32_overflow:218; GFX9: ; %bb.0:219; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0221; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0222; GFX9-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]223; GFX9-NEXT: s_setpc_b64 s[30:31]224;225; GFX10PLUS-LABEL: v_shl_i64_sext_i32_overflow:226; GFX10PLUS: ; %bb.0:227; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0229; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v1, 31, v0230; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1]231; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]232 %and = and i32 %x, 2147483647233 %ext = sext i32 %and to i64234 %shl = shl i64 %ext, 2235 ret i64 %shl236}237 238define amdgpu_kernel void @mulu24_shl64(ptr addrspace(1) nocapture %arg) {239; GFX7-LABEL: mulu24_shl64:240; GFX7: ; %bb.0: ; %bb241; GFX7-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0242; GFX7-NEXT: v_and_b32_e32 v0, 6, v0243; GFX7-NEXT: v_mul_u32_u24_e32 v0, 7, v0244; GFX7-NEXT: v_mov_b32_e32 v1, 0245; GFX7-NEXT: v_lshl_b64 v[2:3], v[0:1], 2246; GFX7-NEXT: s_mov_b32 s2, 0247; GFX7-NEXT: s_mov_b32 s3, 0xf000248; GFX7-NEXT: s_waitcnt lgkmcnt(0)249; GFX7-NEXT: buffer_store_dword v1, v[2:3], s[0:3], 0 addr64250; GFX7-NEXT: s_endpgm251;252; GFX8-LABEL: mulu24_shl64:253; GFX8: ; %bb.0: ; %bb254; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0255; GFX8-NEXT: v_and_b32_e32 v0, 6, v0256; GFX8-NEXT: v_mul_u32_u24_e32 v0, 7, v0257; GFX8-NEXT: v_mov_b32_e32 v1, 0258; GFX8-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]259; GFX8-NEXT: s_waitcnt lgkmcnt(0)260; GFX8-NEXT: v_mov_b32_e32 v5, s1261; GFX8-NEXT: v_mov_b32_e32 v4, s0262; GFX8-NEXT: v_add_u32_e32 v2, vcc, v4, v2263; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v5, v3, vcc264; GFX8-NEXT: flat_store_dword v[2:3], v1265; GFX8-NEXT: s_endpgm266;267; GFX9-LABEL: mulu24_shl64:268; GFX9: ; %bb.0: ; %bb269; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0270; GFX9-NEXT: v_and_b32_e32 v0, 6, v0271; GFX9-NEXT: v_mul_u32_u24_e32 v0, 7, v0272; GFX9-NEXT: v_mov_b32_e32 v1, 0273; GFX9-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]274; GFX9-NEXT: s_waitcnt lgkmcnt(0)275; GFX9-NEXT: v_mov_b32_e32 v5, s1276; GFX9-NEXT: v_mov_b32_e32 v4, s0277; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, v4, v2278; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v5, v3, vcc279; GFX9-NEXT: global_store_dword v[2:3], v1, off280; GFX9-NEXT: s_endpgm281;282; GFX10-LABEL: mulu24_shl64:283; GFX10: ; %bb.0: ; %bb284; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0285; GFX10-NEXT: v_and_b32_e32 v0, 6, v0286; GFX10-NEXT: v_mov_b32_e32 v1, 0287; GFX10-NEXT: v_mul_u32_u24_e32 v0, 7, v0288; GFX10-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]289; GFX10-NEXT: s_waitcnt lgkmcnt(0)290; GFX10-NEXT: v_mov_b32_e32 v5, s1291; GFX10-NEXT: v_mov_b32_e32 v4, s0292; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2293; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, v5, v3, vcc_lo294; GFX10-NEXT: global_store_dword v[2:3], v1, off295; GFX10-NEXT: s_endpgm296;297; GFX11-LABEL: mulu24_shl64:298; GFX11: ; %bb.0: ; %bb299; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0300; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 6, v0301; GFX11-NEXT: v_mul_u32_u24_e32 v0, 7, v0302; GFX11-NEXT: v_lshlrev_b64 v[2:3], 2, v[0:1]303; GFX11-NEXT: s_waitcnt lgkmcnt(0)304; GFX11-NEXT: v_dual_mov_b32 v5, s1 :: v_dual_mov_b32 v4, s0305; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v4, v2306; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, v5, v3, vcc_lo307; GFX11-NEXT: global_store_b32 v[2:3], v1, off308; GFX11-NEXT: s_endpgm309bb:310 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()311 %tmp1 = and i32 %tmp, 6312 %mulconv = mul nuw nsw i32 %tmp1, 7313 %tmp2 = zext i32 %mulconv to i64314 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp2315 store i32 0, ptr addrspace(1) %tmp3, align 4316 ret void317}318 319define amdgpu_kernel void @muli24_shl64(ptr addrspace(1) nocapture %arg, ptr addrspace(1) nocapture readonly %arg1) {320; GFX7-LABEL: muli24_shl64:321; GFX7: ; %bb.0: ; %bb322; GFX7-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0323; GFX7-NEXT: v_lshlrev_b32_e32 v1, 2, v0324; GFX7-NEXT: v_mov_b32_e32 v2, 0325; GFX7-NEXT: s_mov_b32 s6, 0326; GFX7-NEXT: s_mov_b32 s7, 0xf000327; GFX7-NEXT: s_waitcnt lgkmcnt(0)328; GFX7-NEXT: s_mov_b64 s[4:5], s[2:3]329; GFX7-NEXT: buffer_load_dword v1, v[1:2], s[4:7], 0 addr64330; GFX7-NEXT: s_mov_b64 s[2:3], s[6:7]331; GFX7-NEXT: s_waitcnt vmcnt(0)332; GFX7-NEXT: v_or_b32_e32 v1, 0xff800000, v1333; GFX7-NEXT: v_mul_i32_i24_e32 v1, -7, v1334; GFX7-NEXT: v_lshl_b64 v[3:4], v[1:2], 3335; GFX7-NEXT: v_lshlrev_b32_e32 v1, 3, v0336; GFX7-NEXT: buffer_store_dwordx2 v[3:4], v[1:2], s[0:3], 0 addr64337; GFX7-NEXT: s_endpgm338;339; GFX8-LABEL: muli24_shl64:340; GFX8: ; %bb.0: ; %bb341; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0342; GFX8-NEXT: v_lshlrev_b32_e32 v3, 2, v0343; GFX8-NEXT: v_lshlrev_b32_e32 v5, 3, v0344; GFX8-NEXT: s_waitcnt lgkmcnt(0)345; GFX8-NEXT: v_mov_b32_e32 v1, s2346; GFX8-NEXT: v_mov_b32_e32 v2, s3347; GFX8-NEXT: v_add_u32_e32 v1, vcc, v1, v3348; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc349; GFX8-NEXT: flat_load_dword v4, v[1:2]350; GFX8-NEXT: v_mov_b32_e32 v3, s1351; GFX8-NEXT: v_mov_b32_e32 v1, 0352; GFX8-NEXT: v_mov_b32_e32 v2, s0353; GFX8-NEXT: v_add_u32_e32 v2, vcc, v2, v5354; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc355; GFX8-NEXT: s_waitcnt vmcnt(0)356; GFX8-NEXT: v_or_b32_e32 v0, 0xff800000, v4357; GFX8-NEXT: v_mul_i32_i24_e32 v0, -7, v0358; GFX8-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1]359; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]360; GFX8-NEXT: s_endpgm361;362; GFX9-LABEL: muli24_shl64:363; GFX9: ; %bb.0: ; %bb364; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0365; GFX9-NEXT: v_lshlrev_b32_e32 v1, 2, v0366; GFX9-NEXT: v_mov_b32_e32 v2, 0367; GFX9-NEXT: v_lshlrev_b32_e32 v0, 3, v0368; GFX9-NEXT: s_waitcnt lgkmcnt(0)369; GFX9-NEXT: global_load_dword v1, v1, s[2:3]370; GFX9-NEXT: s_waitcnt vmcnt(0)371; GFX9-NEXT: v_or_b32_e32 v1, 0xff800000, v1372; GFX9-NEXT: v_mul_i32_i24_e32 v1, -7, v1373; GFX9-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2]374; GFX9-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1]375; GFX9-NEXT: s_endpgm376;377; GFX10-LABEL: muli24_shl64:378; GFX10: ; %bb.0: ; %bb379; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0380; GFX10-NEXT: v_lshlrev_b32_e32 v1, 2, v0381; GFX10-NEXT: v_mov_b32_e32 v2, 0382; GFX10-NEXT: v_lshlrev_b32_e32 v0, 3, v0383; GFX10-NEXT: s_waitcnt lgkmcnt(0)384; GFX10-NEXT: global_load_dword v1, v1, s[2:3]385; GFX10-NEXT: s_waitcnt vmcnt(0)386; GFX10-NEXT: v_or_b32_e32 v1, 0xff800000, v1387; GFX10-NEXT: v_mul_i32_i24_e32 v1, -7, v1388; GFX10-NEXT: v_lshlrev_b64 v[1:2], 3, v[1:2]389; GFX10-NEXT: global_store_dwordx2 v0, v[1:2], s[0:1]390; GFX10-NEXT: s_endpgm391;392; GFX11-LABEL: muli24_shl64:393; GFX11: ; %bb.0: ; %bb394; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0395; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0x3ff, v0396; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v2397; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v2398; GFX11-NEXT: s_waitcnt lgkmcnt(0)399; GFX11-NEXT: global_load_b32 v0, v0, s[2:3]400; GFX11-NEXT: s_waitcnt vmcnt(0)401; GFX11-NEXT: v_or_b32_e32 v0, 0xff800000, v0402; GFX11-NEXT: v_mul_i32_i24_e32 v0, -7, v0403; GFX11-NEXT: v_lshlrev_b64 v[0:1], 3, v[0:1]404; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]405; GFX11-NEXT: s_endpgm406bb:407 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()408 %tmp2 = sext i32 %tmp to i64409 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i64 %tmp2410 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 4411 %tmp5 = or i32 %tmp4, -8388608412 %tmp6 = mul nsw i32 %tmp5, -7413 %tmp7 = zext i32 %tmp6 to i64414 %tmp8 = shl nuw nsw i64 %tmp7, 3415 %tmp9 = getelementptr inbounds i64, ptr addrspace(1) %arg, i64 %tmp2416 store i64 %tmp8, ptr addrspace(1) %tmp9, align 8417 ret void418}419 420define amdgpu_ps <2 x i64> @s_shl_v2i64_zext_v2i32(<2 x i32> inreg %x) {421; GCN-LABEL: s_shl_v2i64_zext_v2i32:422; GCN: ; %bb.0:423; GCN-NEXT: s_brev_b32 s2, -4424; GCN-NEXT: s_mov_b32 s3, s2425; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]426; GCN-NEXT: s_lshl_b32 s0, s0, 2427; GCN-NEXT: s_lshl_b32 s2, s1, 2428; GCN-NEXT: s_mov_b32 s1, 0429; GCN-NEXT: s_mov_b32 s3, 0430; GCN-NEXT: ; return to shader part epilog431;432; GFX10PLUS-LABEL: s_shl_v2i64_zext_v2i32:433; GFX10PLUS: ; %bb.0:434; GFX10PLUS-NEXT: s_brev_b32 s2, -4435; GFX10PLUS-NEXT: s_mov_b32 s3, s2436; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]437; GFX10PLUS-NEXT: s_mov_b32 s3, 0438; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 2439; GFX10PLUS-NEXT: s_lshl_b32 s2, s1, 2440; GFX10PLUS-NEXT: s_mov_b32 s1, 0441; GFX10PLUS-NEXT: ; return to shader part epilog442 %and = and <2 x i32> %x, <i32 1073741823, i32 1073741823>443 %ext = zext <2 x i32> %and to <2 x i64>444 %shl = shl <2 x i64> %ext, <i64 2, i64 2>445 ret <2 x i64> %shl446}447 448define <2 x i64> @v_shl_v2i64_zext_v2i32(<2 x i32> %x) {449; GCN-LABEL: v_shl_v2i64_zext_v2i32:450; GCN: ; %bb.0:451; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)452; GCN-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0453; GCN-NEXT: v_and_b32_e32 v1, 0x3fffffff, v1454; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0455; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v1456; GCN-NEXT: v_mov_b32_e32 v1, 0457; GCN-NEXT: v_mov_b32_e32 v3, 0458; GCN-NEXT: s_setpc_b64 s[30:31]459;460; GFX10-LABEL: v_shl_v2i64_zext_v2i32:461; GFX10: ; %bb.0:462; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)463; GFX10-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0464; GFX10-NEXT: v_and_b32_e32 v1, 0x3fffffff, v1465; GFX10-NEXT: v_mov_b32_e32 v3, 0466; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0467; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1468; GFX10-NEXT: v_mov_b32_e32 v1, 0469; GFX10-NEXT: s_setpc_b64 s[30:31]470;471; GFX11-LABEL: v_shl_v2i64_zext_v2i32:472; GFX11: ; %bb.0:473; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)474; GFX11-NEXT: v_and_b32_e32 v0, 0x3fffffff, v0475; GFX11-NEXT: v_and_b32_e32 v1, 0x3fffffff, v1476; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1477; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0478; GFX11-NEXT: s_setpc_b64 s[30:31]479 %and = and <2 x i32> %x, <i32 1073741823, i32 1073741823>480 %ext = zext <2 x i32> %and to <2 x i64>481 %shl = shl <2 x i64> %ext, <i64 2, i64 2>482 ret <2 x i64> %shl483}484 485define amdgpu_ps <2 x i64> @s_shl_v2i64_sext_v2i32(<2 x i32> inreg %x) {486; GCN-LABEL: s_shl_v2i64_sext_v2i32:487; GCN: ; %bb.0:488; GCN-NEXT: s_brev_b32 s2, -8489; GCN-NEXT: s_mov_b32 s3, s2490; GCN-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]491; GCN-NEXT: s_lshl_b32 s0, s0, 2492; GCN-NEXT: s_lshl_b32 s2, s1, 2493; GCN-NEXT: s_mov_b32 s1, 0494; GCN-NEXT: s_mov_b32 s3, 0495; GCN-NEXT: ; return to shader part epilog496;497; GFX10PLUS-LABEL: s_shl_v2i64_sext_v2i32:498; GFX10PLUS: ; %bb.0:499; GFX10PLUS-NEXT: s_brev_b32 s2, -8500; GFX10PLUS-NEXT: s_mov_b32 s3, s2501; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]502; GFX10PLUS-NEXT: s_mov_b32 s3, 0503; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 2504; GFX10PLUS-NEXT: s_lshl_b32 s2, s1, 2505; GFX10PLUS-NEXT: s_mov_b32 s1, 0506; GFX10PLUS-NEXT: ; return to shader part epilog507 %and = and <2 x i32> %x, <i32 536870911, i32 536870911>508 %ext = sext <2 x i32> %and to <2 x i64>509 %shl = shl <2 x i64> %ext, <i64 2, i64 2>510 ret <2 x i64> %shl511}512 513define <2 x i64> @v_shl_v2i64_sext_v2i32(<2 x i32> %x) {514; GCN-LABEL: v_shl_v2i64_sext_v2i32:515; GCN: ; %bb.0:516; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)517; GCN-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0518; GCN-NEXT: v_and_b32_e32 v1, 0x1fffffff, v1519; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0520; GCN-NEXT: v_lshlrev_b32_e32 v2, 2, v1521; GCN-NEXT: v_mov_b32_e32 v1, 0522; GCN-NEXT: v_mov_b32_e32 v3, 0523; GCN-NEXT: s_setpc_b64 s[30:31]524;525; GFX10-LABEL: v_shl_v2i64_sext_v2i32:526; GFX10: ; %bb.0:527; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX10-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0529; GFX10-NEXT: v_and_b32_e32 v1, 0x1fffffff, v1530; GFX10-NEXT: v_mov_b32_e32 v3, 0531; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0532; GFX10-NEXT: v_lshlrev_b32_e32 v2, 2, v1533; GFX10-NEXT: v_mov_b32_e32 v1, 0534; GFX10-NEXT: s_setpc_b64 s[30:31]535;536; GFX11-LABEL: v_shl_v2i64_sext_v2i32:537; GFX11: ; %bb.0:538; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)539; GFX11-NEXT: v_and_b32_e32 v0, 0x1fffffff, v0540; GFX11-NEXT: v_and_b32_e32 v1, 0x1fffffff, v1541; GFX11-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v1542; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_lshlrev_b32 v0, 2, v0543; GFX11-NEXT: s_setpc_b64 s[30:31]544 %and = and <2 x i32> %x, <i32 536870911, i32 536870911>545 %ext = sext <2 x i32> %and to <2 x i64>546 %shl = shl <2 x i64> %ext, <i64 2, i64 2>547 ret <2 x i64> %shl548}549 550define amdgpu_ps i32 @s_shl_i32_zext_i16(i16 inreg %x) {551; GCN-LABEL: s_shl_i32_zext_i16:552; GCN: ; %bb.0:553; GCN-NEXT: s_and_b32 s0, s0, 0x3fff554; GCN-NEXT: s_lshl_b32 s0, s0, 2555; GCN-NEXT: ; return to shader part epilog556;557; GFX10PLUS-LABEL: s_shl_i32_zext_i16:558; GFX10PLUS: ; %bb.0:559; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0x3fff560; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 2561; GFX10PLUS-NEXT: ; return to shader part epilog562 %and = and i16 %x, 16383563 %ext = zext i16 %and to i32564 %shl = shl i32 %ext, 2565 ret i32 %shl566}567 568define i32 @v_shl_i32_zext_i16(i16 %x) {569; GFX7-LABEL: v_shl_i32_zext_i16:570; GFX7: ; %bb.0:571; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)572; GFX7-NEXT: v_and_b32_e32 v0, 0x3fff, v0573; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0574; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0575; GFX7-NEXT: s_setpc_b64 s[30:31]576;577; GFX8-LABEL: v_shl_i32_zext_i16:578; GFX8: ; %bb.0:579; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; GFX8-NEXT: v_and_b32_e32 v0, 0x3fff, v0581; GFX8-NEXT: v_lshlrev_b16_e32 v0, 2, v0582; GFX8-NEXT: s_setpc_b64 s[30:31]583;584; GFX9-LABEL: v_shl_i32_zext_i16:585; GFX9: ; %bb.0:586; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)587; GFX9-NEXT: v_and_b32_e32 v0, 0x3fff, v0588; GFX9-NEXT: v_lshlrev_b16_e32 v0, 2, v0589; GFX9-NEXT: s_setpc_b64 s[30:31]590;591; GFX10PLUS-LABEL: v_shl_i32_zext_i16:592; GFX10PLUS: ; %bb.0:593; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0x3fff, v0595; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 2, v0596; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v0597; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]598 %and = and i16 %x, 16383599 %ext = zext i16 %and to i32600 %shl = shl i32 %ext, 2601 ret i32 %shl602}603 604define amdgpu_ps <2 x i32> @s_shl_v2i32_zext_v2i16(<2 x i16> inreg %x) {605; GFX7-LABEL: s_shl_v2i32_zext_v2i16:606; GFX7: ; %bb.0:607; GFX7-NEXT: s_lshl_b32 s1, s1, 16608; GFX7-NEXT: s_and_b32 s0, s0, 0xffff609; GFX7-NEXT: s_or_b32 s0, s1, s0610; GFX7-NEXT: s_and_b32 s0, s0, 0x3fff3fff611; GFX7-NEXT: s_lshr_b32 s1, s0, 16612; GFX7-NEXT: s_lshl_b32 s0, s0, 2613; GFX7-NEXT: s_lshl_b32 s1, s1, 2614; GFX7-NEXT: s_and_b32 s0, s0, 0xffff615; GFX7-NEXT: s_and_b32 s1, s1, 0xffff616; GFX7-NEXT: ; return to shader part epilog617;618; GFX8-LABEL: s_shl_v2i32_zext_v2i16:619; GFX8: ; %bb.0:620; GFX8-NEXT: s_and_b32 s0, s0, 0x3fff3fff621; GFX8-NEXT: s_lshr_b32 s1, s0, 16622; GFX8-NEXT: s_lshl_b32 s0, s0, 2623; GFX8-NEXT: s_lshl_b32 s1, s1, 2624; GFX8-NEXT: s_and_b32 s0, 0xffff, s0625; GFX8-NEXT: s_and_b32 s1, 0xffff, s1626; GFX8-NEXT: ; return to shader part epilog627;628; GFX9-LABEL: s_shl_v2i32_zext_v2i16:629; GFX9: ; %bb.0:630; GFX9-NEXT: s_and_b32 s0, s0, 0x3fff3fff631; GFX9-NEXT: s_lshr_b32 s1, s0, 16632; GFX9-NEXT: s_lshl_b32 s0, s0, 0x20002633; GFX9-NEXT: s_lshl_b32 s1, s1, 2634; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1635; GFX9-NEXT: s_lshr_b32 s1, s0, 16636; GFX9-NEXT: s_and_b32 s0, s0, 0xffff637; GFX9-NEXT: ; return to shader part epilog638;639; GFX10PLUS-LABEL: s_shl_v2i32_zext_v2i16:640; GFX10PLUS: ; %bb.0:641; GFX10PLUS-NEXT: s_and_b32 s0, s0, 0x3fff3fff642; GFX10PLUS-NEXT: s_lshr_b32 s1, s0, 16643; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 0x20002644; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 2645; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s0, s1646; GFX10PLUS-NEXT: s_and_b32 s0, s1, 0xffff647; GFX10PLUS-NEXT: s_lshr_b32 s1, s1, 16648; GFX10PLUS-NEXT: ; return to shader part epilog649 %and = and <2 x i16> %x, <i16 16383, i16 16383>650 %ext = zext <2 x i16> %and to <2 x i32>651 %shl = shl <2 x i32> %ext, <i32 2, i32 2>652 ret <2 x i32> %shl653}654 655; FIXME: This doesn't do what we want. The pre-legalizer combiner656; fails to handle the vector splat. The post-legalizer sees the zext657; legalized into the and. This is probably not that important, since658; we really do this combine in the machine level for lowered659; getelementptrs.660define <2 x i32> @v_shl_v2i32_zext_v2i16(<2 x i16> %x) {661; GFX7-LABEL: v_shl_v2i32_zext_v2i16:662; GFX7: ; %bb.0:663; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)664; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1665; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0666; GFX7-NEXT: v_or_b32_e32 v0, v1, v0667; GFX7-NEXT: v_and_b32_e32 v0, 0x3fff3fff, v0668; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v0669; GFX7-NEXT: v_lshlrev_b32_e32 v0, 2, v0670; GFX7-NEXT: v_lshlrev_b32_e32 v1, 2, v1671; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0672; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1673; GFX7-NEXT: s_setpc_b64 s[30:31]674;675; GFX8-LABEL: v_shl_v2i32_zext_v2i16:676; GFX8: ; %bb.0:677; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)678; GFX8-NEXT: v_and_b32_e32 v1, 0x3fff3fff, v0679; GFX8-NEXT: v_mov_b32_e32 v2, 2680; GFX8-NEXT: v_lshlrev_b16_e32 v0, 2, v1681; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1682; GFX8-NEXT: s_setpc_b64 s[30:31]683;684; GFX9-LABEL: v_shl_v2i32_zext_v2i16:685; GFX9: ; %bb.0:686; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)687; GFX9-NEXT: v_and_b32_e32 v0, 0x3fff3fff, v0688; GFX9-NEXT: v_pk_lshlrev_b16 v0, 2, v0 op_sel_hi:[0,1]689; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0690; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0691; GFX9-NEXT: s_setpc_b64 s[30:31]692;693; GFX10PLUS-LABEL: v_shl_v2i32_zext_v2i16:694; GFX10PLUS: ; %bb.0:695; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)696; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0x3fff3fff, v0697; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, 2, v0 op_sel_hi:[0,1]698; GFX10PLUS-NEXT: v_and_b32_e32 v0, 0xffff, v1699; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v1, 16, v1700; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]701 %and = and <2 x i16> %x, <i16 16383, i16 16383>702 %ext = zext <2 x i16> %and to <2 x i32>703 %shl = shl <2 x i32> %ext, <i32 2, i32 2>704 ret <2 x i32> %shl705}706 707declare i32 @llvm.amdgcn.workitem.id.x() #0708 709attributes #0 = { nounwind readnone speculatable willreturn }710