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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s5; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define i8 @v_shl_i8(i8 %value, i8 %amount) {9; GFX6-LABEL: v_shl_i8:10; GFX6: ; %bb.0:11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v113; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v014; GFX6-NEXT: s_setpc_b64 s[30:31]15;16; GFX8-LABEL: v_shl_i8:17; GFX8: ; %bb.0:18; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)19; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD20; GFX8-NEXT: s_setpc_b64 s[30:31]21;22; GFX9-LABEL: v_shl_i8:23; GFX9: ; %bb.0:24; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; GFX9-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD26; GFX9-NEXT: s_setpc_b64 s[30:31]27;28; GFX10PLUS-LABEL: v_shl_i8:29; GFX10PLUS: ; %bb.0:30; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xff, v132; GFX10PLUS-NEXT: v_lshlrev_b16 v0, v1, v033; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]34 %result = shl i8 %value, %amount35 ret i8 %result36}37 38define i8 @v_shl_i8_7(i8 %value) {39; GFX6-LABEL: v_shl_i8_7:40; GFX6: ; %bb.0:41; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX6-NEXT: v_lshlrev_b32_e32 v0, 7, v043; GFX6-NEXT: s_setpc_b64 s[30:31]44;45; GFX8-LABEL: v_shl_i8_7:46; GFX8: ; %bb.0:47; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)48; GFX8-NEXT: v_lshlrev_b16_e32 v0, 7, v049; GFX8-NEXT: s_setpc_b64 s[30:31]50;51; GFX9-LABEL: v_shl_i8_7:52; GFX9: ; %bb.0:53; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)54; GFX9-NEXT: v_lshlrev_b16_e32 v0, 7, v055; GFX9-NEXT: s_setpc_b64 s[30:31]56;57; GFX10PLUS-LABEL: v_shl_i8_7:58; GFX10PLUS: ; %bb.0:59; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)60; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 7, v061; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]62 %result = shl i8 %value, 763 ret i8 %result64}65 66define amdgpu_ps i8 @s_shl_i8(i8 inreg %value, i8 inreg %amount) {67; GFX6-LABEL: s_shl_i8:68; GFX6: ; %bb.0:69; GFX6-NEXT: s_lshl_b32 s0, s0, s170; GFX6-NEXT: ; return to shader part epilog71;72; GFX8-LABEL: s_shl_i8:73; GFX8: ; %bb.0:74; GFX8-NEXT: s_and_b32 s1, s1, 0xff75; GFX8-NEXT: s_lshl_b32 s0, s0, s176; GFX8-NEXT: ; return to shader part epilog77;78; GFX9-LABEL: s_shl_i8:79; GFX9: ; %bb.0:80; GFX9-NEXT: s_and_b32 s1, s1, 0xff81; GFX9-NEXT: s_lshl_b32 s0, s0, s182; GFX9-NEXT: ; return to shader part epilog83;84; GFX10PLUS-LABEL: s_shl_i8:85; GFX10PLUS: ; %bb.0:86; GFX10PLUS-NEXT: s_and_b32 s1, s1, 0xff87; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s188; GFX10PLUS-NEXT: ; return to shader part epilog89 %result = shl i8 %value, %amount90 ret i8 %result91}92 93define amdgpu_ps i8 @s_shl_i8_7(i8 inreg %value) {94; GCN-LABEL: s_shl_i8_7:95; GCN: ; %bb.0:96; GCN-NEXT: s_lshl_b32 s0, s0, 797; GCN-NEXT: ; return to shader part epilog98;99; GFX10PLUS-LABEL: s_shl_i8_7:100; GFX10PLUS: ; %bb.0:101; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 7102; GFX10PLUS-NEXT: ; return to shader part epilog103 %result = shl i8 %value, 7104 ret i8 %result105}106 107 108define i24 @v_shl_i24(i24 %value, i24 %amount) {109; GCN-LABEL: v_shl_i24:110; GCN: ; %bb.0:111; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)112; GCN-NEXT: v_and_b32_e32 v1, 0xffffff, v1113; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0114; GCN-NEXT: s_setpc_b64 s[30:31]115;116; GFX10PLUS-LABEL: v_shl_i24:117; GFX10PLUS: ; %bb.0:118; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; GFX10PLUS-NEXT: v_and_b32_e32 v1, 0xffffff, v1120; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v1, v0121; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]122 %result = shl i24 %value, %amount123 ret i24 %result124}125 126define i24 @v_shl_i24_7(i24 %value) {127; GCN-LABEL: v_shl_i24_7:128; GCN: ; %bb.0:129; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)130; GCN-NEXT: v_lshlrev_b32_e32 v0, 7, v0131; GCN-NEXT: s_setpc_b64 s[30:31]132;133; GFX10PLUS-LABEL: v_shl_i24_7:134; GFX10PLUS: ; %bb.0:135; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)136; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 7, v0137; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]138 %result = shl i24 %value, 7139 ret i24 %result140}141 142define amdgpu_ps i24 @s_shl_i24(i24 inreg %value, i24 inreg %amount) {143; GCN-LABEL: s_shl_i24:144; GCN: ; %bb.0:145; GCN-NEXT: s_lshl_b32 s0, s0, s1146; GCN-NEXT: ; return to shader part epilog147;148; GFX10PLUS-LABEL: s_shl_i24:149; GFX10PLUS: ; %bb.0:150; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s1151; GFX10PLUS-NEXT: ; return to shader part epilog152 %result = shl i24 %value, %amount153 ret i24 %result154}155 156define amdgpu_ps i24 @s_shl_i24_7(i24 inreg %value) {157; GCN-LABEL: s_shl_i24_7:158; GCN: ; %bb.0:159; GCN-NEXT: s_lshl_b32 s0, s0, 7160; GCN-NEXT: ; return to shader part epilog161;162; GFX10PLUS-LABEL: s_shl_i24_7:163; GFX10PLUS: ; %bb.0:164; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 7165; GFX10PLUS-NEXT: ; return to shader part epilog166 %result = shl i24 %value, 7167 ret i24 %result168}169 170define i32 @v_shl_i32(i32 %value, i32 %amount) {171; GCN-LABEL: v_shl_i32:172; GCN: ; %bb.0:173; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; GCN-NEXT: v_lshlrev_b32_e32 v0, v1, v0175; GCN-NEXT: s_setpc_b64 s[30:31]176;177; GFX10PLUS-LABEL: v_shl_i32:178; GFX10PLUS: ; %bb.0:179; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)180; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v1, v0181; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]182 %result = shl i32 %value, %amount183 ret i32 %result184}185 186define i32 @v_shl_i32_31(i32 %value) {187; GCN-LABEL: v_shl_i32_31:188; GCN: ; %bb.0:189; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0191; GCN-NEXT: s_setpc_b64 s[30:31]192;193; GFX10PLUS-LABEL: v_shl_i32_31:194; GFX10PLUS: ; %bb.0:195; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)196; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 31, v0197; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]198 %result = shl i32 %value, 31199 ret i32 %result200}201 202define amdgpu_ps i32 @s_shl_i32(i32 inreg %value, i32 inreg %amount) {203; GCN-LABEL: s_shl_i32:204; GCN: ; %bb.0:205; GCN-NEXT: s_lshl_b32 s0, s0, s1206; GCN-NEXT: ; return to shader part epilog207;208; GFX10PLUS-LABEL: s_shl_i32:209; GFX10PLUS: ; %bb.0:210; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s1211; GFX10PLUS-NEXT: ; return to shader part epilog212 %result = shl i32 %value, %amount213 ret i32 %result214}215 216define amdgpu_ps i32 @s_shl_i32_31(i32 inreg %value) {217; GCN-LABEL: s_shl_i32_31:218; GCN: ; %bb.0:219; GCN-NEXT: s_lshl_b32 s0, s0, 31220; GCN-NEXT: ; return to shader part epilog221;222; GFX10PLUS-LABEL: s_shl_i32_31:223; GFX10PLUS: ; %bb.0:224; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 31225; GFX10PLUS-NEXT: ; return to shader part epilog226 %result = shl i32 %value, 31227 ret i32 %result228}229 230define amdgpu_ps float @shl_i32_sv(i32 inreg %value, i32 %amount) {231; GFX6-LABEL: shl_i32_sv:232; GFX6: ; %bb.0:233; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0234; GFX6-NEXT: ; return to shader part epilog235;236; GFX8-LABEL: shl_i32_sv:237; GFX8: ; %bb.0:238; GFX8-NEXT: v_lshlrev_b32_e64 v0, v0, s0239; GFX8-NEXT: ; return to shader part epilog240;241; GFX9-LABEL: shl_i32_sv:242; GFX9: ; %bb.0:243; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s0244; GFX9-NEXT: ; return to shader part epilog245;246; GFX10PLUS-LABEL: shl_i32_sv:247; GFX10PLUS: ; %bb.0:248; GFX10PLUS-NEXT: v_lshlrev_b32_e64 v0, v0, s0249; GFX10PLUS-NEXT: ; return to shader part epilog250 %result = shl i32 %value, %amount251 %cast = bitcast i32 %result to float252 ret float %cast253}254 255define amdgpu_ps float @shl_i32_vs(i32 %value, i32 inreg %amount) {256; GCN-LABEL: shl_i32_vs:257; GCN: ; %bb.0:258; GCN-NEXT: v_lshlrev_b32_e32 v0, s0, v0259; GCN-NEXT: ; return to shader part epilog260;261; GFX10PLUS-LABEL: shl_i32_vs:262; GFX10PLUS: ; %bb.0:263; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, s0, v0264; GFX10PLUS-NEXT: ; return to shader part epilog265 %result = shl i32 %value, %amount266 %cast = bitcast i32 %result to float267 ret float %cast268}269 270define <2 x i32> @v_shl_v2i32(<2 x i32> %value, <2 x i32> %amount) {271; GCN-LABEL: v_shl_v2i32:272; GCN: ; %bb.0:273; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)274; GCN-NEXT: v_lshlrev_b32_e32 v0, v2, v0275; GCN-NEXT: v_lshlrev_b32_e32 v1, v3, v1276; GCN-NEXT: s_setpc_b64 s[30:31]277;278; GFX10PLUS-LABEL: v_shl_v2i32:279; GFX10PLUS: ; %bb.0:280; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)281; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v2, v0282; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, v3, v1283; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]284 %result = shl <2 x i32> %value, %amount285 ret <2 x i32> %result286}287 288define <2 x i32> @v_shl_v2i32_31(<2 x i32> %value) {289; GCN-LABEL: v_shl_v2i32_31:290; GCN: ; %bb.0:291; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)292; GCN-NEXT: v_lshlrev_b32_e32 v0, 31, v0293; GCN-NEXT: v_lshlrev_b32_e32 v1, 31, v1294; GCN-NEXT: s_setpc_b64 s[30:31]295;296; GFX10PLUS-LABEL: v_shl_v2i32_31:297; GFX10PLUS: ; %bb.0:298; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)299; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 31, v0300; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 31, v1301; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]302 %result = shl <2 x i32> %value, <i32 31, i32 31>303 ret <2 x i32> %result304}305 306define amdgpu_ps <2 x i32> @s_shl_v2i32(<2 x i32> inreg %value, <2 x i32> inreg %amount) {307; GCN-LABEL: s_shl_v2i32:308; GCN: ; %bb.0:309; GCN-NEXT: s_lshl_b32 s0, s0, s2310; GCN-NEXT: s_lshl_b32 s1, s1, s3311; GCN-NEXT: ; return to shader part epilog312;313; GFX10PLUS-LABEL: s_shl_v2i32:314; GFX10PLUS: ; %bb.0:315; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s2316; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s3317; GFX10PLUS-NEXT: ; return to shader part epilog318 %result = shl <2 x i32> %value, %amount319 ret <2 x i32> %result320}321 322define <3 x i32> @v_shl_v3i32(<3 x i32> %value, <3 x i32> %amount) {323; GCN-LABEL: v_shl_v3i32:324; GCN: ; %bb.0:325; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)326; GCN-NEXT: v_lshlrev_b32_e32 v0, v3, v0327; GCN-NEXT: v_lshlrev_b32_e32 v1, v4, v1328; GCN-NEXT: v_lshlrev_b32_e32 v2, v5, v2329; GCN-NEXT: s_setpc_b64 s[30:31]330;331; GFX10PLUS-LABEL: v_shl_v3i32:332; GFX10PLUS: ; %bb.0:333; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v3, v0335; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, v4, v1336; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v2, v5, v2337; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]338 %result = shl <3 x i32> %value, %amount339 ret <3 x i32> %result340}341 342define amdgpu_ps <3 x i32> @s_shl_v3i32(<3 x i32> inreg %value, <3 x i32> inreg %amount) {343; GCN-LABEL: s_shl_v3i32:344; GCN: ; %bb.0:345; GCN-NEXT: s_lshl_b32 s0, s0, s3346; GCN-NEXT: s_lshl_b32 s1, s1, s4347; GCN-NEXT: s_lshl_b32 s2, s2, s5348; GCN-NEXT: ; return to shader part epilog349;350; GFX10PLUS-LABEL: s_shl_v3i32:351; GFX10PLUS: ; %bb.0:352; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s3353; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s4354; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, s5355; GFX10PLUS-NEXT: ; return to shader part epilog356 %result = shl <3 x i32> %value, %amount357 ret <3 x i32> %result358}359 360define <4 x i32> @v_shl_v4i32(<4 x i32> %value, <4 x i32> %amount) {361; GCN-LABEL: v_shl_v4i32:362; GCN: ; %bb.0:363; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)364; GCN-NEXT: v_lshlrev_b32_e32 v0, v4, v0365; GCN-NEXT: v_lshlrev_b32_e32 v1, v5, v1366; GCN-NEXT: v_lshlrev_b32_e32 v2, v6, v2367; GCN-NEXT: v_lshlrev_b32_e32 v3, v7, v3368; GCN-NEXT: s_setpc_b64 s[30:31]369;370; GFX10PLUS-LABEL: v_shl_v4i32:371; GFX10PLUS: ; %bb.0:372; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)373; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v4, v0374; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, v5, v1375; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v2, v6, v2376; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v3, v7, v3377; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]378 %result = shl <4 x i32> %value, %amount379 ret <4 x i32> %result380}381 382define amdgpu_ps <4 x i32> @s_shl_v4i32(<4 x i32> inreg %value, <4 x i32> inreg %amount) {383; GCN-LABEL: s_shl_v4i32:384; GCN: ; %bb.0:385; GCN-NEXT: s_lshl_b32 s0, s0, s4386; GCN-NEXT: s_lshl_b32 s1, s1, s5387; GCN-NEXT: s_lshl_b32 s2, s2, s6388; GCN-NEXT: s_lshl_b32 s3, s3, s7389; GCN-NEXT: ; return to shader part epilog390;391; GFX10PLUS-LABEL: s_shl_v4i32:392; GFX10PLUS: ; %bb.0:393; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s4394; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s5395; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, s6396; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, s7397; GFX10PLUS-NEXT: ; return to shader part epilog398 %result = shl <4 x i32> %value, %amount399 ret <4 x i32> %result400}401 402define <5 x i32> @v_shl_v5i32(<5 x i32> %value, <5 x i32> %amount) {403; GCN-LABEL: v_shl_v5i32:404; GCN: ; %bb.0:405; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)406; GCN-NEXT: v_lshlrev_b32_e32 v0, v5, v0407; GCN-NEXT: v_lshlrev_b32_e32 v1, v6, v1408; GCN-NEXT: v_lshlrev_b32_e32 v2, v7, v2409; GCN-NEXT: v_lshlrev_b32_e32 v3, v8, v3410; GCN-NEXT: v_lshlrev_b32_e32 v4, v9, v4411; GCN-NEXT: s_setpc_b64 s[30:31]412;413; GFX10PLUS-LABEL: v_shl_v5i32:414; GFX10PLUS: ; %bb.0:415; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, v5, v0417; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, v6, v1418; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v2, v7, v2419; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v3, v8, v3420; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v4, v9, v4421; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]422 %result = shl <5 x i32> %value, %amount423 ret <5 x i32> %result424}425 426define amdgpu_ps <5 x i32> @s_shl_v5i32(<5 x i32> inreg %value, <5 x i32> inreg %amount) {427; GCN-LABEL: s_shl_v5i32:428; GCN: ; %bb.0:429; GCN-NEXT: s_lshl_b32 s0, s0, s5430; GCN-NEXT: s_lshl_b32 s1, s1, s6431; GCN-NEXT: s_lshl_b32 s2, s2, s7432; GCN-NEXT: s_lshl_b32 s3, s3, s8433; GCN-NEXT: s_lshl_b32 s4, s4, s9434; GCN-NEXT: ; return to shader part epilog435;436; GFX10PLUS-LABEL: s_shl_v5i32:437; GFX10PLUS: ; %bb.0:438; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s5439; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s6440; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, s7441; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, s8442; GFX10PLUS-NEXT: s_lshl_b32 s4, s4, s9443; GFX10PLUS-NEXT: ; return to shader part epilog444 %result = shl <5 x i32> %value, %amount445 ret <5 x i32> %result446}447 448define <16 x i32> @v_shl_v16i32(<16 x i32> %value, <16 x i32> %amount) {449; GCN-LABEL: v_shl_v16i32:450; GCN: ; %bb.0:451; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)452; GCN-NEXT: v_lshlrev_b32_e32 v0, v16, v0453; GCN-NEXT: buffer_load_dword v16, off, s[0:3], s32454; GCN-NEXT: v_lshlrev_b32_e32 v1, v17, v1455; GCN-NEXT: v_lshlrev_b32_e32 v2, v18, v2456; GCN-NEXT: v_lshlrev_b32_e32 v3, v19, v3457; GCN-NEXT: v_lshlrev_b32_e32 v4, v20, v4458; GCN-NEXT: v_lshlrev_b32_e32 v5, v21, v5459; GCN-NEXT: v_lshlrev_b32_e32 v6, v22, v6460; GCN-NEXT: v_lshlrev_b32_e32 v7, v23, v7461; GCN-NEXT: v_lshlrev_b32_e32 v8, v24, v8462; GCN-NEXT: v_lshlrev_b32_e32 v9, v25, v9463; GCN-NEXT: v_lshlrev_b32_e32 v10, v26, v10464; GCN-NEXT: v_lshlrev_b32_e32 v11, v27, v11465; GCN-NEXT: v_lshlrev_b32_e32 v12, v28, v12466; GCN-NEXT: v_lshlrev_b32_e32 v13, v29, v13467; GCN-NEXT: v_lshlrev_b32_e32 v14, v30, v14468; GCN-NEXT: s_waitcnt vmcnt(0)469; GCN-NEXT: v_lshlrev_b32_e32 v15, v16, v15470; GCN-NEXT: s_setpc_b64 s[30:31]471;472; GFX10-LABEL: v_shl_v16i32:473; GFX10: ; %bb.0:474; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)475; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32476; GFX10-NEXT: v_lshlrev_b32_e32 v0, v16, v0477; GFX10-NEXT: v_lshlrev_b32_e32 v1, v17, v1478; GFX10-NEXT: v_lshlrev_b32_e32 v2, v18, v2479; GFX10-NEXT: v_lshlrev_b32_e32 v3, v19, v3480; GFX10-NEXT: v_lshlrev_b32_e32 v4, v20, v4481; GFX10-NEXT: v_lshlrev_b32_e32 v5, v21, v5482; GFX10-NEXT: v_lshlrev_b32_e32 v6, v22, v6483; GFX10-NEXT: v_lshlrev_b32_e32 v7, v23, v7484; GFX10-NEXT: v_lshlrev_b32_e32 v8, v24, v8485; GFX10-NEXT: v_lshlrev_b32_e32 v9, v25, v9486; GFX10-NEXT: v_lshlrev_b32_e32 v10, v26, v10487; GFX10-NEXT: v_lshlrev_b32_e32 v11, v27, v11488; GFX10-NEXT: v_lshlrev_b32_e32 v12, v28, v12489; GFX10-NEXT: v_lshlrev_b32_e32 v13, v29, v13490; GFX10-NEXT: v_lshlrev_b32_e32 v14, v30, v14491; GFX10-NEXT: s_waitcnt vmcnt(0)492; GFX10-NEXT: v_lshlrev_b32_e32 v15, v31, v15493; GFX10-NEXT: s_setpc_b64 s[30:31]494;495; GFX11-LABEL: v_shl_v16i32:496; GFX11: ; %bb.0:497; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)498; GFX11-NEXT: scratch_load_b32 v31, off, s32499; GFX11-NEXT: v_lshlrev_b32_e32 v0, v16, v0500; GFX11-NEXT: v_lshlrev_b32_e32 v1, v17, v1501; GFX11-NEXT: v_lshlrev_b32_e32 v2, v18, v2502; GFX11-NEXT: v_lshlrev_b32_e32 v3, v19, v3503; GFX11-NEXT: v_lshlrev_b32_e32 v4, v20, v4504; GFX11-NEXT: v_lshlrev_b32_e32 v5, v21, v5505; GFX11-NEXT: v_lshlrev_b32_e32 v6, v22, v6506; GFX11-NEXT: v_lshlrev_b32_e32 v7, v23, v7507; GFX11-NEXT: v_lshlrev_b32_e32 v8, v24, v8508; GFX11-NEXT: v_lshlrev_b32_e32 v9, v25, v9509; GFX11-NEXT: v_lshlrev_b32_e32 v10, v26, v10510; GFX11-NEXT: v_lshlrev_b32_e32 v11, v27, v11511; GFX11-NEXT: v_lshlrev_b32_e32 v12, v28, v12512; GFX11-NEXT: v_lshlrev_b32_e32 v13, v29, v13513; GFX11-NEXT: v_lshlrev_b32_e32 v14, v30, v14514; GFX11-NEXT: s_waitcnt vmcnt(0)515; GFX11-NEXT: v_lshlrev_b32_e32 v15, v31, v15516; GFX11-NEXT: s_setpc_b64 s[30:31]517 %result = shl <16 x i32> %value, %amount518 ret <16 x i32> %result519}520 521define amdgpu_ps <16 x i32> @s_shl_v16i32(<16 x i32> inreg %value, <16 x i32> inreg %amount) {522; GCN-LABEL: s_shl_v16i32:523; GCN: ; %bb.0:524; GCN-NEXT: s_lshl_b32 s0, s0, s16525; GCN-NEXT: s_lshl_b32 s1, s1, s17526; GCN-NEXT: s_lshl_b32 s2, s2, s18527; GCN-NEXT: s_lshl_b32 s3, s3, s19528; GCN-NEXT: s_lshl_b32 s4, s4, s20529; GCN-NEXT: s_lshl_b32 s5, s5, s21530; GCN-NEXT: s_lshl_b32 s6, s6, s22531; GCN-NEXT: s_lshl_b32 s7, s7, s23532; GCN-NEXT: s_lshl_b32 s8, s8, s24533; GCN-NEXT: s_lshl_b32 s9, s9, s25534; GCN-NEXT: s_lshl_b32 s10, s10, s26535; GCN-NEXT: s_lshl_b32 s11, s11, s27536; GCN-NEXT: s_lshl_b32 s12, s12, s28537; GCN-NEXT: s_lshl_b32 s13, s13, s29538; GCN-NEXT: s_lshl_b32 s14, s14, s30539; GCN-NEXT: s_lshl_b32 s15, s15, s31540; GCN-NEXT: ; return to shader part epilog541;542; GFX10PLUS-LABEL: s_shl_v16i32:543; GFX10PLUS: ; %bb.0:544; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s16545; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s17546; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, s18547; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, s19548; GFX10PLUS-NEXT: s_lshl_b32 s4, s4, s20549; GFX10PLUS-NEXT: s_lshl_b32 s5, s5, s21550; GFX10PLUS-NEXT: s_lshl_b32 s6, s6, s22551; GFX10PLUS-NEXT: s_lshl_b32 s7, s7, s23552; GFX10PLUS-NEXT: s_lshl_b32 s8, s8, s24553; GFX10PLUS-NEXT: s_lshl_b32 s9, s9, s25554; GFX10PLUS-NEXT: s_lshl_b32 s10, s10, s26555; GFX10PLUS-NEXT: s_lshl_b32 s11, s11, s27556; GFX10PLUS-NEXT: s_lshl_b32 s12, s12, s28557; GFX10PLUS-NEXT: s_lshl_b32 s13, s13, s29558; GFX10PLUS-NEXT: s_lshl_b32 s14, s14, s30559; GFX10PLUS-NEXT: s_lshl_b32 s15, s15, s31560; GFX10PLUS-NEXT: ; return to shader part epilog561 %result = shl <16 x i32> %value, %amount562 ret <16 x i32> %result563}564 565define i16 @v_shl_i16(i16 %value, i16 %amount) {566; GFX6-LABEL: v_shl_i16:567; GFX6: ; %bb.0:568; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1570; GFX6-NEXT: v_lshlrev_b32_e32 v0, v1, v0571; GFX6-NEXT: s_setpc_b64 s[30:31]572;573; GFX8-LABEL: v_shl_i16:574; GFX8: ; %bb.0:575; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)576; GFX8-NEXT: v_lshlrev_b16_e32 v0, v1, v0577; GFX8-NEXT: s_setpc_b64 s[30:31]578;579; GFX9-LABEL: v_shl_i16:580; GFX9: ; %bb.0:581; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)582; GFX9-NEXT: v_lshlrev_b16_e32 v0, v1, v0583; GFX9-NEXT: s_setpc_b64 s[30:31]584;585; GFX10PLUS-LABEL: v_shl_i16:586; GFX10PLUS: ; %bb.0:587; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)588; GFX10PLUS-NEXT: v_lshlrev_b16 v0, v1, v0589; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]590 %result = shl i16 %value, %amount591 ret i16 %result592}593 594define i16 @v_shl_i16_15(i16 %value) {595; GFX6-LABEL: v_shl_i16_15:596; GFX6: ; %bb.0:597; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)598; GFX6-NEXT: v_lshlrev_b32_e32 v0, 15, v0599; GFX6-NEXT: s_setpc_b64 s[30:31]600;601; GFX8-LABEL: v_shl_i16_15:602; GFX8: ; %bb.0:603; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)604; GFX8-NEXT: v_lshlrev_b16_e32 v0, 15, v0605; GFX8-NEXT: s_setpc_b64 s[30:31]606;607; GFX9-LABEL: v_shl_i16_15:608; GFX9: ; %bb.0:609; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)610; GFX9-NEXT: v_lshlrev_b16_e32 v0, 15, v0611; GFX9-NEXT: s_setpc_b64 s[30:31]612;613; GFX10PLUS-LABEL: v_shl_i16_15:614; GFX10PLUS: ; %bb.0:615; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)616; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 15, v0617; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]618 %result = shl i16 %value, 15619 ret i16 %result620}621 622define amdgpu_ps i16 @s_shl_i16(i16 inreg %value, i16 inreg %amount) {623; GCN-LABEL: s_shl_i16:624; GCN: ; %bb.0:625; GCN-NEXT: s_lshl_b32 s0, s0, s1626; GCN-NEXT: ; return to shader part epilog627;628; GFX10PLUS-LABEL: s_shl_i16:629; GFX10PLUS: ; %bb.0:630; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s1631; GFX10PLUS-NEXT: ; return to shader part epilog632 %result = shl i16 %value, %amount633 ret i16 %result634}635 636define amdgpu_ps i16 @s_shl_i16_15(i16 inreg %value) {637; GCN-LABEL: s_shl_i16_15:638; GCN: ; %bb.0:639; GCN-NEXT: s_lshl_b32 s0, s0, 15640; GCN-NEXT: ; return to shader part epilog641;642; GFX10PLUS-LABEL: s_shl_i16_15:643; GFX10PLUS: ; %bb.0:644; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 15645; GFX10PLUS-NEXT: ; return to shader part epilog646 %result = shl i16 %value, 15647 ret i16 %result648}649 650define amdgpu_ps half @shl_i16_sv(i16 inreg %value, i16 %amount) {651; GFX6-LABEL: shl_i16_sv:652; GFX6: ; %bb.0:653; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0654; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0655; GFX6-NEXT: ; return to shader part epilog656;657; GFX8-LABEL: shl_i16_sv:658; GFX8: ; %bb.0:659; GFX8-NEXT: v_lshlrev_b16_e64 v0, v0, s0660; GFX8-NEXT: ; return to shader part epilog661;662; GFX9-LABEL: shl_i16_sv:663; GFX9: ; %bb.0:664; GFX9-NEXT: v_lshlrev_b16_e64 v0, v0, s0665; GFX9-NEXT: ; return to shader part epilog666;667; GFX10PLUS-LABEL: shl_i16_sv:668; GFX10PLUS: ; %bb.0:669; GFX10PLUS-NEXT: v_lshlrev_b16 v0, v0, s0670; GFX10PLUS-NEXT: ; return to shader part epilog671 %result = shl i16 %value, %amount672 %cast = bitcast i16 %result to half673 ret half %cast674}675 676define amdgpu_ps half @shl_i16_vs(i16 %value, i16 inreg %amount) {677; GFX6-LABEL: shl_i16_vs:678; GFX6: ; %bb.0:679; GFX6-NEXT: s_and_b32 s0, s0, 0xffff680; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0681; GFX6-NEXT: ; return to shader part epilog682;683; GFX8-LABEL: shl_i16_vs:684; GFX8: ; %bb.0:685; GFX8-NEXT: v_lshlrev_b16_e32 v0, s0, v0686; GFX8-NEXT: ; return to shader part epilog687;688; GFX9-LABEL: shl_i16_vs:689; GFX9: ; %bb.0:690; GFX9-NEXT: v_lshlrev_b16_e32 v0, s0, v0691; GFX9-NEXT: ; return to shader part epilog692;693; GFX10PLUS-LABEL: shl_i16_vs:694; GFX10PLUS: ; %bb.0:695; GFX10PLUS-NEXT: v_lshlrev_b16 v0, s0, v0696; GFX10PLUS-NEXT: ; return to shader part epilog697 %result = shl i16 %value, %amount698 %cast = bitcast i16 %result to half699 ret half %cast700}701 702define <2 x i16> @v_shl_v2i16(<2 x i16> %value, <2 x i16> %amount) {703; GFX6-LABEL: v_shl_v2i16:704; GFX6: ; %bb.0:705; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)706; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v2707; GFX6-NEXT: v_lshlrev_b32_e32 v0, v2, v0708; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3709; GFX6-NEXT: v_lshlrev_b32_e32 v1, v2, v1710; GFX6-NEXT: s_setpc_b64 s[30:31]711;712; GFX8-LABEL: v_shl_v2i16:713; GFX8: ; %bb.0:714; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)715; GFX8-NEXT: v_lshlrev_b16_e32 v2, v1, v0716; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1717; GFX8-NEXT: v_or_b32_e32 v0, v2, v0718; GFX8-NEXT: s_setpc_b64 s[30:31]719;720; GFX9-LABEL: v_shl_v2i16:721; GFX9: ; %bb.0:722; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)723; GFX9-NEXT: v_pk_lshlrev_b16 v0, v1, v0724; GFX9-NEXT: s_setpc_b64 s[30:31]725;726; GFX10PLUS-LABEL: v_shl_v2i16:727; GFX10PLUS: ; %bb.0:728; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)729; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, v1, v0730; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]731 %result = shl <2 x i16> %value, %amount732 ret <2 x i16> %result733}734 735define <2 x i16> @v_shl_v2i16_15(<2 x i16> %value) {736; GFX6-LABEL: v_shl_v2i16_15:737; GFX6: ; %bb.0:738; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)739; GFX6-NEXT: v_lshlrev_b32_e32 v0, 15, v0740; GFX6-NEXT: v_lshlrev_b32_e32 v1, 15, v1741; GFX6-NEXT: s_setpc_b64 s[30:31]742;743; GFX8-LABEL: v_shl_v2i16_15:744; GFX8: ; %bb.0:745; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)746; GFX8-NEXT: v_mov_b32_e32 v2, 15747; GFX8-NEXT: v_lshlrev_b16_e32 v1, 15, v0748; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1749; GFX8-NEXT: v_or_b32_e32 v0, v1, v0750; GFX8-NEXT: s_setpc_b64 s[30:31]751;752; GFX9-LABEL: v_shl_v2i16_15:753; GFX9: ; %bb.0:754; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)755; GFX9-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1]756; GFX9-NEXT: s_setpc_b64 s[30:31]757;758; GFX10PLUS-LABEL: v_shl_v2i16_15:759; GFX10PLUS: ; %bb.0:760; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)761; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, 15, v0 op_sel_hi:[0,1]762; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]763 %result = shl <2 x i16> %value, <i16 15, i16 15>764 ret <2 x i16> %result765}766 767define amdgpu_ps i32 @s_shl_v2i16(<2 x i16> inreg %value, <2 x i16> inreg %amount) {768; GFX6-LABEL: s_shl_v2i16:769; GFX6: ; %bb.0:770; GFX6-NEXT: s_lshl_b32 s1, s1, s3771; GFX6-NEXT: s_lshl_b32 s0, s0, s2772; GFX6-NEXT: s_and_b32 s1, s1, 0xffff773; GFX6-NEXT: s_and_b32 s0, s0, 0xffff774; GFX6-NEXT: s_lshl_b32 s1, s1, 16775; GFX6-NEXT: s_or_b32 s0, s0, s1776; GFX6-NEXT: ; return to shader part epilog777;778; GFX8-LABEL: s_shl_v2i16:779; GFX8: ; %bb.0:780; GFX8-NEXT: s_lshr_b32 s2, s0, 16781; GFX8-NEXT: s_lshr_b32 s3, s1, 16782; GFX8-NEXT: s_lshl_b32 s0, s0, s1783; GFX8-NEXT: s_lshl_b32 s1, s2, s3784; GFX8-NEXT: s_and_b32 s1, 0xffff, s1785; GFX8-NEXT: s_and_b32 s0, 0xffff, s0786; GFX8-NEXT: s_lshl_b32 s1, s1, 16787; GFX8-NEXT: s_or_b32 s0, s0, s1788; GFX8-NEXT: ; return to shader part epilog789;790; GFX9-LABEL: s_shl_v2i16:791; GFX9: ; %bb.0:792; GFX9-NEXT: s_lshr_b32 s2, s0, 16793; GFX9-NEXT: s_lshr_b32 s3, s1, 16794; GFX9-NEXT: s_lshl_b32 s0, s0, s1795; GFX9-NEXT: s_lshl_b32 s1, s2, s3796; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1797; GFX9-NEXT: ; return to shader part epilog798;799; GFX10PLUS-LABEL: s_shl_v2i16:800; GFX10PLUS: ; %bb.0:801; GFX10PLUS-NEXT: s_lshr_b32 s2, s0, 16802; GFX10PLUS-NEXT: s_lshr_b32 s3, s1, 16803; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s1804; GFX10PLUS-NEXT: s_lshl_b32 s1, s2, s3805; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s1806; GFX10PLUS-NEXT: ; return to shader part epilog807 %result = shl <2 x i16> %value, %amount808 %cast = bitcast <2 x i16> %result to i32809 ret i32 %cast810}811 812define amdgpu_ps float @shl_v2i16_sv(<2 x i16> inreg %value, <2 x i16> %amount) {813; GFX6-LABEL: shl_v2i16_sv:814; GFX6: ; %bb.0:815; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1816; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0817; GFX6-NEXT: v_lshl_b32_e32 v1, s1, v1818; GFX6-NEXT: v_lshl_b32_e32 v0, s0, v0819; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1820; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0821; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1822; GFX6-NEXT: v_or_b32_e32 v0, v0, v1823; GFX6-NEXT: ; return to shader part epilog824;825; GFX8-LABEL: shl_v2i16_sv:826; GFX8: ; %bb.0:827; GFX8-NEXT: s_lshr_b32 s1, s0, 16828; GFX8-NEXT: v_mov_b32_e32 v2, s1829; GFX8-NEXT: v_lshlrev_b16_e64 v1, v0, s0830; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD831; GFX8-NEXT: v_or_b32_e32 v0, v1, v0832; GFX8-NEXT: ; return to shader part epilog833;834; GFX9-LABEL: shl_v2i16_sv:835; GFX9: ; %bb.0:836; GFX9-NEXT: v_pk_lshlrev_b16 v0, v0, s0837; GFX9-NEXT: ; return to shader part epilog838;839; GFX10PLUS-LABEL: shl_v2i16_sv:840; GFX10PLUS: ; %bb.0:841; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, v0, s0842; GFX10PLUS-NEXT: ; return to shader part epilog843 %result = shl <2 x i16> %value, %amount844 %cast = bitcast <2 x i16> %result to float845 ret float %cast846}847 848define amdgpu_ps float @shl_v2i16_vs(<2 x i16> %value, <2 x i16> inreg %amount) {849; GFX6-LABEL: shl_v2i16_vs:850; GFX6: ; %bb.0:851; GFX6-NEXT: s_and_b32 s0, s0, 0xffff852; GFX6-NEXT: v_lshlrev_b32_e32 v0, s0, v0853; GFX6-NEXT: s_and_b32 s0, s1, 0xffff854; GFX6-NEXT: v_lshlrev_b32_e32 v1, s0, v1855; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1856; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0857; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1858; GFX6-NEXT: v_or_b32_e32 v0, v0, v1859; GFX6-NEXT: ; return to shader part epilog860;861; GFX8-LABEL: shl_v2i16_vs:862; GFX8: ; %bb.0:863; GFX8-NEXT: s_lshr_b32 s1, s0, 16864; GFX8-NEXT: v_mov_b32_e32 v2, s1865; GFX8-NEXT: v_lshlrev_b16_e32 v1, s0, v0866; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1867; GFX8-NEXT: v_or_b32_e32 v0, v1, v0868; GFX8-NEXT: ; return to shader part epilog869;870; GFX9-LABEL: shl_v2i16_vs:871; GFX9: ; %bb.0:872; GFX9-NEXT: v_pk_lshlrev_b16 v0, s0, v0873; GFX9-NEXT: ; return to shader part epilog874;875; GFX10PLUS-LABEL: shl_v2i16_vs:876; GFX10PLUS: ; %bb.0:877; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, s0, v0878; GFX10PLUS-NEXT: ; return to shader part epilog879 %result = shl <2 x i16> %value, %amount880 %cast = bitcast <2 x i16> %result to float881 ret float %cast882}883 884; FIXME885; define <3 x i16> @v_shl_v3i16(<3 x i16> %value, <3 x i16> %amount) {886; %result = shl <3 x i16> %value, %amount887; ret <3 x i16> %result888; }889 890; define amdgpu_ps <3 x i16> @s_shl_v3i16(<3 x i16> inreg %value, <3 x i16> inreg %amount) {891; %result = shl <3 x i16> %value, %amount892; ret <3 x i16> %result893; }894 895define <2 x float> @v_shl_v4i16(<4 x i16> %value, <4 x i16> %amount) {896; GFX6-LABEL: v_shl_v4i16:897; GFX6: ; %bb.0:898; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)899; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v4900; GFX6-NEXT: v_lshlrev_b32_e32 v0, v4, v0901; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v5902; GFX6-NEXT: v_lshlrev_b32_e32 v1, v4, v1903; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v6904; GFX6-NEXT: v_lshlrev_b32_e32 v2, v4, v2905; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v7906; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v1907; GFX6-NEXT: v_lshlrev_b32_e32 v3, v4, v3908; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v0909; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1910; GFX6-NEXT: v_or_b32_e32 v0, v0, v1911; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v2912; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v3913; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2914; GFX6-NEXT: v_or_b32_e32 v1, v1, v2915; GFX6-NEXT: s_setpc_b64 s[30:31]916;917; GFX8-LABEL: v_shl_v4i16:918; GFX8: ; %bb.0:919; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)920; GFX8-NEXT: v_lshlrev_b16_e32 v4, v2, v0921; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1922; GFX8-NEXT: v_lshlrev_b16_e32 v2, v3, v1923; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v3, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1924; GFX8-NEXT: v_or_b32_e32 v0, v4, v0925; GFX8-NEXT: v_or_b32_e32 v1, v2, v1926; GFX8-NEXT: s_setpc_b64 s[30:31]927;928; GFX9-LABEL: v_shl_v4i16:929; GFX9: ; %bb.0:930; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)931; GFX9-NEXT: v_pk_lshlrev_b16 v0, v2, v0932; GFX9-NEXT: v_pk_lshlrev_b16 v1, v3, v1933; GFX9-NEXT: s_setpc_b64 s[30:31]934;935; GFX10PLUS-LABEL: v_shl_v4i16:936; GFX10PLUS: ; %bb.0:937; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)938; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, v2, v0939; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, v3, v1940; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]941 %result = shl <4 x i16> %value, %amount942 %cast = bitcast <4 x i16> %result to <2 x float>943 ret <2 x float> %cast944}945 946define amdgpu_ps <2 x i32> @s_shl_v4i16(<4 x i16> inreg %value, <4 x i16> inreg %amount) {947; GFX6-LABEL: s_shl_v4i16:948; GFX6: ; %bb.0:949; GFX6-NEXT: s_lshl_b32 s1, s1, s5950; GFX6-NEXT: s_lshl_b32 s0, s0, s4951; GFX6-NEXT: s_and_b32 s1, s1, 0xffff952; GFX6-NEXT: s_lshl_b32 s2, s2, s6953; GFX6-NEXT: s_lshl_b32 s3, s3, s7954; GFX6-NEXT: s_and_b32 s0, s0, 0xffff955; GFX6-NEXT: s_lshl_b32 s1, s1, 16956; GFX6-NEXT: s_or_b32 s0, s0, s1957; GFX6-NEXT: s_and_b32 s1, s2, 0xffff958; GFX6-NEXT: s_and_b32 s2, s3, 0xffff959; GFX6-NEXT: s_lshl_b32 s2, s2, 16960; GFX6-NEXT: s_or_b32 s1, s1, s2961; GFX6-NEXT: ; return to shader part epilog962;963; GFX8-LABEL: s_shl_v4i16:964; GFX8: ; %bb.0:965; GFX8-NEXT: s_lshr_b32 s4, s0, 16966; GFX8-NEXT: s_lshr_b32 s6, s2, 16967; GFX8-NEXT: s_lshl_b32 s0, s0, s2968; GFX8-NEXT: s_lshl_b32 s2, s4, s6969; GFX8-NEXT: s_lshr_b32 s5, s1, 16970; GFX8-NEXT: s_lshr_b32 s7, s3, 16971; GFX8-NEXT: s_and_b32 s2, 0xffff, s2972; GFX8-NEXT: s_lshl_b32 s1, s1, s3973; GFX8-NEXT: s_lshl_b32 s3, s5, s7974; GFX8-NEXT: s_and_b32 s0, 0xffff, s0975; GFX8-NEXT: s_lshl_b32 s2, s2, 16976; GFX8-NEXT: s_or_b32 s0, s0, s2977; GFX8-NEXT: s_and_b32 s2, 0xffff, s3978; GFX8-NEXT: s_and_b32 s1, 0xffff, s1979; GFX8-NEXT: s_lshl_b32 s2, s2, 16980; GFX8-NEXT: s_or_b32 s1, s1, s2981; GFX8-NEXT: ; return to shader part epilog982;983; GFX9-LABEL: s_shl_v4i16:984; GFX9: ; %bb.0:985; GFX9-NEXT: s_lshr_b32 s4, s0, 16986; GFX9-NEXT: s_lshr_b32 s5, s2, 16987; GFX9-NEXT: s_lshl_b32 s0, s0, s2988; GFX9-NEXT: s_lshl_b32 s2, s4, s5989; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2990; GFX9-NEXT: s_lshr_b32 s2, s1, 16991; GFX9-NEXT: s_lshr_b32 s4, s3, 16992; GFX9-NEXT: s_lshl_b32 s1, s1, s3993; GFX9-NEXT: s_lshl_b32 s2, s2, s4994; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2995; GFX9-NEXT: ; return to shader part epilog996;997; GFX10PLUS-LABEL: s_shl_v4i16:998; GFX10PLUS: ; %bb.0:999; GFX10PLUS-NEXT: s_lshr_b32 s4, s0, 161000; GFX10PLUS-NEXT: s_lshr_b32 s5, s2, 161001; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s21002; GFX10PLUS-NEXT: s_lshl_b32 s2, s4, s51003; GFX10PLUS-NEXT: s_lshr_b32 s4, s1, 161004; GFX10PLUS-NEXT: s_lshr_b32 s5, s3, 161005; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s31006; GFX10PLUS-NEXT: s_lshl_b32 s3, s4, s51007; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s21008; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s31009; GFX10PLUS-NEXT: ; return to shader part epilog1010 %result = shl <4 x i16> %value, %amount1011 %cast = bitcast <4 x i16> %result to <2 x i32>1012 ret <2 x i32> %cast1013}1014 1015; FIXME1016; define <5 x i16> @v_shl_v5i16(<5 x i16> %value, <5 x i16> %amount) {1017; %result = shl <5 x i16> %value, %amount1018; ret <5 x i16> %result1019; }1020 1021; define amdgpu_ps <5 x i16> @s_shl_v5i16(<5 x i16> inreg %value, <5 x i16> inreg %amount) {1022; %result = shl <5 x i16> %value, %amount1023; ret <5 x i16> %result1024; }1025 1026; define <3 x float> @v_shl_v6i16(<6 x i16> %value, <6 x i16> %amount) {1027; %result = shl <6 x i16> %value, %amount1028; %cast = bitcast <6 x i16> %result to <3 x float>1029; ret <3 x float> %cast1030; }1031 1032; define amdgpu_ps <3 x i32> @s_shl_v6i16(<6 x i16> inreg %value, <6 x i16> inreg %amount) {1033; %result = shl <6 x i16> %value, %amount1034; %cast = bitcast <6 x i16> %result to <3 x i32>1035; ret <3 x i32> %cast1036; }1037 1038define <4 x float> @v_shl_v8i16(<8 x i16> %value, <8 x i16> %amount) {1039; GFX6-LABEL: v_shl_v8i16:1040; GFX6: ; %bb.0:1041; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1042; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v81043; GFX6-NEXT: v_lshlrev_b32_e32 v0, v8, v01044; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v91045; GFX6-NEXT: v_lshlrev_b32_e32 v1, v8, v11046; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v101047; GFX6-NEXT: v_lshlrev_b32_e32 v2, v8, v21048; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v111049; GFX6-NEXT: v_lshlrev_b32_e32 v3, v8, v31050; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v121051; GFX6-NEXT: v_lshlrev_b32_e32 v4, v8, v41052; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v131053; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v11054; GFX6-NEXT: v_lshlrev_b32_e32 v5, v8, v51055; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v141056; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v01057; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11058; GFX6-NEXT: v_lshlrev_b32_e32 v6, v8, v61059; GFX6-NEXT: v_and_b32_e32 v8, 0xffff, v151060; GFX6-NEXT: v_or_b32_e32 v0, v0, v11061; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v21062; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v31063; GFX6-NEXT: v_lshlrev_b32_e32 v7, v8, v71064; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v21065; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v51066; GFX6-NEXT: v_or_b32_e32 v1, v1, v21067; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v41068; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v31069; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v71070; GFX6-NEXT: v_or_b32_e32 v2, v2, v31071; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v61072; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v41073; GFX6-NEXT: v_or_b32_e32 v3, v3, v41074; GFX6-NEXT: s_setpc_b64 s[30:31]1075;1076; GFX8-LABEL: v_shl_v8i16:1077; GFX8: ; %bb.0:1078; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1079; GFX8-NEXT: v_lshlrev_b16_e32 v8, v4, v01080; GFX8-NEXT: v_lshlrev_b16_sdwa v0, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11081; GFX8-NEXT: v_lshlrev_b16_e32 v4, v5, v11082; GFX8-NEXT: v_lshlrev_b16_sdwa v1, v5, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11083; GFX8-NEXT: v_or_b32_e32 v1, v4, v11084; GFX8-NEXT: v_lshlrev_b16_e32 v4, v6, v21085; GFX8-NEXT: v_lshlrev_b16_sdwa v2, v6, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11086; GFX8-NEXT: v_or_b32_e32 v2, v4, v21087; GFX8-NEXT: v_lshlrev_b16_e32 v4, v7, v31088; GFX8-NEXT: v_lshlrev_b16_sdwa v3, v7, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_11089; GFX8-NEXT: v_or_b32_e32 v0, v8, v01090; GFX8-NEXT: v_or_b32_e32 v3, v4, v31091; GFX8-NEXT: s_setpc_b64 s[30:31]1092;1093; GFX9-LABEL: v_shl_v8i16:1094; GFX9: ; %bb.0:1095; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1096; GFX9-NEXT: v_pk_lshlrev_b16 v0, v4, v01097; GFX9-NEXT: v_pk_lshlrev_b16 v1, v5, v11098; GFX9-NEXT: v_pk_lshlrev_b16 v2, v6, v21099; GFX9-NEXT: v_pk_lshlrev_b16 v3, v7, v31100; GFX9-NEXT: s_setpc_b64 s[30:31]1101;1102; GFX10PLUS-LABEL: v_shl_v8i16:1103; GFX10PLUS: ; %bb.0:1104; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1105; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v0, v4, v01106; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v1, v5, v11107; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v2, v6, v21108; GFX10PLUS-NEXT: v_pk_lshlrev_b16 v3, v7, v31109; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1110 %result = shl <8 x i16> %value, %amount1111 %cast = bitcast <8 x i16> %result to <4 x float>1112 ret <4 x float> %cast1113}1114 1115define amdgpu_ps <4 x i32> @s_shl_v8i16(<8 x i16> inreg %value, <8 x i16> inreg %amount) {1116; GFX6-LABEL: s_shl_v8i16:1117; GFX6: ; %bb.0:1118; GFX6-NEXT: s_lshl_b32 s1, s1, s91119; GFX6-NEXT: s_lshl_b32 s0, s0, s81120; GFX6-NEXT: s_and_b32 s1, s1, 0xffff1121; GFX6-NEXT: s_lshl_b32 s2, s2, s101122; GFX6-NEXT: s_lshl_b32 s3, s3, s111123; GFX6-NEXT: s_and_b32 s0, s0, 0xffff1124; GFX6-NEXT: s_lshl_b32 s1, s1, 161125; GFX6-NEXT: s_lshl_b32 s5, s5, s131126; GFX6-NEXT: s_or_b32 s0, s0, s11127; GFX6-NEXT: s_and_b32 s1, s2, 0xffff1128; GFX6-NEXT: s_and_b32 s2, s3, 0xffff1129; GFX6-NEXT: s_lshl_b32 s4, s4, s121130; GFX6-NEXT: s_lshl_b32 s7, s7, s151131; GFX6-NEXT: s_lshl_b32 s2, s2, 161132; GFX6-NEXT: s_and_b32 s3, s5, 0xffff1133; GFX6-NEXT: s_lshl_b32 s6, s6, s141134; GFX6-NEXT: s_or_b32 s1, s1, s21135; GFX6-NEXT: s_and_b32 s2, s4, 0xffff1136; GFX6-NEXT: s_lshl_b32 s3, s3, 161137; GFX6-NEXT: s_and_b32 s4, s7, 0xffff1138; GFX6-NEXT: s_or_b32 s2, s2, s31139; GFX6-NEXT: s_and_b32 s3, s6, 0xffff1140; GFX6-NEXT: s_lshl_b32 s4, s4, 161141; GFX6-NEXT: s_or_b32 s3, s3, s41142; GFX6-NEXT: ; return to shader part epilog1143;1144; GFX8-LABEL: s_shl_v8i16:1145; GFX8: ; %bb.0:1146; GFX8-NEXT: s_lshr_b32 s8, s0, 161147; GFX8-NEXT: s_lshr_b32 s12, s4, 161148; GFX8-NEXT: s_lshl_b32 s0, s0, s41149; GFX8-NEXT: s_lshl_b32 s4, s8, s121150; GFX8-NEXT: s_lshr_b32 s9, s1, 161151; GFX8-NEXT: s_lshr_b32 s13, s5, 161152; GFX8-NEXT: s_and_b32 s4, 0xffff, s41153; GFX8-NEXT: s_lshl_b32 s1, s1, s51154; GFX8-NEXT: s_lshl_b32 s5, s9, s131155; GFX8-NEXT: s_and_b32 s0, 0xffff, s01156; GFX8-NEXT: s_lshl_b32 s4, s4, 161157; GFX8-NEXT: s_lshr_b32 s10, s2, 161158; GFX8-NEXT: s_lshr_b32 s14, s6, 161159; GFX8-NEXT: s_or_b32 s0, s0, s41160; GFX8-NEXT: s_and_b32 s4, 0xffff, s51161; GFX8-NEXT: s_lshl_b32 s2, s2, s61162; GFX8-NEXT: s_lshl_b32 s6, s10, s141163; GFX8-NEXT: s_and_b32 s1, 0xffff, s11164; GFX8-NEXT: s_lshl_b32 s4, s4, 161165; GFX8-NEXT: s_lshr_b32 s11, s3, 161166; GFX8-NEXT: s_lshr_b32 s15, s7, 161167; GFX8-NEXT: s_or_b32 s1, s1, s41168; GFX8-NEXT: s_and_b32 s4, 0xffff, s61169; GFX8-NEXT: s_lshl_b32 s3, s3, s71170; GFX8-NEXT: s_lshl_b32 s7, s11, s151171; GFX8-NEXT: s_and_b32 s2, 0xffff, s21172; GFX8-NEXT: s_lshl_b32 s4, s4, 161173; GFX8-NEXT: s_or_b32 s2, s2, s41174; GFX8-NEXT: s_and_b32 s4, 0xffff, s71175; GFX8-NEXT: s_and_b32 s3, 0xffff, s31176; GFX8-NEXT: s_lshl_b32 s4, s4, 161177; GFX8-NEXT: s_or_b32 s3, s3, s41178; GFX8-NEXT: ; return to shader part epilog1179;1180; GFX9-LABEL: s_shl_v8i16:1181; GFX9: ; %bb.0:1182; GFX9-NEXT: s_lshr_b32 s8, s0, 161183; GFX9-NEXT: s_lshr_b32 s9, s4, 161184; GFX9-NEXT: s_lshl_b32 s0, s0, s41185; GFX9-NEXT: s_lshl_b32 s4, s8, s91186; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s41187; GFX9-NEXT: s_lshr_b32 s4, s1, 161188; GFX9-NEXT: s_lshr_b32 s8, s5, 161189; GFX9-NEXT: s_lshl_b32 s1, s1, s51190; GFX9-NEXT: s_lshl_b32 s4, s4, s81191; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s41192; GFX9-NEXT: s_lshr_b32 s4, s2, 161193; GFX9-NEXT: s_lshr_b32 s5, s6, 161194; GFX9-NEXT: s_lshl_b32 s2, s2, s61195; GFX9-NEXT: s_lshl_b32 s4, s4, s51196; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s41197; GFX9-NEXT: s_lshr_b32 s4, s3, 161198; GFX9-NEXT: s_lshr_b32 s5, s7, 161199; GFX9-NEXT: s_lshl_b32 s3, s3, s71200; GFX9-NEXT: s_lshl_b32 s4, s4, s51201; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s41202; GFX9-NEXT: ; return to shader part epilog1203;1204; GFX10PLUS-LABEL: s_shl_v8i16:1205; GFX10PLUS: ; %bb.0:1206; GFX10PLUS-NEXT: s_lshr_b32 s8, s0, 161207; GFX10PLUS-NEXT: s_lshr_b32 s9, s4, 161208; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, s41209; GFX10PLUS-NEXT: s_lshl_b32 s4, s8, s91210; GFX10PLUS-NEXT: s_lshr_b32 s8, s1, 161211; GFX10PLUS-NEXT: s_lshr_b32 s9, s5, 161212; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, s51213; GFX10PLUS-NEXT: s_lshl_b32 s5, s8, s91214; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s0, s0, s41215; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s1, s1, s51216; GFX10PLUS-NEXT: s_lshr_b32 s4, s2, 161217; GFX10PLUS-NEXT: s_lshr_b32 s5, s6, 161218; GFX10PLUS-NEXT: s_lshl_b32 s2, s2, s61219; GFX10PLUS-NEXT: s_lshl_b32 s4, s4, s51220; GFX10PLUS-NEXT: s_lshr_b32 s5, s3, 161221; GFX10PLUS-NEXT: s_lshr_b32 s6, s7, 161222; GFX10PLUS-NEXT: s_lshl_b32 s3, s3, s71223; GFX10PLUS-NEXT: s_lshl_b32 s5, s5, s61224; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s2, s2, s41225; GFX10PLUS-NEXT: s_pack_ll_b32_b16 s3, s3, s51226; GFX10PLUS-NEXT: ; return to shader part epilog1227 %result = shl <8 x i16> %value, %amount1228 %cast = bitcast <8 x i16> %result to <4 x i32>1229 ret <4 x i32> %cast1230}1231 1232define i64 @v_shl_i64(i64 %value, i64 %amount) {1233; GFX6-LABEL: v_shl_i64:1234; GFX6: ; %bb.0:1235; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1236; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v21237; GFX6-NEXT: s_setpc_b64 s[30:31]1238;1239; GFX8-LABEL: v_shl_i64:1240; GFX8: ; %bb.0:1241; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1242; GFX8-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1243; GFX8-NEXT: s_setpc_b64 s[30:31]1244;1245; GFX9-LABEL: v_shl_i64:1246; GFX9: ; %bb.0:1247; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1248; GFX9-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1249; GFX9-NEXT: s_setpc_b64 s[30:31]1250;1251; GFX10PLUS-LABEL: v_shl_i64:1252; GFX10PLUS: ; %bb.0:1253; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1254; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], v2, v[0:1]1255; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1256 %result = shl i64 %value, %amount1257 ret i64 %result1258}1259 1260define i64 @v_shl_i64_63(i64 %value) {1261; GCN-LABEL: v_shl_i64_63:1262; GCN: ; %bb.0:1263; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1264; GCN-NEXT: v_lshlrev_b32_e32 v1, 31, v01265; GCN-NEXT: v_mov_b32_e32 v0, 01266; GCN-NEXT: s_setpc_b64 s[30:31]1267;1268; GFX10-LABEL: v_shl_i64_63:1269; GFX10: ; %bb.0:1270; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1271; GFX10-NEXT: v_lshlrev_b32_e32 v1, 31, v01272; GFX10-NEXT: v_mov_b32_e32 v0, 01273; GFX10-NEXT: s_setpc_b64 s[30:31]1274;1275; GFX11-LABEL: v_shl_i64_63:1276; GFX11: ; %bb.0:1277; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1278; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v1, 31, v01279; GFX11-NEXT: s_setpc_b64 s[30:31]1280 %result = shl i64 %value, 631281 ret i64 %result1282}1283 1284define i64 @v_shl_i64_33(i64 %value) {1285; GCN-LABEL: v_shl_i64_33:1286; GCN: ; %bb.0:1287; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1288; GCN-NEXT: v_lshlrev_b32_e32 v1, 1, v01289; GCN-NEXT: v_mov_b32_e32 v0, 01290; GCN-NEXT: s_setpc_b64 s[30:31]1291;1292; GFX10-LABEL: v_shl_i64_33:1293; GFX10: ; %bb.0:1294; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1295; GFX10-NEXT: v_lshlrev_b32_e32 v1, 1, v01296; GFX10-NEXT: v_mov_b32_e32 v0, 01297; GFX10-NEXT: s_setpc_b64 s[30:31]1298;1299; GFX11-LABEL: v_shl_i64_33:1300; GFX11: ; %bb.0:1301; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1302; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_lshlrev_b32 v1, 1, v01303; GFX11-NEXT: s_setpc_b64 s[30:31]1304 %result = shl i64 %value, 331305 ret i64 %result1306}1307 1308define i64 @v_shl_i64_32(i64 %value) {1309; GCN-LABEL: v_shl_i64_32:1310; GCN: ; %bb.0:1311; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1312; GCN-NEXT: v_mov_b32_e32 v1, v01313; GCN-NEXT: v_mov_b32_e32 v0, 01314; GCN-NEXT: s_setpc_b64 s[30:31]1315;1316; GFX10-LABEL: v_shl_i64_32:1317; GFX10: ; %bb.0:1318; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1319; GFX10-NEXT: v_mov_b32_e32 v1, v01320; GFX10-NEXT: v_mov_b32_e32 v0, 01321; GFX10-NEXT: s_setpc_b64 s[30:31]1322;1323; GFX11-LABEL: v_shl_i64_32:1324; GFX11: ; %bb.0:1325; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1326; GFX11-NEXT: v_dual_mov_b32 v1, v0 :: v_dual_mov_b32 v0, 01327; GFX11-NEXT: s_setpc_b64 s[30:31]1328 %result = shl i64 %value, 321329 ret i64 %result1330}1331 1332define i64 @v_shl_i64_31(i64 %value) {1333; GFX6-LABEL: v_shl_i64_31:1334; GFX6: ; %bb.0:1335; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1336; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 311337; GFX6-NEXT: s_setpc_b64 s[30:31]1338;1339; GFX8-LABEL: v_shl_i64_31:1340; GFX8: ; %bb.0:1341; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1342; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1343; GFX8-NEXT: s_setpc_b64 s[30:31]1344;1345; GFX9-LABEL: v_shl_i64_31:1346; GFX9: ; %bb.0:1347; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1348; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1349; GFX9-NEXT: s_setpc_b64 s[30:31]1350;1351; GFX10PLUS-LABEL: v_shl_i64_31:1352; GFX10PLUS: ; %bb.0:1353; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1354; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1355; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1356 %result = shl i64 %value, 311357 ret i64 %result1358}1359 1360define amdgpu_ps i64 @s_shl_i64(i64 inreg %value, i64 inreg %amount) {1361; GCN-LABEL: s_shl_i64:1362; GCN: ; %bb.0:1363; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s21364; GCN-NEXT: ; return to shader part epilog1365;1366; GFX10PLUS-LABEL: s_shl_i64:1367; GFX10PLUS: ; %bb.0:1368; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], s21369; GFX10PLUS-NEXT: ; return to shader part epilog1370 %result = shl i64 %value, %amount1371 ret i64 %result1372}1373 1374define amdgpu_ps i64 @s_shl_i64_63(i64 inreg %value) {1375; GCN-LABEL: s_shl_i64_63:1376; GCN: ; %bb.0:1377; GCN-NEXT: s_lshl_b32 s1, s0, 311378; GCN-NEXT: s_mov_b32 s0, 01379; GCN-NEXT: ; return to shader part epilog1380;1381; GFX10PLUS-LABEL: s_shl_i64_63:1382; GFX10PLUS: ; %bb.0:1383; GFX10PLUS-NEXT: s_lshl_b32 s1, s0, 311384; GFX10PLUS-NEXT: s_mov_b32 s0, 01385; GFX10PLUS-NEXT: ; return to shader part epilog1386 %result = shl i64 %value, 631387 ret i64 %result1388}1389 1390define amdgpu_ps i64 @s_shl_i64_33(i64 inreg %value) {1391; GCN-LABEL: s_shl_i64_33:1392; GCN: ; %bb.0:1393; GCN-NEXT: s_lshl_b32 s1, s0, 11394; GCN-NEXT: s_mov_b32 s0, 01395; GCN-NEXT: ; return to shader part epilog1396;1397; GFX10PLUS-LABEL: s_shl_i64_33:1398; GFX10PLUS: ; %bb.0:1399; GFX10PLUS-NEXT: s_lshl_b32 s1, s0, 11400; GFX10PLUS-NEXT: s_mov_b32 s0, 01401; GFX10PLUS-NEXT: ; return to shader part epilog1402 %result = shl i64 %value, 331403 ret i64 %result1404}1405 1406define amdgpu_ps i64 @s_shl_i64_32(i64 inreg %value) {1407; GCN-LABEL: s_shl_i64_32:1408; GCN: ; %bb.0:1409; GCN-NEXT: s_mov_b32 s1, s01410; GCN-NEXT: s_mov_b32 s0, 01411; GCN-NEXT: ; return to shader part epilog1412;1413; GFX10PLUS-LABEL: s_shl_i64_32:1414; GFX10PLUS: ; %bb.0:1415; GFX10PLUS-NEXT: s_mov_b32 s1, s01416; GFX10PLUS-NEXT: s_mov_b32 s0, 01417; GFX10PLUS-NEXT: ; return to shader part epilog1418 %result = shl i64 %value, 321419 ret i64 %result1420}1421 1422define amdgpu_ps i64 @s_shl_i64_31(i64 inreg %value) {1423; GCN-LABEL: s_shl_i64_31:1424; GCN: ; %bb.0:1425; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], 311426; GCN-NEXT: ; return to shader part epilog1427;1428; GFX10PLUS-LABEL: s_shl_i64_31:1429; GFX10PLUS: ; %bb.0:1430; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 311431; GFX10PLUS-NEXT: ; return to shader part epilog1432 %result = shl i64 %value, 311433 ret i64 %result1434}1435 1436define amdgpu_ps <2 x float> @shl_i64_sv(i64 inreg %value, i64 %amount) {1437; GFX6-LABEL: shl_i64_sv:1438; GFX6: ; %bb.0:1439; GFX6-NEXT: v_lshl_b64 v[0:1], s[0:1], v01440; GFX6-NEXT: ; return to shader part epilog1441;1442; GFX8-LABEL: shl_i64_sv:1443; GFX8: ; %bb.0:1444; GFX8-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]1445; GFX8-NEXT: ; return to shader part epilog1446;1447; GFX9-LABEL: shl_i64_sv:1448; GFX9: ; %bb.0:1449; GFX9-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]1450; GFX9-NEXT: ; return to shader part epilog1451;1452; GFX10PLUS-LABEL: shl_i64_sv:1453; GFX10PLUS: ; %bb.0:1454; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], v0, s[0:1]1455; GFX10PLUS-NEXT: ; return to shader part epilog1456 %result = shl i64 %value, %amount1457 %cast = bitcast i64 %result to <2 x float>1458 ret <2 x float> %cast1459}1460 1461define amdgpu_ps <2 x float> @shl_i64_vs(i64 %value, i64 inreg %amount) {1462; GFX6-LABEL: shl_i64_vs:1463; GFX6: ; %bb.0:1464; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], s01465; GFX6-NEXT: ; return to shader part epilog1466;1467; GFX8-LABEL: shl_i64_vs:1468; GFX8: ; %bb.0:1469; GFX8-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1]1470; GFX8-NEXT: ; return to shader part epilog1471;1472; GFX9-LABEL: shl_i64_vs:1473; GFX9: ; %bb.0:1474; GFX9-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1]1475; GFX9-NEXT: ; return to shader part epilog1476;1477; GFX10PLUS-LABEL: shl_i64_vs:1478; GFX10PLUS: ; %bb.0:1479; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], s0, v[0:1]1480; GFX10PLUS-NEXT: ; return to shader part epilog1481 %result = shl i64 %value, %amount1482 %cast = bitcast i64 %result to <2 x float>1483 ret <2 x float> %cast1484}1485 1486define <2 x i64> @v_shl_v2i64(<2 x i64> %value, <2 x i64> %amount) {1487; GFX6-LABEL: v_shl_v2i64:1488; GFX6: ; %bb.0:1489; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1490; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], v41491; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], v61492; GFX6-NEXT: s_setpc_b64 s[30:31]1493;1494; GFX8-LABEL: v_shl_v2i64:1495; GFX8: ; %bb.0:1496; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1497; GFX8-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]1498; GFX8-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]1499; GFX8-NEXT: s_setpc_b64 s[30:31]1500;1501; GFX9-LABEL: v_shl_v2i64:1502; GFX9: ; %bb.0:1503; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1504; GFX9-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]1505; GFX9-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]1506; GFX9-NEXT: s_setpc_b64 s[30:31]1507;1508; GFX10PLUS-LABEL: v_shl_v2i64:1509; GFX10PLUS: ; %bb.0:1510; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1511; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], v4, v[0:1]1512; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], v6, v[2:3]1513; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1514 %result = shl <2 x i64> %value, %amount1515 ret <2 x i64> %result1516}1517 1518define <2 x i64> @v_shl_v2i64_31(<2 x i64> %value) {1519; GFX6-LABEL: v_shl_v2i64_31:1520; GFX6: ; %bb.0:1521; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1522; GFX6-NEXT: v_lshl_b64 v[0:1], v[0:1], 311523; GFX6-NEXT: v_lshl_b64 v[2:3], v[2:3], 311524; GFX6-NEXT: s_setpc_b64 s[30:31]1525;1526; GFX8-LABEL: v_shl_v2i64_31:1527; GFX8: ; %bb.0:1528; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1529; GFX8-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1530; GFX8-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3]1531; GFX8-NEXT: s_setpc_b64 s[30:31]1532;1533; GFX9-LABEL: v_shl_v2i64_31:1534; GFX9: ; %bb.0:1535; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1536; GFX9-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1537; GFX9-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3]1538; GFX9-NEXT: s_setpc_b64 s[30:31]1539;1540; GFX10PLUS-LABEL: v_shl_v2i64_31:1541; GFX10PLUS: ; %bb.0:1542; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1543; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 31, v[0:1]1544; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 31, v[2:3]1545; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1546 %result = shl <2 x i64> %value, <i64 31, i64 31>1547 ret <2 x i64> %result1548}1549 1550define amdgpu_ps <2 x i64> @s_shl_v2i64(<2 x i64> inreg %value, <2 x i64> inreg %amount) {1551; GCN-LABEL: s_shl_v2i64:1552; GCN: ; %bb.0:1553; GCN-NEXT: s_lshl_b64 s[0:1], s[0:1], s41554; GCN-NEXT: s_lshl_b64 s[2:3], s[2:3], s61555; GCN-NEXT: ; return to shader part epilog1556;1557; GFX10PLUS-LABEL: s_shl_v2i64:1558; GFX10PLUS: ; %bb.0:1559; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], s41560; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], s61561; GFX10PLUS-NEXT: ; return to shader part epilog1562 %result = shl <2 x i64> %value, %amount1563 ret <2 x i64> %result1564}1565 1566define i65 @v_shl_i65(i65 %value, i65 %amount) {1567; GFX6-LABEL: v_shl_i65:1568; GFX6: ; %bb.0:1569; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1570; GFX6-NEXT: v_sub_i32_e32 v4, vcc, 64, v31571; GFX6-NEXT: v_lshr_b64 v[4:5], v[0:1], v41572; GFX6-NEXT: v_lshl_b64 v[5:6], v[2:3], v31573; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0xffffffc0, v31574; GFX6-NEXT: v_lshl_b64 v[6:7], v[0:1], v31575; GFX6-NEXT: v_or_b32_e32 v9, v4, v51576; GFX6-NEXT: v_lshl_b64 v[4:5], v[0:1], v81577; GFX6-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31578; GFX6-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc1579; GFX6-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc1580; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc1581; GFX6-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31582; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc1583; GFX6-NEXT: s_setpc_b64 s[30:31]1584;1585; GFX8-LABEL: v_shl_i65:1586; GFX8: ; %bb.0:1587; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1588; GFX8-NEXT: v_sub_u32_e32 v4, vcc, 64, v31589; GFX8-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]1590; GFX8-NEXT: v_lshlrev_b64 v[5:6], v3, v[2:3]1591; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0xffffffc0, v31592; GFX8-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]1593; GFX8-NEXT: v_or_b32_e32 v9, v4, v51594; GFX8-NEXT: v_lshlrev_b64 v[4:5], v8, v[0:1]1595; GFX8-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31596; GFX8-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc1597; GFX8-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc1598; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc1599; GFX8-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31600; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc1601; GFX8-NEXT: s_setpc_b64 s[30:31]1602;1603; GFX9-LABEL: v_shl_i65:1604; GFX9: ; %bb.0:1605; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1606; GFX9-NEXT: v_sub_u32_e32 v4, 64, v31607; GFX9-NEXT: v_lshrrev_b64 v[4:5], v4, v[0:1]1608; GFX9-NEXT: v_lshlrev_b64 v[5:6], v3, v[2:3]1609; GFX9-NEXT: v_add_u32_e32 v8, 0xffffffc0, v31610; GFX9-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]1611; GFX9-NEXT: v_or_b32_e32 v9, v4, v51612; GFX9-NEXT: v_lshlrev_b64 v[4:5], v8, v[0:1]1613; GFX9-NEXT: v_cmp_gt_u32_e32 vcc, 64, v31614; GFX9-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc1615; GFX9-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc1616; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v9, vcc1617; GFX9-NEXT: v_cmp_eq_u32_e32 vcc, 0, v31618; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc1619; GFX9-NEXT: s_setpc_b64 s[30:31]1620;1621; GFX10-LABEL: v_shl_i65:1622; GFX10: ; %bb.0:1623; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1624; GFX10-NEXT: v_sub_nc_u32_e32 v6, 64, v31625; GFX10-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]1626; GFX10-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v31627; GFX10-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31628; GFX10-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]1629; GFX10-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]1630; GFX10-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]1631; GFX10-NEXT: v_or_b32_e32 v1, v5, v41632; GFX10-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo1633; GFX10-NEXT: v_cndmask_b32_e32 v4, v8, v1, vcc_lo1634; GFX10-NEXT: v_cndmask_b32_e32 v1, 0, v7, vcc_lo1635; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31636; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo1637; GFX10-NEXT: s_setpc_b64 s[30:31]1638;1639; GFX11-LABEL: v_shl_i65:1640; GFX11: ; %bb.0:1641; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1642; GFX11-NEXT: v_sub_nc_u32_e32 v6, 64, v31643; GFX11-NEXT: v_lshlrev_b64 v[4:5], v3, v[2:3]1644; GFX11-NEXT: v_add_nc_u32_e32 v8, 0xffffffc0, v31645; GFX11-NEXT: v_cmp_gt_u32_e32 vcc_lo, 64, v31646; GFX11-NEXT: v_lshrrev_b64 v[5:6], v6, v[0:1]1647; GFX11-NEXT: v_lshlrev_b64 v[6:7], v3, v[0:1]1648; GFX11-NEXT: v_lshlrev_b64 v[8:9], v8, v[0:1]1649; GFX11-NEXT: v_or_b32_e32 v1, v5, v41650; GFX11-NEXT: v_cndmask_b32_e32 v0, 0, v6, vcc_lo1651; GFX11-NEXT: v_dual_cndmask_b32 v4, v8, v1 :: v_dual_cndmask_b32 v1, 0, v71652; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v31653; GFX11-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc_lo1654; GFX11-NEXT: s_setpc_b64 s[30:31]1655 %result = shl i65 %value, %amount1656 ret i65 %result1657}1658 1659define i65 @v_shl_i65_33(i65 %value) {1660; GFX6-LABEL: v_shl_i65_33:1661; GFX6: ; %bb.0:1662; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1663; GFX6-NEXT: v_lshlrev_b32_e32 v4, 1, v01664; GFX6-NEXT: v_lshr_b64 v[2:3], v[0:1], 311665; GFX6-NEXT: v_mov_b32_e32 v0, 01666; GFX6-NEXT: v_mov_b32_e32 v1, v41667; GFX6-NEXT: s_setpc_b64 s[30:31]1668;1669; GFX8-LABEL: v_shl_i65_33:1670; GFX8: ; %bb.0:1671; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1672; GFX8-NEXT: v_lshlrev_b32_e32 v4, 1, v01673; GFX8-NEXT: v_lshrrev_b64 v[2:3], 31, v[0:1]1674; GFX8-NEXT: v_mov_b32_e32 v0, 01675; GFX8-NEXT: v_mov_b32_e32 v1, v41676; GFX8-NEXT: s_setpc_b64 s[30:31]1677;1678; GFX9-LABEL: v_shl_i65_33:1679; GFX9: ; %bb.0:1680; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1681; GFX9-NEXT: v_lshlrev_b32_e32 v4, 1, v01682; GFX9-NEXT: v_lshrrev_b64 v[2:3], 31, v[0:1]1683; GFX9-NEXT: v_mov_b32_e32 v0, 01684; GFX9-NEXT: v_mov_b32_e32 v1, v41685; GFX9-NEXT: s_setpc_b64 s[30:31]1686;1687; GFX10-LABEL: v_shl_i65_33:1688; GFX10: ; %bb.0:1689; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1690; GFX10-NEXT: v_lshlrev_b32_e32 v4, 1, v01691; GFX10-NEXT: v_lshrrev_b64 v[2:3], 31, v[0:1]1692; GFX10-NEXT: v_mov_b32_e32 v0, 01693; GFX10-NEXT: v_mov_b32_e32 v1, v41694; GFX10-NEXT: s_setpc_b64 s[30:31]1695;1696; GFX11-LABEL: v_shl_i65_33:1697; GFX11: ; %bb.0:1698; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1699; GFX11-NEXT: v_lshlrev_b32_e32 v4, 1, v01700; GFX11-NEXT: v_lshrrev_b64 v[2:3], 31, v[0:1]1701; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, v41702; GFX11-NEXT: s_setpc_b64 s[30:31]1703 %result = shl i65 %value, 331704 ret i65 %result1705}1706 1707define amdgpu_ps i65 @s_shl_i65(i65 inreg %value, i65 inreg %amount) {1708; GCN-LABEL: s_shl_i65:1709; GCN: ; %bb.0:1710; GCN-NEXT: s_sub_i32 s10, s3, 641711; GCN-NEXT: s_sub_i32 s6, 64, s31712; GCN-NEXT: s_cmp_lt_u32 s3, 641713; GCN-NEXT: s_cselect_b32 s11, 1, 01714; GCN-NEXT: s_cmp_eq_u32 s3, 01715; GCN-NEXT: s_cselect_b32 s12, 1, 01716; GCN-NEXT: s_lshr_b64 s[6:7], s[0:1], s61717; GCN-NEXT: s_lshl_b64 s[8:9], s[2:3], s31718; GCN-NEXT: s_lshl_b64 s[4:5], s[0:1], s31719; GCN-NEXT: s_or_b64 s[6:7], s[6:7], s[8:9]1720; GCN-NEXT: s_lshl_b64 s[8:9], s[0:1], s101721; GCN-NEXT: s_cmp_lg_u32 s11, 01722; GCN-NEXT: s_cselect_b64 s[0:1], s[4:5], 01723; GCN-NEXT: s_cselect_b32 s3, s6, s81724; GCN-NEXT: s_cmp_lg_u32 s12, 01725; GCN-NEXT: s_cselect_b32 s2, s2, s31726; GCN-NEXT: ; return to shader part epilog1727;1728; GFX10PLUS-LABEL: s_shl_i65:1729; GFX10PLUS: ; %bb.0:1730; GFX10PLUS-NEXT: s_sub_i32 s10, s3, 641731; GFX10PLUS-NEXT: s_sub_i32 s4, 64, s31732; GFX10PLUS-NEXT: s_cmp_lt_u32 s3, 641733; GFX10PLUS-NEXT: s_cselect_b32 s11, 1, 01734; GFX10PLUS-NEXT: s_cmp_eq_u32 s3, 01735; GFX10PLUS-NEXT: s_cselect_b32 s12, 1, 01736; GFX10PLUS-NEXT: s_lshr_b64 s[4:5], s[0:1], s41737; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[2:3], s31738; GFX10PLUS-NEXT: s_lshl_b64 s[8:9], s[0:1], s31739; GFX10PLUS-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]1740; GFX10PLUS-NEXT: s_lshl_b64 s[6:7], s[0:1], s101741; GFX10PLUS-NEXT: s_cmp_lg_u32 s11, 01742; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[8:9], 01743; GFX10PLUS-NEXT: s_cselect_b32 s3, s4, s61744; GFX10PLUS-NEXT: s_cmp_lg_u32 s12, 01745; GFX10PLUS-NEXT: s_cselect_b32 s2, s2, s31746; GFX10PLUS-NEXT: ; return to shader part epilog1747 %result = shl i65 %value, %amount1748 ret i65 %result1749}1750 1751define amdgpu_ps i65 @s_shl_i65_33(i65 inreg %value) {1752; GCN-LABEL: s_shl_i65_33:1753; GCN: ; %bb.0:1754; GCN-NEXT: s_lshl_b32 s4, s0, 11755; GCN-NEXT: s_mov_b32 s6, 01756; GCN-NEXT: s_lshl_b32 s7, s2, 11757; GCN-NEXT: s_lshr_b64 s[0:1], s[0:1], 311758; GCN-NEXT: s_or_b64 s[2:3], s[6:7], s[0:1]1759; GCN-NEXT: s_mov_b32 s0, 01760; GCN-NEXT: s_mov_b32 s1, s41761; GCN-NEXT: ; return to shader part epilog1762;1763; GFX10PLUS-LABEL: s_shl_i65_33:1764; GFX10PLUS: ; %bb.0:1765; GFX10PLUS-NEXT: s_mov_b32 s4, 01766; GFX10PLUS-NEXT: s_lshl_b32 s5, s2, 11767; GFX10PLUS-NEXT: s_lshr_b64 s[2:3], s[0:1], 311768; GFX10PLUS-NEXT: s_lshl_b32 s1, s0, 11769; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[4:5], s[2:3]1770; GFX10PLUS-NEXT: s_mov_b32 s0, 01771; GFX10PLUS-NEXT: ; return to shader part epilog1772 %result = shl i65 %value, 331773 ret i65 %result1774}1775 1776; FIXME: Argument lowering asserts1777; define <2 x i65> @v_shl_v2i65(<2 x i65> %value, <2 x i65> %amount) {1778; %result = shl <2 x i65> %value, %amount1779; ret <2 x i65> %result1780; }1781 1782; define amdgpu_ps <2 x i65> @s_shl_v2i65(<2 x i65> inreg %value, <2 x i65> inreg %amount) {1783; %result = shl <2 x i65> %value, %amount1784; ret <2 x i65> %result1785; }1786