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1; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding -global-isel -new-reg-bank-select | FileCheck --check-prefixes=SI,GCN %s2; RUN: llc < %s -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding -global-isel -new-reg-bank-select | FileCheck --check-prefixes=CI,GCN,SICIVI %s3; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -show-mc-encoding -global-isel -new-reg-bank-select | FileCheck --check-prefixes=VI,GCN,SICIVI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding -global-isel -new-reg-bank-select < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding -global-isel -new-reg-bank-select < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s6 7; SMRD load with an immediate offset.8; GCN-LABEL: {{^}}smrd0:9; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x0110; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x411define amdgpu_kernel void @smrd0(ptr addrspace(4) %ptr) {12entry:13 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 114 %1 = load i32, ptr addrspace(4) %015 store i32 %1, ptr addrspace(1) poison16 ret void17}18 19; SMRD load with the largest possible immediate offset.20; GCN-LABEL: {{^}}smrd1:21; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}22; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc23define amdgpu_kernel void @smrd1(ptr addrspace(4) %ptr) {24entry:25 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 25526 %1 = load i32, ptr addrspace(4) %027 store i32 %1, ptr addrspace(1) poison28 ret void29}30 31; SMRD load with an offset greater than the largest possible immediate.32; GCN-LABEL: {{^}}smrd2:33; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x40034; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]35; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x10036; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40037; GCN: s_endpgm38define amdgpu_kernel void @smrd2(ptr addrspace(4) %ptr) {39entry:40 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 25641 %1 = load i32, ptr addrspace(4) %042 store i32 %1, ptr addrspace(1) poison43 ret void44}45 46; SMRD load with a 64-bit offset47; GCN-LABEL: {{^}}smrd3:48; FIXME: There are too many copies here because we don't fold immediates49; through REG_SEQUENCE50; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b51; TODO: Add VI checks52; XGCN: s_endpgm53define amdgpu_kernel void @smrd3(ptr addrspace(4) %ptr) {54entry:55 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 4294967296 ; 2 ^ 3256 %1 = load i32, ptr addrspace(4) %057 store i32 %1, ptr addrspace(1) poison58 ret void59}60 61; SMRD load with the largest possible immediate offset on VI62; GCN-LABEL: {{^}}smrd4:63; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc64; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]65; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff66; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc67; GFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc68; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]69define amdgpu_kernel void @smrd4(ptr addrspace(4) %ptr) {70entry:71 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 26214372 %1 = load i32, ptr addrspace(4) %073 store i32 %1, ptr addrspace(1) poison74 ret void75}76 77; SMRD load with an offset greater than the largest possible immediate on VI78; GCN-LABEL: {{^}}smrd5:79; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x10000080; SIVIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]81; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4000082; GCN: s_endpgm83define amdgpu_kernel void @smrd5(ptr addrspace(4) %ptr) {84entry:85 %0 = getelementptr i32, ptr addrspace(4) %ptr, i64 26214486 %1 = load i32, ptr addrspace(4) %087 store i32 %1, ptr addrspace(1) poison88 ret void89}90 91; GFX9+ can use a signed immediate byte offset but not without sgpr[offset]92; GCN-LABEL: {{^}}smrd6:93; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -494; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x095; GFX9_10: s_add_u32 s2, s2, -496; GFX9_10: s_addc_u32 s3, s3, -197; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x098define amdgpu_kernel void @smrd6(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {99entry:100 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -1101 %tmp1 = load i32, ptr addrspace(4) %tmp102 store i32 %tmp1, ptr addrspace(1) %out103 ret void104}105 106; Don't use a negative SGPR offset107; GCN-LABEL: {{^}}smrd7:108; GCN: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, 0xffe00000109; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0110; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0111define amdgpu_kernel void @smrd7(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {112entry:113 %tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -524288114 %tmp1 = load i32, ptr addrspace(4) %tmp115 store i32 %tmp1, ptr addrspace(1) %out116 ret void117}118