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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s4 5; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.6 7define i32 @v_srem_i32(i32 %num, i32 %den) {8; GISEL-LABEL: v_srem_i32:9; GISEL: ; %bb.0:10; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v012; GISEL-NEXT: v_ashrrev_i32_e32 v3, 31, v113; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v214; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v315; GISEL-NEXT: v_xor_b32_e32 v0, v0, v216; GISEL-NEXT: v_xor_b32_e32 v1, v1, v317; GISEL-NEXT: v_cvt_f32_u32_e32 v3, v118; GISEL-NEXT: v_sub_i32_e32 v4, vcc, 0, v119; GISEL-NEXT: v_rcp_iflag_f32_e32 v3, v320; GISEL-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v321; GISEL-NEXT: v_cvt_u32_f32_e32 v3, v322; GISEL-NEXT: v_mul_lo_u32 v4, v4, v323; GISEL-NEXT: v_mul_hi_u32 v4, v3, v424; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v425; GISEL-NEXT: v_mul_hi_u32 v3, v0, v326; GISEL-NEXT: v_mul_lo_u32 v3, v3, v127; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v328; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v0, v129; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v130; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc31; GISEL-NEXT: v_sub_i32_e32 v3, vcc, v0, v132; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v133; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc34; GISEL-NEXT: v_xor_b32_e32 v0, v0, v235; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v236; GISEL-NEXT: s_setpc_b64 s[30:31]37;38; CGP-LABEL: v_srem_i32:39; CGP: ; %bb.0:40; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; CGP-NEXT: v_ashrrev_i32_e32 v2, 31, v042; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v143; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v244; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v345; CGP-NEXT: v_xor_b32_e32 v0, v0, v246; CGP-NEXT: v_xor_b32_e32 v1, v1, v347; CGP-NEXT: v_cvt_f32_u32_e32 v3, v148; CGP-NEXT: v_sub_i32_e32 v4, vcc, 0, v149; CGP-NEXT: v_rcp_f32_e32 v3, v350; CGP-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v351; CGP-NEXT: v_cvt_u32_f32_e32 v3, v352; CGP-NEXT: v_mul_lo_u32 v4, v4, v353; CGP-NEXT: v_mul_hi_u32 v4, v3, v454; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v455; CGP-NEXT: v_mul_hi_u32 v3, v0, v356; CGP-NEXT: v_mul_lo_u32 v3, v3, v157; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v358; CGP-NEXT: v_sub_i32_e32 v3, vcc, v0, v159; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v160; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc61; CGP-NEXT: v_sub_i32_e32 v3, vcc, v0, v162; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v163; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc64; CGP-NEXT: v_xor_b32_e32 v0, v0, v265; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v266; CGP-NEXT: s_setpc_b64 s[30:31]67 %result = srem i32 %num, %den68 ret i32 %result69}70 71; FIXME: This is a workaround for not handling uniform VGPR case.72declare i32 @llvm.amdgcn.readfirstlane(i32)73 74define amdgpu_ps i32 @s_srem_i32(i32 inreg %num, i32 inreg %den) {75; GISEL-LABEL: s_srem_i32:76; GISEL: ; %bb.0:77; GISEL-NEXT: s_ashr_i32 s2, s0, 3178; GISEL-NEXT: s_ashr_i32 s3, s1, 3179; GISEL-NEXT: s_add_i32 s0, s0, s280; GISEL-NEXT: s_add_i32 s1, s1, s381; GISEL-NEXT: s_xor_b32 s0, s0, s282; GISEL-NEXT: s_xor_b32 s1, s1, s383; GISEL-NEXT: v_cvt_f32_u32_e32 v0, s184; GISEL-NEXT: s_sub_i32 s3, 0, s185; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v086; GISEL-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v087; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v088; GISEL-NEXT: v_mul_lo_u32 v1, s3, v089; GISEL-NEXT: v_mul_hi_u32 v1, v0, v190; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v191; GISEL-NEXT: v_mul_hi_u32 v0, s0, v092; GISEL-NEXT: v_mul_lo_u32 v0, v0, s193; GISEL-NEXT: v_sub_i32_e32 v0, vcc, s0, v094; GISEL-NEXT: v_subrev_i32_e32 v1, vcc, s1, v095; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v096; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc97; GISEL-NEXT: v_subrev_i32_e32 v1, vcc, s1, v098; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v099; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc100; GISEL-NEXT: v_xor_b32_e32 v0, s2, v0101; GISEL-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0102; GISEL-NEXT: v_readfirstlane_b32 s0, v0103; GISEL-NEXT: ; return to shader part epilog104;105; CGP-LABEL: s_srem_i32:106; CGP: ; %bb.0:107; CGP-NEXT: s_ashr_i32 s2, s0, 31108; CGP-NEXT: s_ashr_i32 s3, s1, 31109; CGP-NEXT: s_add_i32 s0, s0, s2110; CGP-NEXT: s_add_i32 s1, s1, s3111; CGP-NEXT: s_xor_b32 s0, s0, s2112; CGP-NEXT: s_xor_b32 s1, s1, s3113; CGP-NEXT: v_cvt_f32_u32_e32 v0, s1114; CGP-NEXT: s_sub_i32 s3, 0, s1115; CGP-NEXT: v_rcp_f32_e32 v0, v0116; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0117; CGP-NEXT: v_cvt_u32_f32_e32 v0, v0118; CGP-NEXT: v_mul_lo_u32 v1, s3, v0119; CGP-NEXT: v_mul_hi_u32 v1, v0, v1120; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v1121; CGP-NEXT: v_mul_hi_u32 v0, s0, v0122; CGP-NEXT: v_mul_lo_u32 v0, v0, s1123; CGP-NEXT: v_sub_i32_e32 v0, vcc, s0, v0124; CGP-NEXT: v_subrev_i32_e32 v1, vcc, s1, v0125; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v0126; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc127; CGP-NEXT: v_subrev_i32_e32 v1, vcc, s1, v0128; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v0129; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc130; CGP-NEXT: v_xor_b32_e32 v0, s2, v0131; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s2, v0132; CGP-NEXT: v_readfirstlane_b32 s0, v0133; CGP-NEXT: ; return to shader part epilog134 %result = srem i32 %num, %den135 %readlane = call i32 @llvm.amdgcn.readfirstlane(i32 %result)136 ret i32 %readlane137}138 139define <2 x i32> @v_srem_v2i32(<2 x i32> %num, <2 x i32> %den) {140; GISEL-LABEL: v_srem_v2i32:141; GISEL: ; %bb.0:142; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)143; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0144; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v2145; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1146; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3147; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4148; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v5149; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6150; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7151; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4152; GISEL-NEXT: v_xor_b32_e32 v2, v2, v5153; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6154; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7155; GISEL-NEXT: v_cvt_f32_u32_e32 v5, v2156; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v2157; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v3158; GISEL-NEXT: v_sub_i32_e32 v9, vcc, 0, v3159; GISEL-NEXT: v_rcp_iflag_f32_e32 v5, v5160; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8161; GISEL-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5162; GISEL-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8163; GISEL-NEXT: v_cvt_u32_f32_e32 v5, v5164; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8165; GISEL-NEXT: v_mul_lo_u32 v7, v7, v5166; GISEL-NEXT: v_mul_lo_u32 v9, v9, v8167; GISEL-NEXT: v_mul_hi_u32 v7, v5, v7168; GISEL-NEXT: v_mul_hi_u32 v9, v8, v9169; GISEL-NEXT: v_add_i32_e32 v5, vcc, v5, v7170; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v9171; GISEL-NEXT: v_mul_hi_u32 v5, v0, v5172; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7173; GISEL-NEXT: v_mul_lo_u32 v5, v5, v2174; GISEL-NEXT: v_mul_lo_u32 v7, v7, v3175; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v5176; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v7177; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v0, v2178; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v1, v3179; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2180; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc181; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3182; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc183; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v0, v2184; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v1, v3185; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2186; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc187; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3188; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc189; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4190; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6191; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4192; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6193; GISEL-NEXT: s_setpc_b64 s[30:31]194;195; CGP-LABEL: v_srem_v2i32:196; CGP: ; %bb.0:197; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)198; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0199; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v2200; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v1201; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3202; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4203; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5204; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v6205; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7206; CGP-NEXT: v_xor_b32_e32 v0, v0, v4207; CGP-NEXT: v_xor_b32_e32 v2, v2, v5208; CGP-NEXT: v_xor_b32_e32 v1, v1, v6209; CGP-NEXT: v_xor_b32_e32 v3, v3, v7210; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2211; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v2212; CGP-NEXT: v_cvt_f32_u32_e32 v8, v3213; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3214; CGP-NEXT: v_rcp_f32_e32 v5, v5215; CGP-NEXT: v_rcp_f32_e32 v8, v8216; CGP-NEXT: v_mul_f32_e32 v5, 0x4f7ffffe, v5217; CGP-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8218; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5219; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8220; CGP-NEXT: v_mul_lo_u32 v7, v7, v5221; CGP-NEXT: v_mul_lo_u32 v9, v9, v8222; CGP-NEXT: v_mul_hi_u32 v7, v5, v7223; CGP-NEXT: v_mul_hi_u32 v9, v8, v9224; CGP-NEXT: v_add_i32_e32 v5, vcc, v5, v7225; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v9226; CGP-NEXT: v_mul_hi_u32 v5, v0, v5227; CGP-NEXT: v_mul_hi_u32 v7, v1, v7228; CGP-NEXT: v_mul_lo_u32 v5, v5, v2229; CGP-NEXT: v_mul_lo_u32 v7, v7, v3230; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v5231; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7232; CGP-NEXT: v_sub_i32_e32 v5, vcc, v0, v2233; CGP-NEXT: v_sub_i32_e32 v7, vcc, v1, v3234; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2235; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc236; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3237; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc238; CGP-NEXT: v_sub_i32_e32 v5, vcc, v0, v2239; CGP-NEXT: v_sub_i32_e32 v7, vcc, v1, v3240; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2241; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc242; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3243; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc244; CGP-NEXT: v_xor_b32_e32 v0, v0, v4245; CGP-NEXT: v_xor_b32_e32 v1, v1, v6246; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4247; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v6248; CGP-NEXT: s_setpc_b64 s[30:31]249 %result = srem <2 x i32> %num, %den250 ret <2 x i32> %result251}252 253define i32 @v_srem_i32_pow2k_denom(i32 %num) {254; CHECK-LABEL: v_srem_i32_pow2k_denom:255; CHECK: ; %bb.0:256; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)257; CHECK-NEXT: v_mov_b32_e32 v1, 0x80000001258; CHECK-NEXT: v_mul_hi_i32 v1, v0, v1259; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v0260; CHECK-NEXT: v_ashrrev_i32_e32 v1, 11, v1261; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1262; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2263; CHECK-NEXT: v_lshlrev_b32_e32 v1, 12, v1264; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1265; CHECK-NEXT: s_setpc_b64 s[30:31]266 %result = srem i32 %num, 4096267 ret i32 %result268}269 270define <2 x i32> @v_srem_v2i32_pow2k_denom(<2 x i32> %num) {271; GISEL-LABEL: v_srem_v2i32_pow2k_denom:272; GISEL: ; %bb.0:273; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)274; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0275; GISEL-NEXT: v_mov_b32_e32 v3, 0x1000276; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x1000277; GISEL-NEXT: v_mov_b32_e32 v5, 0xfffff000278; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1279; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2280; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4281; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6282; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2283; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4284; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6285; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4286; GISEL-NEXT: v_mul_lo_u32 v7, v4, v5287; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7288; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7289; GISEL-NEXT: v_mul_hi_u32 v7, v0, v4290; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4291; GISEL-NEXT: v_lshlrev_b32_e32 v7, 12, v7292; GISEL-NEXT: v_lshlrev_b32_e32 v4, 12, v4293; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v7294; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v4295; GISEL-NEXT: v_add_i32_e32 v4, vcc, v0, v5296; GISEL-NEXT: v_add_i32_e32 v7, vcc, 0xfffff000, v1297; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3298; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc299; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3300; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc301; GISEL-NEXT: v_add_i32_e32 v4, vcc, v0, v5302; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0xfffff000, v1303; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3304; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc305; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3306; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc307; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2308; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6309; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2310; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6311; GISEL-NEXT: s_setpc_b64 s[30:31]312;313; CGP-LABEL: v_srem_v2i32_pow2k_denom:314; CGP: ; %bb.0:315; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)316; CGP-NEXT: v_mov_b32_e32 v2, 0x80000001317; CGP-NEXT: v_mul_hi_i32 v3, v0, v2318; CGP-NEXT: v_mul_hi_i32 v2, v1, v2319; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v0320; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v1321; CGP-NEXT: v_ashrrev_i32_e32 v3, 11, v3322; CGP-NEXT: v_ashrrev_i32_e32 v2, 11, v2323; CGP-NEXT: v_lshrrev_b32_e32 v4, 31, v3324; CGP-NEXT: v_lshrrev_b32_e32 v5, 31, v2325; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v4326; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v5327; CGP-NEXT: v_lshlrev_b32_e32 v3, 12, v3328; CGP-NEXT: v_lshlrev_b32_e32 v2, 12, v2329; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3330; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v2331; CGP-NEXT: s_setpc_b64 s[30:31]332 %result = srem <2 x i32> %num, <i32 4096, i32 4096>333 ret <2 x i32> %result334}335 336define i32 @v_srem_i32_oddk_denom(i32 %num) {337; CHECK-LABEL: v_srem_i32_oddk_denom:338; CHECK: ; %bb.0:339; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; CHECK-NEXT: v_mov_b32_e32 v1, 0xd9528441341; CHECK-NEXT: v_mul_hi_i32 v1, v0, v1342; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v0343; CHECK-NEXT: v_ashrrev_i32_e32 v1, 20, v1344; CHECK-NEXT: v_lshrrev_b32_e32 v2, 31, v1345; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2346; CHECK-NEXT: v_mov_b32_e32 v2, 0x12d8fb347; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2348; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1349; CHECK-NEXT: s_setpc_b64 s[30:31]350 %result = srem i32 %num, 1235195351 ret i32 %result352}353 354define <2 x i32> @v_srem_v2i32_oddk_denom(<2 x i32> %num) {355; GISEL-LABEL: v_srem_v2i32_oddk_denom:356; GISEL: ; %bb.0:357; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)358; GISEL-NEXT: v_ashrrev_i32_e32 v2, 31, v0359; GISEL-NEXT: v_mov_b32_e32 v3, 0x12d8fb360; GISEL-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb361; GISEL-NEXT: v_mov_b32_e32 v5, 0xffed2705362; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v1363; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v2364; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4365; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v6366; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2367; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4368; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6369; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4370; GISEL-NEXT: v_mul_lo_u32 v7, v4, v5371; GISEL-NEXT: v_mul_hi_u32 v7, v4, v7372; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v7373; GISEL-NEXT: v_mul_hi_u32 v7, v0, v4374; GISEL-NEXT: v_mul_hi_u32 v4, v1, v4375; GISEL-NEXT: v_mul_lo_u32 v7, v7, v3376; GISEL-NEXT: v_mul_lo_u32 v4, v4, v3377; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v7378; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v4379; GISEL-NEXT: v_add_i32_e32 v4, vcc, v0, v5380; GISEL-NEXT: v_add_i32_e32 v7, vcc, 0xffed2705, v1381; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3382; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc383; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3384; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc385; GISEL-NEXT: v_add_i32_e32 v4, vcc, v0, v5386; GISEL-NEXT: v_add_i32_e32 v5, vcc, 0xffed2705, v1387; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3388; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc389; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3390; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc391; GISEL-NEXT: v_xor_b32_e32 v0, v0, v2392; GISEL-NEXT: v_xor_b32_e32 v1, v1, v6393; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2394; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v6395; GISEL-NEXT: s_setpc_b64 s[30:31]396;397; CGP-LABEL: v_srem_v2i32_oddk_denom:398; CGP: ; %bb.0:399; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)400; CGP-NEXT: v_mov_b32_e32 v2, 0xd9528441401; CGP-NEXT: v_mov_b32_e32 v3, 0x12d8fb402; CGP-NEXT: v_mul_hi_i32 v4, v0, v2403; CGP-NEXT: v_mul_hi_i32 v2, v1, v2404; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v0405; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v1406; CGP-NEXT: v_ashrrev_i32_e32 v4, 20, v4407; CGP-NEXT: v_ashrrev_i32_e32 v2, 20, v2408; CGP-NEXT: v_lshrrev_b32_e32 v5, 31, v4409; CGP-NEXT: v_lshrrev_b32_e32 v6, 31, v2410; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5411; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6412; CGP-NEXT: v_mul_lo_u32 v4, v4, v3413; CGP-NEXT: v_mul_lo_u32 v2, v2, v3414; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4415; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v2416; CGP-NEXT: s_setpc_b64 s[30:31]417 %result = srem <2 x i32> %num, <i32 1235195, i32 1235195>418 ret <2 x i32> %result419}420 421define i32 @v_srem_i32_pow2_shl_denom(i32 %x, i32 %y) {422; CHECK-LABEL: v_srem_i32_pow2_shl_denom:423; CHECK: ; %bb.0:424; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)425; CHECK-NEXT: v_lshl_b32_e32 v1, 0x1000, v1426; CHECK-NEXT: v_ashrrev_i32_e32 v2, 31, v0427; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1428; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v2429; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v3430; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2431; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3432; CHECK-NEXT: v_cvt_f32_u32_e32 v3, v1433; CHECK-NEXT: v_sub_i32_e32 v4, vcc, 0, v1434; CHECK-NEXT: v_rcp_iflag_f32_e32 v3, v3435; CHECK-NEXT: v_mul_f32_e32 v3, 0x4f7ffffe, v3436; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3437; CHECK-NEXT: v_mul_lo_u32 v4, v4, v3438; CHECK-NEXT: v_mul_hi_u32 v4, v3, v4439; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4440; CHECK-NEXT: v_mul_hi_u32 v3, v0, v3441; CHECK-NEXT: v_mul_lo_u32 v3, v3, v1442; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3443; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v0, v1444; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1445; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc446; CHECK-NEXT: v_sub_i32_e32 v3, vcc, v0, v1447; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1448; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc449; CHECK-NEXT: v_xor_b32_e32 v0, v0, v2450; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2451; CHECK-NEXT: s_setpc_b64 s[30:31]452 %shl.y = shl i32 4096, %y453 %r = srem i32 %x, %shl.y454 ret i32 %r455}456 457define <2 x i32> @v_srem_v2i32_pow2_shl_denom(<2 x i32> %x, <2 x i32> %y) {458; GISEL-LABEL: v_srem_v2i32_pow2_shl_denom:459; GISEL: ; %bb.0:460; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)461; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2462; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3463; GISEL-NEXT: v_ashrrev_i32_e32 v4, 31, v0464; GISEL-NEXT: v_ashrrev_i32_e32 v5, 31, v1465; GISEL-NEXT: v_ashrrev_i32_e32 v6, 31, v2466; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v4467; GISEL-NEXT: v_ashrrev_i32_e32 v7, 31, v3468; GISEL-NEXT: v_add_i32_e32 v1, vcc, v1, v5469; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v6470; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4471; GISEL-NEXT: v_add_i32_e32 v3, vcc, v3, v7472; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5473; GISEL-NEXT: v_xor_b32_e32 v2, v2, v6474; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7475; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v2476; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v2477; GISEL-NEXT: v_cvt_f32_u32_e32 v8, v3478; GISEL-NEXT: v_sub_i32_e32 v9, vcc, 0, v3479; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6480; GISEL-NEXT: v_rcp_iflag_f32_e32 v8, v8481; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6482; GISEL-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8483; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6484; GISEL-NEXT: v_cvt_u32_f32_e32 v8, v8485; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6486; GISEL-NEXT: v_mul_lo_u32 v9, v9, v8487; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7488; GISEL-NEXT: v_mul_hi_u32 v9, v8, v9489; GISEL-NEXT: v_add_i32_e32 v6, vcc, v6, v7490; GISEL-NEXT: v_add_i32_e32 v7, vcc, v8, v9491; GISEL-NEXT: v_mul_hi_u32 v6, v0, v6492; GISEL-NEXT: v_mul_hi_u32 v7, v1, v7493; GISEL-NEXT: v_mul_lo_u32 v6, v6, v2494; GISEL-NEXT: v_mul_lo_u32 v7, v7, v3495; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6496; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v7497; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v0, v2498; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v1, v3499; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2500; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc501; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3502; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc503; GISEL-NEXT: v_sub_i32_e32 v6, vcc, v0, v2504; GISEL-NEXT: v_sub_i32_e32 v7, vcc, v1, v3505; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2506; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc507; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3508; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc509; GISEL-NEXT: v_xor_b32_e32 v0, v0, v4510; GISEL-NEXT: v_xor_b32_e32 v1, v1, v5511; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4512; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5513; GISEL-NEXT: s_setpc_b64 s[30:31]514;515; CGP-LABEL: v_srem_v2i32_pow2_shl_denom:516; CGP: ; %bb.0:517; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)518; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2519; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3520; CGP-NEXT: v_ashrrev_i32_e32 v4, 31, v0521; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1522; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v2523; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v4524; CGP-NEXT: v_ashrrev_i32_e32 v7, 31, v3525; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v5526; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6527; CGP-NEXT: v_xor_b32_e32 v0, v0, v4528; CGP-NEXT: v_add_i32_e32 v3, vcc, v3, v7529; CGP-NEXT: v_xor_b32_e32 v1, v1, v5530; CGP-NEXT: v_xor_b32_e32 v2, v2, v6531; CGP-NEXT: v_xor_b32_e32 v3, v3, v7532; CGP-NEXT: v_cvt_f32_u32_e32 v6, v2533; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v2534; CGP-NEXT: v_cvt_f32_u32_e32 v8, v3535; CGP-NEXT: v_sub_i32_e32 v9, vcc, 0, v3536; CGP-NEXT: v_rcp_f32_e32 v6, v6537; CGP-NEXT: v_rcp_f32_e32 v8, v8538; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6539; CGP-NEXT: v_mul_f32_e32 v8, 0x4f7ffffe, v8540; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6541; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8542; CGP-NEXT: v_mul_lo_u32 v7, v7, v6543; CGP-NEXT: v_mul_lo_u32 v9, v9, v8544; CGP-NEXT: v_mul_hi_u32 v7, v6, v7545; CGP-NEXT: v_mul_hi_u32 v9, v8, v9546; CGP-NEXT: v_add_i32_e32 v6, vcc, v6, v7547; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v9548; CGP-NEXT: v_mul_hi_u32 v6, v0, v6549; CGP-NEXT: v_mul_hi_u32 v7, v1, v7550; CGP-NEXT: v_mul_lo_u32 v6, v6, v2551; CGP-NEXT: v_mul_lo_u32 v7, v7, v3552; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6553; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v7554; CGP-NEXT: v_sub_i32_e32 v6, vcc, v0, v2555; CGP-NEXT: v_sub_i32_e32 v7, vcc, v1, v3556; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2557; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc558; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3559; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc560; CGP-NEXT: v_sub_i32_e32 v6, vcc, v0, v2561; CGP-NEXT: v_sub_i32_e32 v7, vcc, v1, v3562; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2563; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc564; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3565; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc566; CGP-NEXT: v_xor_b32_e32 v0, v0, v4567; CGP-NEXT: v_xor_b32_e32 v1, v1, v5568; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4569; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5570; CGP-NEXT: s_setpc_b64 s[30:31]571 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y572 %r = srem <2 x i32> %x, %shl.y573 ret <2 x i32> %r574}575 576define i32 @v_srem_i32_24bit(i32 %num, i32 %den) {577; GISEL-LABEL: v_srem_i32_24bit:578; GISEL: ; %bb.0:579; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0581; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1582; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1583; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1584; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2585; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2586; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2587; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2588; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3589; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3590; GISEL-NEXT: v_mul_hi_u32 v2, v0, v2591; GISEL-NEXT: v_mul_lo_u32 v2, v2, v1592; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2593; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1594; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1595; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc596; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1597; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1598; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc599; GISEL-NEXT: s_setpc_b64 s[30:31]600;601; CGP-LABEL: v_srem_i32_24bit:602; CGP: ; %bb.0:603; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)604; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0605; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1606; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1607; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1608; CGP-NEXT: v_rcp_f32_e32 v2, v2609; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2610; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2611; CGP-NEXT: v_mul_lo_u32 v3, v3, v2612; CGP-NEXT: v_mul_hi_u32 v3, v2, v3613; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3614; CGP-NEXT: v_mul_hi_u32 v2, v0, v2615; CGP-NEXT: v_mul_lo_u32 v2, v2, v1616; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2617; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1618; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1619; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc620; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1621; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1622; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc623; CGP-NEXT: s_setpc_b64 s[30:31]624 %num.mask = and i32 %num, 16777215625 %den.mask = and i32 %den, 16777215626 %result = srem i32 %num.mask, %den.mask627 ret i32 %result628}629 630define <2 x i32> @v_srem_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {631; GISEL-LABEL: v_srem_v2i32_24bit:632; GISEL: ; %bb.0:633; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)634; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0635; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1636; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2637; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3638; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2639; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2640; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3641; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3642; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4643; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6644; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4645; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6646; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4647; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6648; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4649; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6650; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5651; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7652; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5653; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7654; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4655; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5656; GISEL-NEXT: v_mul_lo_u32 v4, v4, v2657; GISEL-NEXT: v_mul_lo_u32 v5, v5, v3658; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4659; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5660; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2661; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3662; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2663; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc664; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3665; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc666; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2667; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3668; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2669; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc670; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3671; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc672; GISEL-NEXT: s_setpc_b64 s[30:31]673;674; CGP-LABEL: v_srem_v2i32_24bit:675; CGP: ; %bb.0:676; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)677; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0678; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1679; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2680; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3681; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2682; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2683; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3684; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3685; CGP-NEXT: v_rcp_f32_e32 v4, v4686; CGP-NEXT: v_rcp_f32_e32 v6, v6687; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4688; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6689; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4690; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6691; CGP-NEXT: v_mul_lo_u32 v5, v5, v4692; CGP-NEXT: v_mul_lo_u32 v7, v7, v6693; CGP-NEXT: v_mul_hi_u32 v5, v4, v5694; CGP-NEXT: v_mul_hi_u32 v7, v6, v7695; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5696; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7697; CGP-NEXT: v_mul_hi_u32 v4, v0, v4698; CGP-NEXT: v_mul_hi_u32 v5, v1, v5699; CGP-NEXT: v_mul_lo_u32 v4, v4, v2700; CGP-NEXT: v_mul_lo_u32 v5, v5, v3701; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4702; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5703; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2704; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3705; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2706; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc707; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3708; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc709; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2710; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3711; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2712; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc713; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3714; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc715; CGP-NEXT: s_setpc_b64 s[30:31]716 %num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>717 %den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>718 %result = srem <2 x i32> %num.mask, %den.mask719 ret <2 x i32> %result720}721