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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s7 8define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {9; GFX6-LABEL: v_ssubsat_i7:10; GFX6: ; %bb.0:11; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)12; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v013; GFX6-NEXT: v_max_i32_e32 v2, -1, v014; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v115; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v216; GFX6-NEXT: v_min_i32_e32 v3, -1, v017; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v318; GFX6-NEXT: v_max_i32_e32 v1, v2, v119; GFX6-NEXT: v_min_i32_e32 v1, v1, v320; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v121; GFX6-NEXT: v_ashrrev_i32_e32 v0, 25, v022; GFX6-NEXT: s_setpc_b64 s[30:31]23;24; GFX8-LABEL: v_ssubsat_i7:25; GFX8: ; %bb.0:26; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v028; GFX8-NEXT: v_max_i16_e32 v2, -1, v029; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v130; GFX8-NEXT: v_add_u16_e32 v2, 0x8001, v231; GFX8-NEXT: v_min_i16_e32 v3, -1, v032; GFX8-NEXT: v_add_u16_e32 v3, 0x8000, v333; GFX8-NEXT: v_max_i16_e32 v1, v2, v134; GFX8-NEXT: v_min_i16_e32 v1, v1, v335; GFX8-NEXT: v_sub_u16_e32 v0, v0, v136; GFX8-NEXT: v_ashrrev_i16_e32 v0, 9, v037; GFX8-NEXT: s_setpc_b64 s[30:31]38;39; GFX9-LABEL: v_ssubsat_i7:40; GFX9: ; %bb.0:41; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v043; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v144; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp45; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v046; GFX9-NEXT: s_setpc_b64 s[30:31]47;48; GFX10PLUS-LABEL: v_ssubsat_i7:49; GFX10PLUS: ; %bb.0:50; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 9, v052; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 9, v153; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp54; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v055; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]56 %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)57 ret i7 %result58}59 60define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {61; GFX6-LABEL: s_ssubsat_i7:62; GFX6: ; %bb.0:63; GFX6-NEXT: s_lshl_b32 s0, s0, 2564; GFX6-NEXT: s_max_i32 s2, s0, -165; GFX6-NEXT: s_lshl_b32 s1, s1, 2566; GFX6-NEXT: s_add_i32 s2, s2, 0x8000000167; GFX6-NEXT: s_min_i32 s3, s0, -168; GFX6-NEXT: s_add_i32 s3, s3, 0x8000000069; GFX6-NEXT: s_max_i32 s1, s2, s170; GFX6-NEXT: s_min_i32 s1, s1, s371; GFX6-NEXT: s_sub_i32 s0, s0, s172; GFX6-NEXT: s_ashr_i32 s0, s0, 2573; GFX6-NEXT: ; return to shader part epilog74;75; GFX8-LABEL: s_ssubsat_i7:76; GFX8: ; %bb.0:77; GFX8-NEXT: s_lshl_b32 s0, s0, 978; GFX8-NEXT: s_sext_i32_i16 s2, s079; GFX8-NEXT: s_max_i32 s3, s2, -180; GFX8-NEXT: s_lshl_b32 s1, s1, 981; GFX8-NEXT: s_add_i32 s3, s3, 0x800182; GFX8-NEXT: s_min_i32 s2, s2, -183; GFX8-NEXT: s_sext_i32_i16 s3, s384; GFX8-NEXT: s_sext_i32_i16 s1, s185; GFX8-NEXT: s_add_i32 s2, s2, 0x800086; GFX8-NEXT: s_max_i32 s1, s3, s187; GFX8-NEXT: s_sext_i32_i16 s1, s188; GFX8-NEXT: s_sext_i32_i16 s2, s289; GFX8-NEXT: s_min_i32 s1, s1, s290; GFX8-NEXT: s_sub_i32 s0, s0, s191; GFX8-NEXT: s_sext_i32_i16 s0, s092; GFX8-NEXT: s_ashr_i32 s0, s0, 993; GFX8-NEXT: ; return to shader part epilog94;95; GFX9-LABEL: s_ssubsat_i7:96; GFX9: ; %bb.0:97; GFX9-NEXT: s_lshl_b32 s1, s1, 998; GFX9-NEXT: s_lshl_b32 s0, s0, 999; GFX9-NEXT: v_mov_b32_e32 v0, s1100; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp101; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0102; GFX9-NEXT: v_readfirstlane_b32 s0, v0103; GFX9-NEXT: ; return to shader part epilog104;105; GFX10PLUS-LABEL: s_ssubsat_i7:106; GFX10PLUS: ; %bb.0:107; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 9108; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 9109; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp110; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 9, v0111; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0112; GFX10PLUS-NEXT: ; return to shader part epilog113 %result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)114 ret i7 %result115}116 117define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {118; GFX6-LABEL: v_ssubsat_i8:119; GFX6: ; %bb.0:120; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0122; GFX6-NEXT: v_max_i32_e32 v2, -1, v0123; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1124; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v2125; GFX6-NEXT: v_min_i32_e32 v3, -1, v0126; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v3127; GFX6-NEXT: v_max_i32_e32 v1, v2, v1128; GFX6-NEXT: v_min_i32_e32 v1, v1, v3129; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1130; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0131; GFX6-NEXT: s_setpc_b64 s[30:31]132;133; GFX8-LABEL: v_ssubsat_i8:134; GFX8: ; %bb.0:135; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)136; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0137; GFX8-NEXT: v_max_i16_e32 v2, -1, v0138; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1139; GFX8-NEXT: v_add_u16_e32 v2, 0x8001, v2140; GFX8-NEXT: v_min_i16_e32 v3, -1, v0141; GFX8-NEXT: v_add_u16_e32 v3, 0x8000, v3142; GFX8-NEXT: v_max_i16_e32 v1, v2, v1143; GFX8-NEXT: v_min_i16_e32 v1, v1, v3144; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1145; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0146; GFX8-NEXT: s_setpc_b64 s[30:31]147;148; GFX9-LABEL: v_ssubsat_i8:149; GFX9: ; %bb.0:150; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0152; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1153; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp154; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0155; GFX9-NEXT: s_setpc_b64 s[30:31]156;157; GFX10PLUS-LABEL: v_ssubsat_i8:158; GFX10PLUS: ; %bb.0:159; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; GFX10PLUS-NEXT: v_lshlrev_b16 v0, 8, v0161; GFX10PLUS-NEXT: v_lshlrev_b16 v1, 8, v1162; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp163; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0164; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]165 %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)166 ret i8 %result167}168 169define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {170; GFX6-LABEL: s_ssubsat_i8:171; GFX6: ; %bb.0:172; GFX6-NEXT: s_lshl_b32 s0, s0, 24173; GFX6-NEXT: s_max_i32 s2, s0, -1174; GFX6-NEXT: s_lshl_b32 s1, s1, 24175; GFX6-NEXT: s_add_i32 s2, s2, 0x80000001176; GFX6-NEXT: s_min_i32 s3, s0, -1177; GFX6-NEXT: s_add_i32 s3, s3, 0x80000000178; GFX6-NEXT: s_max_i32 s1, s2, s1179; GFX6-NEXT: s_min_i32 s1, s1, s3180; GFX6-NEXT: s_sub_i32 s0, s0, s1181; GFX6-NEXT: s_ashr_i32 s0, s0, 24182; GFX6-NEXT: ; return to shader part epilog183;184; GFX8-LABEL: s_ssubsat_i8:185; GFX8: ; %bb.0:186; GFX8-NEXT: s_lshl_b32 s0, s0, 8187; GFX8-NEXT: s_sext_i32_i16 s2, s0188; GFX8-NEXT: s_max_i32 s3, s2, -1189; GFX8-NEXT: s_lshl_b32 s1, s1, 8190; GFX8-NEXT: s_add_i32 s3, s3, 0x8001191; GFX8-NEXT: s_min_i32 s2, s2, -1192; GFX8-NEXT: s_sext_i32_i16 s3, s3193; GFX8-NEXT: s_sext_i32_i16 s1, s1194; GFX8-NEXT: s_add_i32 s2, s2, 0x8000195; GFX8-NEXT: s_max_i32 s1, s3, s1196; GFX8-NEXT: s_sext_i32_i16 s1, s1197; GFX8-NEXT: s_sext_i32_i16 s2, s2198; GFX8-NEXT: s_min_i32 s1, s1, s2199; GFX8-NEXT: s_sub_i32 s0, s0, s1200; GFX8-NEXT: s_sext_i32_i16 s0, s0201; GFX8-NEXT: s_ashr_i32 s0, s0, 8202; GFX8-NEXT: ; return to shader part epilog203;204; GFX9-LABEL: s_ssubsat_i8:205; GFX9: ; %bb.0:206; GFX9-NEXT: s_lshl_b32 s1, s1, 8207; GFX9-NEXT: s_lshl_b32 s0, s0, 8208; GFX9-NEXT: v_mov_b32_e32 v0, s1209; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp210; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0211; GFX9-NEXT: v_readfirstlane_b32 s0, v0212; GFX9-NEXT: ; return to shader part epilog213;214; GFX10PLUS-LABEL: s_ssubsat_i8:215; GFX10PLUS: ; %bb.0:216; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 8217; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 8218; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp219; GFX10PLUS-NEXT: v_ashrrev_i16 v0, 8, v0220; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v0221; GFX10PLUS-NEXT: ; return to shader part epilog222 %result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)223 ret i8 %result224}225 226define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {227; GFX6-LABEL: v_ssubsat_v2i8:228; GFX6: ; %bb.0:229; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0231; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0232; GFX6-NEXT: v_max_i32_e32 v4, -1, v0233; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1234; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1235; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v4236; GFX6-NEXT: v_min_i32_e32 v6, -1, v0237; GFX6-NEXT: v_bfrev_b32_e32 v7, 1238; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v7239; GFX6-NEXT: v_max_i32_e32 v1, v4, v1240; GFX6-NEXT: v_min_i32_e32 v1, v1, v6241; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1242; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2243; GFX6-NEXT: v_mov_b32_e32 v5, 0x80000001244; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3245; GFX6-NEXT: v_max_i32_e32 v3, -1, v1246; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v5247; GFX6-NEXT: v_min_i32_e32 v4, -1, v1248; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v4249; GFX6-NEXT: v_max_i32_e32 v2, v3, v2250; GFX6-NEXT: v_min_i32_e32 v2, v2, v4251; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2252; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1253; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0254; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1255; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0256; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1257; GFX6-NEXT: v_or_b32_e32 v0, v0, v1258; GFX6-NEXT: s_setpc_b64 s[30:31]259;260; GFX8-LABEL: v_ssubsat_v2i8:261; GFX8: ; %bb.0:262; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)263; GFX8-NEXT: v_mov_b32_e32 v2, 8264; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD265; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0266; GFX8-NEXT: v_max_i16_e32 v4, -1, v0267; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD268; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1269; GFX8-NEXT: v_add_u16_e32 v4, 0x8001, v4270; GFX8-NEXT: v_min_i16_e32 v5, -1, v0271; GFX8-NEXT: v_add_u16_e32 v5, 0x8000, v5272; GFX8-NEXT: v_max_i16_e32 v1, v4, v1273; GFX8-NEXT: v_min_i16_e32 v1, v1, v5274; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1275; GFX8-NEXT: v_max_i16_e32 v1, -1, v3276; GFX8-NEXT: v_add_u16_e32 v1, 0x8001, v1277; GFX8-NEXT: v_min_i16_e32 v4, -1, v3278; GFX8-NEXT: v_add_u16_e32 v4, 0x8000, v4279; GFX8-NEXT: v_max_i16_e32 v1, v1, v2280; GFX8-NEXT: v_min_i16_e32 v1, v1, v4281; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1282; GFX8-NEXT: v_mov_b32_e32 v2, 0xff283; GFX8-NEXT: v_and_b32_sdwa v0, sext(v0), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD284; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD285; GFX8-NEXT: v_or_b32_e32 v0, v0, v1286; GFX8-NEXT: s_setpc_b64 s[30:31]287;288; GFX9-LABEL: v_ssubsat_v2i8:289; GFX9: ; %bb.0:290; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)291; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0292; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v1293; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0294; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1295; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0296; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1297; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]298; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]299; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp300; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]301; GFX9-NEXT: v_mov_b32_e32 v1, 0xff302; GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD303; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD304; GFX9-NEXT: s_setpc_b64 s[30:31]305;306; GFX10-LABEL: v_ssubsat_v2i8:307; GFX10: ; %bb.0:308; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)309; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0310; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1311; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0312; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1313; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0314; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v1315; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]316; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]317; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp318; GFX10-NEXT: v_mov_b32_e32 v1, 0xff319; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]320; GFX10-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD321; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD322; GFX10-NEXT: s_setpc_b64 s[30:31]323;324; GFX11-LABEL: v_ssubsat_v2i8:325; GFX11: ; %bb.0:326; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)327; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0328; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1329; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0330; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v1331; GFX11-NEXT: v_lshl_or_b32 v0, v2, 16, v0332; GFX11-NEXT: v_lshl_or_b32 v1, v3, 16, v1333; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]334; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]335; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 clamp336; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]337; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0338; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0339; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1340; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1341; GFX11-NEXT: v_or_b32_e32 v0, v0, v1342; GFX11-NEXT: s_setpc_b64 s[30:31]343 %lhs = bitcast i16 %lhs.arg to <2 x i8>344 %rhs = bitcast i16 %rhs.arg to <2 x i8>345 %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)346 %cast.result = bitcast <2 x i8> %result to i16347 ret i16 %cast.result348}349 350define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {351; GFX6-LABEL: s_ssubsat_v2i8:352; GFX6: ; %bb.0:353; GFX6-NEXT: s_lshr_b32 s2, s0, 8354; GFX6-NEXT: s_lshl_b32 s0, s0, 24355; GFX6-NEXT: s_max_i32 s4, s0, -1356; GFX6-NEXT: s_lshr_b32 s3, s1, 8357; GFX6-NEXT: s_lshl_b32 s1, s1, 24358; GFX6-NEXT: s_add_i32 s4, s4, 0x80000001359; GFX6-NEXT: s_min_i32 s5, s0, -1360; GFX6-NEXT: s_add_i32 s5, s5, 0x80000000361; GFX6-NEXT: s_max_i32 s1, s4, s1362; GFX6-NEXT: s_min_i32 s1, s1, s5363; GFX6-NEXT: s_sub_i32 s0, s0, s1364; GFX6-NEXT: s_lshl_b32 s1, s2, 24365; GFX6-NEXT: s_lshl_b32 s2, s3, 24366; GFX6-NEXT: s_max_i32 s3, s1, -1367; GFX6-NEXT: s_add_i32 s3, s3, 0x80000001368; GFX6-NEXT: s_min_i32 s4, s1, -1369; GFX6-NEXT: s_add_i32 s4, s4, 0x80000000370; GFX6-NEXT: s_max_i32 s2, s3, s2371; GFX6-NEXT: s_min_i32 s2, s2, s4372; GFX6-NEXT: s_sub_i32 s1, s1, s2373; GFX6-NEXT: s_ashr_i32 s1, s1, 24374; GFX6-NEXT: s_ashr_i32 s0, s0, 24375; GFX6-NEXT: s_and_b32 s1, s1, 0xff376; GFX6-NEXT: s_and_b32 s0, s0, 0xff377; GFX6-NEXT: s_lshl_b32 s1, s1, 8378; GFX6-NEXT: s_or_b32 s0, s0, s1379; GFX6-NEXT: ; return to shader part epilog380;381; GFX8-LABEL: s_ssubsat_v2i8:382; GFX8: ; %bb.0:383; GFX8-NEXT: s_lshr_b32 s2, s0, 8384; GFX8-NEXT: s_lshl_b32 s0, s0, 8385; GFX8-NEXT: s_sext_i32_i16 s4, s0386; GFX8-NEXT: s_max_i32 s5, s4, -1387; GFX8-NEXT: s_lshr_b32 s3, s1, 8388; GFX8-NEXT: s_lshl_b32 s1, s1, 8389; GFX8-NEXT: s_add_i32 s5, s5, 0x8001390; GFX8-NEXT: s_min_i32 s4, s4, -1391; GFX8-NEXT: s_sext_i32_i16 s5, s5392; GFX8-NEXT: s_sext_i32_i16 s1, s1393; GFX8-NEXT: s_add_i32 s4, s4, 0x8000394; GFX8-NEXT: s_max_i32 s1, s5, s1395; GFX8-NEXT: s_sext_i32_i16 s1, s1396; GFX8-NEXT: s_sext_i32_i16 s4, s4397; GFX8-NEXT: s_min_i32 s1, s1, s4398; GFX8-NEXT: s_sub_i32 s0, s0, s1399; GFX8-NEXT: s_lshl_b32 s1, s2, 8400; GFX8-NEXT: s_lshl_b32 s2, s3, 8401; GFX8-NEXT: s_sext_i32_i16 s3, s1402; GFX8-NEXT: s_max_i32 s4, s3, -1403; GFX8-NEXT: s_add_i32 s4, s4, 0x8001404; GFX8-NEXT: s_min_i32 s3, s3, -1405; GFX8-NEXT: s_sext_i32_i16 s4, s4406; GFX8-NEXT: s_sext_i32_i16 s2, s2407; GFX8-NEXT: s_add_i32 s3, s3, 0x8000408; GFX8-NEXT: s_max_i32 s2, s4, s2409; GFX8-NEXT: s_sext_i32_i16 s2, s2410; GFX8-NEXT: s_sext_i32_i16 s3, s3411; GFX8-NEXT: s_min_i32 s2, s2, s3412; GFX8-NEXT: s_sub_i32 s1, s1, s2413; GFX8-NEXT: s_sext_i32_i16 s1, s1414; GFX8-NEXT: s_sext_i32_i16 s0, s0415; GFX8-NEXT: s_ashr_i32 s1, s1, 8416; GFX8-NEXT: s_ashr_i32 s0, s0, 8417; GFX8-NEXT: s_and_b32 s1, s1, 0xff418; GFX8-NEXT: s_and_b32 s0, s0, 0xff419; GFX8-NEXT: s_lshl_b32 s1, s1, 8420; GFX8-NEXT: s_or_b32 s0, s0, s1421; GFX8-NEXT: ; return to shader part epilog422;423; GFX9-LABEL: s_ssubsat_v2i8:424; GFX9: ; %bb.0:425; GFX9-NEXT: s_lshr_b32 s2, s0, 8426; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2427; GFX9-NEXT: s_lshr_b32 s3, s1, 8428; GFX9-NEXT: s_lshr_b32 s2, s0, 16429; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3430; GFX9-NEXT: s_lshl_b32 s0, s0, 0x80008431; GFX9-NEXT: s_lshl_b32 s2, s2, 8432; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2433; GFX9-NEXT: s_lshr_b32 s2, s1, 16434; GFX9-NEXT: s_lshl_b32 s1, s1, 0x80008435; GFX9-NEXT: s_lshl_b32 s2, s2, 8436; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2437; GFX9-NEXT: v_mov_b32_e32 v0, s1438; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp439; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]440; GFX9-NEXT: v_mov_b32_e32 v1, 0xff441; GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD442; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD443; GFX9-NEXT: v_readfirstlane_b32 s0, v0444; GFX9-NEXT: ; return to shader part epilog445;446; GFX10-LABEL: s_ssubsat_v2i8:447; GFX10: ; %bb.0:448; GFX10-NEXT: s_lshr_b32 s2, s0, 8449; GFX10-NEXT: s_lshr_b32 s3, s1, 8450; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2451; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3452; GFX10-NEXT: s_lshr_b32 s2, s0, 16453; GFX10-NEXT: s_lshr_b32 s3, s1, 16454; GFX10-NEXT: s_lshl_b32 s0, s0, 0x80008455; GFX10-NEXT: s_lshl_b32 s2, s2, 8456; GFX10-NEXT: s_lshl_b32 s1, s1, 0x80008457; GFX10-NEXT: s_lshl_b32 s3, s3, 8458; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2459; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3460; GFX10-NEXT: v_mov_b32_e32 v1, 0xff461; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp462; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]463; GFX10-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD464; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD465; GFX10-NEXT: v_readfirstlane_b32 s0, v0466; GFX10-NEXT: ; return to shader part epilog467;468; GFX11-LABEL: s_ssubsat_v2i8:469; GFX11: ; %bb.0:470; GFX11-NEXT: s_lshr_b32 s2, s0, 8471; GFX11-NEXT: s_lshr_b32 s3, s1, 8472; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2473; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3474; GFX11-NEXT: s_lshr_b32 s2, s0, 16475; GFX11-NEXT: s_lshr_b32 s3, s1, 16476; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008477; GFX11-NEXT: s_lshl_b32 s2, s2, 8478; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008479; GFX11-NEXT: s_lshl_b32 s3, s3, 8480; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2481; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s3482; GFX11-NEXT: v_pk_sub_i16 v0, s0, s1 clamp483; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]484; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0485; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0486; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1487; GFX11-NEXT: v_lshlrev_b16 v1, 8, v1488; GFX11-NEXT: v_or_b32_e32 v0, v0, v1489; GFX11-NEXT: v_readfirstlane_b32 s0, v0490; GFX11-NEXT: ; return to shader part epilog491 %lhs = bitcast i16 %lhs.arg to <2 x i8>492 %rhs = bitcast i16 %rhs.arg to <2 x i8>493 %result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)494 %cast.result = bitcast <2 x i8> %result to i16495 ret i16 %cast.result496}497 498define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {499; GFX6-LABEL: v_ssubsat_v4i8:500; GFX6: ; %bb.0:501; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0503; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0504; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0505; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0506; GFX6-NEXT: v_max_i32_e32 v8, -1, v0507; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1508; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1509; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1510; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1511; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v8512; GFX6-NEXT: v_min_i32_e32 v10, -1, v0513; GFX6-NEXT: v_bfrev_b32_e32 v11, 1514; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v11515; GFX6-NEXT: v_max_i32_e32 v1, v8, v1516; GFX6-NEXT: v_min_i32_e32 v1, v1, v10517; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1518; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2519; GFX6-NEXT: v_mov_b32_e32 v9, 0x80000001520; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5521; GFX6-NEXT: v_max_i32_e32 v5, -1, v1522; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9523; GFX6-NEXT: v_min_i32_e32 v8, -1, v1524; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v11525; GFX6-NEXT: v_max_i32_e32 v2, v5, v2526; GFX6-NEXT: v_min_i32_e32 v2, v2, v8527; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2528; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3529; GFX6-NEXT: v_max_i32_e32 v5, -1, v2530; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6531; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9532; GFX6-NEXT: v_min_i32_e32 v6, -1, v2533; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11534; GFX6-NEXT: v_max_i32_e32 v3, v5, v3535; GFX6-NEXT: v_min_i32_e32 v3, v3, v6536; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3537; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4538; GFX6-NEXT: v_max_i32_e32 v5, -1, v3539; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1540; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7541; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v9542; GFX6-NEXT: v_min_i32_e32 v6, -1, v3543; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0544; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v11545; GFX6-NEXT: v_max_i32_e32 v4, v5, v4546; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v1547; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2548; GFX6-NEXT: v_min_i32_e32 v4, v4, v6549; GFX6-NEXT: v_and_b32_e32 v0, 0xff, v0550; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1551; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4552; GFX6-NEXT: v_or_b32_e32 v0, v0, v1553; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v2554; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3555; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1556; GFX6-NEXT: v_or_b32_e32 v0, v0, v1557; GFX6-NEXT: v_and_b32_e32 v1, 0xff, v3558; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1559; GFX6-NEXT: v_or_b32_e32 v0, v0, v1560; GFX6-NEXT: s_setpc_b64 s[30:31]561;562; GFX8-LABEL: v_ssubsat_v4i8:563; GFX8: ; %bb.0:564; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX8-NEXT: v_mov_b32_e32 v2, 8566; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD567; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0568; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0569; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0570; GFX8-NEXT: v_max_i16_e32 v8, -1, v0571; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD572; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1573; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1574; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1575; GFX8-NEXT: v_add_u16_e32 v8, 0x8001, v8576; GFX8-NEXT: v_min_i16_e32 v9, -1, v0577; GFX8-NEXT: v_add_u16_e32 v9, 0x8000, v9578; GFX8-NEXT: v_max_i16_e32 v1, v8, v1579; GFX8-NEXT: v_min_i16_e32 v1, v1, v9580; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1581; GFX8-NEXT: v_max_i16_e32 v1, -1, v3582; GFX8-NEXT: v_add_u16_e32 v1, 0x8001, v1583; GFX8-NEXT: v_min_i16_e32 v8, -1, v3584; GFX8-NEXT: v_add_u16_e32 v8, 0x8000, v8585; GFX8-NEXT: v_max_i16_e32 v1, v1, v2586; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4587; GFX8-NEXT: v_min_i16_e32 v1, v1, v8588; GFX8-NEXT: v_max_i16_e32 v4, -1, v2589; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1590; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6591; GFX8-NEXT: v_add_u16_e32 v4, 0x8001, v4592; GFX8-NEXT: v_min_i16_e32 v6, -1, v2593; GFX8-NEXT: v_add_u16_e32 v6, 0x8000, v6594; GFX8-NEXT: v_max_i16_e32 v3, v4, v3595; GFX8-NEXT: v_min_i16_e32 v3, v3, v6596; GFX8-NEXT: v_sub_u16_e32 v2, v2, v3597; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5598; GFX8-NEXT: v_max_i16_e32 v5, -1, v3599; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7600; GFX8-NEXT: v_add_u16_e32 v5, 0x8001, v5601; GFX8-NEXT: v_min_i16_e32 v6, -1, v3602; GFX8-NEXT: v_add_u16_e32 v6, 0x8000, v6603; GFX8-NEXT: v_max_i16_e32 v4, v5, v4604; GFX8-NEXT: v_min_i16_e32 v4, v4, v6605; GFX8-NEXT: v_sub_u16_e32 v3, v3, v4606; GFX8-NEXT: v_mov_b32_e32 v4, 0xff607; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD608; GFX8-NEXT: v_and_b32_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD609; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1610; GFX8-NEXT: v_or_b32_e32 v0, v0, v1611; GFX8-NEXT: v_and_b32_sdwa v1, sext(v2), v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD612; GFX8-NEXT: v_or_b32_e32 v0, v0, v1613; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD614; GFX8-NEXT: v_or_b32_e32 v0, v0, v1615; GFX8-NEXT: s_setpc_b64 s[30:31]616;617; GFX9-LABEL: v_ssubsat_v4i8:618; GFX9: ; %bb.0:619; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)620; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0621; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0622; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1623; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v0624; GFX9-NEXT: v_alignbit_b32 v0, v3, v0, 16625; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v1626; GFX9-NEXT: v_lshrrev_b32_e32 v5, 24, v1627; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v6628; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3629; GFX9-NEXT: v_alignbit_b32 v1, v5, v1, 16630; GFX9-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]631; GFX9-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]632; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]633; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]634; GFX9-NEXT: v_pk_sub_i16 v2, v2, v3 clamp635; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp636; GFX9-NEXT: v_pk_ashrrev_i16 v1, 8, v2 op_sel_hi:[0,1]637; GFX9-NEXT: v_mov_b32_e32 v3, 8638; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]639; GFX9-NEXT: v_mov_b32_e32 v2, 0xff640; GFX9-NEXT: v_lshlrev_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2641; GFX9-NEXT: v_and_or_b32 v1, v1, v2, v3642; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v0643; GFX9-NEXT: v_mov_b32_e32 v3, 24644; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2645; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2646; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0647; GFX9-NEXT: s_setpc_b64 s[30:31]648;649; GFX10-LABEL: v_ssubsat_v4i8:650; GFX10: ; %bb.0:651; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)652; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0653; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0654; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v0655; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v1656; GFX10-NEXT: v_and_b32_e32 v6, 0xffff, v1657; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1658; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16659; GFX10-NEXT: v_lshl_or_b32 v2, v2, 16, v4660; GFX10-NEXT: v_mov_b32_e32 v4, 24661; GFX10-NEXT: v_lshl_or_b32 v3, v5, 16, v6662; GFX10-NEXT: v_alignbit_b32 v1, v7, v1, 16663; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]664; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]665; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]666; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]667; GFX10-NEXT: v_pk_sub_i16 v2, v2, v3 clamp668; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp669; GFX10-NEXT: v_mov_b32_e32 v1, 8670; GFX10-NEXT: v_pk_ashrrev_i16 v2, 8, v2 op_sel_hi:[0,1]671; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]672; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2673; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0674; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2675; GFX10-NEXT: v_and_or_b32 v1, 0xff, v2, v1676; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3677; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0678; GFX10-NEXT: s_setpc_b64 s[30:31]679;680; GFX11-LABEL: v_ssubsat_v4i8:681; GFX11: ; %bb.0:682; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)683; GFX11-NEXT: v_lshrrev_b32_e32 v2, 8, v0684; GFX11-NEXT: v_lshrrev_b32_e32 v3, 8, v1685; GFX11-NEXT: v_and_b32_e32 v4, 0xffff, v0686; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v1687; GFX11-NEXT: v_lshrrev_b32_e32 v6, 24, v0688; GFX11-NEXT: v_lshrrev_b32_e32 v7, 24, v1689; GFX11-NEXT: v_lshl_or_b32 v2, v2, 16, v4690; GFX11-NEXT: v_lshl_or_b32 v3, v3, 16, v5691; GFX11-NEXT: v_alignbit_b32 v0, v6, v0, 16692; GFX11-NEXT: v_alignbit_b32 v1, v7, v1, 16693; GFX11-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]694; GFX11-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]695; GFX11-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]696; GFX11-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]697; GFX11-NEXT: v_pk_sub_i16 v2, v2, v3 clamp698; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 clamp699; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v2 op_sel_hi:[0,1]700; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]701; GFX11-NEXT: v_bfe_u32 v2, v1, 16, 8702; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v0703; GFX11-NEXT: v_bfe_u32 v0, v0, 16, 8704; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2705; GFX11-NEXT: v_lshlrev_b32_e32 v3, 16, v3706; GFX11-NEXT: v_lshlrev_b32_e32 v0, 24, v0707; GFX11-NEXT: v_and_or_b32 v1, 0xff, v1, v2708; GFX11-NEXT: v_or3_b32 v0, v1, v3, v0709; GFX11-NEXT: s_setpc_b64 s[30:31]710 %lhs = bitcast i32 %lhs.arg to <4 x i8>711 %rhs = bitcast i32 %rhs.arg to <4 x i8>712 %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)713 %cast.result = bitcast <4 x i8> %result to i32714 ret i32 %cast.result715}716 717define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {718; GFX6-LABEL: s_ssubsat_v4i8:719; GFX6: ; %bb.0:720; GFX6-NEXT: s_lshr_b32 s2, s0, 8721; GFX6-NEXT: s_lshr_b32 s3, s0, 16722; GFX6-NEXT: s_lshr_b32 s4, s0, 24723; GFX6-NEXT: s_lshl_b32 s0, s0, 24724; GFX6-NEXT: s_max_i32 s8, s0, -1725; GFX6-NEXT: s_lshr_b32 s5, s1, 8726; GFX6-NEXT: s_lshr_b32 s6, s1, 16727; GFX6-NEXT: s_lshr_b32 s7, s1, 24728; GFX6-NEXT: s_lshl_b32 s1, s1, 24729; GFX6-NEXT: s_add_i32 s8, s8, 0x80000001730; GFX6-NEXT: s_min_i32 s9, s0, -1731; GFX6-NEXT: s_add_i32 s9, s9, 0x80000000732; GFX6-NEXT: s_max_i32 s1, s8, s1733; GFX6-NEXT: s_min_i32 s1, s1, s9734; GFX6-NEXT: s_sub_i32 s0, s0, s1735; GFX6-NEXT: s_lshl_b32 s1, s2, 24736; GFX6-NEXT: s_lshl_b32 s2, s5, 24737; GFX6-NEXT: s_max_i32 s5, s1, -1738; GFX6-NEXT: s_add_i32 s5, s5, 0x80000001739; GFX6-NEXT: s_min_i32 s8, s1, -1740; GFX6-NEXT: s_add_i32 s8, s8, 0x80000000741; GFX6-NEXT: s_max_i32 s2, s5, s2742; GFX6-NEXT: s_min_i32 s2, s2, s8743; GFX6-NEXT: s_sub_i32 s1, s1, s2744; GFX6-NEXT: s_lshl_b32 s2, s3, 24745; GFX6-NEXT: s_max_i32 s5, s2, -1746; GFX6-NEXT: s_lshl_b32 s3, s6, 24747; GFX6-NEXT: s_add_i32 s5, s5, 0x80000001748; GFX6-NEXT: s_min_i32 s6, s2, -1749; GFX6-NEXT: s_add_i32 s6, s6, 0x80000000750; GFX6-NEXT: s_max_i32 s3, s5, s3751; GFX6-NEXT: s_min_i32 s3, s3, s6752; GFX6-NEXT: s_sub_i32 s2, s2, s3753; GFX6-NEXT: s_lshl_b32 s3, s4, 24754; GFX6-NEXT: s_max_i32 s5, s3, -1755; GFX6-NEXT: s_ashr_i32 s1, s1, 24756; GFX6-NEXT: s_lshl_b32 s4, s7, 24757; GFX6-NEXT: s_add_i32 s5, s5, 0x80000001758; GFX6-NEXT: s_min_i32 s6, s3, -1759; GFX6-NEXT: s_ashr_i32 s0, s0, 24760; GFX6-NEXT: s_add_i32 s6, s6, 0x80000000761; GFX6-NEXT: s_max_i32 s4, s5, s4762; GFX6-NEXT: s_and_b32 s1, s1, 0xff763; GFX6-NEXT: s_ashr_i32 s2, s2, 24764; GFX6-NEXT: s_min_i32 s4, s4, s6765; GFX6-NEXT: s_and_b32 s0, s0, 0xff766; GFX6-NEXT: s_lshl_b32 s1, s1, 8767; GFX6-NEXT: s_sub_i32 s3, s3, s4768; GFX6-NEXT: s_or_b32 s0, s0, s1769; GFX6-NEXT: s_and_b32 s1, s2, 0xff770; GFX6-NEXT: s_ashr_i32 s3, s3, 24771; GFX6-NEXT: s_lshl_b32 s1, s1, 16772; GFX6-NEXT: s_or_b32 s0, s0, s1773; GFX6-NEXT: s_and_b32 s1, s3, 0xff774; GFX6-NEXT: s_lshl_b32 s1, s1, 24775; GFX6-NEXT: s_or_b32 s0, s0, s1776; GFX6-NEXT: ; return to shader part epilog777;778; GFX8-LABEL: s_ssubsat_v4i8:779; GFX8: ; %bb.0:780; GFX8-NEXT: s_lshr_b32 s2, s0, 8781; GFX8-NEXT: s_lshr_b32 s3, s0, 16782; GFX8-NEXT: s_lshr_b32 s4, s0, 24783; GFX8-NEXT: s_lshl_b32 s0, s0, 8784; GFX8-NEXT: s_sext_i32_i16 s8, s0785; GFX8-NEXT: s_max_i32 s9, s8, -1786; GFX8-NEXT: s_lshr_b32 s5, s1, 8787; GFX8-NEXT: s_lshr_b32 s6, s1, 16788; GFX8-NEXT: s_lshr_b32 s7, s1, 24789; GFX8-NEXT: s_lshl_b32 s1, s1, 8790; GFX8-NEXT: s_add_i32 s9, s9, 0x8001791; GFX8-NEXT: s_min_i32 s8, s8, -1792; GFX8-NEXT: s_sext_i32_i16 s9, s9793; GFX8-NEXT: s_sext_i32_i16 s1, s1794; GFX8-NEXT: s_add_i32 s8, s8, 0x8000795; GFX8-NEXT: s_max_i32 s1, s9, s1796; GFX8-NEXT: s_sext_i32_i16 s1, s1797; GFX8-NEXT: s_sext_i32_i16 s8, s8798; GFX8-NEXT: s_min_i32 s1, s1, s8799; GFX8-NEXT: s_sub_i32 s0, s0, s1800; GFX8-NEXT: s_lshl_b32 s1, s2, 8801; GFX8-NEXT: s_lshl_b32 s2, s5, 8802; GFX8-NEXT: s_sext_i32_i16 s5, s1803; GFX8-NEXT: s_max_i32 s8, s5, -1804; GFX8-NEXT: s_add_i32 s8, s8, 0x8001805; GFX8-NEXT: s_min_i32 s5, s5, -1806; GFX8-NEXT: s_sext_i32_i16 s8, s8807; GFX8-NEXT: s_sext_i32_i16 s2, s2808; GFX8-NEXT: s_add_i32 s5, s5, 0x8000809; GFX8-NEXT: s_max_i32 s2, s8, s2810; GFX8-NEXT: s_sext_i32_i16 s2, s2811; GFX8-NEXT: s_sext_i32_i16 s5, s5812; GFX8-NEXT: s_min_i32 s2, s2, s5813; GFX8-NEXT: s_sub_i32 s1, s1, s2814; GFX8-NEXT: s_lshl_b32 s2, s3, 8815; GFX8-NEXT: s_sext_i32_i16 s5, s2816; GFX8-NEXT: s_lshl_b32 s3, s6, 8817; GFX8-NEXT: s_max_i32 s6, s5, -1818; GFX8-NEXT: s_add_i32 s6, s6, 0x8001819; GFX8-NEXT: s_min_i32 s5, s5, -1820; GFX8-NEXT: s_sext_i32_i16 s6, s6821; GFX8-NEXT: s_sext_i32_i16 s3, s3822; GFX8-NEXT: s_add_i32 s5, s5, 0x8000823; GFX8-NEXT: s_max_i32 s3, s6, s3824; GFX8-NEXT: s_sext_i32_i16 s3, s3825; GFX8-NEXT: s_sext_i32_i16 s5, s5826; GFX8-NEXT: s_min_i32 s3, s3, s5827; GFX8-NEXT: s_sub_i32 s2, s2, s3828; GFX8-NEXT: s_lshl_b32 s3, s4, 8829; GFX8-NEXT: s_sext_i32_i16 s5, s3830; GFX8-NEXT: s_max_i32 s6, s5, -1831; GFX8-NEXT: s_lshl_b32 s4, s7, 8832; GFX8-NEXT: s_add_i32 s6, s6, 0x8001833; GFX8-NEXT: s_min_i32 s5, s5, -1834; GFX8-NEXT: s_sext_i32_i16 s6, s6835; GFX8-NEXT: s_sext_i32_i16 s4, s4836; GFX8-NEXT: s_sext_i32_i16 s1, s1837; GFX8-NEXT: s_add_i32 s5, s5, 0x8000838; GFX8-NEXT: s_max_i32 s4, s6, s4839; GFX8-NEXT: s_sext_i32_i16 s0, s0840; GFX8-NEXT: s_ashr_i32 s1, s1, 8841; GFX8-NEXT: s_sext_i32_i16 s4, s4842; GFX8-NEXT: s_sext_i32_i16 s5, s5843; GFX8-NEXT: s_ashr_i32 s0, s0, 8844; GFX8-NEXT: s_sext_i32_i16 s2, s2845; GFX8-NEXT: s_min_i32 s4, s4, s5846; GFX8-NEXT: s_and_b32 s1, s1, 0xff847; GFX8-NEXT: s_ashr_i32 s2, s2, 8848; GFX8-NEXT: s_sub_i32 s3, s3, s4849; GFX8-NEXT: s_and_b32 s0, s0, 0xff850; GFX8-NEXT: s_lshl_b32 s1, s1, 8851; GFX8-NEXT: s_sext_i32_i16 s3, s3852; GFX8-NEXT: s_or_b32 s0, s0, s1853; GFX8-NEXT: s_and_b32 s1, s2, 0xff854; GFX8-NEXT: s_ashr_i32 s3, s3, 8855; GFX8-NEXT: s_lshl_b32 s1, s1, 16856; GFX8-NEXT: s_or_b32 s0, s0, s1857; GFX8-NEXT: s_and_b32 s1, s3, 0xff858; GFX8-NEXT: s_lshl_b32 s1, s1, 24859; GFX8-NEXT: s_or_b32 s0, s0, s1860; GFX8-NEXT: ; return to shader part epilog861;862; GFX9-LABEL: s_ssubsat_v4i8:863; GFX9: ; %bb.0:864; GFX9-NEXT: s_lshr_b32 s2, s0, 8865; GFX9-NEXT: s_lshr_b32 s3, s0, 16866; GFX9-NEXT: s_lshr_b32 s4, s0, 24867; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2868; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4869; GFX9-NEXT: s_lshr_b32 s4, s0, 16870; GFX9-NEXT: s_lshl_b32 s0, s0, 0x80008871; GFX9-NEXT: s_lshl_b32 s4, s4, 8872; GFX9-NEXT: s_lshr_b32 s5, s1, 8873; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4874; GFX9-NEXT: s_lshr_b32 s4, s2, 16875; GFX9-NEXT: s_lshr_b32 s6, s1, 16876; GFX9-NEXT: s_lshr_b32 s7, s1, 24877; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5878; GFX9-NEXT: s_lshl_b32 s2, s2, 0x80008879; GFX9-NEXT: s_lshl_b32 s4, s4, 8880; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4881; GFX9-NEXT: s_lshr_b32 s4, s1, 16882; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7883; GFX9-NEXT: s_lshl_b32 s1, s1, 0x80008884; GFX9-NEXT: s_lshl_b32 s4, s4, 8885; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4886; GFX9-NEXT: s_lshr_b32 s4, s3, 16887; GFX9-NEXT: s_lshl_b32 s3, s3, 0x80008888; GFX9-NEXT: s_lshl_b32 s4, s4, 8889; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4890; GFX9-NEXT: v_mov_b32_e32 v0, s1891; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp892; GFX9-NEXT: v_mov_b32_e32 v1, s3893; GFX9-NEXT: v_pk_sub_i16 v1, s2, v1 clamp894; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]895; GFX9-NEXT: v_mov_b32_e32 v3, 8896; GFX9-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]897; GFX9-NEXT: v_mov_b32_e32 v2, 0xff898; GFX9-NEXT: v_lshlrev_b32_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2899; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v3900; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1901; GFX9-NEXT: v_mov_b32_e32 v3, 24902; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2903; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2904; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1905; GFX9-NEXT: v_readfirstlane_b32 s0, v0906; GFX9-NEXT: ; return to shader part epilog907;908; GFX10-LABEL: s_ssubsat_v4i8:909; GFX10: ; %bb.0:910; GFX10-NEXT: s_lshr_b32 s2, s0, 8911; GFX10-NEXT: s_lshr_b32 s3, s0, 16912; GFX10-NEXT: s_lshr_b32 s4, s0, 24913; GFX10-NEXT: s_lshr_b32 s5, s1, 8914; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2915; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4916; GFX10-NEXT: s_lshr_b32 s6, s1, 16917; GFX10-NEXT: s_lshr_b32 s7, s1, 24918; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5919; GFX10-NEXT: s_lshr_b32 s4, s0, 16920; GFX10-NEXT: s_lshr_b32 s5, s2, 16921; GFX10-NEXT: s_pack_ll_b32_b16 s3, s6, s7922; GFX10-NEXT: s_lshl_b32 s0, s0, 0x80008923; GFX10-NEXT: s_lshl_b32 s4, s4, 8924; GFX10-NEXT: s_lshl_b32 s2, s2, 0x80008925; GFX10-NEXT: s_lshl_b32 s5, s5, 8926; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4927; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s5928; GFX10-NEXT: s_lshr_b32 s4, s1, 16929; GFX10-NEXT: s_lshr_b32 s5, s3, 16930; GFX10-NEXT: s_lshl_b32 s1, s1, 0x80008931; GFX10-NEXT: s_lshl_b32 s4, s4, 8932; GFX10-NEXT: s_lshl_b32 s3, s3, 0x80008933; GFX10-NEXT: s_lshl_b32 s5, s5, 8934; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4935; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5936; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp937; GFX10-NEXT: v_pk_sub_i16 v1, s2, s3 clamp938; GFX10-NEXT: v_mov_b32_e32 v2, 8939; GFX10-NEXT: v_mov_b32_e32 v4, 24940; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]941; GFX10-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]942; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2943; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1944; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2945; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v2946; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3947; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1948; GFX10-NEXT: v_readfirstlane_b32 s0, v0949; GFX10-NEXT: ; return to shader part epilog950;951; GFX11-LABEL: s_ssubsat_v4i8:952; GFX11: ; %bb.0:953; GFX11-NEXT: s_lshr_b32 s2, s0, 8954; GFX11-NEXT: s_lshr_b32 s3, s0, 24955; GFX11-NEXT: s_lshr_b32 s4, s1, 8956; GFX11-NEXT: s_lshr_b32 s5, s1, 24957; GFX11-NEXT: s_pack_ll_b32_b16 s2, s0, s2958; GFX11-NEXT: s_pack_hl_b32_b16 s0, s0, s3959; GFX11-NEXT: s_pack_ll_b32_b16 s3, s1, s4960; GFX11-NEXT: s_lshr_b32 s4, s2, 16961; GFX11-NEXT: s_pack_hl_b32_b16 s1, s1, s5962; GFX11-NEXT: s_lshr_b32 s5, s3, 16963; GFX11-NEXT: s_lshl_b32 s2, s2, 0x80008964; GFX11-NEXT: s_lshl_b32 s4, s4, 8965; GFX11-NEXT: s_lshl_b32 s3, s3, 0x80008966; GFX11-NEXT: s_lshl_b32 s5, s5, 8967; GFX11-NEXT: s_pack_ll_b32_b16 s2, s2, s4968; GFX11-NEXT: s_pack_ll_b32_b16 s3, s3, s5969; GFX11-NEXT: s_lshr_b32 s4, s0, 16970; GFX11-NEXT: s_lshr_b32 s5, s1, 16971; GFX11-NEXT: v_pk_sub_i16 v0, s2, s3 clamp972; GFX11-NEXT: s_lshl_b32 s0, s0, 0x80008973; GFX11-NEXT: s_lshl_b32 s4, s4, 8974; GFX11-NEXT: s_lshl_b32 s1, s1, 0x80008975; GFX11-NEXT: s_lshl_b32 s2, s5, 8976; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s4977; GFX11-NEXT: s_pack_ll_b32_b16 s1, s1, s2978; GFX11-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]979; GFX11-NEXT: v_pk_sub_i16 v1, s0, s1 clamp980; GFX11-NEXT: v_bfe_u32 v2, v0, 16, 8981; GFX11-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]982; GFX11-NEXT: v_lshlrev_b32_e32 v2, 8, v2983; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v1984; GFX11-NEXT: v_bfe_u32 v1, v1, 16, 8985; GFX11-NEXT: v_and_or_b32 v0, 0xff, v0, v2986; GFX11-NEXT: v_lshlrev_b32_e32 v2, 16, v3987; GFX11-NEXT: v_lshlrev_b32_e32 v1, 24, v1988; GFX11-NEXT: v_or3_b32 v0, v0, v2, v1989; GFX11-NEXT: v_readfirstlane_b32 s0, v0990; GFX11-NEXT: ; return to shader part epilog991 %lhs = bitcast i32 %lhs.arg to <4 x i8>992 %rhs = bitcast i32 %rhs.arg to <4 x i8>993 %result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)994 %cast.result = bitcast <4 x i8> %result to i32995 ret i32 %cast.result996}997 998define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {999; GFX6-LABEL: v_ssubsat_i24:1000; GFX6: ; %bb.0:1001; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1002; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v01003; GFX6-NEXT: v_max_i32_e32 v2, -1, v01004; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v11005; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v21006; GFX6-NEXT: v_min_i32_e32 v3, -1, v01007; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v31008; GFX6-NEXT: v_max_i32_e32 v1, v2, v11009; GFX6-NEXT: v_min_i32_e32 v1, v1, v31010; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11011; GFX6-NEXT: v_ashrrev_i32_e32 v0, 8, v01012; GFX6-NEXT: s_setpc_b64 s[30:31]1013;1014; GFX8-LABEL: v_ssubsat_i24:1015; GFX8: ; %bb.0:1016; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1017; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v11018; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 241019; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 241020; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v01021; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 241022; GFX8-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v01023; GFX8-NEXT: v_ashrrev_i32_e32 v0, 23, v31024; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0xff800000, v01025; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]1026; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc1027; GFX8-NEXT: s_setpc_b64 s[30:31]1028;1029; GFX9-LABEL: v_ssubsat_i24:1030; GFX9: ; %bb.0:1031; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1032; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v01033; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v11034; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp1035; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v01036; GFX9-NEXT: s_setpc_b64 s[30:31]1037;1038; GFX10PLUS-LABEL: v_ssubsat_i24:1039; GFX10PLUS: ; %bb.0:1040; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1041; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v01042; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v11043; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v1 clamp1044; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v01045; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1046 %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)1047 ret i24 %result1048}1049 1050define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {1051; GFX6-LABEL: s_ssubsat_i24:1052; GFX6: ; %bb.0:1053; GFX6-NEXT: s_lshl_b32 s0, s0, 81054; GFX6-NEXT: s_max_i32 s2, s0, -11055; GFX6-NEXT: s_lshl_b32 s1, s1, 81056; GFX6-NEXT: s_add_i32 s2, s2, 0x800000011057; GFX6-NEXT: s_min_i32 s3, s0, -11058; GFX6-NEXT: s_add_i32 s3, s3, 0x800000001059; GFX6-NEXT: s_max_i32 s1, s2, s11060; GFX6-NEXT: s_min_i32 s1, s1, s31061; GFX6-NEXT: s_sub_i32 s0, s0, s11062; GFX6-NEXT: s_ashr_i32 s0, s0, 81063; GFX6-NEXT: ; return to shader part epilog1064;1065; GFX8-LABEL: s_ssubsat_i24:1066; GFX8: ; %bb.0:1067; GFX8-NEXT: s_sub_i32 s2, s0, s11068; GFX8-NEXT: s_bfe_i32 s3, s2, 0x1800001069; GFX8-NEXT: s_bfe_i32 s0, s0, 0x1800001070; GFX8-NEXT: s_cmp_lt_i32 s3, s01071; GFX8-NEXT: s_cselect_b32 s0, 1, 01072; GFX8-NEXT: s_bfe_i32 s1, s1, 0x1800001073; GFX8-NEXT: s_cmp_gt_i32 s1, 01074; GFX8-NEXT: s_cselect_b32 s1, 1, 01075; GFX8-NEXT: s_xor_b32 s0, s1, s01076; GFX8-NEXT: s_ashr_i32 s1, s3, 231077; GFX8-NEXT: s_add_i32 s1, s1, 0xff8000001078; GFX8-NEXT: s_cmp_lg_u32 s0, 01079; GFX8-NEXT: s_cselect_b32 s0, s1, s21080; GFX8-NEXT: ; return to shader part epilog1081;1082; GFX9-LABEL: s_ssubsat_i24:1083; GFX9: ; %bb.0:1084; GFX9-NEXT: s_lshl_b32 s1, s1, 81085; GFX9-NEXT: s_lshl_b32 s0, s0, 81086; GFX9-NEXT: v_mov_b32_e32 v0, s11087; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1088; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v01089; GFX9-NEXT: v_readfirstlane_b32 s0, v01090; GFX9-NEXT: ; return to shader part epilog1091;1092; GFX10PLUS-LABEL: s_ssubsat_i24:1093; GFX10PLUS: ; %bb.0:1094; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 81095; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 81096; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s1 clamp1097; GFX10PLUS-NEXT: v_ashrrev_i32_e32 v0, 8, v01098; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01099; GFX10PLUS-NEXT: ; return to shader part epilog1100 %result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)1101 ret i24 %result1102}1103 1104define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {1105; GFX6-LABEL: v_ssubsat_i32:1106; GFX6: ; %bb.0:1107; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1108; GFX6-NEXT: v_max_i32_e32 v2, -1, v01109; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v21110; GFX6-NEXT: v_min_i32_e32 v3, -1, v01111; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v31112; GFX6-NEXT: v_max_i32_e32 v1, v2, v11113; GFX6-NEXT: v_min_i32_e32 v1, v1, v31114; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11115; GFX6-NEXT: s_setpc_b64 s[30:31]1116;1117; GFX8-LABEL: v_ssubsat_i32:1118; GFX8: ; %bb.0:1119; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1120; GFX8-NEXT: v_max_i32_e32 v2, -1, v01121; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x80000001, v21122; GFX8-NEXT: v_min_i32_e32 v3, -1, v01123; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000000, v31124; GFX8-NEXT: v_max_i32_e32 v1, v2, v11125; GFX8-NEXT: v_min_i32_e32 v1, v1, v31126; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v11127; GFX8-NEXT: s_setpc_b64 s[30:31]1128;1129; GFX9-LABEL: v_ssubsat_i32:1130; GFX9: ; %bb.0:1131; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1132; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp1133; GFX9-NEXT: s_setpc_b64 s[30:31]1134;1135; GFX10PLUS-LABEL: v_ssubsat_i32:1136; GFX10PLUS: ; %bb.0:1137; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1138; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v1 clamp1139; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1140 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)1141 ret i32 %result1142}1143 1144define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {1145; GFX6-LABEL: s_ssubsat_i32:1146; GFX6: ; %bb.0:1147; GFX6-NEXT: s_max_i32 s2, s0, -11148; GFX6-NEXT: s_add_i32 s2, s2, 0x800000011149; GFX6-NEXT: s_min_i32 s3, s0, -11150; GFX6-NEXT: s_add_i32 s3, s3, 0x800000001151; GFX6-NEXT: s_max_i32 s1, s2, s11152; GFX6-NEXT: s_min_i32 s1, s1, s31153; GFX6-NEXT: s_sub_i32 s0, s0, s11154; GFX6-NEXT: ; return to shader part epilog1155;1156; GFX8-LABEL: s_ssubsat_i32:1157; GFX8: ; %bb.0:1158; GFX8-NEXT: s_max_i32 s2, s0, -11159; GFX8-NEXT: s_add_i32 s2, s2, 0x800000011160; GFX8-NEXT: s_min_i32 s3, s0, -11161; GFX8-NEXT: s_add_i32 s3, s3, 0x800000001162; GFX8-NEXT: s_max_i32 s1, s2, s11163; GFX8-NEXT: s_min_i32 s1, s1, s31164; GFX8-NEXT: s_sub_i32 s0, s0, s11165; GFX8-NEXT: ; return to shader part epilog1166;1167; GFX9-LABEL: s_ssubsat_i32:1168; GFX9: ; %bb.0:1169; GFX9-NEXT: v_mov_b32_e32 v0, s11170; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1171; GFX9-NEXT: v_readfirstlane_b32 s0, v01172; GFX9-NEXT: ; return to shader part epilog1173;1174; GFX10PLUS-LABEL: s_ssubsat_i32:1175; GFX10PLUS: ; %bb.0:1176; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s1 clamp1177; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01178; GFX10PLUS-NEXT: ; return to shader part epilog1179 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)1180 ret i32 %result1181}1182 1183define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {1184; GFX6-LABEL: ssubsat_i32_sv:1185; GFX6: ; %bb.0:1186; GFX6-NEXT: s_max_i32 s1, s0, -11187; GFX6-NEXT: s_add_i32 s1, s1, 0x800000011188; GFX6-NEXT: s_min_i32 s2, s0, -11189; GFX6-NEXT: s_add_i32 s2, s2, 0x800000001190; GFX6-NEXT: v_max_i32_e32 v0, s1, v01191; GFX6-NEXT: v_min_i32_e32 v0, s2, v01192; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v01193; GFX6-NEXT: ; return to shader part epilog1194;1195; GFX8-LABEL: ssubsat_i32_sv:1196; GFX8: ; %bb.0:1197; GFX8-NEXT: s_max_i32 s1, s0, -11198; GFX8-NEXT: s_add_i32 s1, s1, 0x800000011199; GFX8-NEXT: s_min_i32 s2, s0, -11200; GFX8-NEXT: s_add_i32 s2, s2, 0x800000001201; GFX8-NEXT: v_max_i32_e32 v0, s1, v01202; GFX8-NEXT: v_min_i32_e32 v0, s2, v01203; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v01204; GFX8-NEXT: ; return to shader part epilog1205;1206; GFX9-LABEL: ssubsat_i32_sv:1207; GFX9: ; %bb.0:1208; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1209; GFX9-NEXT: ; return to shader part epilog1210;1211; GFX10PLUS-LABEL: ssubsat_i32_sv:1212; GFX10PLUS: ; %bb.0:1213; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, v0 clamp1214; GFX10PLUS-NEXT: ; return to shader part epilog1215 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)1216 %cast = bitcast i32 %result to float1217 ret float %cast1218}1219 1220define amdgpu_ps float @ssubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {1221; GFX6-LABEL: ssubsat_i32_vs:1222; GFX6: ; %bb.0:1223; GFX6-NEXT: v_max_i32_e32 v1, -1, v01224; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000001, v11225; GFX6-NEXT: v_min_i32_e32 v2, -1, v01226; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000000, v21227; GFX6-NEXT: v_max_i32_e32 v1, s0, v11228; GFX6-NEXT: v_min_i32_e32 v1, v1, v21229; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11230; GFX6-NEXT: ; return to shader part epilog1231;1232; GFX8-LABEL: ssubsat_i32_vs:1233; GFX8: ; %bb.0:1234; GFX8-NEXT: v_max_i32_e32 v1, -1, v01235; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000001, v11236; GFX8-NEXT: v_min_i32_e32 v2, -1, v01237; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x80000000, v21238; GFX8-NEXT: v_max_i32_e32 v1, s0, v11239; GFX8-NEXT: v_min_i32_e32 v1, v1, v21240; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v11241; GFX8-NEXT: ; return to shader part epilog1242;1243; GFX9-LABEL: ssubsat_i32_vs:1244; GFX9: ; %bb.0:1245; GFX9-NEXT: v_sub_i32 v0, v0, s0 clamp1246; GFX9-NEXT: ; return to shader part epilog1247;1248; GFX10PLUS-LABEL: ssubsat_i32_vs:1249; GFX10PLUS: ; %bb.0:1250; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, s0 clamp1251; GFX10PLUS-NEXT: ; return to shader part epilog1252 %result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)1253 %cast = bitcast i32 %result to float1254 ret float %cast1255}1256 1257define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {1258; GFX6-LABEL: v_ssubsat_v2i32:1259; GFX6: ; %bb.0:1260; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1261; GFX6-NEXT: v_max_i32_e32 v4, -1, v01262; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v41263; GFX6-NEXT: v_min_i32_e32 v5, -1, v01264; GFX6-NEXT: v_bfrev_b32_e32 v6, 11265; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v61266; GFX6-NEXT: v_max_i32_e32 v2, v4, v21267; GFX6-NEXT: v_min_i32_e32 v2, v2, v51268; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v21269; GFX6-NEXT: v_max_i32_e32 v2, -1, v11270; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v21271; GFX6-NEXT: v_min_i32_e32 v4, -1, v11272; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v41273; GFX6-NEXT: v_max_i32_e32 v2, v2, v31274; GFX6-NEXT: v_min_i32_e32 v2, v2, v41275; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v21276; GFX6-NEXT: s_setpc_b64 s[30:31]1277;1278; GFX8-LABEL: v_ssubsat_v2i32:1279; GFX8: ; %bb.0:1280; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1281; GFX8-NEXT: v_max_i32_e32 v4, -1, v01282; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000001, v41283; GFX8-NEXT: v_min_i32_e32 v5, -1, v01284; GFX8-NEXT: v_bfrev_b32_e32 v6, 11285; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v61286; GFX8-NEXT: v_max_i32_e32 v2, v4, v21287; GFX8-NEXT: v_min_i32_e32 v2, v2, v51288; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v21289; GFX8-NEXT: v_max_i32_e32 v2, -1, v11290; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0x80000001, v21291; GFX8-NEXT: v_min_i32_e32 v4, -1, v11292; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000000, v41293; GFX8-NEXT: v_max_i32_e32 v2, v2, v31294; GFX8-NEXT: v_min_i32_e32 v2, v2, v41295; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v21296; GFX8-NEXT: s_setpc_b64 s[30:31]1297;1298; GFX9-LABEL: v_ssubsat_v2i32:1299; GFX9: ; %bb.0:1300; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1301; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp1302; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp1303; GFX9-NEXT: s_setpc_b64 s[30:31]1304;1305; GFX10PLUS-LABEL: v_ssubsat_v2i32:1306; GFX10PLUS: ; %bb.0:1307; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1308; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v2 clamp1309; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v3 clamp1310; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1311 %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1312 ret <2 x i32> %result1313}1314 1315define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {1316; GFX6-LABEL: s_ssubsat_v2i32:1317; GFX6: ; %bb.0:1318; GFX6-NEXT: s_max_i32 s4, s0, -11319; GFX6-NEXT: s_add_i32 s4, s4, 0x800000011320; GFX6-NEXT: s_min_i32 s5, s0, -11321; GFX6-NEXT: s_add_i32 s5, s5, 0x800000001322; GFX6-NEXT: s_max_i32 s2, s4, s21323; GFX6-NEXT: s_min_i32 s2, s2, s51324; GFX6-NEXT: s_sub_i32 s0, s0, s21325; GFX6-NEXT: s_max_i32 s2, s1, -11326; GFX6-NEXT: s_add_i32 s2, s2, 0x800000011327; GFX6-NEXT: s_min_i32 s4, s1, -11328; GFX6-NEXT: s_add_i32 s4, s4, 0x800000001329; GFX6-NEXT: s_max_i32 s2, s2, s31330; GFX6-NEXT: s_min_i32 s2, s2, s41331; GFX6-NEXT: s_sub_i32 s1, s1, s21332; GFX6-NEXT: ; return to shader part epilog1333;1334; GFX8-LABEL: s_ssubsat_v2i32:1335; GFX8: ; %bb.0:1336; GFX8-NEXT: s_max_i32 s4, s0, -11337; GFX8-NEXT: s_add_i32 s4, s4, 0x800000011338; GFX8-NEXT: s_min_i32 s5, s0, -11339; GFX8-NEXT: s_add_i32 s5, s5, 0x800000001340; GFX8-NEXT: s_max_i32 s2, s4, s21341; GFX8-NEXT: s_min_i32 s2, s2, s51342; GFX8-NEXT: s_sub_i32 s0, s0, s21343; GFX8-NEXT: s_max_i32 s2, s1, -11344; GFX8-NEXT: s_add_i32 s2, s2, 0x800000011345; GFX8-NEXT: s_min_i32 s4, s1, -11346; GFX8-NEXT: s_add_i32 s4, s4, 0x800000001347; GFX8-NEXT: s_max_i32 s2, s2, s31348; GFX8-NEXT: s_min_i32 s2, s2, s41349; GFX8-NEXT: s_sub_i32 s1, s1, s21350; GFX8-NEXT: ; return to shader part epilog1351;1352; GFX9-LABEL: s_ssubsat_v2i32:1353; GFX9: ; %bb.0:1354; GFX9-NEXT: v_mov_b32_e32 v0, s21355; GFX9-NEXT: v_mov_b32_e32 v1, s31356; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1357; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp1358; GFX9-NEXT: v_readfirstlane_b32 s0, v01359; GFX9-NEXT: v_readfirstlane_b32 s1, v11360; GFX9-NEXT: ; return to shader part epilog1361;1362; GFX10PLUS-LABEL: s_ssubsat_v2i32:1363; GFX10PLUS: ; %bb.0:1364; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s2 clamp1365; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s3 clamp1366; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01367; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11368; GFX10PLUS-NEXT: ; return to shader part epilog1369 %result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1370 ret <2 x i32> %result1371}1372 1373define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {1374; GFX6-LABEL: v_ssubsat_v3i32:1375; GFX6: ; %bb.0:1376; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1377; GFX6-NEXT: v_max_i32_e32 v6, -1, v01378; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000001, v61379; GFX6-NEXT: v_min_i32_e32 v8, -1, v01380; GFX6-NEXT: v_bfrev_b32_e32 v9, 11381; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v91382; GFX6-NEXT: v_max_i32_e32 v3, v6, v31383; GFX6-NEXT: v_min_i32_e32 v3, v3, v81384; GFX6-NEXT: v_mov_b32_e32 v7, 0x800000011385; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v31386; GFX6-NEXT: v_max_i32_e32 v3, -1, v11387; GFX6-NEXT: v_add_i32_e32 v3, vcc, v3, v71388; GFX6-NEXT: v_min_i32_e32 v6, -1, v11389; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v91390; GFX6-NEXT: v_max_i32_e32 v3, v3, v41391; GFX6-NEXT: v_min_i32_e32 v3, v3, v61392; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v31393; GFX6-NEXT: v_max_i32_e32 v3, -1, v21394; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000001, v31395; GFX6-NEXT: v_min_i32_e32 v4, -1, v21396; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v41397; GFX6-NEXT: v_max_i32_e32 v3, v3, v51398; GFX6-NEXT: v_min_i32_e32 v3, v3, v41399; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v31400; GFX6-NEXT: s_setpc_b64 s[30:31]1401;1402; GFX8-LABEL: v_ssubsat_v3i32:1403; GFX8: ; %bb.0:1404; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1405; GFX8-NEXT: v_max_i32_e32 v6, -1, v01406; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000001, v61407; GFX8-NEXT: v_min_i32_e32 v8, -1, v01408; GFX8-NEXT: v_bfrev_b32_e32 v9, 11409; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v91410; GFX8-NEXT: v_max_i32_e32 v3, v6, v31411; GFX8-NEXT: v_min_i32_e32 v3, v3, v81412; GFX8-NEXT: v_mov_b32_e32 v7, 0x800000011413; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v31414; GFX8-NEXT: v_max_i32_e32 v3, -1, v11415; GFX8-NEXT: v_add_u32_e32 v3, vcc, v3, v71416; GFX8-NEXT: v_min_i32_e32 v6, -1, v11417; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v91418; GFX8-NEXT: v_max_i32_e32 v3, v3, v41419; GFX8-NEXT: v_min_i32_e32 v3, v3, v61420; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v31421; GFX8-NEXT: v_max_i32_e32 v3, -1, v21422; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000001, v31423; GFX8-NEXT: v_min_i32_e32 v4, -1, v21424; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000000, v41425; GFX8-NEXT: v_max_i32_e32 v3, v3, v51426; GFX8-NEXT: v_min_i32_e32 v3, v3, v41427; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v31428; GFX8-NEXT: s_setpc_b64 s[30:31]1429;1430; GFX9-LABEL: v_ssubsat_v3i32:1431; GFX9: ; %bb.0:1432; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1433; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp1434; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp1435; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp1436; GFX9-NEXT: s_setpc_b64 s[30:31]1437;1438; GFX10PLUS-LABEL: v_ssubsat_v3i32:1439; GFX10PLUS: ; %bb.0:1440; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1441; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v3 clamp1442; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v4 clamp1443; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v5 clamp1444; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1445 %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1446 ret <3 x i32> %result1447}1448 1449define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {1450; GFX6-LABEL: s_ssubsat_v3i32:1451; GFX6: ; %bb.0:1452; GFX6-NEXT: s_max_i32 s6, s0, -11453; GFX6-NEXT: s_add_i32 s6, s6, 0x800000011454; GFX6-NEXT: s_min_i32 s7, s0, -11455; GFX6-NEXT: s_add_i32 s7, s7, 0x800000001456; GFX6-NEXT: s_max_i32 s3, s6, s31457; GFX6-NEXT: s_min_i32 s3, s3, s71458; GFX6-NEXT: s_sub_i32 s0, s0, s31459; GFX6-NEXT: s_max_i32 s3, s1, -11460; GFX6-NEXT: s_add_i32 s3, s3, 0x800000011461; GFX6-NEXT: s_min_i32 s6, s1, -11462; GFX6-NEXT: s_add_i32 s6, s6, 0x800000001463; GFX6-NEXT: s_max_i32 s3, s3, s41464; GFX6-NEXT: s_min_i32 s3, s3, s61465; GFX6-NEXT: s_sub_i32 s1, s1, s31466; GFX6-NEXT: s_max_i32 s3, s2, -11467; GFX6-NEXT: s_add_i32 s3, s3, 0x800000011468; GFX6-NEXT: s_min_i32 s4, s2, -11469; GFX6-NEXT: s_add_i32 s4, s4, 0x800000001470; GFX6-NEXT: s_max_i32 s3, s3, s51471; GFX6-NEXT: s_min_i32 s3, s3, s41472; GFX6-NEXT: s_sub_i32 s2, s2, s31473; GFX6-NEXT: ; return to shader part epilog1474;1475; GFX8-LABEL: s_ssubsat_v3i32:1476; GFX8: ; %bb.0:1477; GFX8-NEXT: s_max_i32 s6, s0, -11478; GFX8-NEXT: s_add_i32 s6, s6, 0x800000011479; GFX8-NEXT: s_min_i32 s7, s0, -11480; GFX8-NEXT: s_add_i32 s7, s7, 0x800000001481; GFX8-NEXT: s_max_i32 s3, s6, s31482; GFX8-NEXT: s_min_i32 s3, s3, s71483; GFX8-NEXT: s_sub_i32 s0, s0, s31484; GFX8-NEXT: s_max_i32 s3, s1, -11485; GFX8-NEXT: s_add_i32 s3, s3, 0x800000011486; GFX8-NEXT: s_min_i32 s6, s1, -11487; GFX8-NEXT: s_add_i32 s6, s6, 0x800000001488; GFX8-NEXT: s_max_i32 s3, s3, s41489; GFX8-NEXT: s_min_i32 s3, s3, s61490; GFX8-NEXT: s_sub_i32 s1, s1, s31491; GFX8-NEXT: s_max_i32 s3, s2, -11492; GFX8-NEXT: s_add_i32 s3, s3, 0x800000011493; GFX8-NEXT: s_min_i32 s4, s2, -11494; GFX8-NEXT: s_add_i32 s4, s4, 0x800000001495; GFX8-NEXT: s_max_i32 s3, s3, s51496; GFX8-NEXT: s_min_i32 s3, s3, s41497; GFX8-NEXT: s_sub_i32 s2, s2, s31498; GFX8-NEXT: ; return to shader part epilog1499;1500; GFX9-LABEL: s_ssubsat_v3i32:1501; GFX9: ; %bb.0:1502; GFX9-NEXT: v_mov_b32_e32 v0, s31503; GFX9-NEXT: v_mov_b32_e32 v1, s41504; GFX9-NEXT: v_mov_b32_e32 v2, s51505; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1506; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp1507; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp1508; GFX9-NEXT: v_readfirstlane_b32 s0, v01509; GFX9-NEXT: v_readfirstlane_b32 s1, v11510; GFX9-NEXT: v_readfirstlane_b32 s2, v21511; GFX9-NEXT: ; return to shader part epilog1512;1513; GFX10PLUS-LABEL: s_ssubsat_v3i32:1514; GFX10PLUS: ; %bb.0:1515; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s3 clamp1516; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s4 clamp1517; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s5 clamp1518; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01519; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11520; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21521; GFX10PLUS-NEXT: ; return to shader part epilog1522 %result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1523 ret <3 x i32> %result1524}1525 1526define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {1527; GFX6-LABEL: v_ssubsat_v4i32:1528; GFX6: ; %bb.0:1529; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1530; GFX6-NEXT: v_max_i32_e32 v8, -1, v01531; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v81532; GFX6-NEXT: v_min_i32_e32 v10, -1, v01533; GFX6-NEXT: v_bfrev_b32_e32 v11, 11534; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v111535; GFX6-NEXT: v_max_i32_e32 v4, v8, v41536; GFX6-NEXT: v_min_i32_e32 v4, v4, v101537; GFX6-NEXT: v_mov_b32_e32 v9, 0x800000011538; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v41539; GFX6-NEXT: v_max_i32_e32 v4, -1, v11540; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v91541; GFX6-NEXT: v_min_i32_e32 v8, -1, v11542; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v111543; GFX6-NEXT: v_max_i32_e32 v4, v4, v51544; GFX6-NEXT: v_min_i32_e32 v4, v4, v81545; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v41546; GFX6-NEXT: v_max_i32_e32 v4, -1, v21547; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v91548; GFX6-NEXT: v_min_i32_e32 v5, -1, v21549; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v111550; GFX6-NEXT: v_max_i32_e32 v4, v4, v61551; GFX6-NEXT: v_min_i32_e32 v4, v4, v51552; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v41553; GFX6-NEXT: v_max_i32_e32 v4, -1, v31554; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v41555; GFX6-NEXT: v_min_i32_e32 v5, -1, v31556; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000000, v51557; GFX6-NEXT: v_max_i32_e32 v4, v4, v71558; GFX6-NEXT: v_min_i32_e32 v4, v4, v51559; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v41560; GFX6-NEXT: s_setpc_b64 s[30:31]1561;1562; GFX8-LABEL: v_ssubsat_v4i32:1563; GFX8: ; %bb.0:1564; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1565; GFX8-NEXT: v_max_i32_e32 v8, -1, v01566; GFX8-NEXT: v_add_u32_e32 v8, vcc, 0x80000001, v81567; GFX8-NEXT: v_min_i32_e32 v10, -1, v01568; GFX8-NEXT: v_bfrev_b32_e32 v11, 11569; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v111570; GFX8-NEXT: v_max_i32_e32 v4, v8, v41571; GFX8-NEXT: v_min_i32_e32 v4, v4, v101572; GFX8-NEXT: v_mov_b32_e32 v9, 0x800000011573; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v41574; GFX8-NEXT: v_max_i32_e32 v4, -1, v11575; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v91576; GFX8-NEXT: v_min_i32_e32 v8, -1, v11577; GFX8-NEXT: v_add_u32_e32 v8, vcc, v8, v111578; GFX8-NEXT: v_max_i32_e32 v4, v4, v51579; GFX8-NEXT: v_min_i32_e32 v4, v4, v81580; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v41581; GFX8-NEXT: v_max_i32_e32 v4, -1, v21582; GFX8-NEXT: v_add_u32_e32 v4, vcc, v4, v91583; GFX8-NEXT: v_min_i32_e32 v5, -1, v21584; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v111585; GFX8-NEXT: v_max_i32_e32 v4, v4, v61586; GFX8-NEXT: v_min_i32_e32 v4, v4, v51587; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v41588; GFX8-NEXT: v_max_i32_e32 v4, -1, v31589; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0x80000001, v41590; GFX8-NEXT: v_min_i32_e32 v5, -1, v31591; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000000, v51592; GFX8-NEXT: v_max_i32_e32 v4, v4, v71593; GFX8-NEXT: v_min_i32_e32 v4, v4, v51594; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v41595; GFX8-NEXT: s_setpc_b64 s[30:31]1596;1597; GFX9-LABEL: v_ssubsat_v4i32:1598; GFX9: ; %bb.0:1599; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1600; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp1601; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp1602; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp1603; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp1604; GFX9-NEXT: s_setpc_b64 s[30:31]1605;1606; GFX10PLUS-LABEL: v_ssubsat_v4i32:1607; GFX10PLUS: ; %bb.0:1608; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1609; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v4 clamp1610; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v5 clamp1611; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v6 clamp1612; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v7 clamp1613; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1614 %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1615 ret <4 x i32> %result1616}1617 1618define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {1619; GFX6-LABEL: s_ssubsat_v4i32:1620; GFX6: ; %bb.0:1621; GFX6-NEXT: s_max_i32 s8, s0, -11622; GFX6-NEXT: s_add_i32 s8, s8, 0x800000011623; GFX6-NEXT: s_min_i32 s9, s0, -11624; GFX6-NEXT: s_add_i32 s9, s9, 0x800000001625; GFX6-NEXT: s_max_i32 s4, s8, s41626; GFX6-NEXT: s_min_i32 s4, s4, s91627; GFX6-NEXT: s_sub_i32 s0, s0, s41628; GFX6-NEXT: s_max_i32 s4, s1, -11629; GFX6-NEXT: s_add_i32 s4, s4, 0x800000011630; GFX6-NEXT: s_min_i32 s8, s1, -11631; GFX6-NEXT: s_add_i32 s8, s8, 0x800000001632; GFX6-NEXT: s_max_i32 s4, s4, s51633; GFX6-NEXT: s_min_i32 s4, s4, s81634; GFX6-NEXT: s_sub_i32 s1, s1, s41635; GFX6-NEXT: s_max_i32 s4, s2, -11636; GFX6-NEXT: s_add_i32 s4, s4, 0x800000011637; GFX6-NEXT: s_min_i32 s5, s2, -11638; GFX6-NEXT: s_add_i32 s5, s5, 0x800000001639; GFX6-NEXT: s_max_i32 s4, s4, s61640; GFX6-NEXT: s_min_i32 s4, s4, s51641; GFX6-NEXT: s_sub_i32 s2, s2, s41642; GFX6-NEXT: s_max_i32 s4, s3, -11643; GFX6-NEXT: s_add_i32 s4, s4, 0x800000011644; GFX6-NEXT: s_min_i32 s5, s3, -11645; GFX6-NEXT: s_add_i32 s5, s5, 0x800000001646; GFX6-NEXT: s_max_i32 s4, s4, s71647; GFX6-NEXT: s_min_i32 s4, s4, s51648; GFX6-NEXT: s_sub_i32 s3, s3, s41649; GFX6-NEXT: ; return to shader part epilog1650;1651; GFX8-LABEL: s_ssubsat_v4i32:1652; GFX8: ; %bb.0:1653; GFX8-NEXT: s_max_i32 s8, s0, -11654; GFX8-NEXT: s_add_i32 s8, s8, 0x800000011655; GFX8-NEXT: s_min_i32 s9, s0, -11656; GFX8-NEXT: s_add_i32 s9, s9, 0x800000001657; GFX8-NEXT: s_max_i32 s4, s8, s41658; GFX8-NEXT: s_min_i32 s4, s4, s91659; GFX8-NEXT: s_sub_i32 s0, s0, s41660; GFX8-NEXT: s_max_i32 s4, s1, -11661; GFX8-NEXT: s_add_i32 s4, s4, 0x800000011662; GFX8-NEXT: s_min_i32 s8, s1, -11663; GFX8-NEXT: s_add_i32 s8, s8, 0x800000001664; GFX8-NEXT: s_max_i32 s4, s4, s51665; GFX8-NEXT: s_min_i32 s4, s4, s81666; GFX8-NEXT: s_sub_i32 s1, s1, s41667; GFX8-NEXT: s_max_i32 s4, s2, -11668; GFX8-NEXT: s_add_i32 s4, s4, 0x800000011669; GFX8-NEXT: s_min_i32 s5, s2, -11670; GFX8-NEXT: s_add_i32 s5, s5, 0x800000001671; GFX8-NEXT: s_max_i32 s4, s4, s61672; GFX8-NEXT: s_min_i32 s4, s4, s51673; GFX8-NEXT: s_sub_i32 s2, s2, s41674; GFX8-NEXT: s_max_i32 s4, s3, -11675; GFX8-NEXT: s_add_i32 s4, s4, 0x800000011676; GFX8-NEXT: s_min_i32 s5, s3, -11677; GFX8-NEXT: s_add_i32 s5, s5, 0x800000001678; GFX8-NEXT: s_max_i32 s4, s4, s71679; GFX8-NEXT: s_min_i32 s4, s4, s51680; GFX8-NEXT: s_sub_i32 s3, s3, s41681; GFX8-NEXT: ; return to shader part epilog1682;1683; GFX9-LABEL: s_ssubsat_v4i32:1684; GFX9: ; %bb.0:1685; GFX9-NEXT: v_mov_b32_e32 v0, s41686; GFX9-NEXT: v_mov_b32_e32 v1, s51687; GFX9-NEXT: v_mov_b32_e32 v2, s61688; GFX9-NEXT: v_mov_b32_e32 v3, s71689; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1690; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp1691; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp1692; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp1693; GFX9-NEXT: v_readfirstlane_b32 s0, v01694; GFX9-NEXT: v_readfirstlane_b32 s1, v11695; GFX9-NEXT: v_readfirstlane_b32 s2, v21696; GFX9-NEXT: v_readfirstlane_b32 s3, v31697; GFX9-NEXT: ; return to shader part epilog1698;1699; GFX10PLUS-LABEL: s_ssubsat_v4i32:1700; GFX10PLUS: ; %bb.0:1701; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s4 clamp1702; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s5 clamp1703; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s6 clamp1704; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s7 clamp1705; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01706; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11707; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21708; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v31709; GFX10PLUS-NEXT: ; return to shader part epilog1710 %result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1711 ret <4 x i32> %result1712}1713 1714define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {1715; GFX6-LABEL: v_ssubsat_v5i32:1716; GFX6: ; %bb.0:1717; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1718; GFX6-NEXT: v_max_i32_e32 v10, -1, v01719; GFX6-NEXT: v_add_i32_e32 v10, vcc, 0x80000001, v101720; GFX6-NEXT: v_min_i32_e32 v12, -1, v01721; GFX6-NEXT: v_bfrev_b32_e32 v13, 11722; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v131723; GFX6-NEXT: v_max_i32_e32 v5, v10, v51724; GFX6-NEXT: v_min_i32_e32 v5, v5, v121725; GFX6-NEXT: v_mov_b32_e32 v11, 0x800000011726; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v51727; GFX6-NEXT: v_max_i32_e32 v5, -1, v11728; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v111729; GFX6-NEXT: v_min_i32_e32 v10, -1, v11730; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v131731; GFX6-NEXT: v_max_i32_e32 v5, v5, v61732; GFX6-NEXT: v_min_i32_e32 v5, v5, v101733; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v51734; GFX6-NEXT: v_max_i32_e32 v5, -1, v21735; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v111736; GFX6-NEXT: v_min_i32_e32 v6, -1, v21737; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v131738; GFX6-NEXT: v_max_i32_e32 v5, v5, v71739; GFX6-NEXT: v_min_i32_e32 v5, v5, v61740; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v51741; GFX6-NEXT: v_max_i32_e32 v5, -1, v31742; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v111743; GFX6-NEXT: v_min_i32_e32 v6, -1, v31744; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v131745; GFX6-NEXT: v_max_i32_e32 v5, v5, v81746; GFX6-NEXT: v_min_i32_e32 v5, v5, v61747; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v51748; GFX6-NEXT: v_max_i32_e32 v5, -1, v41749; GFX6-NEXT: v_add_i32_e32 v5, vcc, 0x80000001, v51750; GFX6-NEXT: v_min_i32_e32 v6, -1, v41751; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0x80000000, v61752; GFX6-NEXT: v_max_i32_e32 v5, v5, v91753; GFX6-NEXT: v_min_i32_e32 v5, v5, v61754; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v51755; GFX6-NEXT: s_setpc_b64 s[30:31]1756;1757; GFX8-LABEL: v_ssubsat_v5i32:1758; GFX8: ; %bb.0:1759; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1760; GFX8-NEXT: v_max_i32_e32 v10, -1, v01761; GFX8-NEXT: v_add_u32_e32 v10, vcc, 0x80000001, v101762; GFX8-NEXT: v_min_i32_e32 v12, -1, v01763; GFX8-NEXT: v_bfrev_b32_e32 v13, 11764; GFX8-NEXT: v_add_u32_e32 v12, vcc, v12, v131765; GFX8-NEXT: v_max_i32_e32 v5, v10, v51766; GFX8-NEXT: v_min_i32_e32 v5, v5, v121767; GFX8-NEXT: v_mov_b32_e32 v11, 0x800000011768; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v51769; GFX8-NEXT: v_max_i32_e32 v5, -1, v11770; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v111771; GFX8-NEXT: v_min_i32_e32 v10, -1, v11772; GFX8-NEXT: v_add_u32_e32 v10, vcc, v10, v131773; GFX8-NEXT: v_max_i32_e32 v5, v5, v61774; GFX8-NEXT: v_min_i32_e32 v5, v5, v101775; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v51776; GFX8-NEXT: v_max_i32_e32 v5, -1, v21777; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v111778; GFX8-NEXT: v_min_i32_e32 v6, -1, v21779; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v131780; GFX8-NEXT: v_max_i32_e32 v5, v5, v71781; GFX8-NEXT: v_min_i32_e32 v5, v5, v61782; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v51783; GFX8-NEXT: v_max_i32_e32 v5, -1, v31784; GFX8-NEXT: v_add_u32_e32 v5, vcc, v5, v111785; GFX8-NEXT: v_min_i32_e32 v6, -1, v31786; GFX8-NEXT: v_add_u32_e32 v6, vcc, v6, v131787; GFX8-NEXT: v_max_i32_e32 v5, v5, v81788; GFX8-NEXT: v_min_i32_e32 v5, v5, v61789; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v51790; GFX8-NEXT: v_max_i32_e32 v5, -1, v41791; GFX8-NEXT: v_add_u32_e32 v5, vcc, 0x80000001, v51792; GFX8-NEXT: v_min_i32_e32 v6, -1, v41793; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0x80000000, v61794; GFX8-NEXT: v_max_i32_e32 v5, v5, v91795; GFX8-NEXT: v_min_i32_e32 v5, v5, v61796; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v51797; GFX8-NEXT: s_setpc_b64 s[30:31]1798;1799; GFX9-LABEL: v_ssubsat_v5i32:1800; GFX9: ; %bb.0:1801; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1802; GFX9-NEXT: v_sub_i32 v0, v0, v5 clamp1803; GFX9-NEXT: v_sub_i32 v1, v1, v6 clamp1804; GFX9-NEXT: v_sub_i32 v2, v2, v7 clamp1805; GFX9-NEXT: v_sub_i32 v3, v3, v8 clamp1806; GFX9-NEXT: v_sub_i32 v4, v4, v9 clamp1807; GFX9-NEXT: s_setpc_b64 s[30:31]1808;1809; GFX10PLUS-LABEL: v_ssubsat_v5i32:1810; GFX10PLUS: ; %bb.0:1811; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1812; GFX10PLUS-NEXT: v_sub_nc_i32 v0, v0, v5 clamp1813; GFX10PLUS-NEXT: v_sub_nc_i32 v1, v1, v6 clamp1814; GFX10PLUS-NEXT: v_sub_nc_i32 v2, v2, v7 clamp1815; GFX10PLUS-NEXT: v_sub_nc_i32 v3, v3, v8 clamp1816; GFX10PLUS-NEXT: v_sub_nc_i32 v4, v4, v9 clamp1817; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1818 %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1819 ret <5 x i32> %result1820}1821 1822define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {1823; GFX6-LABEL: s_ssubsat_v5i32:1824; GFX6: ; %bb.0:1825; GFX6-NEXT: s_max_i32 s10, s0, -11826; GFX6-NEXT: s_add_i32 s10, s10, 0x800000011827; GFX6-NEXT: s_min_i32 s11, s0, -11828; GFX6-NEXT: s_add_i32 s11, s11, 0x800000001829; GFX6-NEXT: s_max_i32 s5, s10, s51830; GFX6-NEXT: s_min_i32 s5, s5, s111831; GFX6-NEXT: s_sub_i32 s0, s0, s51832; GFX6-NEXT: s_max_i32 s5, s1, -11833; GFX6-NEXT: s_add_i32 s5, s5, 0x800000011834; GFX6-NEXT: s_min_i32 s10, s1, -11835; GFX6-NEXT: s_add_i32 s10, s10, 0x800000001836; GFX6-NEXT: s_max_i32 s5, s5, s61837; GFX6-NEXT: s_min_i32 s5, s5, s101838; GFX6-NEXT: s_sub_i32 s1, s1, s51839; GFX6-NEXT: s_max_i32 s5, s2, -11840; GFX6-NEXT: s_add_i32 s5, s5, 0x800000011841; GFX6-NEXT: s_min_i32 s6, s2, -11842; GFX6-NEXT: s_add_i32 s6, s6, 0x800000001843; GFX6-NEXT: s_max_i32 s5, s5, s71844; GFX6-NEXT: s_min_i32 s5, s5, s61845; GFX6-NEXT: s_sub_i32 s2, s2, s51846; GFX6-NEXT: s_max_i32 s5, s3, -11847; GFX6-NEXT: s_add_i32 s5, s5, 0x800000011848; GFX6-NEXT: s_min_i32 s6, s3, -11849; GFX6-NEXT: s_add_i32 s6, s6, 0x800000001850; GFX6-NEXT: s_max_i32 s5, s5, s81851; GFX6-NEXT: s_min_i32 s5, s5, s61852; GFX6-NEXT: s_sub_i32 s3, s3, s51853; GFX6-NEXT: s_max_i32 s5, s4, -11854; GFX6-NEXT: s_add_i32 s5, s5, 0x800000011855; GFX6-NEXT: s_min_i32 s6, s4, -11856; GFX6-NEXT: s_add_i32 s6, s6, 0x800000001857; GFX6-NEXT: s_max_i32 s5, s5, s91858; GFX6-NEXT: s_min_i32 s5, s5, s61859; GFX6-NEXT: s_sub_i32 s4, s4, s51860; GFX6-NEXT: ; return to shader part epilog1861;1862; GFX8-LABEL: s_ssubsat_v5i32:1863; GFX8: ; %bb.0:1864; GFX8-NEXT: s_max_i32 s10, s0, -11865; GFX8-NEXT: s_add_i32 s10, s10, 0x800000011866; GFX8-NEXT: s_min_i32 s11, s0, -11867; GFX8-NEXT: s_add_i32 s11, s11, 0x800000001868; GFX8-NEXT: s_max_i32 s5, s10, s51869; GFX8-NEXT: s_min_i32 s5, s5, s111870; GFX8-NEXT: s_sub_i32 s0, s0, s51871; GFX8-NEXT: s_max_i32 s5, s1, -11872; GFX8-NEXT: s_add_i32 s5, s5, 0x800000011873; GFX8-NEXT: s_min_i32 s10, s1, -11874; GFX8-NEXT: s_add_i32 s10, s10, 0x800000001875; GFX8-NEXT: s_max_i32 s5, s5, s61876; GFX8-NEXT: s_min_i32 s5, s5, s101877; GFX8-NEXT: s_sub_i32 s1, s1, s51878; GFX8-NEXT: s_max_i32 s5, s2, -11879; GFX8-NEXT: s_add_i32 s5, s5, 0x800000011880; GFX8-NEXT: s_min_i32 s6, s2, -11881; GFX8-NEXT: s_add_i32 s6, s6, 0x800000001882; GFX8-NEXT: s_max_i32 s5, s5, s71883; GFX8-NEXT: s_min_i32 s5, s5, s61884; GFX8-NEXT: s_sub_i32 s2, s2, s51885; GFX8-NEXT: s_max_i32 s5, s3, -11886; GFX8-NEXT: s_add_i32 s5, s5, 0x800000011887; GFX8-NEXT: s_min_i32 s6, s3, -11888; GFX8-NEXT: s_add_i32 s6, s6, 0x800000001889; GFX8-NEXT: s_max_i32 s5, s5, s81890; GFX8-NEXT: s_min_i32 s5, s5, s61891; GFX8-NEXT: s_sub_i32 s3, s3, s51892; GFX8-NEXT: s_max_i32 s5, s4, -11893; GFX8-NEXT: s_add_i32 s5, s5, 0x800000011894; GFX8-NEXT: s_min_i32 s6, s4, -11895; GFX8-NEXT: s_add_i32 s6, s6, 0x800000001896; GFX8-NEXT: s_max_i32 s5, s5, s91897; GFX8-NEXT: s_min_i32 s5, s5, s61898; GFX8-NEXT: s_sub_i32 s4, s4, s51899; GFX8-NEXT: ; return to shader part epilog1900;1901; GFX9-LABEL: s_ssubsat_v5i32:1902; GFX9: ; %bb.0:1903; GFX9-NEXT: v_mov_b32_e32 v0, s51904; GFX9-NEXT: v_mov_b32_e32 v1, s61905; GFX9-NEXT: v_mov_b32_e32 v2, s71906; GFX9-NEXT: v_mov_b32_e32 v3, s81907; GFX9-NEXT: v_mov_b32_e32 v4, s91908; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp1909; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp1910; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp1911; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp1912; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp1913; GFX9-NEXT: v_readfirstlane_b32 s0, v01914; GFX9-NEXT: v_readfirstlane_b32 s1, v11915; GFX9-NEXT: v_readfirstlane_b32 s2, v21916; GFX9-NEXT: v_readfirstlane_b32 s3, v31917; GFX9-NEXT: v_readfirstlane_b32 s4, v41918; GFX9-NEXT: ; return to shader part epilog1919;1920; GFX10PLUS-LABEL: s_ssubsat_v5i32:1921; GFX10PLUS: ; %bb.0:1922; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s5 clamp1923; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s6 clamp1924; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s7 clamp1925; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s8 clamp1926; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s9 clamp1927; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01928; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11929; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21930; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v31931; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v41932; GFX10PLUS-NEXT: ; return to shader part epilog1933 %result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1934 ret <5 x i32> %result1935}1936 1937define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {1938; GFX6-LABEL: v_ssubsat_v16i32:1939; GFX6: ; %bb.0:1940; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1941; GFX6-NEXT: v_max_i32_e32 v32, -1, v01942; GFX6-NEXT: v_mov_b32_e32 v31, 0x800000011943; GFX6-NEXT: v_add_i32_e32 v32, vcc, v32, v311944; GFX6-NEXT: v_max_i32_e32 v32, v32, v161945; GFX6-NEXT: v_min_i32_e32 v33, -1, v01946; GFX6-NEXT: v_bfrev_b32_e32 v16, 11947; GFX6-NEXT: v_add_i32_e32 v33, vcc, v33, v161948; GFX6-NEXT: v_min_i32_e32 v32, v32, v331949; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v321950; GFX6-NEXT: v_max_i32_e32 v32, -1, v11951; GFX6-NEXT: v_add_i32_e32 v32, vcc, v32, v311952; GFX6-NEXT: v_max_i32_e32 v17, v32, v171953; GFX6-NEXT: v_min_i32_e32 v32, -1, v11954; GFX6-NEXT: v_add_i32_e32 v32, vcc, v32, v161955; GFX6-NEXT: v_min_i32_e32 v17, v17, v321956; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v171957; GFX6-NEXT: v_max_i32_e32 v17, -1, v21958; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311959; GFX6-NEXT: v_max_i32_e32 v17, v17, v181960; GFX6-NEXT: v_min_i32_e32 v18, -1, v21961; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161962; GFX6-NEXT: v_min_i32_e32 v17, v17, v181963; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v171964; GFX6-NEXT: v_max_i32_e32 v17, -1, v31965; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311966; GFX6-NEXT: v_max_i32_e32 v17, v17, v191967; GFX6-NEXT: buffer_load_dword v19, off, s[0:3], s321968; GFX6-NEXT: v_min_i32_e32 v18, -1, v31969; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161970; GFX6-NEXT: v_min_i32_e32 v17, v17, v181971; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v171972; GFX6-NEXT: v_max_i32_e32 v17, -1, v41973; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311974; GFX6-NEXT: v_min_i32_e32 v18, -1, v41975; GFX6-NEXT: v_max_i32_e32 v17, v17, v201976; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161977; GFX6-NEXT: v_min_i32_e32 v17, v17, v181978; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v171979; GFX6-NEXT: v_max_i32_e32 v17, -1, v51980; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311981; GFX6-NEXT: v_min_i32_e32 v18, -1, v51982; GFX6-NEXT: v_max_i32_e32 v17, v17, v211983; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161984; GFX6-NEXT: v_min_i32_e32 v17, v17, v181985; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v171986; GFX6-NEXT: v_max_i32_e32 v17, -1, v61987; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311988; GFX6-NEXT: v_min_i32_e32 v18, -1, v61989; GFX6-NEXT: v_max_i32_e32 v17, v17, v221990; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161991; GFX6-NEXT: v_min_i32_e32 v17, v17, v181992; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v171993; GFX6-NEXT: v_max_i32_e32 v17, -1, v71994; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v311995; GFX6-NEXT: v_min_i32_e32 v18, -1, v71996; GFX6-NEXT: v_max_i32_e32 v17, v17, v231997; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v161998; GFX6-NEXT: v_min_i32_e32 v17, v17, v181999; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v172000; GFX6-NEXT: v_max_i32_e32 v17, -1, v82001; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312002; GFX6-NEXT: v_min_i32_e32 v18, -1, v82003; GFX6-NEXT: v_max_i32_e32 v17, v17, v242004; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162005; GFX6-NEXT: v_min_i32_e32 v17, v17, v182006; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v172007; GFX6-NEXT: v_max_i32_e32 v17, -1, v92008; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312009; GFX6-NEXT: v_min_i32_e32 v18, -1, v92010; GFX6-NEXT: v_max_i32_e32 v17, v17, v252011; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162012; GFX6-NEXT: v_min_i32_e32 v17, v17, v182013; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v172014; GFX6-NEXT: v_max_i32_e32 v17, -1, v102015; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312016; GFX6-NEXT: v_min_i32_e32 v18, -1, v102017; GFX6-NEXT: v_max_i32_e32 v17, v17, v262018; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162019; GFX6-NEXT: v_min_i32_e32 v17, v17, v182020; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v172021; GFX6-NEXT: v_max_i32_e32 v17, -1, v112022; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312023; GFX6-NEXT: v_min_i32_e32 v18, -1, v112024; GFX6-NEXT: v_max_i32_e32 v17, v17, v272025; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162026; GFX6-NEXT: v_min_i32_e32 v17, v17, v182027; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v172028; GFX6-NEXT: v_max_i32_e32 v17, -1, v122029; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312030; GFX6-NEXT: v_min_i32_e32 v18, -1, v122031; GFX6-NEXT: v_max_i32_e32 v17, v17, v282032; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162033; GFX6-NEXT: v_min_i32_e32 v17, v17, v182034; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v172035; GFX6-NEXT: v_max_i32_e32 v17, -1, v132036; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312037; GFX6-NEXT: v_min_i32_e32 v18, -1, v132038; GFX6-NEXT: v_max_i32_e32 v17, v17, v292039; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162040; GFX6-NEXT: v_min_i32_e32 v17, v17, v182041; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v172042; GFX6-NEXT: v_max_i32_e32 v17, -1, v142043; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312044; GFX6-NEXT: v_min_i32_e32 v18, -1, v142045; GFX6-NEXT: v_max_i32_e32 v17, v17, v302046; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v162047; GFX6-NEXT: v_min_i32_e32 v17, v17, v182048; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v172049; GFX6-NEXT: v_max_i32_e32 v17, -1, v152050; GFX6-NEXT: v_add_i32_e32 v17, vcc, v17, v312051; GFX6-NEXT: v_min_i32_e32 v18, -1, v152052; GFX6-NEXT: v_add_i32_e32 v16, vcc, v18, v162053; GFX6-NEXT: s_waitcnt vmcnt(0)2054; GFX6-NEXT: v_max_i32_e32 v17, v17, v192055; GFX6-NEXT: v_min_i32_e32 v16, v17, v162056; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v162057; GFX6-NEXT: s_setpc_b64 s[30:31]2058;2059; GFX8-LABEL: v_ssubsat_v16i32:2060; GFX8: ; %bb.0:2061; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2062; GFX8-NEXT: v_max_i32_e32 v32, -1, v02063; GFX8-NEXT: v_mov_b32_e32 v31, 0x800000012064; GFX8-NEXT: v_add_u32_e32 v32, vcc, v32, v312065; GFX8-NEXT: v_max_i32_e32 v32, v32, v162066; GFX8-NEXT: v_min_i32_e32 v33, -1, v02067; GFX8-NEXT: v_bfrev_b32_e32 v16, 12068; GFX8-NEXT: v_add_u32_e32 v33, vcc, v33, v162069; GFX8-NEXT: v_min_i32_e32 v32, v32, v332070; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v322071; GFX8-NEXT: v_max_i32_e32 v32, -1, v12072; GFX8-NEXT: v_add_u32_e32 v32, vcc, v32, v312073; GFX8-NEXT: v_max_i32_e32 v17, v32, v172074; GFX8-NEXT: v_min_i32_e32 v32, -1, v12075; GFX8-NEXT: v_add_u32_e32 v32, vcc, v32, v162076; GFX8-NEXT: v_min_i32_e32 v17, v17, v322077; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v172078; GFX8-NEXT: v_max_i32_e32 v17, -1, v22079; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312080; GFX8-NEXT: v_max_i32_e32 v17, v17, v182081; GFX8-NEXT: v_min_i32_e32 v18, -1, v22082; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162083; GFX8-NEXT: v_min_i32_e32 v17, v17, v182084; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v172085; GFX8-NEXT: v_max_i32_e32 v17, -1, v32086; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312087; GFX8-NEXT: v_max_i32_e32 v17, v17, v192088; GFX8-NEXT: buffer_load_dword v19, off, s[0:3], s322089; GFX8-NEXT: v_min_i32_e32 v18, -1, v32090; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162091; GFX8-NEXT: v_min_i32_e32 v17, v17, v182092; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v172093; GFX8-NEXT: v_max_i32_e32 v17, -1, v42094; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312095; GFX8-NEXT: v_min_i32_e32 v18, -1, v42096; GFX8-NEXT: v_max_i32_e32 v17, v17, v202097; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162098; GFX8-NEXT: v_min_i32_e32 v17, v17, v182099; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v172100; GFX8-NEXT: v_max_i32_e32 v17, -1, v52101; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312102; GFX8-NEXT: v_min_i32_e32 v18, -1, v52103; GFX8-NEXT: v_max_i32_e32 v17, v17, v212104; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162105; GFX8-NEXT: v_min_i32_e32 v17, v17, v182106; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v172107; GFX8-NEXT: v_max_i32_e32 v17, -1, v62108; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312109; GFX8-NEXT: v_min_i32_e32 v18, -1, v62110; GFX8-NEXT: v_max_i32_e32 v17, v17, v222111; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162112; GFX8-NEXT: v_min_i32_e32 v17, v17, v182113; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v172114; GFX8-NEXT: v_max_i32_e32 v17, -1, v72115; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312116; GFX8-NEXT: v_min_i32_e32 v18, -1, v72117; GFX8-NEXT: v_max_i32_e32 v17, v17, v232118; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162119; GFX8-NEXT: v_min_i32_e32 v17, v17, v182120; GFX8-NEXT: v_sub_u32_e32 v7, vcc, v7, v172121; GFX8-NEXT: v_max_i32_e32 v17, -1, v82122; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312123; GFX8-NEXT: v_min_i32_e32 v18, -1, v82124; GFX8-NEXT: v_max_i32_e32 v17, v17, v242125; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162126; GFX8-NEXT: v_min_i32_e32 v17, v17, v182127; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v8, v172128; GFX8-NEXT: v_max_i32_e32 v17, -1, v92129; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312130; GFX8-NEXT: v_min_i32_e32 v18, -1, v92131; GFX8-NEXT: v_max_i32_e32 v17, v17, v252132; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162133; GFX8-NEXT: v_min_i32_e32 v17, v17, v182134; GFX8-NEXT: v_sub_u32_e32 v9, vcc, v9, v172135; GFX8-NEXT: v_max_i32_e32 v17, -1, v102136; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312137; GFX8-NEXT: v_min_i32_e32 v18, -1, v102138; GFX8-NEXT: v_max_i32_e32 v17, v17, v262139; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162140; GFX8-NEXT: v_min_i32_e32 v17, v17, v182141; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v10, v172142; GFX8-NEXT: v_max_i32_e32 v17, -1, v112143; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312144; GFX8-NEXT: v_min_i32_e32 v18, -1, v112145; GFX8-NEXT: v_max_i32_e32 v17, v17, v272146; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162147; GFX8-NEXT: v_min_i32_e32 v17, v17, v182148; GFX8-NEXT: v_sub_u32_e32 v11, vcc, v11, v172149; GFX8-NEXT: v_max_i32_e32 v17, -1, v122150; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312151; GFX8-NEXT: v_min_i32_e32 v18, -1, v122152; GFX8-NEXT: v_max_i32_e32 v17, v17, v282153; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162154; GFX8-NEXT: v_min_i32_e32 v17, v17, v182155; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v12, v172156; GFX8-NEXT: v_max_i32_e32 v17, -1, v132157; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312158; GFX8-NEXT: v_min_i32_e32 v18, -1, v132159; GFX8-NEXT: v_max_i32_e32 v17, v17, v292160; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162161; GFX8-NEXT: v_min_i32_e32 v17, v17, v182162; GFX8-NEXT: v_sub_u32_e32 v13, vcc, v13, v172163; GFX8-NEXT: v_max_i32_e32 v17, -1, v142164; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312165; GFX8-NEXT: v_min_i32_e32 v18, -1, v142166; GFX8-NEXT: v_max_i32_e32 v17, v17, v302167; GFX8-NEXT: v_add_u32_e32 v18, vcc, v18, v162168; GFX8-NEXT: v_min_i32_e32 v17, v17, v182169; GFX8-NEXT: v_sub_u32_e32 v14, vcc, v14, v172170; GFX8-NEXT: v_max_i32_e32 v17, -1, v152171; GFX8-NEXT: v_add_u32_e32 v17, vcc, v17, v312172; GFX8-NEXT: v_min_i32_e32 v18, -1, v152173; GFX8-NEXT: v_add_u32_e32 v16, vcc, v18, v162174; GFX8-NEXT: s_waitcnt vmcnt(0)2175; GFX8-NEXT: v_max_i32_e32 v17, v17, v192176; GFX8-NEXT: v_min_i32_e32 v16, v17, v162177; GFX8-NEXT: v_sub_u32_e32 v15, vcc, v15, v162178; GFX8-NEXT: s_setpc_b64 s[30:31]2179;2180; GFX9-LABEL: v_ssubsat_v16i32:2181; GFX9: ; %bb.0:2182; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2183; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp2184; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s322185; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp2186; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp2187; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp2188; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp2189; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp2190; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp2191; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp2192; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp2193; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp2194; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp2195; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp2196; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp2197; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp2198; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp2199; GFX9-NEXT: s_waitcnt vmcnt(0)2200; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp2201; GFX9-NEXT: s_setpc_b64 s[30:31]2202;2203; GFX10-LABEL: v_ssubsat_v16i32:2204; GFX10: ; %bb.0:2205; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2206; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s322207; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp2208; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp2209; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp2210; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp2211; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp2212; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp2213; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp2214; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp2215; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp2216; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp2217; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp2218; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp2219; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp2220; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp2221; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp2222; GFX10-NEXT: s_waitcnt vmcnt(0)2223; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp2224; GFX10-NEXT: s_setpc_b64 s[30:31]2225;2226; GFX11-LABEL: v_ssubsat_v16i32:2227; GFX11: ; %bb.0:2228; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2229; GFX11-NEXT: scratch_load_b32 v31, off, s322230; GFX11-NEXT: v_sub_nc_i32 v0, v0, v16 clamp2231; GFX11-NEXT: v_sub_nc_i32 v1, v1, v17 clamp2232; GFX11-NEXT: v_sub_nc_i32 v2, v2, v18 clamp2233; GFX11-NEXT: v_sub_nc_i32 v3, v3, v19 clamp2234; GFX11-NEXT: v_sub_nc_i32 v4, v4, v20 clamp2235; GFX11-NEXT: v_sub_nc_i32 v5, v5, v21 clamp2236; GFX11-NEXT: v_sub_nc_i32 v6, v6, v22 clamp2237; GFX11-NEXT: v_sub_nc_i32 v7, v7, v23 clamp2238; GFX11-NEXT: v_sub_nc_i32 v8, v8, v24 clamp2239; GFX11-NEXT: v_sub_nc_i32 v9, v9, v25 clamp2240; GFX11-NEXT: v_sub_nc_i32 v10, v10, v26 clamp2241; GFX11-NEXT: v_sub_nc_i32 v11, v11, v27 clamp2242; GFX11-NEXT: v_sub_nc_i32 v12, v12, v28 clamp2243; GFX11-NEXT: v_sub_nc_i32 v13, v13, v29 clamp2244; GFX11-NEXT: v_sub_nc_i32 v14, v14, v30 clamp2245; GFX11-NEXT: s_waitcnt vmcnt(0)2246; GFX11-NEXT: v_sub_nc_i32 v15, v15, v31 clamp2247; GFX11-NEXT: s_setpc_b64 s[30:31]2248 %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)2249 ret <16 x i32> %result2250}2251 2252define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {2253; GFX6-LABEL: s_ssubsat_v16i32:2254; GFX6: ; %bb.0:2255; GFX6-NEXT: s_max_i32 s32, s0, -12256; GFX6-NEXT: s_add_i32 s32, s32, 0x800000012257; GFX6-NEXT: s_min_i32 s33, s0, -12258; GFX6-NEXT: s_add_i32 s33, s33, 0x800000002259; GFX6-NEXT: s_max_i32 s16, s32, s162260; GFX6-NEXT: s_min_i32 s16, s16, s332261; GFX6-NEXT: s_sub_i32 s0, s0, s162262; GFX6-NEXT: s_max_i32 s16, s1, -12263; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012264; GFX6-NEXT: s_min_i32 s32, s1, -12265; GFX6-NEXT: s_add_i32 s32, s32, 0x800000002266; GFX6-NEXT: s_max_i32 s16, s16, s172267; GFX6-NEXT: s_min_i32 s16, s16, s322268; GFX6-NEXT: s_sub_i32 s1, s1, s162269; GFX6-NEXT: s_max_i32 s16, s2, -12270; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012271; GFX6-NEXT: s_min_i32 s17, s2, -12272; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002273; GFX6-NEXT: s_max_i32 s16, s16, s182274; GFX6-NEXT: s_min_i32 s16, s16, s172275; GFX6-NEXT: s_sub_i32 s2, s2, s162276; GFX6-NEXT: s_max_i32 s16, s3, -12277; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012278; GFX6-NEXT: s_min_i32 s17, s3, -12279; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002280; GFX6-NEXT: s_max_i32 s16, s16, s192281; GFX6-NEXT: s_min_i32 s16, s16, s172282; GFX6-NEXT: s_sub_i32 s3, s3, s162283; GFX6-NEXT: s_max_i32 s16, s4, -12284; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012285; GFX6-NEXT: s_min_i32 s17, s4, -12286; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002287; GFX6-NEXT: s_max_i32 s16, s16, s202288; GFX6-NEXT: s_min_i32 s16, s16, s172289; GFX6-NEXT: s_sub_i32 s4, s4, s162290; GFX6-NEXT: s_max_i32 s16, s5, -12291; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012292; GFX6-NEXT: s_min_i32 s17, s5, -12293; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002294; GFX6-NEXT: s_max_i32 s16, s16, s212295; GFX6-NEXT: s_min_i32 s16, s16, s172296; GFX6-NEXT: s_sub_i32 s5, s5, s162297; GFX6-NEXT: s_max_i32 s16, s6, -12298; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012299; GFX6-NEXT: s_min_i32 s17, s6, -12300; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002301; GFX6-NEXT: s_max_i32 s16, s16, s222302; GFX6-NEXT: s_min_i32 s16, s16, s172303; GFX6-NEXT: s_sub_i32 s6, s6, s162304; GFX6-NEXT: s_max_i32 s16, s7, -12305; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012306; GFX6-NEXT: s_min_i32 s17, s7, -12307; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002308; GFX6-NEXT: s_max_i32 s16, s16, s232309; GFX6-NEXT: s_min_i32 s16, s16, s172310; GFX6-NEXT: s_sub_i32 s7, s7, s162311; GFX6-NEXT: s_max_i32 s16, s8, -12312; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012313; GFX6-NEXT: s_min_i32 s17, s8, -12314; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002315; GFX6-NEXT: s_max_i32 s16, s16, s242316; GFX6-NEXT: s_min_i32 s16, s16, s172317; GFX6-NEXT: s_sub_i32 s8, s8, s162318; GFX6-NEXT: s_max_i32 s16, s9, -12319; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012320; GFX6-NEXT: s_min_i32 s17, s9, -12321; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002322; GFX6-NEXT: s_max_i32 s16, s16, s252323; GFX6-NEXT: s_min_i32 s16, s16, s172324; GFX6-NEXT: s_sub_i32 s9, s9, s162325; GFX6-NEXT: s_max_i32 s16, s10, -12326; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012327; GFX6-NEXT: s_min_i32 s17, s10, -12328; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002329; GFX6-NEXT: s_max_i32 s16, s16, s262330; GFX6-NEXT: s_min_i32 s16, s16, s172331; GFX6-NEXT: s_sub_i32 s10, s10, s162332; GFX6-NEXT: s_max_i32 s16, s11, -12333; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012334; GFX6-NEXT: s_min_i32 s17, s11, -12335; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002336; GFX6-NEXT: s_max_i32 s16, s16, s272337; GFX6-NEXT: s_min_i32 s16, s16, s172338; GFX6-NEXT: s_sub_i32 s11, s11, s162339; GFX6-NEXT: s_max_i32 s16, s12, -12340; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012341; GFX6-NEXT: s_min_i32 s17, s12, -12342; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002343; GFX6-NEXT: s_max_i32 s16, s16, s282344; GFX6-NEXT: s_min_i32 s16, s16, s172345; GFX6-NEXT: s_sub_i32 s12, s12, s162346; GFX6-NEXT: s_max_i32 s16, s13, -12347; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012348; GFX6-NEXT: s_min_i32 s17, s13, -12349; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002350; GFX6-NEXT: s_max_i32 s16, s16, s292351; GFX6-NEXT: s_min_i32 s16, s16, s172352; GFX6-NEXT: s_sub_i32 s13, s13, s162353; GFX6-NEXT: s_max_i32 s16, s14, -12354; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012355; GFX6-NEXT: s_min_i32 s17, s14, -12356; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002357; GFX6-NEXT: s_max_i32 s16, s16, s302358; GFX6-NEXT: s_min_i32 s16, s16, s172359; GFX6-NEXT: s_sub_i32 s14, s14, s162360; GFX6-NEXT: s_max_i32 s16, s15, -12361; GFX6-NEXT: s_add_i32 s16, s16, 0x800000012362; GFX6-NEXT: s_min_i32 s17, s15, -12363; GFX6-NEXT: s_add_i32 s17, s17, 0x800000002364; GFX6-NEXT: s_max_i32 s16, s16, s312365; GFX6-NEXT: s_min_i32 s16, s16, s172366; GFX6-NEXT: s_sub_i32 s15, s15, s162367; GFX6-NEXT: ; return to shader part epilog2368;2369; GFX8-LABEL: s_ssubsat_v16i32:2370; GFX8: ; %bb.0:2371; GFX8-NEXT: s_max_i32 s32, s0, -12372; GFX8-NEXT: s_add_i32 s32, s32, 0x800000012373; GFX8-NEXT: s_min_i32 s33, s0, -12374; GFX8-NEXT: s_add_i32 s33, s33, 0x800000002375; GFX8-NEXT: s_max_i32 s16, s32, s162376; GFX8-NEXT: s_min_i32 s16, s16, s332377; GFX8-NEXT: s_sub_i32 s0, s0, s162378; GFX8-NEXT: s_max_i32 s16, s1, -12379; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012380; GFX8-NEXT: s_min_i32 s32, s1, -12381; GFX8-NEXT: s_add_i32 s32, s32, 0x800000002382; GFX8-NEXT: s_max_i32 s16, s16, s172383; GFX8-NEXT: s_min_i32 s16, s16, s322384; GFX8-NEXT: s_sub_i32 s1, s1, s162385; GFX8-NEXT: s_max_i32 s16, s2, -12386; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012387; GFX8-NEXT: s_min_i32 s17, s2, -12388; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002389; GFX8-NEXT: s_max_i32 s16, s16, s182390; GFX8-NEXT: s_min_i32 s16, s16, s172391; GFX8-NEXT: s_sub_i32 s2, s2, s162392; GFX8-NEXT: s_max_i32 s16, s3, -12393; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012394; GFX8-NEXT: s_min_i32 s17, s3, -12395; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002396; GFX8-NEXT: s_max_i32 s16, s16, s192397; GFX8-NEXT: s_min_i32 s16, s16, s172398; GFX8-NEXT: s_sub_i32 s3, s3, s162399; GFX8-NEXT: s_max_i32 s16, s4, -12400; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012401; GFX8-NEXT: s_min_i32 s17, s4, -12402; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002403; GFX8-NEXT: s_max_i32 s16, s16, s202404; GFX8-NEXT: s_min_i32 s16, s16, s172405; GFX8-NEXT: s_sub_i32 s4, s4, s162406; GFX8-NEXT: s_max_i32 s16, s5, -12407; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012408; GFX8-NEXT: s_min_i32 s17, s5, -12409; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002410; GFX8-NEXT: s_max_i32 s16, s16, s212411; GFX8-NEXT: s_min_i32 s16, s16, s172412; GFX8-NEXT: s_sub_i32 s5, s5, s162413; GFX8-NEXT: s_max_i32 s16, s6, -12414; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012415; GFX8-NEXT: s_min_i32 s17, s6, -12416; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002417; GFX8-NEXT: s_max_i32 s16, s16, s222418; GFX8-NEXT: s_min_i32 s16, s16, s172419; GFX8-NEXT: s_sub_i32 s6, s6, s162420; GFX8-NEXT: s_max_i32 s16, s7, -12421; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012422; GFX8-NEXT: s_min_i32 s17, s7, -12423; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002424; GFX8-NEXT: s_max_i32 s16, s16, s232425; GFX8-NEXT: s_min_i32 s16, s16, s172426; GFX8-NEXT: s_sub_i32 s7, s7, s162427; GFX8-NEXT: s_max_i32 s16, s8, -12428; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012429; GFX8-NEXT: s_min_i32 s17, s8, -12430; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002431; GFX8-NEXT: s_max_i32 s16, s16, s242432; GFX8-NEXT: s_min_i32 s16, s16, s172433; GFX8-NEXT: s_sub_i32 s8, s8, s162434; GFX8-NEXT: s_max_i32 s16, s9, -12435; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012436; GFX8-NEXT: s_min_i32 s17, s9, -12437; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002438; GFX8-NEXT: s_max_i32 s16, s16, s252439; GFX8-NEXT: s_min_i32 s16, s16, s172440; GFX8-NEXT: s_sub_i32 s9, s9, s162441; GFX8-NEXT: s_max_i32 s16, s10, -12442; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012443; GFX8-NEXT: s_min_i32 s17, s10, -12444; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002445; GFX8-NEXT: s_max_i32 s16, s16, s262446; GFX8-NEXT: s_min_i32 s16, s16, s172447; GFX8-NEXT: s_sub_i32 s10, s10, s162448; GFX8-NEXT: s_max_i32 s16, s11, -12449; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012450; GFX8-NEXT: s_min_i32 s17, s11, -12451; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002452; GFX8-NEXT: s_max_i32 s16, s16, s272453; GFX8-NEXT: s_min_i32 s16, s16, s172454; GFX8-NEXT: s_sub_i32 s11, s11, s162455; GFX8-NEXT: s_max_i32 s16, s12, -12456; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012457; GFX8-NEXT: s_min_i32 s17, s12, -12458; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002459; GFX8-NEXT: s_max_i32 s16, s16, s282460; GFX8-NEXT: s_min_i32 s16, s16, s172461; GFX8-NEXT: s_sub_i32 s12, s12, s162462; GFX8-NEXT: s_max_i32 s16, s13, -12463; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012464; GFX8-NEXT: s_min_i32 s17, s13, -12465; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002466; GFX8-NEXT: s_max_i32 s16, s16, s292467; GFX8-NEXT: s_min_i32 s16, s16, s172468; GFX8-NEXT: s_sub_i32 s13, s13, s162469; GFX8-NEXT: s_max_i32 s16, s14, -12470; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012471; GFX8-NEXT: s_min_i32 s17, s14, -12472; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002473; GFX8-NEXT: s_max_i32 s16, s16, s302474; GFX8-NEXT: s_min_i32 s16, s16, s172475; GFX8-NEXT: s_sub_i32 s14, s14, s162476; GFX8-NEXT: s_max_i32 s16, s15, -12477; GFX8-NEXT: s_add_i32 s16, s16, 0x800000012478; GFX8-NEXT: s_min_i32 s17, s15, -12479; GFX8-NEXT: s_add_i32 s17, s17, 0x800000002480; GFX8-NEXT: s_max_i32 s16, s16, s312481; GFX8-NEXT: s_min_i32 s16, s16, s172482; GFX8-NEXT: s_sub_i32 s15, s15, s162483; GFX8-NEXT: ; return to shader part epilog2484;2485; GFX9-LABEL: s_ssubsat_v16i32:2486; GFX9: ; %bb.0:2487; GFX9-NEXT: v_mov_b32_e32 v0, s162488; GFX9-NEXT: v_mov_b32_e32 v1, s172489; GFX9-NEXT: v_mov_b32_e32 v2, s182490; GFX9-NEXT: v_mov_b32_e32 v3, s192491; GFX9-NEXT: v_mov_b32_e32 v4, s202492; GFX9-NEXT: v_mov_b32_e32 v5, s212493; GFX9-NEXT: v_mov_b32_e32 v6, s222494; GFX9-NEXT: v_mov_b32_e32 v7, s232495; GFX9-NEXT: v_mov_b32_e32 v8, s242496; GFX9-NEXT: v_mov_b32_e32 v9, s252497; GFX9-NEXT: v_mov_b32_e32 v10, s262498; GFX9-NEXT: v_mov_b32_e32 v11, s272499; GFX9-NEXT: v_mov_b32_e32 v12, s282500; GFX9-NEXT: v_mov_b32_e32 v13, s292501; GFX9-NEXT: v_mov_b32_e32 v14, s302502; GFX9-NEXT: v_mov_b32_e32 v15, s312503; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp2504; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp2505; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp2506; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp2507; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp2508; GFX9-NEXT: v_sub_i32 v5, s5, v5 clamp2509; GFX9-NEXT: v_sub_i32 v6, s6, v6 clamp2510; GFX9-NEXT: v_sub_i32 v7, s7, v7 clamp2511; GFX9-NEXT: v_sub_i32 v8, s8, v8 clamp2512; GFX9-NEXT: v_sub_i32 v9, s9, v9 clamp2513; GFX9-NEXT: v_sub_i32 v10, s10, v10 clamp2514; GFX9-NEXT: v_sub_i32 v11, s11, v11 clamp2515; GFX9-NEXT: v_sub_i32 v12, s12, v12 clamp2516; GFX9-NEXT: v_sub_i32 v13, s13, v13 clamp2517; GFX9-NEXT: v_sub_i32 v14, s14, v14 clamp2518; GFX9-NEXT: v_sub_i32 v15, s15, v15 clamp2519; GFX9-NEXT: v_readfirstlane_b32 s0, v02520; GFX9-NEXT: v_readfirstlane_b32 s1, v12521; GFX9-NEXT: v_readfirstlane_b32 s2, v22522; GFX9-NEXT: v_readfirstlane_b32 s3, v32523; GFX9-NEXT: v_readfirstlane_b32 s4, v42524; GFX9-NEXT: v_readfirstlane_b32 s5, v52525; GFX9-NEXT: v_readfirstlane_b32 s6, v62526; GFX9-NEXT: v_readfirstlane_b32 s7, v72527; GFX9-NEXT: v_readfirstlane_b32 s8, v82528; GFX9-NEXT: v_readfirstlane_b32 s9, v92529; GFX9-NEXT: v_readfirstlane_b32 s10, v102530; GFX9-NEXT: v_readfirstlane_b32 s11, v112531; GFX9-NEXT: v_readfirstlane_b32 s12, v122532; GFX9-NEXT: v_readfirstlane_b32 s13, v132533; GFX9-NEXT: v_readfirstlane_b32 s14, v142534; GFX9-NEXT: v_readfirstlane_b32 s15, v152535; GFX9-NEXT: ; return to shader part epilog2536;2537; GFX10PLUS-LABEL: s_ssubsat_v16i32:2538; GFX10PLUS: ; %bb.0:2539; GFX10PLUS-NEXT: v_sub_nc_i32 v0, s0, s16 clamp2540; GFX10PLUS-NEXT: v_sub_nc_i32 v1, s1, s17 clamp2541; GFX10PLUS-NEXT: v_sub_nc_i32 v2, s2, s18 clamp2542; GFX10PLUS-NEXT: v_sub_nc_i32 v3, s3, s19 clamp2543; GFX10PLUS-NEXT: v_sub_nc_i32 v4, s4, s20 clamp2544; GFX10PLUS-NEXT: v_sub_nc_i32 v5, s5, s21 clamp2545; GFX10PLUS-NEXT: v_sub_nc_i32 v6, s6, s22 clamp2546; GFX10PLUS-NEXT: v_sub_nc_i32 v7, s7, s23 clamp2547; GFX10PLUS-NEXT: v_sub_nc_i32 v8, s8, s24 clamp2548; GFX10PLUS-NEXT: v_sub_nc_i32 v9, s9, s25 clamp2549; GFX10PLUS-NEXT: v_sub_nc_i32 v10, s10, s26 clamp2550; GFX10PLUS-NEXT: v_sub_nc_i32 v11, s11, s27 clamp2551; GFX10PLUS-NEXT: v_sub_nc_i32 v12, s12, s28 clamp2552; GFX10PLUS-NEXT: v_sub_nc_i32 v13, s13, s29 clamp2553; GFX10PLUS-NEXT: v_sub_nc_i32 v14, s14, s30 clamp2554; GFX10PLUS-NEXT: v_sub_nc_i32 v15, s15, s31 clamp2555; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02556; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v12557; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v22558; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v32559; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v42560; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v52561; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v62562; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v72563; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v82564; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v92565; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v102566; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v112567; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v122568; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v132569; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v142570; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v152571; GFX10PLUS-NEXT: ; return to shader part epilog2572 %result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)2573 ret <16 x i32> %result2574}2575 2576define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {2577; GFX6-LABEL: v_ssubsat_i16:2578; GFX6: ; %bb.0:2579; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2580; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02581; GFX6-NEXT: v_max_i32_e32 v2, -1, v02582; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12583; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v22584; GFX6-NEXT: v_min_i32_e32 v3, -1, v02585; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v32586; GFX6-NEXT: v_max_i32_e32 v1, v2, v12587; GFX6-NEXT: v_min_i32_e32 v1, v1, v32588; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v12589; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02590; GFX6-NEXT: s_setpc_b64 s[30:31]2591;2592; GFX8-LABEL: v_ssubsat_i16:2593; GFX8: ; %bb.0:2594; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2595; GFX8-NEXT: v_max_i16_e32 v2, -1, v02596; GFX8-NEXT: v_add_u16_e32 v2, 0x8001, v22597; GFX8-NEXT: v_min_i16_e32 v3, -1, v02598; GFX8-NEXT: v_add_u16_e32 v3, 0x8000, v32599; GFX8-NEXT: v_max_i16_e32 v1, v2, v12600; GFX8-NEXT: v_min_i16_e32 v1, v1, v32601; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12602; GFX8-NEXT: s_setpc_b64 s[30:31]2603;2604; GFX9-LABEL: v_ssubsat_i16:2605; GFX9: ; %bb.0:2606; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2607; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp2608; GFX9-NEXT: s_setpc_b64 s[30:31]2609;2610; GFX10PLUS-LABEL: v_ssubsat_i16:2611; GFX10PLUS: ; %bb.0:2612; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2613; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, v1 clamp2614; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2615 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)2616 ret i16 %result2617}2618 2619define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {2620; GFX6-LABEL: s_ssubsat_i16:2621; GFX6: ; %bb.0:2622; GFX6-NEXT: s_lshl_b32 s0, s0, 162623; GFX6-NEXT: s_max_i32 s2, s0, -12624; GFX6-NEXT: s_lshl_b32 s1, s1, 162625; GFX6-NEXT: s_add_i32 s2, s2, 0x800000012626; GFX6-NEXT: s_min_i32 s3, s0, -12627; GFX6-NEXT: s_add_i32 s3, s3, 0x800000002628; GFX6-NEXT: s_max_i32 s1, s2, s12629; GFX6-NEXT: s_min_i32 s1, s1, s32630; GFX6-NEXT: s_sub_i32 s0, s0, s12631; GFX6-NEXT: s_ashr_i32 s0, s0, 162632; GFX6-NEXT: ; return to shader part epilog2633;2634; GFX8-LABEL: s_ssubsat_i16:2635; GFX8: ; %bb.0:2636; GFX8-NEXT: s_sext_i32_i16 s2, s02637; GFX8-NEXT: s_max_i32 s3, s2, -12638; GFX8-NEXT: s_add_i32 s3, s3, 0x80012639; GFX8-NEXT: s_min_i32 s2, s2, -12640; GFX8-NEXT: s_sext_i32_i16 s3, s32641; GFX8-NEXT: s_sext_i32_i16 s1, s12642; GFX8-NEXT: s_add_i32 s2, s2, 0x80002643; GFX8-NEXT: s_max_i32 s1, s3, s12644; GFX8-NEXT: s_sext_i32_i16 s1, s12645; GFX8-NEXT: s_sext_i32_i16 s2, s22646; GFX8-NEXT: s_min_i32 s1, s1, s22647; GFX8-NEXT: s_sub_i32 s0, s0, s12648; GFX8-NEXT: ; return to shader part epilog2649;2650; GFX9-LABEL: s_ssubsat_i16:2651; GFX9: ; %bb.0:2652; GFX9-NEXT: v_mov_b32_e32 v0, s12653; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp2654; GFX9-NEXT: v_readfirstlane_b32 s0, v02655; GFX9-NEXT: ; return to shader part epilog2656;2657; GFX10PLUS-LABEL: s_ssubsat_i16:2658; GFX10PLUS: ; %bb.0:2659; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, s1 clamp2660; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02661; GFX10PLUS-NEXT: ; return to shader part epilog2662 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)2663 ret i16 %result2664}2665 2666define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {2667; GFX6-LABEL: ssubsat_i16_sv:2668; GFX6: ; %bb.0:2669; GFX6-NEXT: s_lshl_b32 s0, s0, 162670; GFX6-NEXT: s_max_i32 s1, s0, -12671; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02672; GFX6-NEXT: s_add_i32 s1, s1, 0x800000012673; GFX6-NEXT: s_min_i32 s2, s0, -12674; GFX6-NEXT: s_add_i32 s2, s2, 0x800000002675; GFX6-NEXT: v_max_i32_e32 v0, s1, v02676; GFX6-NEXT: v_min_i32_e32 v0, s2, v02677; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v02678; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02679; GFX6-NEXT: ; return to shader part epilog2680;2681; GFX8-LABEL: ssubsat_i16_sv:2682; GFX8: ; %bb.0:2683; GFX8-NEXT: s_sext_i32_i16 s1, s02684; GFX8-NEXT: s_max_i32 s2, s1, -12685; GFX8-NEXT: s_add_i32 s2, s2, 0x80012686; GFX8-NEXT: s_min_i32 s1, s1, -12687; GFX8-NEXT: s_add_i32 s1, s1, 0x80002688; GFX8-NEXT: v_max_i16_e32 v0, s2, v02689; GFX8-NEXT: v_min_i16_e32 v0, s1, v02690; GFX8-NEXT: v_sub_u16_e32 v0, s0, v02691; GFX8-NEXT: ; return to shader part epilog2692;2693; GFX9-LABEL: ssubsat_i16_sv:2694; GFX9: ; %bb.0:2695; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp2696; GFX9-NEXT: ; return to shader part epilog2697;2698; GFX10PLUS-LABEL: ssubsat_i16_sv:2699; GFX10PLUS: ; %bb.0:2700; GFX10PLUS-NEXT: v_sub_nc_i16 v0, s0, v0 clamp2701; GFX10PLUS-NEXT: ; return to shader part epilog2702 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)2703 %cast = bitcast i16 %result to half2704 ret half %cast2705}2706 2707define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {2708; GFX6-LABEL: ssubsat_i16_vs:2709; GFX6: ; %bb.0:2710; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02711; GFX6-NEXT: v_max_i32_e32 v1, -1, v02712; GFX6-NEXT: s_lshl_b32 s0, s0, 162713; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000001, v12714; GFX6-NEXT: v_min_i32_e32 v2, -1, v02715; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000000, v22716; GFX6-NEXT: v_max_i32_e32 v1, s0, v12717; GFX6-NEXT: v_min_i32_e32 v1, v1, v22718; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v12719; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02720; GFX6-NEXT: ; return to shader part epilog2721;2722; GFX8-LABEL: ssubsat_i16_vs:2723; GFX8: ; %bb.0:2724; GFX8-NEXT: v_max_i16_e32 v1, -1, v02725; GFX8-NEXT: v_add_u16_e32 v1, 0x8001, v12726; GFX8-NEXT: v_min_i16_e32 v2, -1, v02727; GFX8-NEXT: v_add_u16_e32 v2, 0x8000, v22728; GFX8-NEXT: v_max_i16_e32 v1, s0, v12729; GFX8-NEXT: v_min_i16_e32 v1, v1, v22730; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12731; GFX8-NEXT: ; return to shader part epilog2732;2733; GFX9-LABEL: ssubsat_i16_vs:2734; GFX9: ; %bb.0:2735; GFX9-NEXT: v_sub_i16 v0, v0, s0 clamp2736; GFX9-NEXT: ; return to shader part epilog2737;2738; GFX10PLUS-LABEL: ssubsat_i16_vs:2739; GFX10PLUS: ; %bb.0:2740; GFX10PLUS-NEXT: v_sub_nc_i16 v0, v0, s0 clamp2741; GFX10PLUS-NEXT: ; return to shader part epilog2742 %result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)2743 %cast = bitcast i16 %result to half2744 ret half %cast2745}2746 2747define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {2748; GFX6-LABEL: v_ssubsat_v2i16:2749; GFX6: ; %bb.0:2750; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2751; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02752; GFX6-NEXT: v_max_i32_e32 v4, -1, v02753; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22754; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000001, v42755; GFX6-NEXT: v_min_i32_e32 v5, -1, v02756; GFX6-NEXT: v_bfrev_b32_e32 v6, 12757; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v62758; GFX6-NEXT: v_max_i32_e32 v2, v4, v22759; GFX6-NEXT: v_min_i32_e32 v2, v2, v52760; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12761; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22762; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v32763; GFX6-NEXT: v_max_i32_e32 v3, -1, v12764; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000001, v32765; GFX6-NEXT: v_min_i32_e32 v4, -1, v12766; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0x80000000, v42767; GFX6-NEXT: v_max_i32_e32 v2, v3, v22768; GFX6-NEXT: v_min_i32_e32 v2, v2, v42769; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v22770; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02771; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v12772; GFX6-NEXT: s_setpc_b64 s[30:31]2773;2774; GFX8-LABEL: v_ssubsat_v2i16:2775; GFX8: ; %bb.0:2776; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2777; GFX8-NEXT: v_max_i16_e32 v2, -1, v02778; GFX8-NEXT: v_add_u16_e32 v2, 0x8001, v22779; GFX8-NEXT: v_min_i16_e32 v3, -1, v02780; GFX8-NEXT: v_add_u16_e32 v3, 0x8000, v32781; GFX8-NEXT: v_max_i16_e32 v2, v2, v12782; GFX8-NEXT: v_min_i16_e32 v2, v2, v32783; GFX8-NEXT: v_mov_b32_e32 v3, -12784; GFX8-NEXT: v_max_i16_sdwa v4, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2785; GFX8-NEXT: v_add_u16_e32 v4, 0x8001, v42786; GFX8-NEXT: v_min_i16_sdwa v3, v0, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2787; GFX8-NEXT: v_add_u16_e32 v3, 0x8000, v32788; GFX8-NEXT: v_max_i16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12789; GFX8-NEXT: v_min_i16_e32 v1, v1, v32790; GFX8-NEXT: v_sub_u16_e32 v2, v0, v22791; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2792; GFX8-NEXT: v_or_b32_e32 v0, v2, v02793; GFX8-NEXT: s_setpc_b64 s[30:31]2794;2795; GFX9-LABEL: v_ssubsat_v2i16:2796; GFX9: ; %bb.0:2797; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2798; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp2799; GFX9-NEXT: s_setpc_b64 s[30:31]2800;2801; GFX10PLUS-LABEL: v_ssubsat_v2i16:2802; GFX10PLUS: ; %bb.0:2803; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2804; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v1 clamp2805; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2806 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2807 ret <2 x i16> %result2808}2809 2810define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {2811; GFX6-LABEL: s_ssubsat_v2i16:2812; GFX6: ; %bb.0:2813; GFX6-NEXT: s_lshl_b32 s0, s0, 162814; GFX6-NEXT: s_max_i32 s4, s0, -12815; GFX6-NEXT: s_lshl_b32 s2, s2, 162816; GFX6-NEXT: s_add_i32 s4, s4, 0x800000012817; GFX6-NEXT: s_min_i32 s5, s0, -12818; GFX6-NEXT: s_add_i32 s5, s5, 0x800000002819; GFX6-NEXT: s_max_i32 s2, s4, s22820; GFX6-NEXT: s_min_i32 s2, s2, s52821; GFX6-NEXT: s_lshl_b32 s1, s1, 162822; GFX6-NEXT: s_sub_i32 s0, s0, s22823; GFX6-NEXT: s_lshl_b32 s2, s3, 162824; GFX6-NEXT: s_max_i32 s3, s1, -12825; GFX6-NEXT: s_add_i32 s3, s3, 0x800000012826; GFX6-NEXT: s_min_i32 s4, s1, -12827; GFX6-NEXT: s_add_i32 s4, s4, 0x800000002828; GFX6-NEXT: s_max_i32 s2, s3, s22829; GFX6-NEXT: s_min_i32 s2, s2, s42830; GFX6-NEXT: s_sub_i32 s1, s1, s22831; GFX6-NEXT: s_ashr_i32 s1, s1, 162832; GFX6-NEXT: s_ashr_i32 s0, s0, 162833; GFX6-NEXT: s_and_b32 s1, s1, 0xffff2834; GFX6-NEXT: s_and_b32 s0, s0, 0xffff2835; GFX6-NEXT: s_lshl_b32 s1, s1, 162836; GFX6-NEXT: s_or_b32 s0, s0, s12837; GFX6-NEXT: ; return to shader part epilog2838;2839; GFX8-LABEL: s_ssubsat_v2i16:2840; GFX8: ; %bb.0:2841; GFX8-NEXT: s_sext_i32_i16 s4, s02842; GFX8-NEXT: s_max_i32 s5, s4, -12843; GFX8-NEXT: s_add_i32 s5, s5, 0x80012844; GFX8-NEXT: s_lshr_b32 s3, s1, 162845; GFX8-NEXT: s_min_i32 s4, s4, -12846; GFX8-NEXT: s_sext_i32_i16 s5, s52847; GFX8-NEXT: s_sext_i32_i16 s1, s12848; GFX8-NEXT: s_add_i32 s4, s4, 0x80002849; GFX8-NEXT: s_max_i32 s1, s5, s12850; GFX8-NEXT: s_sext_i32_i16 s1, s12851; GFX8-NEXT: s_sext_i32_i16 s4, s42852; GFX8-NEXT: s_lshr_b32 s2, s0, 162853; GFX8-NEXT: s_min_i32 s1, s1, s42854; GFX8-NEXT: s_sub_i32 s0, s0, s12855; GFX8-NEXT: s_sext_i32_i16 s1, s22856; GFX8-NEXT: s_max_i32 s4, s1, -12857; GFX8-NEXT: s_add_i32 s4, s4, 0x80012858; GFX8-NEXT: s_min_i32 s1, s1, -12859; GFX8-NEXT: s_sext_i32_i16 s4, s42860; GFX8-NEXT: s_sext_i32_i16 s3, s32861; GFX8-NEXT: s_add_i32 s1, s1, 0x80002862; GFX8-NEXT: s_max_i32 s3, s4, s32863; GFX8-NEXT: s_sext_i32_i16 s3, s32864; GFX8-NEXT: s_sext_i32_i16 s1, s12865; GFX8-NEXT: s_min_i32 s1, s3, s12866; GFX8-NEXT: s_sub_i32 s1, s2, s12867; GFX8-NEXT: s_and_b32 s1, 0xffff, s12868; GFX8-NEXT: s_and_b32 s0, 0xffff, s02869; GFX8-NEXT: s_lshl_b32 s1, s1, 162870; GFX8-NEXT: s_or_b32 s0, s0, s12871; GFX8-NEXT: ; return to shader part epilog2872;2873; GFX9-LABEL: s_ssubsat_v2i16:2874; GFX9: ; %bb.0:2875; GFX9-NEXT: v_mov_b32_e32 v0, s12876; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp2877; GFX9-NEXT: v_readfirstlane_b32 s0, v02878; GFX9-NEXT: ; return to shader part epilog2879;2880; GFX10PLUS-LABEL: s_ssubsat_v2i16:2881; GFX10PLUS: ; %bb.0:2882; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s1 clamp2883; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02884; GFX10PLUS-NEXT: ; return to shader part epilog2885 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2886 %cast = bitcast <2 x i16> %result to i322887 ret i32 %cast2888}2889 2890define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {2891; GFX6-LABEL: ssubsat_v2i16_sv:2892; GFX6: ; %bb.0:2893; GFX6-NEXT: s_lshl_b32 s0, s0, 162894; GFX6-NEXT: s_max_i32 s2, s0, -12895; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02896; GFX6-NEXT: s_add_i32 s2, s2, 0x800000012897; GFX6-NEXT: s_min_i32 s3, s0, -12898; GFX6-NEXT: s_add_i32 s3, s3, 0x800000002899; GFX6-NEXT: v_max_i32_e32 v0, s2, v02900; GFX6-NEXT: v_min_i32_e32 v0, s3, v02901; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v02902; GFX6-NEXT: s_lshl_b32 s0, s1, 162903; GFX6-NEXT: s_max_i32 s1, s0, -12904; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12905; GFX6-NEXT: s_add_i32 s1, s1, 0x800000012906; GFX6-NEXT: s_min_i32 s2, s0, -12907; GFX6-NEXT: s_add_i32 s2, s2, 0x800000002908; GFX6-NEXT: v_max_i32_e32 v1, s1, v12909; GFX6-NEXT: v_min_i32_e32 v1, s2, v12910; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v12911; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v12912; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02913; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12914; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02915; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12916; GFX6-NEXT: v_or_b32_e32 v0, v0, v12917; GFX6-NEXT: ; return to shader part epilog2918;2919; GFX8-LABEL: ssubsat_v2i16_sv:2920; GFX8: ; %bb.0:2921; GFX8-NEXT: s_sext_i32_i16 s2, s02922; GFX8-NEXT: s_max_i32 s3, s2, -12923; GFX8-NEXT: s_add_i32 s3, s3, 0x80012924; GFX8-NEXT: s_min_i32 s2, s2, -12925; GFX8-NEXT: s_lshr_b32 s1, s0, 162926; GFX8-NEXT: s_add_i32 s2, s2, 0x80002927; GFX8-NEXT: v_max_i16_e32 v1, s3, v02928; GFX8-NEXT: v_min_i16_e32 v1, s2, v12929; GFX8-NEXT: s_sext_i32_i16 s2, s12930; GFX8-NEXT: s_max_i32 s3, s2, -12931; GFX8-NEXT: s_add_i32 s3, s3, 0x80012932; GFX8-NEXT: s_min_i32 s2, s2, -12933; GFX8-NEXT: v_mov_b32_e32 v2, s32934; GFX8-NEXT: s_add_i32 s2, s2, 0x80002935; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12936; GFX8-NEXT: v_min_i16_e32 v0, s2, v02937; GFX8-NEXT: v_mov_b32_e32 v2, s12938; GFX8-NEXT: v_sub_u16_e32 v1, s0, v12939; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2940; GFX8-NEXT: v_or_b32_e32 v0, v1, v02941; GFX8-NEXT: ; return to shader part epilog2942;2943; GFX9-LABEL: ssubsat_v2i16_sv:2944; GFX9: ; %bb.0:2945; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp2946; GFX9-NEXT: ; return to shader part epilog2947;2948; GFX10PLUS-LABEL: ssubsat_v2i16_sv:2949; GFX10PLUS: ; %bb.0:2950; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, v0 clamp2951; GFX10PLUS-NEXT: ; return to shader part epilog2952 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2953 %cast = bitcast <2 x i16> %result to float2954 ret float %cast2955}2956 2957define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {2958; GFX6-LABEL: ssubsat_v2i16_vs:2959; GFX6: ; %bb.0:2960; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02961; GFX6-NEXT: v_max_i32_e32 v2, -1, v02962; GFX6-NEXT: s_lshl_b32 s0, s0, 162963; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0x80000001, v22964; GFX6-NEXT: v_min_i32_e32 v4, -1, v02965; GFX6-NEXT: v_bfrev_b32_e32 v5, 12966; GFX6-NEXT: v_add_i32_e32 v4, vcc, v4, v52967; GFX6-NEXT: v_max_i32_e32 v2, s0, v22968; GFX6-NEXT: v_min_i32_e32 v2, v2, v42969; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12970; GFX6-NEXT: v_mov_b32_e32 v3, 0x800000012971; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22972; GFX6-NEXT: v_max_i32_e32 v2, -1, v12973; GFX6-NEXT: s_lshl_b32 s0, s1, 162974; GFX6-NEXT: v_add_i32_e32 v2, vcc, v2, v32975; GFX6-NEXT: v_min_i32_e32 v3, -1, v12976; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v32977; GFX6-NEXT: v_max_i32_e32 v2, s0, v22978; GFX6-NEXT: v_min_i32_e32 v2, v2, v32979; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v22980; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v12981; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v02982; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12983; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02984; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12985; GFX6-NEXT: v_or_b32_e32 v0, v0, v12986; GFX6-NEXT: ; return to shader part epilog2987;2988; GFX8-LABEL: ssubsat_v2i16_vs:2989; GFX8: ; %bb.0:2990; GFX8-NEXT: v_max_i16_e32 v1, -1, v02991; GFX8-NEXT: v_add_u16_e32 v1, 0x8001, v12992; GFX8-NEXT: v_min_i16_e32 v2, -1, v02993; GFX8-NEXT: v_add_u16_e32 v2, 0x8000, v22994; GFX8-NEXT: v_max_i16_e32 v1, s0, v12995; GFX8-NEXT: v_min_i16_e32 v1, v1, v22996; GFX8-NEXT: v_mov_b32_e32 v2, -12997; GFX8-NEXT: v_max_i16_sdwa v3, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2998; GFX8-NEXT: s_lshr_b32 s1, s0, 162999; GFX8-NEXT: v_add_u16_e32 v3, 0x8001, v33000; GFX8-NEXT: v_min_i16_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3001; GFX8-NEXT: v_add_u16_e32 v2, 0x8000, v23002; GFX8-NEXT: v_max_i16_e32 v3, s1, v33003; GFX8-NEXT: v_min_i16_e32 v2, v3, v23004; GFX8-NEXT: v_sub_u16_e32 v1, v0, v13005; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3006; GFX8-NEXT: v_or_b32_e32 v0, v1, v03007; GFX8-NEXT: ; return to shader part epilog3008;3009; GFX9-LABEL: ssubsat_v2i16_vs:3010; GFX9: ; %bb.0:3011; GFX9-NEXT: v_pk_sub_i16 v0, v0, s0 clamp3012; GFX9-NEXT: ; return to shader part epilog3013;3014; GFX10PLUS-LABEL: ssubsat_v2i16_vs:3015; GFX10PLUS: ; %bb.0:3016; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, s0 clamp3017; GFX10PLUS-NEXT: ; return to shader part epilog3018 %result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)3019 %cast = bitcast <2 x i16> %result to float3020 ret float %cast3021}3022 3023; FIXME: v3i16 insert/extract3024; define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {3025; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)3026; ret <3 x i16> %result3027; }3028 3029; define amdgpu_ps <3 x i16> @s_ssubsat_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs) {3030; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)3031; ret <3 x i16> %result3032; }3033 3034define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {3035; GFX6-LABEL: v_ssubsat_v4i16:3036; GFX6: ; %bb.0:3037; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3038; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v03039; GFX6-NEXT: v_max_i32_e32 v8, -1, v03040; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v43041; GFX6-NEXT: v_add_i32_e32 v8, vcc, 0x80000001, v83042; GFX6-NEXT: v_min_i32_e32 v10, -1, v03043; GFX6-NEXT: v_bfrev_b32_e32 v11, 13044; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v113045; GFX6-NEXT: v_max_i32_e32 v4, v8, v43046; GFX6-NEXT: v_min_i32_e32 v4, v4, v103047; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13048; GFX6-NEXT: v_mov_b32_e32 v9, 0x800000013049; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v43050; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v53051; GFX6-NEXT: v_max_i32_e32 v5, -1, v13052; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v93053; GFX6-NEXT: v_min_i32_e32 v8, -1, v13054; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v113055; GFX6-NEXT: v_max_i32_e32 v4, v5, v43056; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23057; GFX6-NEXT: v_min_i32_e32 v4, v4, v83058; GFX6-NEXT: v_max_i32_e32 v5, -1, v23059; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v43060; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v63061; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v93062; GFX6-NEXT: v_min_i32_e32 v6, -1, v23063; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v113064; GFX6-NEXT: v_max_i32_e32 v4, v5, v43065; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v33066; GFX6-NEXT: v_min_i32_e32 v4, v4, v63067; GFX6-NEXT: v_max_i32_e32 v5, -1, v33068; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v43069; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v73070; GFX6-NEXT: v_add_i32_e32 v5, vcc, v5, v93071; GFX6-NEXT: v_min_i32_e32 v6, -1, v33072; GFX6-NEXT: v_add_i32_e32 v6, vcc, v6, v113073; GFX6-NEXT: v_max_i32_e32 v4, v5, v43074; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v13075; GFX6-NEXT: v_min_i32_e32 v4, v4, v63076; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v03077; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v43078; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v13079; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v23080; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v33081; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v03082; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13083; GFX6-NEXT: v_or_b32_e32 v0, v0, v13084; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v23085; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v33086; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23087; GFX6-NEXT: v_or_b32_e32 v1, v1, v23088; GFX6-NEXT: s_setpc_b64 s[30:31]3089;3090; GFX8-LABEL: v_ssubsat_v4i16:3091; GFX8: ; %bb.0:3092; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3093; GFX8-NEXT: v_max_i16_e32 v4, -1, v03094; GFX8-NEXT: v_add_u16_e32 v4, 0x8001, v43095; GFX8-NEXT: v_min_i16_e32 v5, -1, v03096; GFX8-NEXT: v_add_u16_e32 v5, 0x8000, v53097; GFX8-NEXT: v_max_i16_e32 v4, v4, v23098; GFX8-NEXT: v_min_i16_e32 v4, v4, v53099; GFX8-NEXT: v_mov_b32_e32 v5, -13100; GFX8-NEXT: v_max_i16_sdwa v6, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3101; GFX8-NEXT: v_add_u16_e32 v6, 0x8001, v63102; GFX8-NEXT: v_min_i16_sdwa v7, v0, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3103; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v73104; GFX8-NEXT: v_max_i16_sdwa v2, v6, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13105; GFX8-NEXT: v_max_i16_e32 v6, -1, v13106; GFX8-NEXT: v_min_i16_e32 v2, v2, v73107; GFX8-NEXT: v_add_u16_e32 v6, 0x8001, v63108; GFX8-NEXT: v_min_i16_e32 v7, -1, v13109; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v73110; GFX8-NEXT: v_max_i16_e32 v6, v6, v33111; GFX8-NEXT: v_min_i16_e32 v6, v6, v73112; GFX8-NEXT: v_max_i16_sdwa v7, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3113; GFX8-NEXT: v_add_u16_e32 v7, 0x8001, v73114; GFX8-NEXT: v_min_i16_sdwa v5, v1, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3115; GFX8-NEXT: v_add_u16_e32 v5, 0x8000, v53116; GFX8-NEXT: v_max_i16_sdwa v3, v7, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13117; GFX8-NEXT: v_min_i16_e32 v3, v3, v53118; GFX8-NEXT: v_sub_u16_e32 v4, v0, v43119; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3120; GFX8-NEXT: v_sub_u16_e32 v2, v1, v63121; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3122; GFX8-NEXT: v_or_b32_e32 v0, v4, v03123; GFX8-NEXT: v_or_b32_e32 v1, v2, v13124; GFX8-NEXT: s_setpc_b64 s[30:31]3125;3126; GFX9-LABEL: v_ssubsat_v4i16:3127; GFX9: ; %bb.0:3128; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp3130; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp3131; GFX9-NEXT: s_setpc_b64 s[30:31]3132;3133; GFX10PLUS-LABEL: v_ssubsat_v4i16:3134; GFX10PLUS: ; %bb.0:3135; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3136; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v2 clamp3137; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v3 clamp3138; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]3139 %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)3140 %cast = bitcast <4 x i16> %result to <2 x float>3141 ret <2 x float> %cast3142}3143 3144define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {3145; GFX6-LABEL: s_ssubsat_v4i16:3146; GFX6: ; %bb.0:3147; GFX6-NEXT: s_lshl_b32 s0, s0, 163148; GFX6-NEXT: s_max_i32 s8, s0, -13149; GFX6-NEXT: s_lshl_b32 s4, s4, 163150; GFX6-NEXT: s_add_i32 s8, s8, 0x800000013151; GFX6-NEXT: s_min_i32 s9, s0, -13152; GFX6-NEXT: s_add_i32 s9, s9, 0x800000003153; GFX6-NEXT: s_max_i32 s4, s8, s43154; GFX6-NEXT: s_min_i32 s4, s4, s93155; GFX6-NEXT: s_lshl_b32 s1, s1, 163156; GFX6-NEXT: s_sub_i32 s0, s0, s43157; GFX6-NEXT: s_lshl_b32 s4, s5, 163158; GFX6-NEXT: s_max_i32 s5, s1, -13159; GFX6-NEXT: s_add_i32 s5, s5, 0x800000013160; GFX6-NEXT: s_min_i32 s8, s1, -13161; GFX6-NEXT: s_add_i32 s8, s8, 0x800000003162; GFX6-NEXT: s_max_i32 s4, s5, s43163; GFX6-NEXT: s_lshl_b32 s2, s2, 163164; GFX6-NEXT: s_min_i32 s4, s4, s83165; GFX6-NEXT: s_max_i32 s5, s2, -13166; GFX6-NEXT: s_sub_i32 s1, s1, s43167; GFX6-NEXT: s_lshl_b32 s4, s6, 163168; GFX6-NEXT: s_add_i32 s5, s5, 0x800000013169; GFX6-NEXT: s_min_i32 s6, s2, -13170; GFX6-NEXT: s_add_i32 s6, s6, 0x800000003171; GFX6-NEXT: s_max_i32 s4, s5, s43172; GFX6-NEXT: s_lshl_b32 s3, s3, 163173; GFX6-NEXT: s_min_i32 s4, s4, s63174; GFX6-NEXT: s_max_i32 s5, s3, -13175; GFX6-NEXT: s_sub_i32 s2, s2, s43176; GFX6-NEXT: s_lshl_b32 s4, s7, 163177; GFX6-NEXT: s_add_i32 s5, s5, 0x800000013178; GFX6-NEXT: s_min_i32 s6, s3, -13179; GFX6-NEXT: s_add_i32 s6, s6, 0x800000003180; GFX6-NEXT: s_max_i32 s4, s5, s43181; GFX6-NEXT: s_ashr_i32 s1, s1, 163182; GFX6-NEXT: s_min_i32 s4, s4, s63183; GFX6-NEXT: s_ashr_i32 s0, s0, 163184; GFX6-NEXT: s_sub_i32 s3, s3, s43185; GFX6-NEXT: s_and_b32 s1, s1, 0xffff3186; GFX6-NEXT: s_ashr_i32 s2, s2, 163187; GFX6-NEXT: s_ashr_i32 s3, s3, 163188; GFX6-NEXT: s_and_b32 s0, s0, 0xffff3189; GFX6-NEXT: s_lshl_b32 s1, s1, 163190; GFX6-NEXT: s_or_b32 s0, s0, s13191; GFX6-NEXT: s_and_b32 s1, s2, 0xffff3192; GFX6-NEXT: s_and_b32 s2, s3, 0xffff3193; GFX6-NEXT: s_lshl_b32 s2, s2, 163194; GFX6-NEXT: s_or_b32 s1, s1, s23195; GFX6-NEXT: ; return to shader part epilog3196;3197; GFX8-LABEL: s_ssubsat_v4i16:3198; GFX8: ; %bb.0:3199; GFX8-NEXT: s_sext_i32_i16 s8, s03200; GFX8-NEXT: s_max_i32 s9, s8, -13201; GFX8-NEXT: s_add_i32 s9, s9, 0x80013202; GFX8-NEXT: s_lshr_b32 s6, s2, 163203; GFX8-NEXT: s_min_i32 s8, s8, -13204; GFX8-NEXT: s_sext_i32_i16 s9, s93205; GFX8-NEXT: s_sext_i32_i16 s2, s23206; GFX8-NEXT: s_add_i32 s8, s8, 0x80003207; GFX8-NEXT: s_max_i32 s2, s9, s23208; GFX8-NEXT: s_sext_i32_i16 s2, s23209; GFX8-NEXT: s_sext_i32_i16 s8, s83210; GFX8-NEXT: s_lshr_b32 s4, s0, 163211; GFX8-NEXT: s_min_i32 s2, s2, s83212; GFX8-NEXT: s_sub_i32 s0, s0, s23213; GFX8-NEXT: s_sext_i32_i16 s2, s43214; GFX8-NEXT: s_max_i32 s8, s2, -13215; GFX8-NEXT: s_add_i32 s8, s8, 0x80013216; GFX8-NEXT: s_min_i32 s2, s2, -13217; GFX8-NEXT: s_sext_i32_i16 s8, s83218; GFX8-NEXT: s_sext_i32_i16 s6, s63219; GFX8-NEXT: s_add_i32 s2, s2, 0x80003220; GFX8-NEXT: s_max_i32 s6, s8, s63221; GFX8-NEXT: s_sext_i32_i16 s6, s63222; GFX8-NEXT: s_sext_i32_i16 s2, s23223; GFX8-NEXT: s_min_i32 s2, s6, s23224; GFX8-NEXT: s_sub_i32 s2, s4, s23225; GFX8-NEXT: s_sext_i32_i16 s4, s13226; GFX8-NEXT: s_max_i32 s6, s4, -13227; GFX8-NEXT: s_add_i32 s6, s6, 0x80013228; GFX8-NEXT: s_lshr_b32 s7, s3, 163229; GFX8-NEXT: s_min_i32 s4, s4, -13230; GFX8-NEXT: s_sext_i32_i16 s6, s63231; GFX8-NEXT: s_sext_i32_i16 s3, s33232; GFX8-NEXT: s_add_i32 s4, s4, 0x80003233; GFX8-NEXT: s_max_i32 s3, s6, s33234; GFX8-NEXT: s_sext_i32_i16 s3, s33235; GFX8-NEXT: s_sext_i32_i16 s4, s43236; GFX8-NEXT: s_lshr_b32 s5, s1, 163237; GFX8-NEXT: s_min_i32 s3, s3, s43238; GFX8-NEXT: s_sub_i32 s1, s1, s33239; GFX8-NEXT: s_sext_i32_i16 s3, s53240; GFX8-NEXT: s_max_i32 s4, s3, -13241; GFX8-NEXT: s_add_i32 s4, s4, 0x80013242; GFX8-NEXT: s_min_i32 s3, s3, -13243; GFX8-NEXT: s_sext_i32_i16 s4, s43244; GFX8-NEXT: s_sext_i32_i16 s6, s73245; GFX8-NEXT: s_add_i32 s3, s3, 0x80003246; GFX8-NEXT: s_max_i32 s4, s4, s63247; GFX8-NEXT: s_sext_i32_i16 s4, s43248; GFX8-NEXT: s_sext_i32_i16 s3, s33249; GFX8-NEXT: s_min_i32 s3, s4, s33250; GFX8-NEXT: s_and_b32 s2, 0xffff, s23251; GFX8-NEXT: s_sub_i32 s3, s5, s33252; GFX8-NEXT: s_and_b32 s0, 0xffff, s03253; GFX8-NEXT: s_lshl_b32 s2, s2, 163254; GFX8-NEXT: s_or_b32 s0, s0, s23255; GFX8-NEXT: s_and_b32 s2, 0xffff, s33256; GFX8-NEXT: s_and_b32 s1, 0xffff, s13257; GFX8-NEXT: s_lshl_b32 s2, s2, 163258; GFX8-NEXT: s_or_b32 s1, s1, s23259; GFX8-NEXT: ; return to shader part epilog3260;3261; GFX9-LABEL: s_ssubsat_v4i16:3262; GFX9: ; %bb.0:3263; GFX9-NEXT: v_mov_b32_e32 v0, s23264; GFX9-NEXT: v_mov_b32_e32 v1, s33265; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp3266; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp3267; GFX9-NEXT: v_readfirstlane_b32 s0, v03268; GFX9-NEXT: v_readfirstlane_b32 s1, v13269; GFX9-NEXT: ; return to shader part epilog3270;3271; GFX10PLUS-LABEL: s_ssubsat_v4i16:3272; GFX10PLUS: ; %bb.0:3273; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s2 clamp3274; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s3 clamp3275; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v03276; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v13277; GFX10PLUS-NEXT: ; return to shader part epilog3278 %result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)3279 %cast = bitcast <4 x i16> %result to <2 x i32>3280 ret <2 x i32> %cast3281}3282 3283; FIXME3284; define <5 x i16> @v_ssubsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {3285; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)3286; ret <5 x i16> %result3287; }3288 3289; define amdgpu_ps <5 x i16> @s_ssubsat_v5i16(<5 x i16> inreg %lhs, <5 x i16> inreg %rhs) {3290; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)3291; ret <5 x i16> %result3292; }3293 3294define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {3295; GFX6-LABEL: v_ssubsat_v6i16:3296; GFX6: ; %bb.0:3297; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3298; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v03299; GFX6-NEXT: v_max_i32_e32 v12, -1, v03300; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v63301; GFX6-NEXT: v_add_i32_e32 v12, vcc, 0x80000001, v123302; GFX6-NEXT: v_min_i32_e32 v14, -1, v03303; GFX6-NEXT: v_bfrev_b32_e32 v15, 13304; GFX6-NEXT: v_add_i32_e32 v14, vcc, v14, v153305; GFX6-NEXT: v_max_i32_e32 v6, v12, v63306; GFX6-NEXT: v_min_i32_e32 v6, v6, v143307; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13308; GFX6-NEXT: v_mov_b32_e32 v13, 0x800000013309; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v63310; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v73311; GFX6-NEXT: v_max_i32_e32 v7, -1, v13312; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v133313; GFX6-NEXT: v_min_i32_e32 v12, -1, v13314; GFX6-NEXT: v_add_i32_e32 v12, vcc, v12, v153315; GFX6-NEXT: v_max_i32_e32 v6, v7, v63316; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23317; GFX6-NEXT: v_min_i32_e32 v6, v6, v123318; GFX6-NEXT: v_max_i32_e32 v7, -1, v23319; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v63320; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v83321; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v133322; GFX6-NEXT: v_min_i32_e32 v8, -1, v23323; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v153324; GFX6-NEXT: v_max_i32_e32 v6, v7, v63325; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v33326; GFX6-NEXT: v_min_i32_e32 v6, v6, v83327; GFX6-NEXT: v_max_i32_e32 v7, -1, v33328; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v63329; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v93330; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v133331; GFX6-NEXT: v_min_i32_e32 v8, -1, v33332; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v153333; GFX6-NEXT: v_max_i32_e32 v6, v7, v63334; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v43335; GFX6-NEXT: v_min_i32_e32 v6, v6, v83336; GFX6-NEXT: v_max_i32_e32 v7, -1, v43337; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v63338; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v103339; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v133340; GFX6-NEXT: v_min_i32_e32 v8, -1, v43341; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v153342; GFX6-NEXT: v_max_i32_e32 v6, v7, v63343; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v53344; GFX6-NEXT: v_min_i32_e32 v6, v6, v83345; GFX6-NEXT: v_max_i32_e32 v7, -1, v53346; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v63347; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v113348; GFX6-NEXT: v_add_i32_e32 v7, vcc, v7, v133349; GFX6-NEXT: v_min_i32_e32 v8, -1, v53350; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v13351; GFX6-NEXT: v_add_i32_e32 v8, vcc, v8, v153352; GFX6-NEXT: v_max_i32_e32 v6, v7, v63353; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v03354; GFX6-NEXT: v_min_i32_e32 v6, v6, v83355; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v13356; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v23357; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v33358; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v63359; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v03360; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13361; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v53362; GFX6-NEXT: v_or_b32_e32 v0, v0, v13363; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v23364; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v33365; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v43366; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23367; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v53368; GFX6-NEXT: v_or_b32_e32 v1, v1, v23369; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v43370; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v33371; GFX6-NEXT: v_or_b32_e32 v2, v2, v33372; GFX6-NEXT: s_setpc_b64 s[30:31]3373;3374; GFX8-LABEL: v_ssubsat_v6i16:3375; GFX8: ; %bb.0:3376; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3377; GFX8-NEXT: v_max_i16_e32 v6, -1, v03378; GFX8-NEXT: v_add_u16_e32 v6, 0x8001, v63379; GFX8-NEXT: v_min_i16_e32 v7, -1, v03380; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v73381; GFX8-NEXT: v_max_i16_e32 v6, v6, v33382; GFX8-NEXT: v_min_i16_e32 v6, v6, v73383; GFX8-NEXT: v_mov_b32_e32 v7, -13384; GFX8-NEXT: v_max_i16_sdwa v8, v0, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3385; GFX8-NEXT: v_add_u16_e32 v8, 0x8001, v83386; GFX8-NEXT: v_min_i16_sdwa v9, v0, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3387; GFX8-NEXT: v_add_u16_e32 v9, 0x8000, v93388; GFX8-NEXT: v_max_i16_sdwa v3, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13389; GFX8-NEXT: v_max_i16_e32 v8, -1, v13390; GFX8-NEXT: v_min_i16_e32 v3, v3, v93391; GFX8-NEXT: v_add_u16_e32 v8, 0x8001, v83392; GFX8-NEXT: v_min_i16_e32 v9, -1, v13393; GFX8-NEXT: v_add_u16_e32 v9, 0x8000, v93394; GFX8-NEXT: v_max_i16_e32 v8, v8, v43395; GFX8-NEXT: v_min_i16_e32 v8, v8, v93396; GFX8-NEXT: v_max_i16_sdwa v9, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3397; GFX8-NEXT: v_add_u16_e32 v9, 0x8001, v93398; GFX8-NEXT: v_min_i16_sdwa v10, v1, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3399; GFX8-NEXT: v_add_u16_e32 v10, 0x8000, v103400; GFX8-NEXT: v_max_i16_sdwa v4, v9, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13401; GFX8-NEXT: v_max_i16_e32 v9, -1, v23402; GFX8-NEXT: v_min_i16_e32 v4, v4, v103403; GFX8-NEXT: v_add_u16_e32 v9, 0x8001, v93404; GFX8-NEXT: v_min_i16_e32 v10, -1, v23405; GFX8-NEXT: v_add_u16_e32 v10, 0x8000, v103406; GFX8-NEXT: v_max_i16_e32 v9, v9, v53407; GFX8-NEXT: v_min_i16_e32 v9, v9, v103408; GFX8-NEXT: v_max_i16_sdwa v10, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3409; GFX8-NEXT: v_add_u16_e32 v10, 0x8001, v103410; GFX8-NEXT: v_min_i16_sdwa v7, v2, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3411; GFX8-NEXT: v_add_u16_e32 v7, 0x8000, v73412; GFX8-NEXT: v_max_i16_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13413; GFX8-NEXT: v_min_i16_e32 v5, v5, v73414; GFX8-NEXT: v_sub_u16_e32 v6, v0, v63415; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3416; GFX8-NEXT: v_sub_u16_e32 v3, v1, v83417; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3418; GFX8-NEXT: v_or_b32_e32 v1, v3, v13419; GFX8-NEXT: v_sub_u16_e32 v3, v2, v93420; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3421; GFX8-NEXT: v_or_b32_e32 v0, v6, v03422; GFX8-NEXT: v_or_b32_e32 v2, v3, v23423; GFX8-NEXT: s_setpc_b64 s[30:31]3424;3425; GFX9-LABEL: v_ssubsat_v6i16:3426; GFX9: ; %bb.0:3427; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3428; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 clamp3429; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 clamp3430; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5 clamp3431; GFX9-NEXT: s_setpc_b64 s[30:31]3432;3433; GFX10PLUS-LABEL: v_ssubsat_v6i16:3434; GFX10PLUS: ; %bb.0:3435; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3436; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v3 clamp3437; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v4 clamp3438; GFX10PLUS-NEXT: v_pk_sub_i16 v2, v2, v5 clamp3439; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]3440 %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)3441 %cast = bitcast <6 x i16> %result to <3 x float>3442 ret <3 x float> %cast3443}3444 3445define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {3446; GFX6-LABEL: s_ssubsat_v6i16:3447; GFX6: ; %bb.0:3448; GFX6-NEXT: s_lshl_b32 s0, s0, 163449; GFX6-NEXT: s_max_i32 s12, s0, -13450; GFX6-NEXT: s_lshl_b32 s6, s6, 163451; GFX6-NEXT: s_add_i32 s12, s12, 0x800000013452; GFX6-NEXT: s_min_i32 s13, s0, -13453; GFX6-NEXT: s_add_i32 s13, s13, 0x800000003454; GFX6-NEXT: s_max_i32 s6, s12, s63455; GFX6-NEXT: s_min_i32 s6, s6, s133456; GFX6-NEXT: s_lshl_b32 s1, s1, 163457; GFX6-NEXT: s_sub_i32 s0, s0, s63458; GFX6-NEXT: s_lshl_b32 s6, s7, 163459; GFX6-NEXT: s_max_i32 s7, s1, -13460; GFX6-NEXT: s_add_i32 s7, s7, 0x800000013461; GFX6-NEXT: s_min_i32 s12, s1, -13462; GFX6-NEXT: s_add_i32 s12, s12, 0x800000003463; GFX6-NEXT: s_max_i32 s6, s7, s63464; GFX6-NEXT: s_lshl_b32 s2, s2, 163465; GFX6-NEXT: s_min_i32 s6, s6, s123466; GFX6-NEXT: s_max_i32 s7, s2, -13467; GFX6-NEXT: s_sub_i32 s1, s1, s63468; GFX6-NEXT: s_lshl_b32 s6, s8, 163469; GFX6-NEXT: s_add_i32 s7, s7, 0x800000013470; GFX6-NEXT: s_min_i32 s8, s2, -13471; GFX6-NEXT: s_add_i32 s8, s8, 0x800000003472; GFX6-NEXT: s_max_i32 s6, s7, s63473; GFX6-NEXT: s_lshl_b32 s3, s3, 163474; GFX6-NEXT: s_min_i32 s6, s6, s83475; GFX6-NEXT: s_max_i32 s7, s3, -13476; GFX6-NEXT: s_sub_i32 s2, s2, s63477; GFX6-NEXT: s_lshl_b32 s6, s9, 163478; GFX6-NEXT: s_add_i32 s7, s7, 0x800000013479; GFX6-NEXT: s_min_i32 s8, s3, -13480; GFX6-NEXT: s_add_i32 s8, s8, 0x800000003481; GFX6-NEXT: s_max_i32 s6, s7, s63482; GFX6-NEXT: s_lshl_b32 s4, s4, 163483; GFX6-NEXT: s_min_i32 s6, s6, s83484; GFX6-NEXT: s_max_i32 s7, s4, -13485; GFX6-NEXT: s_sub_i32 s3, s3, s63486; GFX6-NEXT: s_lshl_b32 s6, s10, 163487; GFX6-NEXT: s_add_i32 s7, s7, 0x800000013488; GFX6-NEXT: s_min_i32 s8, s4, -13489; GFX6-NEXT: s_add_i32 s8, s8, 0x800000003490; GFX6-NEXT: s_max_i32 s6, s7, s63491; GFX6-NEXT: s_lshl_b32 s5, s5, 163492; GFX6-NEXT: s_min_i32 s6, s6, s83493; GFX6-NEXT: s_max_i32 s7, s5, -13494; GFX6-NEXT: s_sub_i32 s4, s4, s63495; GFX6-NEXT: s_lshl_b32 s6, s11, 163496; GFX6-NEXT: s_add_i32 s7, s7, 0x800000013497; GFX6-NEXT: s_min_i32 s8, s5, -13498; GFX6-NEXT: s_ashr_i32 s1, s1, 163499; GFX6-NEXT: s_add_i32 s8, s8, 0x800000003500; GFX6-NEXT: s_max_i32 s6, s7, s63501; GFX6-NEXT: s_ashr_i32 s0, s0, 163502; GFX6-NEXT: s_min_i32 s6, s6, s83503; GFX6-NEXT: s_and_b32 s1, s1, 0xffff3504; GFX6-NEXT: s_ashr_i32 s2, s2, 163505; GFX6-NEXT: s_ashr_i32 s3, s3, 163506; GFX6-NEXT: s_sub_i32 s5, s5, s63507; GFX6-NEXT: s_and_b32 s0, s0, 0xffff3508; GFX6-NEXT: s_lshl_b32 s1, s1, 163509; GFX6-NEXT: s_ashr_i32 s5, s5, 163510; GFX6-NEXT: s_or_b32 s0, s0, s13511; GFX6-NEXT: s_and_b32 s1, s2, 0xffff3512; GFX6-NEXT: s_and_b32 s2, s3, 0xffff3513; GFX6-NEXT: s_ashr_i32 s4, s4, 163514; GFX6-NEXT: s_lshl_b32 s2, s2, 163515; GFX6-NEXT: s_and_b32 s3, s5, 0xffff3516; GFX6-NEXT: s_or_b32 s1, s1, s23517; GFX6-NEXT: s_and_b32 s2, s4, 0xffff3518; GFX6-NEXT: s_lshl_b32 s3, s3, 163519; GFX6-NEXT: s_or_b32 s2, s2, s33520; GFX6-NEXT: ; return to shader part epilog3521;3522; GFX8-LABEL: s_ssubsat_v6i16:3523; GFX8: ; %bb.0:3524; GFX8-NEXT: s_sext_i32_i16 s12, s03525; GFX8-NEXT: s_max_i32 s13, s12, -13526; GFX8-NEXT: s_add_i32 s13, s13, 0x80013527; GFX8-NEXT: s_lshr_b32 s9, s3, 163528; GFX8-NEXT: s_min_i32 s12, s12, -13529; GFX8-NEXT: s_sext_i32_i16 s13, s133530; GFX8-NEXT: s_sext_i32_i16 s3, s33531; GFX8-NEXT: s_add_i32 s12, s12, 0x80003532; GFX8-NEXT: s_max_i32 s3, s13, s33533; GFX8-NEXT: s_sext_i32_i16 s3, s33534; GFX8-NEXT: s_sext_i32_i16 s12, s123535; GFX8-NEXT: s_lshr_b32 s6, s0, 163536; GFX8-NEXT: s_min_i32 s3, s3, s123537; GFX8-NEXT: s_sub_i32 s0, s0, s33538; GFX8-NEXT: s_sext_i32_i16 s3, s63539; GFX8-NEXT: s_max_i32 s12, s3, -13540; GFX8-NEXT: s_add_i32 s12, s12, 0x80013541; GFX8-NEXT: s_min_i32 s3, s3, -13542; GFX8-NEXT: s_sext_i32_i16 s12, s123543; GFX8-NEXT: s_sext_i32_i16 s9, s93544; GFX8-NEXT: s_add_i32 s3, s3, 0x80003545; GFX8-NEXT: s_max_i32 s9, s12, s93546; GFX8-NEXT: s_sext_i32_i16 s9, s93547; GFX8-NEXT: s_sext_i32_i16 s3, s33548; GFX8-NEXT: s_min_i32 s3, s9, s33549; GFX8-NEXT: s_sub_i32 s3, s6, s33550; GFX8-NEXT: s_sext_i32_i16 s6, s13551; GFX8-NEXT: s_max_i32 s9, s6, -13552; GFX8-NEXT: s_add_i32 s9, s9, 0x80013553; GFX8-NEXT: s_lshr_b32 s10, s4, 163554; GFX8-NEXT: s_min_i32 s6, s6, -13555; GFX8-NEXT: s_sext_i32_i16 s9, s93556; GFX8-NEXT: s_sext_i32_i16 s4, s43557; GFX8-NEXT: s_add_i32 s6, s6, 0x80003558; GFX8-NEXT: s_max_i32 s4, s9, s43559; GFX8-NEXT: s_sext_i32_i16 s4, s43560; GFX8-NEXT: s_sext_i32_i16 s6, s63561; GFX8-NEXT: s_lshr_b32 s7, s1, 163562; GFX8-NEXT: s_min_i32 s4, s4, s63563; GFX8-NEXT: s_sub_i32 s1, s1, s43564; GFX8-NEXT: s_sext_i32_i16 s4, s73565; GFX8-NEXT: s_max_i32 s6, s4, -13566; GFX8-NEXT: s_add_i32 s6, s6, 0x80013567; GFX8-NEXT: s_min_i32 s4, s4, -13568; GFX8-NEXT: s_sext_i32_i16 s6, s63569; GFX8-NEXT: s_sext_i32_i16 s9, s103570; GFX8-NEXT: s_add_i32 s4, s4, 0x80003571; GFX8-NEXT: s_max_i32 s6, s6, s93572; GFX8-NEXT: s_sext_i32_i16 s6, s63573; GFX8-NEXT: s_sext_i32_i16 s4, s43574; GFX8-NEXT: s_min_i32 s4, s6, s43575; GFX8-NEXT: s_sext_i32_i16 s6, s23576; GFX8-NEXT: s_sub_i32 s4, s7, s43577; GFX8-NEXT: s_max_i32 s7, s6, -13578; GFX8-NEXT: s_add_i32 s7, s7, 0x80013579; GFX8-NEXT: s_lshr_b32 s11, s5, 163580; GFX8-NEXT: s_min_i32 s6, s6, -13581; GFX8-NEXT: s_sext_i32_i16 s7, s73582; GFX8-NEXT: s_sext_i32_i16 s5, s53583; GFX8-NEXT: s_add_i32 s6, s6, 0x80003584; GFX8-NEXT: s_max_i32 s5, s7, s53585; GFX8-NEXT: s_sext_i32_i16 s5, s53586; GFX8-NEXT: s_sext_i32_i16 s6, s63587; GFX8-NEXT: s_lshr_b32 s8, s2, 163588; GFX8-NEXT: s_min_i32 s5, s5, s63589; GFX8-NEXT: s_sub_i32 s2, s2, s53590; GFX8-NEXT: s_sext_i32_i16 s5, s83591; GFX8-NEXT: s_max_i32 s6, s5, -13592; GFX8-NEXT: s_add_i32 s6, s6, 0x80013593; GFX8-NEXT: s_min_i32 s5, s5, -13594; GFX8-NEXT: s_sext_i32_i16 s6, s63595; GFX8-NEXT: s_sext_i32_i16 s7, s113596; GFX8-NEXT: s_add_i32 s5, s5, 0x80003597; GFX8-NEXT: s_max_i32 s6, s6, s73598; GFX8-NEXT: s_and_b32 s3, 0xffff, s33599; GFX8-NEXT: s_sext_i32_i16 s6, s63600; GFX8-NEXT: s_sext_i32_i16 s5, s53601; GFX8-NEXT: s_and_b32 s0, 0xffff, s03602; GFX8-NEXT: s_lshl_b32 s3, s3, 163603; GFX8-NEXT: s_min_i32 s5, s6, s53604; GFX8-NEXT: s_or_b32 s0, s0, s33605; GFX8-NEXT: s_and_b32 s3, 0xffff, s43606; GFX8-NEXT: s_sub_i32 s5, s8, s53607; GFX8-NEXT: s_and_b32 s1, 0xffff, s13608; GFX8-NEXT: s_lshl_b32 s3, s3, 163609; GFX8-NEXT: s_or_b32 s1, s1, s33610; GFX8-NEXT: s_and_b32 s3, 0xffff, s53611; GFX8-NEXT: s_and_b32 s2, 0xffff, s23612; GFX8-NEXT: s_lshl_b32 s3, s3, 163613; GFX8-NEXT: s_or_b32 s2, s2, s33614; GFX8-NEXT: ; return to shader part epilog3615;3616; GFX9-LABEL: s_ssubsat_v6i16:3617; GFX9: ; %bb.0:3618; GFX9-NEXT: v_mov_b32_e32 v0, s33619; GFX9-NEXT: v_mov_b32_e32 v1, s43620; GFX9-NEXT: v_mov_b32_e32 v2, s53621; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp3622; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp3623; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp3624; GFX9-NEXT: v_readfirstlane_b32 s0, v03625; GFX9-NEXT: v_readfirstlane_b32 s1, v13626; GFX9-NEXT: v_readfirstlane_b32 s2, v23627; GFX9-NEXT: ; return to shader part epilog3628;3629; GFX10PLUS-LABEL: s_ssubsat_v6i16:3630; GFX10PLUS: ; %bb.0:3631; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s3 clamp3632; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s4 clamp3633; GFX10PLUS-NEXT: v_pk_sub_i16 v2, s2, s5 clamp3634; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v03635; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v13636; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v23637; GFX10PLUS-NEXT: ; return to shader part epilog3638 %result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)3639 %cast = bitcast <6 x i16> %result to <3 x i32>3640 ret <3 x i32> %cast3641}3642 3643define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {3644; GFX6-LABEL: v_ssubsat_v8i16:3645; GFX6: ; %bb.0:3646; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3647; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v03648; GFX6-NEXT: v_max_i32_e32 v16, -1, v03649; GFX6-NEXT: v_mov_b32_e32 v17, 0x800000013650; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v83651; GFX6-NEXT: v_add_i32_e32 v16, vcc, v16, v173652; GFX6-NEXT: v_min_i32_e32 v18, -1, v03653; GFX6-NEXT: v_bfrev_b32_e32 v19, 13654; GFX6-NEXT: v_add_i32_e32 v18, vcc, v18, v193655; GFX6-NEXT: v_max_i32_e32 v8, v16, v83656; GFX6-NEXT: v_min_i32_e32 v8, v8, v183657; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13658; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v83659; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v93660; GFX6-NEXT: v_max_i32_e32 v9, -1, v13661; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173662; GFX6-NEXT: v_min_i32_e32 v16, -1, v13663; GFX6-NEXT: v_add_i32_e32 v16, vcc, v16, v193664; GFX6-NEXT: v_max_i32_e32 v8, v9, v83665; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23666; GFX6-NEXT: v_min_i32_e32 v8, v8, v163667; GFX6-NEXT: v_max_i32_e32 v9, -1, v23668; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v83669; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v103670; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173671; GFX6-NEXT: v_min_i32_e32 v10, -1, v23672; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193673; GFX6-NEXT: v_max_i32_e32 v8, v9, v83674; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v33675; GFX6-NEXT: v_min_i32_e32 v8, v8, v103676; GFX6-NEXT: v_max_i32_e32 v9, -1, v33677; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v83678; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v113679; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173680; GFX6-NEXT: v_min_i32_e32 v10, -1, v33681; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193682; GFX6-NEXT: v_max_i32_e32 v8, v9, v83683; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v43684; GFX6-NEXT: v_min_i32_e32 v8, v8, v103685; GFX6-NEXT: v_max_i32_e32 v9, -1, v43686; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v83687; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v123688; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173689; GFX6-NEXT: v_min_i32_e32 v10, -1, v43690; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193691; GFX6-NEXT: v_max_i32_e32 v8, v9, v83692; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v53693; GFX6-NEXT: v_min_i32_e32 v8, v8, v103694; GFX6-NEXT: v_max_i32_e32 v9, -1, v53695; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v83696; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v133697; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173698; GFX6-NEXT: v_min_i32_e32 v10, -1, v53699; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193700; GFX6-NEXT: v_max_i32_e32 v8, v9, v83701; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v63702; GFX6-NEXT: v_min_i32_e32 v8, v8, v103703; GFX6-NEXT: v_max_i32_e32 v9, -1, v63704; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v83705; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v143706; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173707; GFX6-NEXT: v_min_i32_e32 v10, -1, v63708; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193709; GFX6-NEXT: v_max_i32_e32 v8, v9, v83710; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v73711; GFX6-NEXT: v_min_i32_e32 v8, v8, v103712; GFX6-NEXT: v_max_i32_e32 v9, -1, v73713; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v13714; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v83715; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v153716; GFX6-NEXT: v_add_i32_e32 v9, vcc, v9, v173717; GFX6-NEXT: v_min_i32_e32 v10, -1, v73718; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v03719; GFX6-NEXT: v_add_i32_e32 v10, vcc, v10, v193720; GFX6-NEXT: v_max_i32_e32 v8, v9, v83721; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v13722; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v23723; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v33724; GFX6-NEXT: v_min_i32_e32 v8, v8, v103725; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v03726; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v13727; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v53728; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v83729; GFX6-NEXT: v_or_b32_e32 v0, v0, v13730; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v23731; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v33732; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v43733; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v73734; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v23735; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v53736; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v63737; GFX6-NEXT: v_or_b32_e32 v1, v1, v23738; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v43739; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v33740; GFX6-NEXT: v_and_b32_e32 v4, 0xffff, v73741; GFX6-NEXT: v_or_b32_e32 v2, v2, v33742; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v63743; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v43744; GFX6-NEXT: v_or_b32_e32 v3, v3, v43745; GFX6-NEXT: s_setpc_b64 s[30:31]3746;3747; GFX8-LABEL: v_ssubsat_v8i16:3748; GFX8: ; %bb.0:3749; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3750; GFX8-NEXT: v_max_i16_e32 v8, -1, v03751; GFX8-NEXT: v_add_u16_e32 v8, 0x8001, v83752; GFX8-NEXT: v_min_i16_e32 v9, -1, v03753; GFX8-NEXT: v_add_u16_e32 v9, 0x8000, v93754; GFX8-NEXT: v_max_i16_e32 v8, v8, v43755; GFX8-NEXT: v_min_i16_e32 v8, v8, v93756; GFX8-NEXT: v_mov_b32_e32 v9, -13757; GFX8-NEXT: v_max_i16_sdwa v10, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3758; GFX8-NEXT: v_add_u16_e32 v10, 0x8001, v103759; GFX8-NEXT: v_min_i16_sdwa v11, v0, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3760; GFX8-NEXT: v_add_u16_e32 v11, 0x8000, v113761; GFX8-NEXT: v_max_i16_sdwa v4, v10, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13762; GFX8-NEXT: v_max_i16_e32 v10, -1, v13763; GFX8-NEXT: v_min_i16_e32 v4, v4, v113764; GFX8-NEXT: v_add_u16_e32 v10, 0x8001, v103765; GFX8-NEXT: v_min_i16_e32 v11, -1, v13766; GFX8-NEXT: v_add_u16_e32 v11, 0x8000, v113767; GFX8-NEXT: v_max_i16_e32 v10, v10, v53768; GFX8-NEXT: v_min_i16_e32 v10, v10, v113769; GFX8-NEXT: v_max_i16_sdwa v11, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3770; GFX8-NEXT: v_add_u16_e32 v11, 0x8001, v113771; GFX8-NEXT: v_min_i16_sdwa v12, v1, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3772; GFX8-NEXT: v_add_u16_e32 v12, 0x8000, v123773; GFX8-NEXT: v_max_i16_sdwa v5, v11, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13774; GFX8-NEXT: v_max_i16_e32 v11, -1, v23775; GFX8-NEXT: v_min_i16_e32 v5, v5, v123776; GFX8-NEXT: v_add_u16_e32 v11, 0x8001, v113777; GFX8-NEXT: v_min_i16_e32 v12, -1, v23778; GFX8-NEXT: v_add_u16_e32 v12, 0x8000, v123779; GFX8-NEXT: v_max_i16_e32 v11, v11, v63780; GFX8-NEXT: v_min_i16_e32 v11, v11, v123781; GFX8-NEXT: v_max_i16_sdwa v12, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3782; GFX8-NEXT: v_add_u16_e32 v12, 0x8001, v123783; GFX8-NEXT: v_min_i16_sdwa v13, v2, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3784; GFX8-NEXT: v_add_u16_e32 v13, 0x8000, v133785; GFX8-NEXT: v_max_i16_sdwa v6, v12, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13786; GFX8-NEXT: v_max_i16_e32 v12, -1, v33787; GFX8-NEXT: v_min_i16_e32 v6, v6, v133788; GFX8-NEXT: v_add_u16_e32 v12, 0x8001, v123789; GFX8-NEXT: v_min_i16_e32 v13, -1, v33790; GFX8-NEXT: v_add_u16_e32 v13, 0x8000, v133791; GFX8-NEXT: v_max_i16_e32 v12, v12, v73792; GFX8-NEXT: v_min_i16_e32 v12, v12, v133793; GFX8-NEXT: v_max_i16_sdwa v13, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3794; GFX8-NEXT: v_add_u16_e32 v13, 0x8001, v133795; GFX8-NEXT: v_min_i16_sdwa v9, v3, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3796; GFX8-NEXT: v_add_u16_e32 v9, 0x8000, v93797; GFX8-NEXT: v_max_i16_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13798; GFX8-NEXT: v_sub_u16_e32 v8, v0, v83799; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3800; GFX8-NEXT: v_sub_u16_e32 v4, v1, v103801; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3802; GFX8-NEXT: v_min_i16_e32 v7, v7, v93803; GFX8-NEXT: v_or_b32_e32 v1, v4, v13804; GFX8-NEXT: v_sub_u16_e32 v4, v2, v113805; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3806; GFX8-NEXT: v_or_b32_e32 v2, v4, v23807; GFX8-NEXT: v_sub_u16_e32 v4, v3, v123808; GFX8-NEXT: v_sub_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3809; GFX8-NEXT: v_or_b32_e32 v0, v8, v03810; GFX8-NEXT: v_or_b32_e32 v3, v4, v33811; GFX8-NEXT: s_setpc_b64 s[30:31]3812;3813; GFX9-LABEL: v_ssubsat_v8i16:3814; GFX9: ; %bb.0:3815; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3816; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 clamp3817; GFX9-NEXT: v_pk_sub_i16 v1, v1, v5 clamp3818; GFX9-NEXT: v_pk_sub_i16 v2, v2, v6 clamp3819; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7 clamp3820; GFX9-NEXT: s_setpc_b64 s[30:31]3821;3822; GFX10PLUS-LABEL: v_ssubsat_v8i16:3823; GFX10PLUS: ; %bb.0:3824; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3825; GFX10PLUS-NEXT: v_pk_sub_i16 v0, v0, v4 clamp3826; GFX10PLUS-NEXT: v_pk_sub_i16 v1, v1, v5 clamp3827; GFX10PLUS-NEXT: v_pk_sub_i16 v2, v2, v6 clamp3828; GFX10PLUS-NEXT: v_pk_sub_i16 v3, v3, v7 clamp3829; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]3830 %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)3831 %cast = bitcast <8 x i16> %result to <4 x float>3832 ret <4 x float> %cast3833}3834 3835define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {3836; GFX6-LABEL: s_ssubsat_v8i16:3837; GFX6: ; %bb.0:3838; GFX6-NEXT: s_lshl_b32 s0, s0, 163839; GFX6-NEXT: s_max_i32 s16, s0, -13840; GFX6-NEXT: s_lshl_b32 s8, s8, 163841; GFX6-NEXT: s_add_i32 s16, s16, 0x800000013842; GFX6-NEXT: s_min_i32 s17, s0, -13843; GFX6-NEXT: s_add_i32 s17, s17, 0x800000003844; GFX6-NEXT: s_max_i32 s8, s16, s83845; GFX6-NEXT: s_min_i32 s8, s8, s173846; GFX6-NEXT: s_lshl_b32 s1, s1, 163847; GFX6-NEXT: s_sub_i32 s0, s0, s83848; GFX6-NEXT: s_lshl_b32 s8, s9, 163849; GFX6-NEXT: s_max_i32 s9, s1, -13850; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013851; GFX6-NEXT: s_min_i32 s16, s1, -13852; GFX6-NEXT: s_add_i32 s16, s16, 0x800000003853; GFX6-NEXT: s_max_i32 s8, s9, s83854; GFX6-NEXT: s_lshl_b32 s2, s2, 163855; GFX6-NEXT: s_min_i32 s8, s8, s163856; GFX6-NEXT: s_max_i32 s9, s2, -13857; GFX6-NEXT: s_sub_i32 s1, s1, s83858; GFX6-NEXT: s_lshl_b32 s8, s10, 163859; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013860; GFX6-NEXT: s_min_i32 s10, s2, -13861; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003862; GFX6-NEXT: s_max_i32 s8, s9, s83863; GFX6-NEXT: s_lshl_b32 s3, s3, 163864; GFX6-NEXT: s_min_i32 s8, s8, s103865; GFX6-NEXT: s_max_i32 s9, s3, -13866; GFX6-NEXT: s_sub_i32 s2, s2, s83867; GFX6-NEXT: s_lshl_b32 s8, s11, 163868; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013869; GFX6-NEXT: s_min_i32 s10, s3, -13870; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003871; GFX6-NEXT: s_max_i32 s8, s9, s83872; GFX6-NEXT: s_lshl_b32 s4, s4, 163873; GFX6-NEXT: s_min_i32 s8, s8, s103874; GFX6-NEXT: s_max_i32 s9, s4, -13875; GFX6-NEXT: s_sub_i32 s3, s3, s83876; GFX6-NEXT: s_lshl_b32 s8, s12, 163877; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013878; GFX6-NEXT: s_min_i32 s10, s4, -13879; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003880; GFX6-NEXT: s_max_i32 s8, s9, s83881; GFX6-NEXT: s_lshl_b32 s5, s5, 163882; GFX6-NEXT: s_min_i32 s8, s8, s103883; GFX6-NEXT: s_max_i32 s9, s5, -13884; GFX6-NEXT: s_sub_i32 s4, s4, s83885; GFX6-NEXT: s_lshl_b32 s8, s13, 163886; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013887; GFX6-NEXT: s_min_i32 s10, s5, -13888; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003889; GFX6-NEXT: s_max_i32 s8, s9, s83890; GFX6-NEXT: s_lshl_b32 s6, s6, 163891; GFX6-NEXT: s_min_i32 s8, s8, s103892; GFX6-NEXT: s_max_i32 s9, s6, -13893; GFX6-NEXT: s_sub_i32 s5, s5, s83894; GFX6-NEXT: s_lshl_b32 s8, s14, 163895; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013896; GFX6-NEXT: s_min_i32 s10, s6, -13897; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003898; GFX6-NEXT: s_max_i32 s8, s9, s83899; GFX6-NEXT: s_lshl_b32 s7, s7, 163900; GFX6-NEXT: s_min_i32 s8, s8, s103901; GFX6-NEXT: s_max_i32 s9, s7, -13902; GFX6-NEXT: s_ashr_i32 s1, s1, 163903; GFX6-NEXT: s_sub_i32 s6, s6, s83904; GFX6-NEXT: s_lshl_b32 s8, s15, 163905; GFX6-NEXT: s_add_i32 s9, s9, 0x800000013906; GFX6-NEXT: s_min_i32 s10, s7, -13907; GFX6-NEXT: s_ashr_i32 s0, s0, 163908; GFX6-NEXT: s_add_i32 s10, s10, 0x800000003909; GFX6-NEXT: s_max_i32 s8, s9, s83910; GFX6-NEXT: s_and_b32 s1, s1, 0xffff3911; GFX6-NEXT: s_ashr_i32 s2, s2, 163912; GFX6-NEXT: s_ashr_i32 s3, s3, 163913; GFX6-NEXT: s_min_i32 s8, s8, s103914; GFX6-NEXT: s_and_b32 s0, s0, 0xffff3915; GFX6-NEXT: s_lshl_b32 s1, s1, 163916; GFX6-NEXT: s_ashr_i32 s5, s5, 163917; GFX6-NEXT: s_sub_i32 s7, s7, s83918; GFX6-NEXT: s_or_b32 s0, s0, s13919; GFX6-NEXT: s_and_b32 s1, s2, 0xffff3920; GFX6-NEXT: s_and_b32 s2, s3, 0xffff3921; GFX6-NEXT: s_ashr_i32 s4, s4, 163922; GFX6-NEXT: s_ashr_i32 s7, s7, 163923; GFX6-NEXT: s_lshl_b32 s2, s2, 163924; GFX6-NEXT: s_and_b32 s3, s5, 0xffff3925; GFX6-NEXT: s_ashr_i32 s6, s6, 163926; GFX6-NEXT: s_or_b32 s1, s1, s23927; GFX6-NEXT: s_and_b32 s2, s4, 0xffff3928; GFX6-NEXT: s_lshl_b32 s3, s3, 163929; GFX6-NEXT: s_and_b32 s4, s7, 0xffff3930; GFX6-NEXT: s_or_b32 s2, s2, s33931; GFX6-NEXT: s_and_b32 s3, s6, 0xffff3932; GFX6-NEXT: s_lshl_b32 s4, s4, 163933; GFX6-NEXT: s_or_b32 s3, s3, s43934; GFX6-NEXT: ; return to shader part epilog3935;3936; GFX8-LABEL: s_ssubsat_v8i16:3937; GFX8: ; %bb.0:3938; GFX8-NEXT: s_sext_i32_i16 s16, s03939; GFX8-NEXT: s_max_i32 s17, s16, -13940; GFX8-NEXT: s_add_i32 s17, s17, 0x80013941; GFX8-NEXT: s_lshr_b32 s12, s4, 163942; GFX8-NEXT: s_min_i32 s16, s16, -13943; GFX8-NEXT: s_sext_i32_i16 s17, s173944; GFX8-NEXT: s_sext_i32_i16 s4, s43945; GFX8-NEXT: s_add_i32 s16, s16, 0x80003946; GFX8-NEXT: s_max_i32 s4, s17, s43947; GFX8-NEXT: s_sext_i32_i16 s4, s43948; GFX8-NEXT: s_sext_i32_i16 s16, s163949; GFX8-NEXT: s_lshr_b32 s8, s0, 163950; GFX8-NEXT: s_min_i32 s4, s4, s163951; GFX8-NEXT: s_sub_i32 s0, s0, s43952; GFX8-NEXT: s_sext_i32_i16 s4, s83953; GFX8-NEXT: s_max_i32 s16, s4, -13954; GFX8-NEXT: s_add_i32 s16, s16, 0x80013955; GFX8-NEXT: s_min_i32 s4, s4, -13956; GFX8-NEXT: s_sext_i32_i16 s16, s163957; GFX8-NEXT: s_sext_i32_i16 s12, s123958; GFX8-NEXT: s_add_i32 s4, s4, 0x80003959; GFX8-NEXT: s_max_i32 s12, s16, s123960; GFX8-NEXT: s_sext_i32_i16 s12, s123961; GFX8-NEXT: s_sext_i32_i16 s4, s43962; GFX8-NEXT: s_min_i32 s4, s12, s43963; GFX8-NEXT: s_sub_i32 s4, s8, s43964; GFX8-NEXT: s_sext_i32_i16 s8, s13965; GFX8-NEXT: s_max_i32 s12, s8, -13966; GFX8-NEXT: s_add_i32 s12, s12, 0x80013967; GFX8-NEXT: s_lshr_b32 s13, s5, 163968; GFX8-NEXT: s_min_i32 s8, s8, -13969; GFX8-NEXT: s_sext_i32_i16 s12, s123970; GFX8-NEXT: s_sext_i32_i16 s5, s53971; GFX8-NEXT: s_add_i32 s8, s8, 0x80003972; GFX8-NEXT: s_max_i32 s5, s12, s53973; GFX8-NEXT: s_sext_i32_i16 s5, s53974; GFX8-NEXT: s_sext_i32_i16 s8, s83975; GFX8-NEXT: s_lshr_b32 s9, s1, 163976; GFX8-NEXT: s_min_i32 s5, s5, s83977; GFX8-NEXT: s_sub_i32 s1, s1, s53978; GFX8-NEXT: s_sext_i32_i16 s5, s93979; GFX8-NEXT: s_max_i32 s8, s5, -13980; GFX8-NEXT: s_add_i32 s8, s8, 0x80013981; GFX8-NEXT: s_min_i32 s5, s5, -13982; GFX8-NEXT: s_sext_i32_i16 s8, s83983; GFX8-NEXT: s_sext_i32_i16 s12, s133984; GFX8-NEXT: s_add_i32 s5, s5, 0x80003985; GFX8-NEXT: s_max_i32 s8, s8, s123986; GFX8-NEXT: s_sext_i32_i16 s8, s83987; GFX8-NEXT: s_sext_i32_i16 s5, s53988; GFX8-NEXT: s_min_i32 s5, s8, s53989; GFX8-NEXT: s_sext_i32_i16 s8, s23990; GFX8-NEXT: s_sub_i32 s5, s9, s53991; GFX8-NEXT: s_max_i32 s9, s8, -13992; GFX8-NEXT: s_add_i32 s9, s9, 0x80013993; GFX8-NEXT: s_lshr_b32 s14, s6, 163994; GFX8-NEXT: s_min_i32 s8, s8, -13995; GFX8-NEXT: s_sext_i32_i16 s9, s93996; GFX8-NEXT: s_sext_i32_i16 s6, s63997; GFX8-NEXT: s_add_i32 s8, s8, 0x80003998; GFX8-NEXT: s_max_i32 s6, s9, s63999; GFX8-NEXT: s_sext_i32_i16 s6, s64000; GFX8-NEXT: s_sext_i32_i16 s8, s84001; GFX8-NEXT: s_lshr_b32 s10, s2, 164002; GFX8-NEXT: s_min_i32 s6, s6, s84003; GFX8-NEXT: s_sub_i32 s2, s2, s64004; GFX8-NEXT: s_sext_i32_i16 s6, s104005; GFX8-NEXT: s_max_i32 s8, s6, -14006; GFX8-NEXT: s_add_i32 s8, s8, 0x80014007; GFX8-NEXT: s_min_i32 s6, s6, -14008; GFX8-NEXT: s_sext_i32_i16 s8, s84009; GFX8-NEXT: s_sext_i32_i16 s9, s144010; GFX8-NEXT: s_add_i32 s6, s6, 0x80004011; GFX8-NEXT: s_max_i32 s8, s8, s94012; GFX8-NEXT: s_sext_i32_i16 s8, s84013; GFX8-NEXT: s_sext_i32_i16 s6, s64014; GFX8-NEXT: s_min_i32 s6, s8, s64015; GFX8-NEXT: s_sext_i32_i16 s8, s34016; GFX8-NEXT: s_max_i32 s9, s8, -14017; GFX8-NEXT: s_add_i32 s9, s9, 0x80014018; GFX8-NEXT: s_lshr_b32 s15, s7, 164019; GFX8-NEXT: s_min_i32 s8, s8, -14020; GFX8-NEXT: s_sext_i32_i16 s9, s94021; GFX8-NEXT: s_sext_i32_i16 s7, s74022; GFX8-NEXT: s_add_i32 s8, s8, 0x80004023; GFX8-NEXT: s_max_i32 s7, s9, s74024; GFX8-NEXT: s_sext_i32_i16 s7, s74025; GFX8-NEXT: s_sext_i32_i16 s8, s84026; GFX8-NEXT: s_lshr_b32 s11, s3, 164027; GFX8-NEXT: s_min_i32 s7, s7, s84028; GFX8-NEXT: s_sub_i32 s3, s3, s74029; GFX8-NEXT: s_sext_i32_i16 s7, s114030; GFX8-NEXT: s_max_i32 s8, s7, -14031; GFX8-NEXT: s_add_i32 s8, s8, 0x80014032; GFX8-NEXT: s_and_b32 s4, 0xffff, s44033; GFX8-NEXT: s_min_i32 s7, s7, -14034; GFX8-NEXT: s_sext_i32_i16 s8, s84035; GFX8-NEXT: s_sext_i32_i16 s9, s154036; GFX8-NEXT: s_and_b32 s0, 0xffff, s04037; GFX8-NEXT: s_lshl_b32 s4, s4, 164038; GFX8-NEXT: s_add_i32 s7, s7, 0x80004039; GFX8-NEXT: s_max_i32 s8, s8, s94040; GFX8-NEXT: s_or_b32 s0, s0, s44041; GFX8-NEXT: s_and_b32 s4, 0xffff, s54042; GFX8-NEXT: s_sub_i32 s6, s10, s64043; GFX8-NEXT: s_sext_i32_i16 s8, s84044; GFX8-NEXT: s_sext_i32_i16 s7, s74045; GFX8-NEXT: s_and_b32 s1, 0xffff, s14046; GFX8-NEXT: s_lshl_b32 s4, s4, 164047; GFX8-NEXT: s_min_i32 s7, s8, s74048; GFX8-NEXT: s_or_b32 s1, s1, s44049; GFX8-NEXT: s_and_b32 s4, 0xffff, s64050; GFX8-NEXT: s_sub_i32 s7, s11, s74051; GFX8-NEXT: s_and_b32 s2, 0xffff, s24052; GFX8-NEXT: s_lshl_b32 s4, s4, 164053; GFX8-NEXT: s_or_b32 s2, s2, s44054; GFX8-NEXT: s_and_b32 s4, 0xffff, s74055; GFX8-NEXT: s_and_b32 s3, 0xffff, s34056; GFX8-NEXT: s_lshl_b32 s4, s4, 164057; GFX8-NEXT: s_or_b32 s3, s3, s44058; GFX8-NEXT: ; return to shader part epilog4059;4060; GFX9-LABEL: s_ssubsat_v8i16:4061; GFX9: ; %bb.0:4062; GFX9-NEXT: v_mov_b32_e32 v0, s44063; GFX9-NEXT: v_mov_b32_e32 v1, s54064; GFX9-NEXT: v_mov_b32_e32 v2, s64065; GFX9-NEXT: v_mov_b32_e32 v3, s74066; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp4067; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp4068; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp4069; GFX9-NEXT: v_pk_sub_i16 v3, s3, v3 clamp4070; GFX9-NEXT: v_readfirstlane_b32 s0, v04071; GFX9-NEXT: v_readfirstlane_b32 s1, v14072; GFX9-NEXT: v_readfirstlane_b32 s2, v24073; GFX9-NEXT: v_readfirstlane_b32 s3, v34074; GFX9-NEXT: ; return to shader part epilog4075;4076; GFX10PLUS-LABEL: s_ssubsat_v8i16:4077; GFX10PLUS: ; %bb.0:4078; GFX10PLUS-NEXT: v_pk_sub_i16 v0, s0, s4 clamp4079; GFX10PLUS-NEXT: v_pk_sub_i16 v1, s1, s5 clamp4080; GFX10PLUS-NEXT: v_pk_sub_i16 v2, s2, s6 clamp4081; GFX10PLUS-NEXT: v_pk_sub_i16 v3, s3, s7 clamp4082; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v04083; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v14084; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v24085; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v34086; GFX10PLUS-NEXT: ; return to shader part epilog4087 %result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)4088 %cast = bitcast <8 x i16> %result to <4 x i32>4089 ret <4 x i32> %cast4090}4091 4092define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {4093; GFX6-LABEL: v_ssubsat_i48:4094; GFX6: ; %bb.0:4095; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4096; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v24097; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v1, v3, vcc4098; GFX6-NEXT: v_bfe_i32 v5, v4, 0, 164099; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 164100; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 164101; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]4102; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]4103; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v54104; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0xffff8000, v04105; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v54106; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4107; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc4108; GFX6-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc4109; GFX6-NEXT: s_setpc_b64 s[30:31]4110;4111; GFX8-LABEL: v_ssubsat_i48:4112; GFX8: ; %bb.0:4113; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4114; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v24115; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v1, v3, vcc4116; GFX8-NEXT: v_bfe_i32 v5, v4, 0, 164117; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 164118; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 164119; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]4120; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]4121; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v54122; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0xffff8000, v04123; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v54124; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4125; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v1, vcc4126; GFX8-NEXT: v_cndmask_b32_e32 v1, v6, v2, vcc4127; GFX8-NEXT: s_setpc_b64 s[30:31]4128;4129; GFX9-LABEL: v_ssubsat_i48:4130; GFX9: ; %bb.0:4131; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4132; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4133; GFX9-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]4134; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v24135; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc4136; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]4137; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]4138; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v54139; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04140; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc4141; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4142; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4143; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4144; GFX9-NEXT: s_setpc_b64 s[30:31]4145;4146; GFX10-LABEL: v_ssubsat_i48:4147; GFX10: ; %bb.0:4148; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4149; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4150; GFX10-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]4151; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v24152; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo4153; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]4154; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v54155; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]4156; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v64157; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s44158; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo4159; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo4160; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4161; GFX10-NEXT: s_setpc_b64 s[30:31]4162;4163; GFX11-LABEL: v_ssubsat_i48:4164; GFX11: ; %bb.0:4165; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4166; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4167; GFX11-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]4168; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v24169; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo4170; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]4171; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v54172; GFX11-NEXT: v_cmp_lt_i64_e64 s0, v[4:5], v[0:1]4173; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v64174; GFX11-NEXT: s_xor_b32 vcc_lo, vcc_lo, s04175; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v14176; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4177; GFX11-NEXT: s_setpc_b64 s[30:31]4178 %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)4179 ret i48 %result4180}4181 4182define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {4183; GFX6-LABEL: s_ssubsat_i48:4184; GFX6: ; %bb.0:4185; GFX6-NEXT: s_sub_u32 s4, s0, s24186; GFX6-NEXT: s_subb_u32 s3, s1, s34187; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004188; GFX6-NEXT: v_mov_b32_e32 v0, s04189; GFX6-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x3000004190; GFX6-NEXT: v_mov_b32_e32 v1, s14191; GFX6-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x3000004192; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]4193; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04194; GFX6-NEXT: s_ashr_i32 s2, s7, 314195; GFX6-NEXT: s_ashr_i32 s5, s7, 154196; GFX6-NEXT: s_addk_i32 s2, 0x80004197; GFX6-NEXT: v_mov_b32_e32 v0, s54198; GFX6-NEXT: v_mov_b32_e32 v1, s24199; GFX6-NEXT: v_mov_b32_e32 v2, s44200; GFX6-NEXT: v_mov_b32_e32 v3, s34201; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc4202; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4203; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4204; GFX6-NEXT: v_readfirstlane_b32 s0, v04205; GFX6-NEXT: v_readfirstlane_b32 s1, v14206; GFX6-NEXT: ; return to shader part epilog4207;4208; GFX8-LABEL: s_ssubsat_i48:4209; GFX8: ; %bb.0:4210; GFX8-NEXT: s_sub_u32 s4, s0, s24211; GFX8-NEXT: s_subb_u32 s3, s1, s34212; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004213; GFX8-NEXT: v_mov_b32_e32 v0, s04214; GFX8-NEXT: s_bfe_i64 s[6:7], s[4:5], 0x3000004215; GFX8-NEXT: v_mov_b32_e32 v1, s14216; GFX8-NEXT: s_bfe_i64 s[0:1], s[2:3], 0x3000004217; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[6:7], v[0:1]4218; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04219; GFX8-NEXT: s_ashr_i32 s2, s7, 314220; GFX8-NEXT: s_ashr_i32 s5, s7, 154221; GFX8-NEXT: s_addk_i32 s2, 0x80004222; GFX8-NEXT: v_mov_b32_e32 v0, s54223; GFX8-NEXT: v_mov_b32_e32 v1, s24224; GFX8-NEXT: v_mov_b32_e32 v2, s44225; GFX8-NEXT: v_mov_b32_e32 v3, s34226; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc4227; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4228; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4229; GFX8-NEXT: v_readfirstlane_b32 s0, v04230; GFX8-NEXT: v_readfirstlane_b32 s1, v14231; GFX8-NEXT: ; return to shader part epilog4232;4233; GFX9-LABEL: s_ssubsat_i48:4234; GFX9: ; %bb.0:4235; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 164236; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 164237; GFX9-NEXT: s_sub_u32 s4, s0, s24238; GFX9-NEXT: v_mov_b32_e32 v0, s04239; GFX9-NEXT: s_subb_u32 s5, s1, s34240; GFX9-NEXT: v_mov_b32_e32 v1, s14241; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]4242; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 04243; GFX9-NEXT: s_ashr_i32 s2, s5, 314244; GFX9-NEXT: s_add_i32 s3, s2, 0x800000004245; GFX9-NEXT: v_mov_b32_e32 v0, s24246; GFX9-NEXT: v_mov_b32_e32 v1, s34247; GFX9-NEXT: v_mov_b32_e32 v2, s44248; GFX9-NEXT: v_mov_b32_e32 v3, s54249; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4250; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4251; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4252; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4253; GFX9-NEXT: v_readfirstlane_b32 s0, v04254; GFX9-NEXT: v_readfirstlane_b32 s1, v14255; GFX9-NEXT: ; return to shader part epilog4256;4257; GFX10-LABEL: s_ssubsat_i48:4258; GFX10: ; %bb.0:4259; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 164260; GFX10-NEXT: s_lshl_b64 s[2:3], s[2:3], 164261; GFX10-NEXT: s_sub_u32 s4, s0, s24262; GFX10-NEXT: s_subb_u32 s5, s1, s34263; GFX10-NEXT: v_mov_b32_e32 v0, s44264; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]4265; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 04266; GFX10-NEXT: v_mov_b32_e32 v1, s54267; GFX10-NEXT: s_ashr_i32 s2, s5, 314268; GFX10-NEXT: s_add_i32 s3, s2, 0x800000004269; GFX10-NEXT: s_xor_b32 s0, s1, s04270; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, s04271; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, s04272; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4273; GFX10-NEXT: v_readfirstlane_b32 s0, v04274; GFX10-NEXT: v_readfirstlane_b32 s1, v14275; GFX10-NEXT: ; return to shader part epilog4276;4277; GFX11-LABEL: s_ssubsat_i48:4278; GFX11: ; %bb.0:4279; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 164280; GFX11-NEXT: s_lshl_b64 s[2:3], s[2:3], 164281; GFX11-NEXT: s_sub_u32 s4, s0, s24282; GFX11-NEXT: s_subb_u32 s5, s1, s34283; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s54284; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]4285; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 04286; GFX11-NEXT: s_ashr_i32 s2, s5, 314287; GFX11-NEXT: s_add_i32 s3, s2, 0x800000004288; GFX11-NEXT: s_xor_b32 s0, s1, s04289; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, s04290; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, s04291; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4292; GFX11-NEXT: v_readfirstlane_b32 s0, v04293; GFX11-NEXT: v_readfirstlane_b32 s1, v14294; GFX11-NEXT: ; return to shader part epilog4295 %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)4296 ret i48 %result4297}4298 4299define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {4300; GFX6-LABEL: ssubsat_i48_sv:4301; GFX6: ; %bb.0:4302; GFX6-NEXT: v_mov_b32_e32 v3, s14303; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v04304; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc4305; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 164306; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004307; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 164308; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]4309; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]4310; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v34311; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v34312; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v04313; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]4314; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4315; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc4316; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v14317; GFX6-NEXT: ; return to shader part epilog4318;4319; GFX8-LABEL: ssubsat_i48_sv:4320; GFX8: ; %bb.0:4321; GFX8-NEXT: v_mov_b32_e32 v3, s14322; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v04323; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v3, v1, vcc4324; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 164325; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004326; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 164327; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]4328; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]4329; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v34330; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v34331; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v04332; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]4333; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4334; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc4335; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v14336; GFX8-NEXT: ; return to shader part epilog4337;4338; GFX9-LABEL: ssubsat_i48_sv:4339; GFX9: ; %bb.0:4340; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4341; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 164342; GFX9-NEXT: v_mov_b32_e32 v3, s14343; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v04344; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc4345; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]4346; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]4347; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v34348; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04349; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4350; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4351; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4352; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4353; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v14354; GFX9-NEXT: ; return to shader part epilog4355;4356; GFX10-LABEL: ssubsat_i48_sv:4357; GFX10: ; %bb.0:4358; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4359; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 164360; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v04361; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo4362; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v34363; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]4364; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]4365; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44366; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4367; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo4368; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo4369; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4370; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v14371; GFX10-NEXT: ; return to shader part epilog4372;4373; GFX11-LABEL: ssubsat_i48_sv:4374; GFX11: ; %bb.0:4375; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4376; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 164377; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v04378; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, s1, v1, vcc_lo4379; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v34380; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]4381; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]4382; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44383; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4384; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v14385; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4386; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v14387; GFX11-NEXT: ; return to shader part epilog4388 %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)4389 %ext.result = zext i48 %result to i644390 %cast = bitcast i64 %ext.result to <2 x float>4391 ret <2 x float> %cast4392}4393 4394define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {4395; GFX6-LABEL: ssubsat_i48_vs:4396; GFX6: ; %bb.0:4397; GFX6-NEXT: v_mov_b32_e32 v3, s14398; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v04399; GFX6-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc4400; GFX6-NEXT: v_bfe_i32 v3, v2, 0, 164401; GFX6-NEXT: v_bfe_i32 v1, v0, 0, 164402; GFX6-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004403; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]4404; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04405; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v34406; GFX6-NEXT: v_ashrrev_i32_e32 v1, 15, v34407; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0xffff8000, v04408; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]4409; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4410; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc4411; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v14412; GFX6-NEXT: ; return to shader part epilog4413;4414; GFX8-LABEL: ssubsat_i48_vs:4415; GFX8: ; %bb.0:4416; GFX8-NEXT: v_mov_b32_e32 v3, s14417; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v04418; GFX8-NEXT: v_subb_u32_e32 v4, vcc, v1, v3, vcc4419; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 164420; GFX8-NEXT: v_bfe_i32 v1, v0, 0, 164421; GFX8-NEXT: s_bfe_i64 s[0:1], s[0:1], 0x3000004422; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]4423; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04424; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v34425; GFX8-NEXT: v_ashrrev_i32_e32 v1, 15, v34426; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0xffff8000, v04427; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]4428; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc4429; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v3, vcc4430; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v14431; GFX8-NEXT: ; return to shader part epilog4432;4433; GFX9-LABEL: ssubsat_i48_vs:4434; GFX9: ; %bb.0:4435; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4436; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 164437; GFX9-NEXT: v_mov_b32_e32 v3, s14438; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v04439; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc4440; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]4441; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04442; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v34443; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04444; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4445; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4446; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4447; GFX9-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4448; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v14449; GFX9-NEXT: ; return to shader part epilog4450;4451; GFX10-LABEL: ssubsat_i48_vs:4452; GFX10: ; %bb.0:4453; GFX10-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4454; GFX10-NEXT: s_lshl_b64 s[0:1], s[0:1], 164455; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s04456; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo4457; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 04458; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v34459; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]4460; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44461; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4462; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo4463; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo4464; GFX10-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4465; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v14466; GFX10-NEXT: ; return to shader part epilog4467;4468; GFX11-LABEL: ssubsat_i48_vs:4469; GFX11: ; %bb.0:4470; GFX11-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]4471; GFX11-NEXT: s_lshl_b64 s[0:1], s[0:1], 164472; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s04473; GFX11-NEXT: v_subrev_co_ci_u32_e64 v3, null, s1, v1, vcc_lo4474; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 04475; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v34476; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]4477; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44478; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4479; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v14480; GFX11-NEXT: v_ashrrev_i64 v[0:1], 16, v[0:1]4481; GFX11-NEXT: v_and_b32_e32 v1, 0xffff, v14482; GFX11-NEXT: ; return to shader part epilog4483 %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)4484 %ext.result = zext i48 %result to i644485 %cast = bitcast i64 %ext.result to <2 x float>4486 ret <2 x float> %cast4487}4488 4489define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {4490; GFX6-LABEL: v_ssubsat_i64:4491; GFX6: ; %bb.0:4492; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4493; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v24494; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc4495; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]4496; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]4497; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v54498; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v04499; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4500; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4501; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4502; GFX6-NEXT: s_setpc_b64 s[30:31]4503;4504; GFX8-LABEL: v_ssubsat_i64:4505; GFX8: ; %bb.0:4506; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4507; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v24508; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc4509; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[0:1]4510; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[2:3]4511; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v54512; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v04513; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4514; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4515; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4516; GFX8-NEXT: s_setpc_b64 s[30:31]4517;4518; GFX9-LABEL: v_ssubsat_i64:4519; GFX9: ; %bb.0:4520; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4521; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v24522; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc4523; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]4524; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]4525; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v54526; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04527; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc4528; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4529; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4530; GFX9-NEXT: s_setpc_b64 s[30:31]4531;4532; GFX10-LABEL: v_ssubsat_i64:4533; GFX10: ; %bb.0:4534; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4535; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v24536; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo4537; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[2:3]4538; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v54539; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]4540; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v64541; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo4542; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc_lo4543; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo4544; GFX10-NEXT: s_setpc_b64 s[30:31]4545;4546; GFX11-LABEL: v_ssubsat_i64:4547; GFX11: ; %bb.0:4548; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4549; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v24550; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, null, v1, v3, vcc_lo4551; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[2:3]4552; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v54553; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[4:5], v[0:1]4554; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v64555; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4556; GFX11-NEXT: v_dual_cndmask_b32 v0, v4, v6 :: v_dual_cndmask_b32 v1, v5, v14557; GFX11-NEXT: s_setpc_b64 s[30:31]4558 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)4559 ret i64 %result4560}4561 4562define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {4563; GFX6-LABEL: s_ssubsat_i64:4564; GFX6: ; %bb.0:4565; GFX6-NEXT: s_sub_u32 s4, s0, s24566; GFX6-NEXT: v_mov_b32_e32 v0, s04567; GFX6-NEXT: s_subb_u32 s5, s1, s34568; GFX6-NEXT: v_mov_b32_e32 v1, s14569; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]4570; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 04571; GFX6-NEXT: s_ashr_i32 s2, s5, 314572; GFX6-NEXT: s_add_i32 s3, s2, 0x800000004573; GFX6-NEXT: v_mov_b32_e32 v0, s24574; GFX6-NEXT: v_mov_b32_e32 v1, s34575; GFX6-NEXT: v_mov_b32_e32 v2, s44576; GFX6-NEXT: v_mov_b32_e32 v3, s54577; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc4578; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4579; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4580; GFX6-NEXT: v_readfirstlane_b32 s0, v04581; GFX6-NEXT: v_readfirstlane_b32 s1, v14582; GFX6-NEXT: ; return to shader part epilog4583;4584; GFX8-LABEL: s_ssubsat_i64:4585; GFX8: ; %bb.0:4586; GFX8-NEXT: s_sub_u32 s4, s0, s24587; GFX8-NEXT: v_mov_b32_e32 v0, s04588; GFX8-NEXT: s_subb_u32 s5, s1, s34589; GFX8-NEXT: v_mov_b32_e32 v1, s14590; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]4591; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 04592; GFX8-NEXT: s_ashr_i32 s2, s5, 314593; GFX8-NEXT: s_add_i32 s3, s2, 0x800000004594; GFX8-NEXT: v_mov_b32_e32 v0, s24595; GFX8-NEXT: v_mov_b32_e32 v1, s34596; GFX8-NEXT: v_mov_b32_e32 v2, s44597; GFX8-NEXT: v_mov_b32_e32 v3, s54598; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc4599; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4600; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4601; GFX8-NEXT: v_readfirstlane_b32 s0, v04602; GFX8-NEXT: v_readfirstlane_b32 s1, v14603; GFX8-NEXT: ; return to shader part epilog4604;4605; GFX9-LABEL: s_ssubsat_i64:4606; GFX9: ; %bb.0:4607; GFX9-NEXT: s_sub_u32 s4, s0, s24608; GFX9-NEXT: v_mov_b32_e32 v0, s04609; GFX9-NEXT: s_subb_u32 s5, s1, s34610; GFX9-NEXT: v_mov_b32_e32 v1, s14611; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]4612; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 04613; GFX9-NEXT: s_ashr_i32 s2, s5, 314614; GFX9-NEXT: s_add_i32 s3, s2, 0x800000004615; GFX9-NEXT: v_mov_b32_e32 v0, s24616; GFX9-NEXT: v_mov_b32_e32 v1, s34617; GFX9-NEXT: v_mov_b32_e32 v2, s44618; GFX9-NEXT: v_mov_b32_e32 v3, s54619; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4620; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4621; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4622; GFX9-NEXT: v_readfirstlane_b32 s0, v04623; GFX9-NEXT: v_readfirstlane_b32 s1, v14624; GFX9-NEXT: ; return to shader part epilog4625;4626; GFX10-LABEL: s_ssubsat_i64:4627; GFX10: ; %bb.0:4628; GFX10-NEXT: s_sub_u32 s4, s0, s24629; GFX10-NEXT: s_subb_u32 s5, s1, s34630; GFX10-NEXT: v_mov_b32_e32 v0, s44631; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]4632; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 04633; GFX10-NEXT: v_mov_b32_e32 v1, s54634; GFX10-NEXT: s_ashr_i32 s2, s5, 314635; GFX10-NEXT: s_add_i32 s3, s2, 0x800000004636; GFX10-NEXT: s_xor_b32 s0, s1, s04637; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, s04638; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s3, s04639; GFX10-NEXT: v_readfirstlane_b32 s0, v04640; GFX10-NEXT: v_readfirstlane_b32 s1, v14641; GFX10-NEXT: ; return to shader part epilog4642;4643; GFX11-LABEL: s_ssubsat_i64:4644; GFX11: ; %bb.0:4645; GFX11-NEXT: s_sub_u32 s4, s0, s24646; GFX11-NEXT: s_subb_u32 s5, s1, s34647; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s54648; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]4649; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 04650; GFX11-NEXT: s_ashr_i32 s2, s5, 314651; GFX11-NEXT: s_add_i32 s3, s2, 0x800000004652; GFX11-NEXT: s_xor_b32 s0, s1, s04653; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, s04654; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, s04655; GFX11-NEXT: v_readfirstlane_b32 s0, v04656; GFX11-NEXT: v_readfirstlane_b32 s1, v14657; GFX11-NEXT: ; return to shader part epilog4658 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)4659 ret i64 %result4660}4661 4662define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {4663; GFX6-LABEL: ssubsat_i64_sv:4664; GFX6: ; %bb.0:4665; GFX6-NEXT: v_mov_b32_e32 v3, s14666; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v04667; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc4668; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]4669; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]4670; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v34671; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v04672; GFX6-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]4673; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4674; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4675; GFX6-NEXT: ; return to shader part epilog4676;4677; GFX8-LABEL: ssubsat_i64_sv:4678; GFX8: ; %bb.0:4679; GFX8-NEXT: v_mov_b32_e32 v3, s14680; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v04681; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc4682; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], v[2:3]4683; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], 0, v[0:1]4684; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v34685; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v04686; GFX8-NEXT: s_xor_b64 vcc, s[2:3], s[0:1]4687; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4688; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4689; GFX8-NEXT: ; return to shader part epilog4690;4691; GFX9-LABEL: ssubsat_i64_sv:4692; GFX9: ; %bb.0:4693; GFX9-NEXT: v_mov_b32_e32 v3, s14694; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v04695; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc4696; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]4697; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]4698; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v34699; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04700; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4701; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4702; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4703; GFX9-NEXT: ; return to shader part epilog4704;4705; GFX10-LABEL: ssubsat_i64_sv:4706; GFX10: ; %bb.0:4707; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v04708; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo4709; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v34710; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]4711; GFX10-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]4712; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44713; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4714; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo4715; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo4716; GFX10-NEXT: ; return to shader part epilog4717;4718; GFX11-LABEL: ssubsat_i64_sv:4719; GFX11: ; %bb.0:4720; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v04721; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, null, s1, v1, vcc_lo4722; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v34723; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[0:1], v[2:3]4724; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[0:1]4725; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44726; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4727; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v14728; GFX11-NEXT: ; return to shader part epilog4729 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)4730 %cast = bitcast i64 %result to <2 x float>4731 ret <2 x float> %cast4732}4733 4734define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {4735; GFX6-LABEL: ssubsat_i64_vs:4736; GFX6: ; %bb.0:4737; GFX6-NEXT: v_mov_b32_e32 v3, s14738; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v04739; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc4740; GFX6-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]4741; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04742; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v34743; GFX6-NEXT: v_add_i32_e32 v1, vcc, 0x80000000, v04744; GFX6-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]4745; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4746; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4747; GFX6-NEXT: ; return to shader part epilog4748;4749; GFX8-LABEL: ssubsat_i64_vs:4750; GFX8: ; %bb.0:4751; GFX8-NEXT: v_mov_b32_e32 v3, s14752; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v04753; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc4754; GFX8-NEXT: v_cmp_lt_i64_e64 s[2:3], v[2:3], v[0:1]4755; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04756; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v34757; GFX8-NEXT: v_add_u32_e32 v1, vcc, 0x80000000, v04758; GFX8-NEXT: s_xor_b64 vcc, s[0:1], s[2:3]4759; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4760; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4761; GFX8-NEXT: ; return to shader part epilog4762;4763; GFX9-LABEL: ssubsat_i64_vs:4764; GFX9: ; %bb.0:4765; GFX9-NEXT: v_mov_b32_e32 v3, s14766; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v04767; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc4768; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]4769; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[0:1], 04770; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v34771; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04772; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc4773; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc4774; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc4775; GFX9-NEXT: ; return to shader part epilog4776;4777; GFX10-LABEL: ssubsat_i64_vs:4778; GFX10: ; %bb.0:4779; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s04780; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo4781; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 04782; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v34783; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]4784; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44785; GFX10-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4786; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc_lo4787; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo4788; GFX10-NEXT: ; return to shader part epilog4789;4790; GFX11-LABEL: ssubsat_i64_vs:4791; GFX11: ; %bb.0:4792; GFX11-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s04793; GFX11-NEXT: v_subrev_co_ci_u32_e64 v3, null, s1, v1, vcc_lo4794; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], 04795; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v34796; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]4797; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v44798; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4799; GFX11-NEXT: v_dual_cndmask_b32 v0, v2, v4 :: v_dual_cndmask_b32 v1, v3, v14800; GFX11-NEXT: ; return to shader part epilog4801 %result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)4802 %cast = bitcast i64 %result to <2 x float>4803 ret <2 x float> %cast4804}4805 4806define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {4807; GFX6-LABEL: v_ssubsat_v2i64:4808; GFX6: ; %bb.0:4809; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4810; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v0, v44811; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc4812; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]4813; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]4814; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v94815; GFX6-NEXT: v_bfrev_b32_e32 v1, 14816; GFX6-NEXT: v_add_i32_e32 v1, vcc, v0, v14817; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4818; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc4819; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc4820; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v2, v64821; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc4822; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[2:3]4823; GFX6-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[6:7]4824; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v54825; GFX6-NEXT: v_add_i32_e32 v3, vcc, 0x80000000, v24826; GFX6-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4827; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc4828; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc4829; GFX6-NEXT: s_setpc_b64 s[30:31]4830;4831; GFX8-LABEL: v_ssubsat_v2i64:4832; GFX8: ; %bb.0:4833; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4834; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v0, v44835; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc4836; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[8:9], v[0:1]4837; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[4:5]4838; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v94839; GFX8-NEXT: v_bfrev_b32_e32 v1, 14840; GFX8-NEXT: v_add_u32_e32 v1, vcc, v0, v14841; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4842; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc4843; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc4844; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v2, v64845; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc4846; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], v[4:5], v[2:3]4847; GFX8-NEXT: v_cmp_lt_i64_e64 s[6:7], 0, v[6:7]4848; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v54849; GFX8-NEXT: v_add_u32_e32 v3, vcc, 0x80000000, v24850; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]4851; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc4852; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc4853; GFX8-NEXT: s_setpc_b64 s[30:31]4854;4855; GFX9-LABEL: v_ssubsat_v2i64:4856; GFX9: ; %bb.0:4857; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4858; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v44859; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v5, vcc4860; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]4861; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]4862; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v94863; GFX9-NEXT: v_add_u32_e32 v1, 0x80000000, v04864; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc4865; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v0, vcc4866; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc4867; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v2, v64868; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v7, vcc4869; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]4870; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]4871; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v54872; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v24873; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc4874; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc4875; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc4876; GFX9-NEXT: s_setpc_b64 s[30:31]4877;4878; GFX10-LABEL: v_ssubsat_v2i64:4879; GFX10: ; %bb.0:4880; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4881; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v44882; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo4883; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v64884; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo4885; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v94886; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]4887; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5]4888; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v114889; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[2:3]4890; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7]4891; GFX10-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v124892; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v44893; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo4894; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v12, vcc_lo4895; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc_lo4896; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s54897; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v4, vcc_lo4898; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo4899; GFX10-NEXT: s_setpc_b64 s[30:31]4900;4901; GFX11-LABEL: v_ssubsat_v2i64:4902; GFX11: ; %bb.0:4903; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4904; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v44905; GFX11-NEXT: v_sub_co_ci_u32_e64 v9, null, v1, v5, vcc_lo4906; GFX11-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v64907; GFX11-NEXT: v_sub_co_ci_u32_e64 v11, null, v3, v7, vcc_lo4908; GFX11-NEXT: v_ashrrev_i32_e32 v12, 31, v94909; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]4910; GFX11-NEXT: v_cmp_lt_i64_e64 s0, 0, v[4:5]4911; GFX11-NEXT: v_ashrrev_i32_e32 v4, 31, v114912; GFX11-NEXT: v_cmp_lt_i64_e64 s1, v[10:11], v[2:3]4913; GFX11-NEXT: v_cmp_lt_i64_e64 s2, 0, v[6:7]4914; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x80000000, v124915; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v44916; GFX11-NEXT: s_xor_b32 vcc_lo, s0, vcc_lo4917; GFX11-NEXT: v_dual_cndmask_b32 v0, v8, v12 :: v_dual_cndmask_b32 v1, v9, v14918; GFX11-NEXT: s_xor_b32 vcc_lo, s2, s14919; GFX11-NEXT: v_dual_cndmask_b32 v2, v10, v4 :: v_dual_cndmask_b32 v3, v11, v34920; GFX11-NEXT: s_setpc_b64 s[30:31]4921 %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)4922 ret <2 x i64> %result4923}4924 4925define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {4926; GFX6-LABEL: s_ssubsat_v2i64:4927; GFX6: ; %bb.0:4928; GFX6-NEXT: s_sub_u32 s8, s0, s44929; GFX6-NEXT: v_mov_b32_e32 v0, s04930; GFX6-NEXT: s_subb_u32 s9, s1, s54931; GFX6-NEXT: v_mov_b32_e32 v1, s14932; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]4933; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 04934; GFX6-NEXT: s_ashr_i32 s4, s9, 314935; GFX6-NEXT: s_add_i32 s5, s4, 0x800000004936; GFX6-NEXT: v_mov_b32_e32 v0, s44937; GFX6-NEXT: v_mov_b32_e32 v1, s54938; GFX6-NEXT: v_mov_b32_e32 v2, s84939; GFX6-NEXT: v_mov_b32_e32 v3, s94940; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc4941; GFX6-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc4942; GFX6-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc4943; GFX6-NEXT: s_sub_u32 s0, s2, s64944; GFX6-NEXT: v_mov_b32_e32 v0, s24945; GFX6-NEXT: s_subb_u32 s1, s3, s74946; GFX6-NEXT: v_mov_b32_e32 v1, s34947; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]4948; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 04949; GFX6-NEXT: s_ashr_i32 s4, s1, 314950; GFX6-NEXT: s_add_i32 s5, s4, 0x800000004951; GFX6-NEXT: v_mov_b32_e32 v0, s44952; GFX6-NEXT: v_mov_b32_e32 v1, s54953; GFX6-NEXT: v_mov_b32_e32 v4, s04954; GFX6-NEXT: v_mov_b32_e32 v5, s14955; GFX6-NEXT: s_xor_b64 vcc, s[2:3], vcc4956; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4957; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4958; GFX6-NEXT: v_readfirstlane_b32 s0, v24959; GFX6-NEXT: v_readfirstlane_b32 s1, v34960; GFX6-NEXT: v_readfirstlane_b32 s2, v04961; GFX6-NEXT: v_readfirstlane_b32 s3, v14962; GFX6-NEXT: ; return to shader part epilog4963;4964; GFX8-LABEL: s_ssubsat_v2i64:4965; GFX8: ; %bb.0:4966; GFX8-NEXT: s_sub_u32 s8, s0, s44967; GFX8-NEXT: v_mov_b32_e32 v0, s04968; GFX8-NEXT: s_subb_u32 s9, s1, s54969; GFX8-NEXT: v_mov_b32_e32 v1, s14970; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]4971; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 04972; GFX8-NEXT: s_ashr_i32 s4, s9, 314973; GFX8-NEXT: s_add_i32 s5, s4, 0x800000004974; GFX8-NEXT: v_mov_b32_e32 v0, s44975; GFX8-NEXT: v_mov_b32_e32 v1, s54976; GFX8-NEXT: v_mov_b32_e32 v2, s84977; GFX8-NEXT: v_mov_b32_e32 v3, s94978; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc4979; GFX8-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc4980; GFX8-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc4981; GFX8-NEXT: s_sub_u32 s0, s2, s64982; GFX8-NEXT: v_mov_b32_e32 v0, s24983; GFX8-NEXT: s_subb_u32 s1, s3, s74984; GFX8-NEXT: v_mov_b32_e32 v1, s34985; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]4986; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 04987; GFX8-NEXT: s_ashr_i32 s4, s1, 314988; GFX8-NEXT: s_add_i32 s5, s4, 0x800000004989; GFX8-NEXT: v_mov_b32_e32 v0, s44990; GFX8-NEXT: v_mov_b32_e32 v1, s54991; GFX8-NEXT: v_mov_b32_e32 v4, s04992; GFX8-NEXT: v_mov_b32_e32 v5, s14993; GFX8-NEXT: s_xor_b64 vcc, s[2:3], vcc4994; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc4995; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc4996; GFX8-NEXT: v_readfirstlane_b32 s0, v24997; GFX8-NEXT: v_readfirstlane_b32 s1, v34998; GFX8-NEXT: v_readfirstlane_b32 s2, v04999; GFX8-NEXT: v_readfirstlane_b32 s3, v15000; GFX8-NEXT: ; return to shader part epilog5001;5002; GFX9-LABEL: s_ssubsat_v2i64:5003; GFX9: ; %bb.0:5004; GFX9-NEXT: s_sub_u32 s8, s0, s45005; GFX9-NEXT: v_mov_b32_e32 v0, s05006; GFX9-NEXT: s_subb_u32 s9, s1, s55007; GFX9-NEXT: v_mov_b32_e32 v1, s15008; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]5009; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 05010; GFX9-NEXT: s_ashr_i32 s4, s9, 315011; GFX9-NEXT: s_add_i32 s5, s4, 0x800000005012; GFX9-NEXT: v_mov_b32_e32 v0, s45013; GFX9-NEXT: v_mov_b32_e32 v1, s55014; GFX9-NEXT: v_mov_b32_e32 v2, s85015; GFX9-NEXT: v_mov_b32_e32 v3, s95016; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc5017; GFX9-NEXT: v_cndmask_b32_e32 v2, v2, v0, vcc5018; GFX9-NEXT: v_cndmask_b32_e32 v3, v3, v1, vcc5019; GFX9-NEXT: s_sub_u32 s0, s2, s65020; GFX9-NEXT: v_mov_b32_e32 v0, s25021; GFX9-NEXT: s_subb_u32 s1, s3, s75022; GFX9-NEXT: v_mov_b32_e32 v1, s35023; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]5024; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 05025; GFX9-NEXT: s_ashr_i32 s4, s1, 315026; GFX9-NEXT: s_add_i32 s5, s4, 0x800000005027; GFX9-NEXT: v_mov_b32_e32 v0, s45028; GFX9-NEXT: v_mov_b32_e32 v1, s55029; GFX9-NEXT: v_mov_b32_e32 v4, s05030; GFX9-NEXT: v_mov_b32_e32 v5, s15031; GFX9-NEXT: s_xor_b64 vcc, s[2:3], vcc5032; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc5033; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc5034; GFX9-NEXT: v_readfirstlane_b32 s0, v25035; GFX9-NEXT: v_readfirstlane_b32 s1, v35036; GFX9-NEXT: v_readfirstlane_b32 s2, v05037; GFX9-NEXT: v_readfirstlane_b32 s3, v15038; GFX9-NEXT: ; return to shader part epilog5039;5040; GFX10-LABEL: s_ssubsat_v2i64:5041; GFX10: ; %bb.0:5042; GFX10-NEXT: s_sub_u32 s8, s0, s45043; GFX10-NEXT: s_subb_u32 s9, s1, s55044; GFX10-NEXT: v_mov_b32_e32 v0, s85045; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]5046; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[4:5], 05047; GFX10-NEXT: s_ashr_i32 s4, s9, 315048; GFX10-NEXT: v_mov_b32_e32 v1, s95049; GFX10-NEXT: s_add_i32 s8, s4, 0x800000005050; GFX10-NEXT: s_xor_b32 s5, s1, s05051; GFX10-NEXT: s_sub_u32 s0, s2, s65052; GFX10-NEXT: s_subb_u32 s1, s3, s75053; GFX10-NEXT: v_mov_b32_e32 v2, s05054; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[0:1], s[2:3]5055; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 05056; GFX10-NEXT: v_mov_b32_e32 v3, s15057; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s4, s55058; GFX10-NEXT: s_ashr_i32 s4, s1, 315059; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, s55060; GFX10-NEXT: s_add_i32 s0, s4, 0x800000005061; GFX10-NEXT: s_xor_b32 s1, s3, s25062; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s4, s15063; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s0, s15064; GFX10-NEXT: v_readfirstlane_b32 s0, v05065; GFX10-NEXT: v_readfirstlane_b32 s1, v15066; GFX10-NEXT: v_readfirstlane_b32 s2, v25067; GFX10-NEXT: v_readfirstlane_b32 s3, v35068; GFX10-NEXT: ; return to shader part epilog5069;5070; GFX11-LABEL: s_ssubsat_v2i64:5071; GFX11: ; %bb.0:5072; GFX11-NEXT: s_sub_u32 s8, s0, s45073; GFX11-NEXT: s_subb_u32 s9, s1, s55074; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s95075; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]5076; GFX11-NEXT: v_cmp_gt_i64_e64 s1, s[4:5], 05077; GFX11-NEXT: s_ashr_i32 s4, s9, 315078; GFX11-NEXT: s_add_i32 s8, s4, 0x800000005079; GFX11-NEXT: s_xor_b32 s5, s1, s05080; GFX11-NEXT: s_sub_u32 s0, s2, s65081; GFX11-NEXT: s_subb_u32 s1, s3, s75082; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s15083; GFX11-NEXT: v_cmp_lt_i64_e64 s2, s[0:1], s[2:3]5084; GFX11-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 05085; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s4, s55086; GFX11-NEXT: s_ashr_i32 s4, s1, 315087; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, s55088; GFX11-NEXT: s_add_i32 s0, s4, 0x800000005089; GFX11-NEXT: s_xor_b32 s1, s3, s25090; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s4, s15091; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s0, s15092; GFX11-NEXT: v_readfirstlane_b32 s0, v05093; GFX11-NEXT: v_readfirstlane_b32 s1, v15094; GFX11-NEXT: v_readfirstlane_b32 s2, v25095; GFX11-NEXT: v_readfirstlane_b32 s3, v35096; GFX11-NEXT: ; return to shader part epilog5097 %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)5098 ret <2 x i64> %result5099}5100 5101define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {5102; GFX6-LABEL: s_ssubsat_i128:5103; GFX6: ; %bb.0:5104; GFX6-NEXT: s_sub_u32 s8, s0, s45105; GFX6-NEXT: v_mov_b32_e32 v0, s05106; GFX6-NEXT: s_subb_u32 s9, s1, s55107; GFX6-NEXT: v_mov_b32_e32 v1, s15108; GFX6-NEXT: s_subb_u32 s10, s2, s65109; GFX6-NEXT: v_mov_b32_e32 v2, s25110; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]5111; GFX6-NEXT: s_subb_u32 s11, s3, s75112; GFX6-NEXT: v_mov_b32_e32 v3, s35113; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5114; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]5115; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 05116; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5117; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[2:3]5118; GFX6-NEXT: v_mov_b32_e32 v3, s95119; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5120; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5121; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 05122; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 05123; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5124; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5125; GFX6-NEXT: v_xor_b32_e32 v0, v1, v05126; GFX6-NEXT: s_ashr_i32 s0, s11, 315127; GFX6-NEXT: v_and_b32_e32 v0, 1, v05128; GFX6-NEXT: s_add_i32 s1, s0, 0x800000005129; GFX6-NEXT: v_mov_b32_e32 v1, s05130; GFX6-NEXT: v_mov_b32_e32 v2, s85131; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05132; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5133; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc5134; GFX6-NEXT: v_mov_b32_e32 v3, s15135; GFX6-NEXT: v_mov_b32_e32 v4, s105136; GFX6-NEXT: v_mov_b32_e32 v5, s115137; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc5138; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc5139; GFX6-NEXT: v_readfirstlane_b32 s0, v05140; GFX6-NEXT: v_readfirstlane_b32 s1, v25141; GFX6-NEXT: v_readfirstlane_b32 s2, v15142; GFX6-NEXT: v_readfirstlane_b32 s3, v35143; GFX6-NEXT: ; return to shader part epilog5144;5145; GFX8-LABEL: s_ssubsat_i128:5146; GFX8: ; %bb.0:5147; GFX8-NEXT: s_sub_u32 s8, s0, s45148; GFX8-NEXT: s_subb_u32 s9, s1, s55149; GFX8-NEXT: v_mov_b32_e32 v0, s05150; GFX8-NEXT: s_subb_u32 s10, s2, s65151; GFX8-NEXT: v_mov_b32_e32 v1, s15152; GFX8-NEXT: s_subb_u32 s11, s3, s75153; GFX8-NEXT: v_mov_b32_e32 v2, s25154; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]5155; GFX8-NEXT: v_mov_b32_e32 v3, s35156; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]5157; GFX8-NEXT: s_cselect_b32 s0, 1, 05158; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5159; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]5160; GFX8-NEXT: s_and_b32 s0, 1, s05161; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5162; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05163; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 05164; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5165; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 05166; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5167; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 05168; GFX8-NEXT: s_cselect_b32 s2, 1, 05169; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5170; GFX8-NEXT: s_and_b32 s0, 1, s25171; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05172; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5173; GFX8-NEXT: v_xor_b32_e32 v0, v1, v05174; GFX8-NEXT: s_ashr_i32 s0, s11, 315175; GFX8-NEXT: v_and_b32_e32 v0, 1, v05176; GFX8-NEXT: s_add_i32 s1, s0, 0x800000005177; GFX8-NEXT: v_mov_b32_e32 v1, s05178; GFX8-NEXT: v_mov_b32_e32 v2, s85179; GFX8-NEXT: v_mov_b32_e32 v3, s95180; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05181; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5182; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc5183; GFX8-NEXT: v_mov_b32_e32 v3, s15184; GFX8-NEXT: v_mov_b32_e32 v4, s105185; GFX8-NEXT: v_mov_b32_e32 v5, s115186; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc5187; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc5188; GFX8-NEXT: v_readfirstlane_b32 s0, v05189; GFX8-NEXT: v_readfirstlane_b32 s1, v25190; GFX8-NEXT: v_readfirstlane_b32 s2, v15191; GFX8-NEXT: v_readfirstlane_b32 s3, v35192; GFX8-NEXT: ; return to shader part epilog5193;5194; GFX9-LABEL: s_ssubsat_i128:5195; GFX9: ; %bb.0:5196; GFX9-NEXT: s_sub_u32 s8, s0, s45197; GFX9-NEXT: s_subb_u32 s9, s1, s55198; GFX9-NEXT: v_mov_b32_e32 v0, s05199; GFX9-NEXT: s_subb_u32 s10, s2, s65200; GFX9-NEXT: v_mov_b32_e32 v1, s15201; GFX9-NEXT: s_subb_u32 s11, s3, s75202; GFX9-NEXT: v_mov_b32_e32 v2, s25203; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[0:1]5204; GFX9-NEXT: v_mov_b32_e32 v3, s35205; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]5206; GFX9-NEXT: s_cselect_b32 s0, 1, 05207; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5208; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[2:3]5209; GFX9-NEXT: s_and_b32 s0, 1, s05210; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5211; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05212; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 05213; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5214; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 05215; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5216; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 05217; GFX9-NEXT: s_cselect_b32 s2, 1, 05218; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5219; GFX9-NEXT: s_and_b32 s0, 1, s25220; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05221; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5222; GFX9-NEXT: v_xor_b32_e32 v0, v1, v05223; GFX9-NEXT: s_ashr_i32 s0, s11, 315224; GFX9-NEXT: v_and_b32_e32 v0, 1, v05225; GFX9-NEXT: s_add_i32 s1, s0, 0x800000005226; GFX9-NEXT: v_mov_b32_e32 v1, s05227; GFX9-NEXT: v_mov_b32_e32 v2, s85228; GFX9-NEXT: v_mov_b32_e32 v3, s95229; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05230; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc5231; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc5232; GFX9-NEXT: v_mov_b32_e32 v3, s15233; GFX9-NEXT: v_mov_b32_e32 v4, s105234; GFX9-NEXT: v_mov_b32_e32 v5, s115235; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v1, vcc5236; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc5237; GFX9-NEXT: v_readfirstlane_b32 s0, v05238; GFX9-NEXT: v_readfirstlane_b32 s1, v25239; GFX9-NEXT: v_readfirstlane_b32 s2, v15240; GFX9-NEXT: v_readfirstlane_b32 s3, v35241; GFX9-NEXT: ; return to shader part epilog5242;5243; GFX10-LABEL: s_ssubsat_i128:5244; GFX10: ; %bb.0:5245; GFX10-NEXT: s_sub_u32 s8, s0, s45246; GFX10-NEXT: s_subb_u32 s9, s1, s55247; GFX10-NEXT: s_subb_u32 s10, s2, s65248; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]5249; GFX10-NEXT: s_subb_u32 s11, s3, s75250; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]5251; GFX10-NEXT: s_cselect_b32 s12, 1, 05252; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s05253; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]5254; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 05255; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s05256; GFX10-NEXT: s_and_b32 s0, 1, s125257; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 05258; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s25259; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 05260; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s05261; GFX10-NEXT: s_cselect_b32 s1, 1, 05262; GFX10-NEXT: s_ashr_i32 s0, s11, 315263; GFX10-NEXT: s_and_b32 s1, 1, s15264; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s25265; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5266; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s15267; GFX10-NEXT: s_add_i32 s1, s0, 0x800000005268; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo5269; GFX10-NEXT: v_mov_b32_e32 v2, s105270; GFX10-NEXT: v_mov_b32_e32 v3, s115271; GFX10-NEXT: v_xor_b32_e32 v0, v1, v05272; GFX10-NEXT: v_mov_b32_e32 v1, s85273; GFX10-NEXT: v_and_b32_e32 v0, 1, v05274; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05275; GFX10-NEXT: v_mov_b32_e32 v0, s95276; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo5277; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo5278; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo5279; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo5280; GFX10-NEXT: v_readfirstlane_b32 s0, v15281; GFX10-NEXT: v_readfirstlane_b32 s1, v05282; GFX10-NEXT: v_readfirstlane_b32 s2, v25283; GFX10-NEXT: v_readfirstlane_b32 s3, v35284; GFX10-NEXT: ; return to shader part epilog5285;5286; GFX11-LABEL: s_ssubsat_i128:5287; GFX11: ; %bb.0:5288; GFX11-NEXT: s_sub_u32 s8, s0, s45289; GFX11-NEXT: s_subb_u32 s9, s1, s55290; GFX11-NEXT: s_subb_u32 s10, s2, s65291; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]5292; GFX11-NEXT: s_subb_u32 s11, s3, s75293; GFX11-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]5294; GFX11-NEXT: s_cselect_b32 s12, 1, 05295; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s05296; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[10:11], s[2:3]5297; GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[4:5], 05298; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s05299; GFX11-NEXT: s_and_b32 s0, 1, s125300; GFX11-NEXT: s_cmp_eq_u64 s[6:7], 05301; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s25302; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[6:7], 05303; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s05304; GFX11-NEXT: s_cselect_b32 s1, 1, 05305; GFX11-NEXT: s_ashr_i32 s0, s11, 315306; GFX11-NEXT: s_and_b32 s1, 1, s15307; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s25308; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5309; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s15310; GFX11-NEXT: s_add_i32 s1, s0, 0x800000005311; GFX11-NEXT: v_dual_cndmask_b32 v1, v3, v2 :: v_dual_mov_b32 v2, s105312; GFX11-NEXT: v_mov_b32_e32 v3, s115313; GFX11-NEXT: v_xor_b32_e32 v0, v1, v05314; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_and_b32 v0, 1, v05315; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05316; GFX11-NEXT: v_mov_b32_e32 v0, s95317; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo5318; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo5319; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo5320; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s1, vcc_lo5321; GFX11-NEXT: v_readfirstlane_b32 s0, v15322; GFX11-NEXT: v_readfirstlane_b32 s1, v05323; GFX11-NEXT: v_readfirstlane_b32 s2, v25324; GFX11-NEXT: v_readfirstlane_b32 s3, v35325; GFX11-NEXT: ; return to shader part epilog5326 %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)5327 ret i128 %result5328}5329 5330define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {5331; GFX6-LABEL: ssubsat_i128_sv:5332; GFX6: ; %bb.0:5333; GFX6-NEXT: v_mov_b32_e32 v5, s15334; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v05335; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc5336; GFX6-NEXT: v_mov_b32_e32 v6, s25337; GFX6-NEXT: v_mov_b32_e32 v7, s35338; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc5339; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc5340; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]5341; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5342; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]5343; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc5344; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]5345; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc5346; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]5347; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5348; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]5349; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5350; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]5351; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v75352; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5353; GFX6-NEXT: v_xor_b32_e32 v0, v0, v85354; GFX6-NEXT: v_bfrev_b32_e32 v1, 15355; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v15356; GFX6-NEXT: v_and_b32_e32 v0, 1, v05357; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05358; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5359; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5360; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5361; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5362; GFX6-NEXT: ; return to shader part epilog5363;5364; GFX8-LABEL: ssubsat_i128_sv:5365; GFX8: ; %bb.0:5366; GFX8-NEXT: v_mov_b32_e32 v5, s15367; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s0, v05368; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc5369; GFX8-NEXT: v_mov_b32_e32 v6, s25370; GFX8-NEXT: v_mov_b32_e32 v7, s35371; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc5372; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc5373; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]5374; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5375; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]5376; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc5377; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]5378; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc5379; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]5380; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5381; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]5382; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5383; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]5384; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v75385; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5386; GFX8-NEXT: v_xor_b32_e32 v0, v0, v85387; GFX8-NEXT: v_bfrev_b32_e32 v1, 15388; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v15389; GFX8-NEXT: v_and_b32_e32 v0, 1, v05390; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05391; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5392; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5393; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5394; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5395; GFX8-NEXT: ; return to shader part epilog5396;5397; GFX9-LABEL: ssubsat_i128_sv:5398; GFX9: ; %bb.0:5399; GFX9-NEXT: v_mov_b32_e32 v5, s15400; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v05401; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v1, vcc5402; GFX9-NEXT: v_mov_b32_e32 v6, s25403; GFX9-NEXT: v_mov_b32_e32 v7, s35404; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v2, vcc5405; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v3, vcc5406; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]5407; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc5408; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]5409; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc5410; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]5411; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc5412; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]5413; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5414; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]5415; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5416; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]5417; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v75418; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5419; GFX9-NEXT: v_xor_b32_e32 v0, v0, v85420; GFX9-NEXT: v_and_b32_e32 v0, 1, v05421; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v25422; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05423; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5424; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5425; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5426; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5427; GFX9-NEXT: ; return to shader part epilog5428;5429; GFX10-LABEL: ssubsat_i128_sv:5430; GFX10: ; %bb.0:5431; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v05432; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo5433; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo5434; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo5435; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]5436; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo5437; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]5438; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo5439; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]5440; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5441; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]5442; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5443; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]5444; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo5445; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]5446; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v75447; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5448; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v25449; GFX10-NEXT: v_xor_b32_e32 v0, v0, v85450; GFX10-NEXT: v_and_b32_e32 v0, 1, v05451; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05452; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo5453; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo5454; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo5455; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo5456; GFX10-NEXT: ; return to shader part epilog5457;5458; GFX11-LABEL: ssubsat_i128_sv:5459; GFX11: ; %bb.0:5460; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v05461; GFX11-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo5462; GFX11-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo5463; GFX11-NEXT: v_sub_co_ci_u32_e64 v7, null, s3, v3, vcc_lo5464; GFX11-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]5465; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo5466; GFX11-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]5467; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo5468; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]5469; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5470; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]5471; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5472; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]5473; GFX11-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo5474; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]5475; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v75476; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_add_nc_u32 v3, 0x80000000, v25477; GFX11-NEXT: v_xor_b32_e32 v0, v0, v85478; GFX11-NEXT: v_and_b32_e32 v0, 1, v05479; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05480; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo5481; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo5482; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v35483; GFX11-NEXT: ; return to shader part epilog5484 %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)5485 %cast = bitcast i128 %result to <4 x float>5486 ret <4 x float> %cast5487}5488 5489define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {5490; GFX6-LABEL: ssubsat_i128_vs:5491; GFX6: ; %bb.0:5492; GFX6-NEXT: v_mov_b32_e32 v5, s15493; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s0, v05494; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc5495; GFX6-NEXT: v_mov_b32_e32 v6, s25496; GFX6-NEXT: v_mov_b32_e32 v7, s35497; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc5498; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc5499; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]5500; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 05501; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5502; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]5503; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5504; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]5505; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5506; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5507; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 05508; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[2:3], 05509; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5510; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5511; GFX6-NEXT: v_xor_b32_e32 v0, v1, v05512; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v75513; GFX6-NEXT: v_bfrev_b32_e32 v1, 15514; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v15515; GFX6-NEXT: v_and_b32_e32 v0, 1, v05516; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05517; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5518; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5519; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5520; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5521; GFX6-NEXT: ; return to shader part epilog5522;5523; GFX8-LABEL: ssubsat_i128_vs:5524; GFX8: ; %bb.0:5525; GFX8-NEXT: v_mov_b32_e32 v5, s15526; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s0, v05527; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc5528; GFX8-NEXT: v_mov_b32_e32 v6, s25529; GFX8-NEXT: v_mov_b32_e32 v7, s35530; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc5531; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc5532; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]5533; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 05534; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5535; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]5536; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 05537; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5538; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]5539; GFX8-NEXT: s_cselect_b32 s4, 1, 05540; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5541; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5542; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 05543; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5544; GFX8-NEXT: s_and_b32 s0, 1, s45545; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05546; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5547; GFX8-NEXT: v_xor_b32_e32 v0, v1, v05548; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v75549; GFX8-NEXT: v_bfrev_b32_e32 v1, 15550; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v15551; GFX8-NEXT: v_and_b32_e32 v0, 1, v05552; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05553; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5554; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5555; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5556; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5557; GFX8-NEXT: ; return to shader part epilog5558;5559; GFX9-LABEL: ssubsat_i128_vs:5560; GFX9: ; %bb.0:5561; GFX9-NEXT: v_mov_b32_e32 v5, s15562; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s0, v05563; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v5, vcc5564; GFX9-NEXT: v_mov_b32_e32 v6, s25565; GFX9-NEXT: v_mov_b32_e32 v7, s35566; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v2, v6, vcc5567; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v3, v7, vcc5568; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]5569; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 05570; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5571; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]5572; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 05573; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5574; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]5575; GFX9-NEXT: s_cselect_b32 s4, 1, 05576; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5577; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5578; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 05579; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5580; GFX9-NEXT: s_and_b32 s0, 1, s45581; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s05582; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5583; GFX9-NEXT: v_xor_b32_e32 v0, v1, v05584; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v75585; GFX9-NEXT: v_and_b32_e32 v0, 1, v05586; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v25587; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05588; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc5589; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc5590; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc5591; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc5592; GFX9-NEXT: ; return to shader part epilog5593;5594; GFX10-LABEL: ssubsat_i128_vs:5595; GFX10: ; %bb.0:5596; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s05597; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo5598; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo5599; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo5600; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]5601; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 05602; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 05603; GFX10-NEXT: s_cselect_b32 s4, 1, 05604; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5605; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]5606; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s05607; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 05608; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5609; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]5610; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s05611; GFX10-NEXT: s_and_b32 s0, 1, s45612; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v75613; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5614; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s05615; GFX10-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v25616; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo5617; GFX10-NEXT: v_xor_b32_e32 v0, v1, v05618; GFX10-NEXT: v_and_b32_e32 v0, 1, v05619; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05620; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo5621; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo5622; GFX10-NEXT: v_cndmask_b32_e32 v2, v6, v2, vcc_lo5623; GFX10-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc_lo5624; GFX10-NEXT: ; return to shader part epilog5625;5626; GFX11-LABEL: ssubsat_i128_vs:5627; GFX11: ; %bb.0:5628; GFX11-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s05629; GFX11-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo5630; GFX11-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo5631; GFX11-NEXT: v_subrev_co_ci_u32_e64 v7, null, s3, v3, vcc_lo5632; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]5633; GFX11-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 05634; GFX11-NEXT: s_cmp_eq_u64 s[2:3], 05635; GFX11-NEXT: s_cselect_b32 s4, 1, 05636; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5637; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]5638; GFX11-NEXT: v_cndmask_b32_e64 v8, 0, 1, s05639; GFX11-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 05640; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5641; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]5642; GFX11-NEXT: v_cndmask_b32_e64 v9, 0, 1, s05643; GFX11-NEXT: s_and_b32 s0, 1, s45644; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v75645; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5646; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s05647; GFX11-NEXT: v_add_nc_u32_e32 v3, 0x80000000, v25648; GFX11-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo5649; GFX11-NEXT: v_xor_b32_e32 v0, v1, v05650; GFX11-NEXT: v_and_b32_e32 v0, 1, v05651; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05652; GFX11-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc_lo5653; GFX11-NEXT: v_cndmask_b32_e32 v1, v5, v2, vcc_lo5654; GFX11-NEXT: v_dual_cndmask_b32 v2, v6, v2 :: v_dual_cndmask_b32 v3, v7, v35655; GFX11-NEXT: ; return to shader part epilog5656 %result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)5657 %cast = bitcast i128 %result to <4 x float>5658 ret <4 x float> %cast5659}5660 5661define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {5662; GFX6-LABEL: v_ssubsat_v2i128:5663; GFX6: ; %bb.0:5664; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5665; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v0, v85666; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc5667; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc5668; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc5669; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]5670; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5671; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]5672; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5673; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]5674; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5675; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]5676; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5677; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]5678; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5679; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]5680; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5681; GFX6-NEXT: v_xor_b32_e32 v0, v1, v05682; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v195683; GFX6-NEXT: v_bfrev_b32_e32 v1, 15684; GFX6-NEXT: v_add_i32_e32 v3, vcc, v2, v15685; GFX6-NEXT: v_and_b32_e32 v0, 1, v05686; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05687; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc5688; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc5689; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc5690; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc5691; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v125692; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc5693; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc5694; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc5695; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]5696; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc5697; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]5698; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5699; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]5700; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc5701; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]5702; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5703; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]5704; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc5705; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]5706; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc5707; GFX6-NEXT: v_xor_b32_e32 v4, v5, v45708; GFX6-NEXT: v_ashrrev_i32_e32 v6, 31, v115709; GFX6-NEXT: v_add_i32_e32 v7, vcc, 0x80000000, v65710; GFX6-NEXT: v_and_b32_e32 v4, 1, v45711; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45712; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc5713; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc5714; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc5715; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc5716; GFX6-NEXT: s_setpc_b64 s[30:31]5717;5718; GFX8-LABEL: v_ssubsat_v2i128:5719; GFX8: ; %bb.0:5720; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5721; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v0, v85722; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc5723; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc5724; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc5725; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]5726; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5727; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]5728; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5729; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]5730; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5731; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]5732; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5733; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]5734; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5735; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]5736; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5737; GFX8-NEXT: v_xor_b32_e32 v0, v1, v05738; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v195739; GFX8-NEXT: v_bfrev_b32_e32 v1, 15740; GFX8-NEXT: v_add_u32_e32 v3, vcc, v2, v15741; GFX8-NEXT: v_and_b32_e32 v0, 1, v05742; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05743; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc5744; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc5745; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc5746; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc5747; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v125748; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc5749; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc5750; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc5751; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]5752; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc5753; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]5754; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5755; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]5756; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc5757; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]5758; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5759; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]5760; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc5761; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]5762; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc5763; GFX8-NEXT: v_xor_b32_e32 v4, v5, v45764; GFX8-NEXT: v_ashrrev_i32_e32 v6, 31, v115765; GFX8-NEXT: v_add_u32_e32 v7, vcc, 0x80000000, v65766; GFX8-NEXT: v_and_b32_e32 v4, 1, v45767; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45768; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc5769; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc5770; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc5771; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc5772; GFX8-NEXT: s_setpc_b64 s[30:31]5773;5774; GFX9-LABEL: v_ssubsat_v2i128:5775; GFX9: ; %bb.0:5776; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5777; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v0, v85778; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v1, v9, vcc5779; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc5780; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc5781; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]5782; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5783; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]5784; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5785; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]5786; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5787; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]5788; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5789; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]5790; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc5791; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]5792; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5793; GFX9-NEXT: v_xor_b32_e32 v0, v1, v05794; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v195795; GFX9-NEXT: v_and_b32_e32 v0, 1, v05796; GFX9-NEXT: v_add_u32_e32 v3, 0x80000000, v25797; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05798; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc5799; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc5800; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc5801; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc5802; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v125803; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc5804; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc5805; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc5806; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]5807; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc5808; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]5809; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5810; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]5811; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc5812; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]5813; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc5814; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]5815; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc5816; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]5817; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc5818; GFX9-NEXT: v_xor_b32_e32 v4, v5, v45819; GFX9-NEXT: v_ashrrev_i32_e32 v6, 31, v115820; GFX9-NEXT: v_and_b32_e32 v4, 1, v45821; GFX9-NEXT: v_add_u32_e32 v7, 0x80000000, v65822; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v45823; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc5824; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v6, vcc5825; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc5826; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc5827; GFX9-NEXT: s_setpc_b64 s[30:31]5828;5829; GFX10-LABEL: v_ssubsat_v2i128:5830; GFX10: ; %bb.0:5831; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5832; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v85833; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo5834; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo5835; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo5836; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]5837; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5838; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]5839; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5840; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]5841; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5842; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]5843; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5844; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]5845; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5846; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v125847; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo5848; GFX10-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo5849; GFX10-NEXT: v_sub_co_ci_u32_e32 v21, vcc_lo, v7, v15, vcc_lo5850; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]5851; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo5852; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5]5853; GFX10-NEXT: v_xor_b32_e32 v0, v1, v05854; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5855; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7]5856; GFX10-NEXT: v_and_b32_e32 v0, 1, v05857; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo5858; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13]5859; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo5860; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]5861; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo5862; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7]5863; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v215864; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo5865; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]5866; GFX10-NEXT: v_add_nc_u32_e32 v7, 0x80000000, v65867; GFX10-NEXT: v_cndmask_b32_e32 v2, v5, v4, vcc_lo5868; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05869; GFX10-NEXT: v_xor_b32_e32 v1, v2, v15870; GFX10-NEXT: v_ashrrev_i32_e32 v2, 31, v195871; GFX10-NEXT: v_and_b32_e32 v3, 1, v15872; GFX10-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v25873; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo5874; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc_lo5875; GFX10-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc_lo5876; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v35877; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v4, vcc_lo5878; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v6, s45879; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s45880; GFX10-NEXT: v_cndmask_b32_e64 v6, v20, v6, s45881; GFX10-NEXT: v_cndmask_b32_e64 v7, v21, v7, s45882; GFX10-NEXT: s_setpc_b64 s[30:31]5883;5884; GFX11-LABEL: v_ssubsat_v2i128:5885; GFX11: ; %bb.0:5886; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5887; GFX11-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v85888; GFX11-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo5889; GFX11-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo5890; GFX11-NEXT: v_sub_co_ci_u32_e64 v19, null, v3, v11, vcc_lo5891; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]5892; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo5893; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]5894; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5895; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]5896; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo5897; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]5898; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo5899; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]5900; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5901; GFX11-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v125902; GFX11-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo5903; GFX11-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v6, v14, vcc_lo5904; GFX11-NEXT: v_sub_co_ci_u32_e64 v21, null, v7, v15, vcc_lo5905; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]5906; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo5907; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[8:9], v[4:5]5908; GFX11-NEXT: v_xor_b32_e32 v0, v1, v05909; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc_lo5910; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[20:21], v[6:7]5911; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc_lo5912; GFX11-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[12:13]5913; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc_lo5914; GFX11-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[14:15]5915; GFX11-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc_lo5916; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[20:21], v[6:7]5917; GFX11-NEXT: v_ashrrev_i32_e32 v6, 31, v215918; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo5919; GFX11-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[14:15]5920; GFX11-NEXT: v_dual_cndmask_b32 v2, v5, v4 :: v_dual_add_nc_u32 v7, 0x80000000, v65921; GFX11-NEXT: v_xor_b32_e32 v1, v2, v15922; GFX11-NEXT: v_ashrrev_i32_e32 v2, 31, v195923; GFX11-NEXT: v_and_b32_e32 v0, 1, v05924; GFX11-NEXT: v_add_nc_u32_e32 v4, 0x80000000, v25925; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v05926; GFX11-NEXT: v_dual_cndmask_b32 v0, v16, v2 :: v_dual_and_b32 v3, 1, v15927; GFX11-NEXT: v_cmp_ne_u32_e64 s0, 0, v35928; GFX11-NEXT: v_cndmask_b32_e32 v1, v17, v2, vcc_lo5929; GFX11-NEXT: v_dual_cndmask_b32 v2, v18, v2 :: v_dual_cndmask_b32 v3, v19, v45930; GFX11-NEXT: v_cndmask_b32_e64 v4, v8, v6, s05931; GFX11-NEXT: v_cndmask_b32_e64 v5, v9, v6, s05932; GFX11-NEXT: v_cndmask_b32_e64 v6, v20, v6, s05933; GFX11-NEXT: v_cndmask_b32_e64 v7, v21, v7, s05934; GFX11-NEXT: s_setpc_b64 s[30:31]5935 %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)5936 ret <2 x i128> %result5937}5938 5939define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {5940; GFX6-LABEL: s_ssubsat_v2i128:5941; GFX6: ; %bb.0:5942; GFX6-NEXT: s_sub_u32 s16, s0, s85943; GFX6-NEXT: v_mov_b32_e32 v0, s05944; GFX6-NEXT: s_subb_u32 s17, s1, s95945; GFX6-NEXT: v_mov_b32_e32 v1, s15946; GFX6-NEXT: s_subb_u32 s18, s2, s105947; GFX6-NEXT: v_mov_b32_e32 v2, s25948; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]5949; GFX6-NEXT: s_subb_u32 s19, s3, s115950; GFX6-NEXT: v_mov_b32_e32 v3, s35951; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5952; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]5953; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 05954; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5955; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[2:3]5956; GFX6-NEXT: v_mov_b32_e32 v3, s175957; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5958; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]5959; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 05960; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 05961; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]5962; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5963; GFX6-NEXT: v_xor_b32_e32 v0, v1, v05964; GFX6-NEXT: s_ashr_i32 s0, s19, 315965; GFX6-NEXT: v_and_b32_e32 v0, 1, v05966; GFX6-NEXT: s_add_i32 s1, s0, 0x800000005967; GFX6-NEXT: v_mov_b32_e32 v1, s05968; GFX6-NEXT: v_mov_b32_e32 v2, s165969; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v05970; GFX6-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc5971; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc5972; GFX6-NEXT: v_mov_b32_e32 v0, s15973; GFX6-NEXT: v_mov_b32_e32 v2, s185974; GFX6-NEXT: v_mov_b32_e32 v3, s195975; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc5976; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc5977; GFX6-NEXT: s_sub_u32 s0, s4, s125978; GFX6-NEXT: v_mov_b32_e32 v0, s45979; GFX6-NEXT: s_subb_u32 s1, s5, s135980; GFX6-NEXT: v_mov_b32_e32 v1, s55981; GFX6-NEXT: s_subb_u32 s2, s6, s145982; GFX6-NEXT: v_mov_b32_e32 v2, s65983; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]5984; GFX6-NEXT: s_subb_u32 s3, s7, s155985; GFX6-NEXT: v_mov_b32_e32 v3, s75986; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc5987; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]5988; GFX6-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 05989; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc5990; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[2:3]5991; GFX6-NEXT: v_mov_b32_e32 v3, s15992; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc5993; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]5994; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 05995; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 05996; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]5997; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc5998; GFX6-NEXT: v_xor_b32_e32 v0, v1, v05999; GFX6-NEXT: s_ashr_i32 s4, s3, 316000; GFX6-NEXT: v_and_b32_e32 v0, 1, v06001; GFX6-NEXT: s_add_i32 s5, s4, 0x800000006002; GFX6-NEXT: v_mov_b32_e32 v1, s46003; GFX6-NEXT: v_mov_b32_e32 v2, s06004; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06005; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6006; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc6007; GFX6-NEXT: v_mov_b32_e32 v3, s56008; GFX6-NEXT: v_mov_b32_e32 v8, s26009; GFX6-NEXT: v_mov_b32_e32 v9, s36010; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc6011; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc6012; GFX6-NEXT: v_readfirstlane_b32 s0, v46013; GFX6-NEXT: v_readfirstlane_b32 s1, v56014; GFX6-NEXT: v_readfirstlane_b32 s2, v66015; GFX6-NEXT: v_readfirstlane_b32 s3, v76016; GFX6-NEXT: v_readfirstlane_b32 s4, v06017; GFX6-NEXT: v_readfirstlane_b32 s5, v26018; GFX6-NEXT: v_readfirstlane_b32 s6, v16019; GFX6-NEXT: v_readfirstlane_b32 s7, v36020; GFX6-NEXT: ; return to shader part epilog6021;6022; GFX8-LABEL: s_ssubsat_v2i128:6023; GFX8: ; %bb.0:6024; GFX8-NEXT: s_sub_u32 s16, s0, s86025; GFX8-NEXT: s_subb_u32 s17, s1, s96026; GFX8-NEXT: v_mov_b32_e32 v0, s06027; GFX8-NEXT: s_subb_u32 s18, s2, s106028; GFX8-NEXT: v_mov_b32_e32 v1, s16029; GFX8-NEXT: s_subb_u32 s19, s3, s116030; GFX8-NEXT: v_mov_b32_e32 v2, s26031; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]6032; GFX8-NEXT: v_mov_b32_e32 v3, s36033; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]6034; GFX8-NEXT: s_cselect_b32 s0, 1, 06035; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6036; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]6037; GFX8-NEXT: s_and_b32 s0, 1, s06038; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc6039; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s06040; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 06041; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc6042; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 06043; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]6044; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 06045; GFX8-NEXT: s_cselect_b32 s2, 1, 06046; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]6047; GFX8-NEXT: s_and_b32 s0, 1, s26048; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s06049; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6050; GFX8-NEXT: v_xor_b32_e32 v0, v1, v06051; GFX8-NEXT: s_ashr_i32 s0, s19, 316052; GFX8-NEXT: v_and_b32_e32 v0, 1, v06053; GFX8-NEXT: s_add_i32 s1, s0, 0x800000006054; GFX8-NEXT: v_mov_b32_e32 v1, s06055; GFX8-NEXT: v_mov_b32_e32 v2, s166056; GFX8-NEXT: v_mov_b32_e32 v3, s176057; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06058; GFX8-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc6059; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc6060; GFX8-NEXT: v_mov_b32_e32 v0, s16061; GFX8-NEXT: v_mov_b32_e32 v2, s186062; GFX8-NEXT: v_mov_b32_e32 v3, s196063; GFX8-NEXT: s_sub_u32 s0, s4, s126064; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc6065; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc6066; GFX8-NEXT: s_subb_u32 s1, s5, s136067; GFX8-NEXT: v_mov_b32_e32 v0, s46068; GFX8-NEXT: s_subb_u32 s2, s6, s146069; GFX8-NEXT: v_mov_b32_e32 v1, s56070; GFX8-NEXT: s_subb_u32 s3, s7, s156071; GFX8-NEXT: v_mov_b32_e32 v2, s66072; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]6073; GFX8-NEXT: v_mov_b32_e32 v3, s76074; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]6075; GFX8-NEXT: s_cselect_b32 s4, 1, 06076; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6077; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]6078; GFX8-NEXT: s_and_b32 s4, 1, s46079; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc6080; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s46081; GFX8-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 06082; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc6083; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 06084; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]6085; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 06086; GFX8-NEXT: s_cselect_b32 s6, 1, 06087; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]6088; GFX8-NEXT: s_and_b32 s4, 1, s66089; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s46090; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6091; GFX8-NEXT: v_xor_b32_e32 v0, v1, v06092; GFX8-NEXT: s_ashr_i32 s4, s3, 316093; GFX8-NEXT: v_and_b32_e32 v0, 1, v06094; GFX8-NEXT: s_add_i32 s5, s4, 0x800000006095; GFX8-NEXT: v_mov_b32_e32 v1, s46096; GFX8-NEXT: v_mov_b32_e32 v2, s06097; GFX8-NEXT: v_mov_b32_e32 v3, s16098; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06099; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6100; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc6101; GFX8-NEXT: v_mov_b32_e32 v3, s56102; GFX8-NEXT: v_mov_b32_e32 v8, s26103; GFX8-NEXT: v_mov_b32_e32 v9, s36104; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc6105; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc6106; GFX8-NEXT: v_readfirstlane_b32 s0, v46107; GFX8-NEXT: v_readfirstlane_b32 s1, v56108; GFX8-NEXT: v_readfirstlane_b32 s2, v66109; GFX8-NEXT: v_readfirstlane_b32 s3, v76110; GFX8-NEXT: v_readfirstlane_b32 s4, v06111; GFX8-NEXT: v_readfirstlane_b32 s5, v26112; GFX8-NEXT: v_readfirstlane_b32 s6, v16113; GFX8-NEXT: v_readfirstlane_b32 s7, v36114; GFX8-NEXT: ; return to shader part epilog6115;6116; GFX9-LABEL: s_ssubsat_v2i128:6117; GFX9: ; %bb.0:6118; GFX9-NEXT: s_sub_u32 s16, s0, s86119; GFX9-NEXT: s_subb_u32 s17, s1, s96120; GFX9-NEXT: v_mov_b32_e32 v0, s06121; GFX9-NEXT: s_subb_u32 s18, s2, s106122; GFX9-NEXT: v_mov_b32_e32 v1, s16123; GFX9-NEXT: s_subb_u32 s19, s3, s116124; GFX9-NEXT: v_mov_b32_e32 v2, s26125; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[0:1]6126; GFX9-NEXT: v_mov_b32_e32 v3, s36127; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]6128; GFX9-NEXT: s_cselect_b32 s0, 1, 06129; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6130; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[2:3]6131; GFX9-NEXT: s_and_b32 s0, 1, s06132; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc6133; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s06134; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 06135; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc6136; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 06137; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]6138; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 06139; GFX9-NEXT: s_cselect_b32 s2, 1, 06140; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]6141; GFX9-NEXT: s_and_b32 s0, 1, s26142; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s06143; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6144; GFX9-NEXT: v_xor_b32_e32 v0, v1, v06145; GFX9-NEXT: s_ashr_i32 s0, s19, 316146; GFX9-NEXT: v_and_b32_e32 v0, 1, v06147; GFX9-NEXT: s_add_i32 s1, s0, 0x800000006148; GFX9-NEXT: v_mov_b32_e32 v1, s06149; GFX9-NEXT: v_mov_b32_e32 v2, s166150; GFX9-NEXT: v_mov_b32_e32 v3, s176151; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06152; GFX9-NEXT: v_cndmask_b32_e32 v4, v2, v1, vcc6153; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc6154; GFX9-NEXT: v_mov_b32_e32 v0, s16155; GFX9-NEXT: v_mov_b32_e32 v2, s186156; GFX9-NEXT: v_mov_b32_e32 v3, s196157; GFX9-NEXT: s_sub_u32 s0, s4, s126158; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v1, vcc6159; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v0, vcc6160; GFX9-NEXT: s_subb_u32 s1, s5, s136161; GFX9-NEXT: v_mov_b32_e32 v0, s46162; GFX9-NEXT: s_subb_u32 s2, s6, s146163; GFX9-NEXT: v_mov_b32_e32 v1, s56164; GFX9-NEXT: s_subb_u32 s3, s7, s156165; GFX9-NEXT: v_mov_b32_e32 v2, s66166; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[0:1]6167; GFX9-NEXT: v_mov_b32_e32 v3, s76168; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]6169; GFX9-NEXT: s_cselect_b32 s4, 1, 06170; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc6171; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[2:3]6172; GFX9-NEXT: s_and_b32 s4, 1, s46173; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc6174; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s46175; GFX9-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 06176; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc6177; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 06178; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]6179; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 06180; GFX9-NEXT: s_cselect_b32 s6, 1, 06181; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]6182; GFX9-NEXT: s_and_b32 s4, 1, s66183; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s46184; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc6185; GFX9-NEXT: v_xor_b32_e32 v0, v1, v06186; GFX9-NEXT: s_ashr_i32 s4, s3, 316187; GFX9-NEXT: v_and_b32_e32 v0, 1, v06188; GFX9-NEXT: s_add_i32 s5, s4, 0x800000006189; GFX9-NEXT: v_mov_b32_e32 v1, s46190; GFX9-NEXT: v_mov_b32_e32 v2, s06191; GFX9-NEXT: v_mov_b32_e32 v3, s16192; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v06193; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v1, vcc6194; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v1, vcc6195; GFX9-NEXT: v_mov_b32_e32 v3, s56196; GFX9-NEXT: v_mov_b32_e32 v8, s26197; GFX9-NEXT: v_mov_b32_e32 v9, s36198; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc6199; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc6200; GFX9-NEXT: v_readfirstlane_b32 s0, v46201; GFX9-NEXT: v_readfirstlane_b32 s1, v56202; GFX9-NEXT: v_readfirstlane_b32 s2, v66203; GFX9-NEXT: v_readfirstlane_b32 s3, v76204; GFX9-NEXT: v_readfirstlane_b32 s4, v06205; GFX9-NEXT: v_readfirstlane_b32 s5, v26206; GFX9-NEXT: v_readfirstlane_b32 s6, v16207; GFX9-NEXT: v_readfirstlane_b32 s7, v36208; GFX9-NEXT: ; return to shader part epilog6209;6210; GFX10-LABEL: s_ssubsat_v2i128:6211; GFX10: ; %bb.0:6212; GFX10-NEXT: s_sub_u32 s18, s0, s86213; GFX10-NEXT: s_subb_u32 s19, s1, s96214; GFX10-NEXT: s_subb_u32 s16, s2, s106215; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[18:19], s[0:1]6216; GFX10-NEXT: s_subb_u32 s17, s3, s116217; GFX10-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]6218; GFX10-NEXT: s_cselect_b32 s20, 1, 06219; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s06220; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]6221; GFX10-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 06222; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s06223; GFX10-NEXT: s_and_b32 s0, 1, s206224; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 06225; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s26226; GFX10-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 06227; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s06228; GFX10-NEXT: s_cselect_b32 s1, 1, 06229; GFX10-NEXT: s_ashr_i32 s8, s17, 316230; GFX10-NEXT: s_and_b32 s1, 1, s16231; GFX10-NEXT: s_add_i32 s9, s8, 0x800000006232; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s26233; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo6234; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s16235; GFX10-NEXT: s_sub_u32 s0, s4, s126236; GFX10-NEXT: s_subb_u32 s1, s5, s136237; GFX10-NEXT: s_subb_u32 s2, s6, s146238; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]6239; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo6240; GFX10-NEXT: s_subb_u32 s3, s7, s156241; GFX10-NEXT: v_mov_b32_e32 v5, s06242; GFX10-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]6243; GFX10-NEXT: v_mov_b32_e32 v6, s26244; GFX10-NEXT: v_xor_b32_e32 v0, v1, v06245; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s46246; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[6:7]6247; GFX10-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 06248; GFX10-NEXT: s_cselect_b32 s10, 1, 06249; GFX10-NEXT: v_and_b32_e32 v0, 1, v06250; GFX10-NEXT: v_mov_b32_e32 v7, s36251; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s46252; GFX10-NEXT: s_and_b32 s4, 1, s106253; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 06254; GFX10-NEXT: v_cndmask_b32_e64 v3, 0, 1, s66255; GFX10-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 06256; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s46257; GFX10-NEXT: s_cselect_b32 s5, 1, 06258; GFX10-NEXT: s_ashr_i32 s4, s3, 316259; GFX10-NEXT: s_and_b32 s5, 1, s56260; GFX10-NEXT: s_add_i32 s0, s4, 0x800000006261; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s66262; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo6263; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s56264; GFX10-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc_lo6265; GFX10-NEXT: v_mov_b32_e32 v3, s186266; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06267; GFX10-NEXT: v_mov_b32_e32 v0, s196268; GFX10-NEXT: v_mov_b32_e32 v4, s176269; GFX10-NEXT: v_xor_b32_e32 v1, v2, v16270; GFX10-NEXT: v_mov_b32_e32 v2, s166271; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s8, vcc_lo6272; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s8, vcc_lo6273; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s9, vcc_lo6274; GFX10-NEXT: v_and_b32_e32 v1, 1, v16275; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s8, vcc_lo6276; GFX10-NEXT: v_readfirstlane_b32 s3, v46277; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16278; GFX10-NEXT: v_mov_b32_e32 v1, s16279; GFX10-NEXT: v_readfirstlane_b32 s1, v06280; GFX10-NEXT: v_readfirstlane_b32 s2, v26281; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s4, vcc_lo6282; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo6283; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s4, vcc_lo6284; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s0, vcc_lo6285; GFX10-NEXT: v_readfirstlane_b32 s0, v36286; GFX10-NEXT: v_readfirstlane_b32 s4, v56287; GFX10-NEXT: v_readfirstlane_b32 s5, v16288; GFX10-NEXT: v_readfirstlane_b32 s6, v66289; GFX10-NEXT: v_readfirstlane_b32 s7, v76290; GFX10-NEXT: ; return to shader part epilog6291;6292; GFX11-LABEL: s_ssubsat_v2i128:6293; GFX11: ; %bb.0:6294; GFX11-NEXT: s_sub_u32 s18, s0, s86295; GFX11-NEXT: s_subb_u32 s19, s1, s96296; GFX11-NEXT: s_subb_u32 s16, s2, s106297; GFX11-NEXT: v_cmp_lt_u64_e64 s0, s[18:19], s[0:1]6298; GFX11-NEXT: s_subb_u32 s17, s3, s116299; GFX11-NEXT: s_cmp_eq_u64 s[16:17], s[2:3]6300; GFX11-NEXT: s_cselect_b32 s20, 1, 06301; GFX11-NEXT: v_cndmask_b32_e64 v0, 0, 1, s06302; GFX11-NEXT: v_cmp_lt_i64_e64 s0, s[16:17], s[2:3]6303; GFX11-NEXT: v_cmp_gt_u64_e64 s2, s[8:9], 06304; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s06305; GFX11-NEXT: s_and_b32 s0, 1, s206306; GFX11-NEXT: s_cmp_eq_u64 s[10:11], 06307; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s26308; GFX11-NEXT: v_cmp_gt_i64_e64 s2, s[10:11], 06309; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s06310; GFX11-NEXT: s_cselect_b32 s1, 1, 06311; GFX11-NEXT: s_ashr_i32 s8, s17, 316312; GFX11-NEXT: s_and_b32 s1, 1, s16313; GFX11-NEXT: s_add_i32 s9, s8, 0x800000006314; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s26315; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo6316; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s16317; GFX11-NEXT: s_sub_u32 s0, s4, s126318; GFX11-NEXT: s_subb_u32 s1, s5, s136319; GFX11-NEXT: s_subb_u32 s2, s6, s146320; GFX11-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]6321; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc_lo6322; GFX11-NEXT: s_subb_u32 s3, s7, s156323; GFX11-NEXT: v_dual_mov_b32 v6, s2 :: v_dual_mov_b32 v7, s36324; GFX11-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]6325; GFX11-NEXT: v_xor_b32_e32 v0, v1, v06326; GFX11-NEXT: v_cndmask_b32_e64 v1, 0, 1, s46327; GFX11-NEXT: v_cmp_lt_i64_e64 s4, s[2:3], s[6:7]6328; GFX11-NEXT: v_cmp_gt_u64_e64 s6, s[12:13], 06329; GFX11-NEXT: s_cselect_b32 s10, 1, 06330; GFX11-NEXT: v_mov_b32_e32 v5, s06331; GFX11-NEXT: v_cndmask_b32_e64 v2, 0, 1, s46332; GFX11-NEXT: s_and_b32 s4, 1, s106333; GFX11-NEXT: s_cmp_eq_u64 s[14:15], 06334; GFX11-NEXT: v_cndmask_b32_e64 v3, 0, 1, s66335; GFX11-NEXT: v_cmp_gt_i64_e64 s6, s[14:15], 06336; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s46337; GFX11-NEXT: s_cselect_b32 s5, 1, 06338; GFX11-NEXT: v_and_b32_e32 v0, 1, v06339; GFX11-NEXT: s_and_b32 s5, 1, s56340; GFX11-NEXT: s_ashr_i32 s4, s3, 316341; GFX11-NEXT: v_cndmask_b32_e64 v4, 0, 1, s66342; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo6343; GFX11-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s56344; GFX11-NEXT: s_add_i32 s0, s4, 0x800000006345; GFX11-NEXT: v_dual_cndmask_b32 v2, v4, v3 :: v_dual_mov_b32 v3, s186346; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v06347; GFX11-NEXT: v_mov_b32_e32 v4, s176348; GFX11-NEXT: v_xor_b32_e32 v1, v2, v16349; GFX11-NEXT: v_mov_b32_e32 v0, s196350; GFX11-NEXT: v_mov_b32_e32 v2, s166351; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s8, vcc_lo6352; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s9, vcc_lo6353; GFX11-NEXT: v_and_b32_e32 v1, 1, v16354; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s8, vcc_lo6355; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s8, vcc_lo6356; GFX11-NEXT: v_readfirstlane_b32 s3, v46357; GFX11-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v16358; GFX11-NEXT: v_mov_b32_e32 v1, s16359; GFX11-NEXT: v_readfirstlane_b32 s1, v06360; GFX11-NEXT: v_readfirstlane_b32 s2, v26361; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s4, vcc_lo6362; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo6363; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s4, vcc_lo6364; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s0, vcc_lo6365; GFX11-NEXT: v_readfirstlane_b32 s0, v36366; GFX11-NEXT: v_readfirstlane_b32 s4, v56367; GFX11-NEXT: v_readfirstlane_b32 s5, v16368; GFX11-NEXT: v_readfirstlane_b32 s6, v66369; GFX11-NEXT: v_readfirstlane_b32 s7, v76370; GFX11-NEXT: ; return to shader part epilog6371 %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)6372 ret <2 x i128> %result6373}6374 6375declare i7 @llvm.ssub.sat.i7(i7, i7) #06376declare i8 @llvm.ssub.sat.i8(i8, i8) #06377declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>) #06378declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>) #06379 6380declare i16 @llvm.ssub.sat.i16(i16, i16) #06381declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #06382declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #06383declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #06384declare <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16>, <5 x i16>) #06385declare <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16>, <6 x i16>) #06386declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #06387 6388declare i24 @llvm.ssub.sat.i24(i24, i24) #06389 6390declare i32 @llvm.ssub.sat.i32(i32, i32) #06391declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #06392declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #06393declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #06394declare <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32>, <5 x i32>) #06395declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #06396 6397declare i48 @llvm.ssub.sat.i48(i48, i48) #06398 6399declare i64 @llvm.ssub.sat.i64(i64, i64) #06400declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>) #06401 6402declare i128 @llvm.ssub.sat.i128(i128, i128) #06403declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>) #06404 6405attributes #0 = { nounwind readnone speculatable willreturn }6406