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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji < %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s6 7define <2 x i16> @v_sub_v2i16(<2 x i16> %a, <2 x i16> %b) {8; GFX9-LABEL: v_sub_v2i16:9; GFX9: ; %bb.0:10; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GFX9-NEXT: v_pk_sub_i16 v0, v0, v112; GFX9-NEXT: s_setpc_b64 s[30:31]13;14; GFX8-LABEL: v_sub_v2i16:15; GFX8: ; %bb.0:16; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)17; GFX8-NEXT: v_sub_u16_e32 v2, v0, v118; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_119; GFX8-NEXT: v_or_b32_e32 v0, v2, v020; GFX8-NEXT: s_setpc_b64 s[30:31]21;22; GFX10-LABEL: v_sub_v2i16:23; GFX10: ; %bb.0:24; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)25; GFX10-NEXT: v_pk_sub_i16 v0, v0, v126; GFX10-NEXT: s_setpc_b64 s[30:31]27;28; GFX11-LABEL: v_sub_v2i16:29; GFX11: ; %bb.0:30; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; GFX11-NEXT: v_pk_sub_i16 v0, v0, v132; GFX11-NEXT: s_setpc_b64 s[30:31]33 %sub = sub <2 x i16> %a, %b34 ret <2 x i16> %sub35}36 37define <2 x i16> @v_sub_v2i16_fneg_lhs(<2 x half> %a, <2 x i16> %b) {38; GFX9-LABEL: v_sub_v2i16_fneg_lhs:39; GFX9: ; %bb.0:40; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]42; GFX9-NEXT: s_setpc_b64 s[30:31]43;44; GFX8-LABEL: v_sub_v2i16_fneg_lhs:45; GFX8: ; %bb.0:46; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v048; GFX8-NEXT: v_sub_u16_e32 v2, v0, v149; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_150; GFX8-NEXT: v_or_b32_e32 v0, v2, v051; GFX8-NEXT: s_setpc_b64 s[30:31]52;53; GFX10-LABEL: v_sub_v2i16_fneg_lhs:54; GFX10: ; %bb.0:55; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]57; GFX10-NEXT: s_setpc_b64 s[30:31]58;59; GFX11-LABEL: v_sub_v2i16_fneg_lhs:60; GFX11: ; %bb.0:61; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)62; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,0] neg_hi:[1,0]63; GFX11-NEXT: s_setpc_b64 s[30:31]64 %neg.a = fneg <2 x half> %a65 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>66 %sub = sub <2 x i16> %cast.neg.a, %b67 ret <2 x i16> %sub68}69 70define <2 x i16> @v_sub_v2i16_fneg_rhs(<2 x i16> %a, <2 x half> %b) {71; GFX9-LABEL: v_sub_v2i16_fneg_rhs:72; GFX9: ; %bb.0:73; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]75; GFX9-NEXT: s_setpc_b64 s[30:31]76;77; GFX8-LABEL: v_sub_v2i16_fneg_rhs:78; GFX8: ; %bb.0:79; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v181; GFX8-NEXT: v_sub_u16_e32 v2, v0, v182; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_183; GFX8-NEXT: v_or_b32_e32 v0, v2, v084; GFX8-NEXT: s_setpc_b64 s[30:31]85;86; GFX10-LABEL: v_sub_v2i16_fneg_rhs:87; GFX10: ; %bb.0:88; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)89; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]90; GFX10-NEXT: s_setpc_b64 s[30:31]91;92; GFX11-LABEL: v_sub_v2i16_fneg_rhs:93; GFX11: ; %bb.0:94; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[0,1] neg_hi:[0,1]96; GFX11-NEXT: s_setpc_b64 s[30:31]97 %neg.b = fneg <2 x half> %b98 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>99 %sub = sub <2 x i16> %a, %cast.neg.b100 ret <2 x i16> %sub101}102 103define <2 x i16> @v_sub_v2i16_fneg_lhs_fneg_rhs(<2 x half> %a, <2 x half> %b) {104; GFX9-LABEL: v_sub_v2i16_fneg_lhs_fneg_rhs:105; GFX9: ; %bb.0:106; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]108; GFX9-NEXT: s_setpc_b64 s[30:31]109;110; GFX8-LABEL: v_sub_v2i16_fneg_lhs_fneg_rhs:111; GFX8: ; %bb.0:112; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GFX8-NEXT: v_xor_b32_e32 v0, 0x80008000, v0114; GFX8-NEXT: v_xor_b32_e32 v1, 0x80008000, v1115; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1116; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1117; GFX8-NEXT: v_or_b32_e32 v0, v2, v0118; GFX8-NEXT: s_setpc_b64 s[30:31]119;120; GFX10-LABEL: v_sub_v2i16_fneg_lhs_fneg_rhs:121; GFX10: ; %bb.0:122; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)123; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]124; GFX10-NEXT: s_setpc_b64 s[30:31]125;126; GFX11-LABEL: v_sub_v2i16_fneg_lhs_fneg_rhs:127; GFX11: ; %bb.0:128; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; GFX11-NEXT: v_pk_sub_i16 v0, v0, v1 neg_lo:[1,1] neg_hi:[1,1]130; GFX11-NEXT: s_setpc_b64 s[30:31]131 %neg.a = fneg <2 x half> %a132 %neg.b = fneg <2 x half> %b133 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>134 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>135 %sub = sub <2 x i16> %cast.neg.a, %cast.neg.b136 ret <2 x i16> %sub137}138 139define <2 x i16> @v_sub_v2i16_neg_inline_imm_splat(<2 x i16> %a) {140; GFX9-LABEL: v_sub_v2i16_neg_inline_imm_splat:141; GFX9: ; %bb.0:142; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)143; GFX9-NEXT: v_mov_b32_e32 v1, 0xffc0ffc0144; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1145; GFX9-NEXT: s_setpc_b64 s[30:31]146;147; GFX8-LABEL: v_sub_v2i16_neg_inline_imm_splat:148; GFX8: ; %bb.0:149; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150; GFX8-NEXT: v_mov_b32_e32 v2, 64151; GFX8-NEXT: v_add_u16_e32 v1, 64, v0152; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD153; GFX8-NEXT: v_or_b32_e32 v0, v1, v0154; GFX8-NEXT: s_setpc_b64 s[30:31]155;156; GFX10-LABEL: v_sub_v2i16_neg_inline_imm_splat:157; GFX10: ; %bb.0:158; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0xffc0ffc0160; GFX10-NEXT: s_setpc_b64 s[30:31]161;162; GFX11-LABEL: v_sub_v2i16_neg_inline_imm_splat:163; GFX11: ; %bb.0:164; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; GFX11-NEXT: v_pk_sub_i16 v0, v0, 0xffc0ffc0166; GFX11-NEXT: s_setpc_b64 s[30:31]167 %sub = sub <2 x i16> %a, <i16 -64, i16 -64>168 ret <2 x i16> %sub169}170 171define <2 x i16> @v_sub_v2i16_neg_inline_imm_lo(<2 x i16> %a) {172; GFX9-LABEL: v_sub_v2i16_neg_inline_imm_lo:173; GFX9: ; %bb.0:174; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)175; GFX9-NEXT: v_mov_b32_e32 v1, 0x4ffc0176; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1177; GFX9-NEXT: s_setpc_b64 s[30:31]178;179; GFX8-LABEL: v_sub_v2i16_neg_inline_imm_lo:180; GFX8: ; %bb.0:181; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)182; GFX8-NEXT: v_mov_b32_e32 v2, -4183; GFX8-NEXT: v_add_u16_e32 v1, 64, v0184; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD185; GFX8-NEXT: v_or_b32_e32 v0, v1, v0186; GFX8-NEXT: s_setpc_b64 s[30:31]187;188; GFX10-LABEL: v_sub_v2i16_neg_inline_imm_lo:189; GFX10: ; %bb.0:190; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)191; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0x4ffc0192; GFX10-NEXT: s_setpc_b64 s[30:31]193;194; GFX11-LABEL: v_sub_v2i16_neg_inline_imm_lo:195; GFX11: ; %bb.0:196; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX11-NEXT: v_pk_sub_i16 v0, v0, 0x4ffc0198; GFX11-NEXT: s_setpc_b64 s[30:31]199 %sub = sub <2 x i16> %a, <i16 -64, i16 4>200 ret <2 x i16> %sub201}202 203define <2 x i16> @v_sub_v2i16_neg_inline_imm_hi(<2 x i16> %a) {204; GFX9-LABEL: v_sub_v2i16_neg_inline_imm_hi:205; GFX9: ; %bb.0:206; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)207; GFX9-NEXT: v_mov_b32_e32 v1, 0xffc00004208; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1209; GFX9-NEXT: s_setpc_b64 s[30:31]210;211; GFX8-LABEL: v_sub_v2i16_neg_inline_imm_hi:212; GFX8: ; %bb.0:213; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; GFX8-NEXT: v_mov_b32_e32 v2, 64215; GFX8-NEXT: v_add_u16_e32 v1, -4, v0216; GFX8-NEXT: v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD217; GFX8-NEXT: v_or_b32_e32 v0, v1, v0218; GFX8-NEXT: s_setpc_b64 s[30:31]219;220; GFX10-LABEL: v_sub_v2i16_neg_inline_imm_hi:221; GFX10: ; %bb.0:222; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)223; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0xffc00004224; GFX10-NEXT: s_setpc_b64 s[30:31]225;226; GFX11-LABEL: v_sub_v2i16_neg_inline_imm_hi:227; GFX11: ; %bb.0:228; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)229; GFX11-NEXT: v_pk_sub_i16 v0, v0, 0xffc00004230; GFX11-NEXT: s_setpc_b64 s[30:31]231 %sub = sub <2 x i16> %a, <i16 4, i16 -64>232 ret <2 x i16> %sub233}234 235define amdgpu_ps i32 @s_sub_v2i16_neg_inline_imm_splat(<2 x i16> inreg %a) {236; GFX9-LABEL: s_sub_v2i16_neg_inline_imm_splat:237; GFX9: ; %bb.0:238; GFX9-NEXT: s_lshr_b32 s1, s0, 16239; GFX9-NEXT: s_sub_i32 s0, s0, 0xffc0ffc0240; GFX9-NEXT: s_sub_i32 s1, s1, 0xffc0241; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1242; GFX9-NEXT: ; return to shader part epilog243;244; GFX8-LABEL: s_sub_v2i16_neg_inline_imm_splat:245; GFX8: ; %bb.0:246; GFX8-NEXT: s_lshr_b32 s1, s0, 16247; GFX8-NEXT: s_add_i32 s1, s1, 64248; GFX8-NEXT: s_add_i32 s0, s0, 64249; GFX8-NEXT: s_and_b32 s1, 0xffff, s1250; GFX8-NEXT: s_and_b32 s0, 0xffff, s0251; GFX8-NEXT: s_lshl_b32 s1, s1, 16252; GFX8-NEXT: s_or_b32 s0, s0, s1253; GFX8-NEXT: ; return to shader part epilog254;255; GFX10-LABEL: s_sub_v2i16_neg_inline_imm_splat:256; GFX10: ; %bb.0:257; GFX10-NEXT: s_lshr_b32 s1, s0, 16258; GFX10-NEXT: s_sub_i32 s0, s0, 0xffc0ffc0259; GFX10-NEXT: s_sub_i32 s1, s1, 0xffc0260; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1261; GFX10-NEXT: ; return to shader part epilog262;263; GFX11-LABEL: s_sub_v2i16_neg_inline_imm_splat:264; GFX11: ; %bb.0:265; GFX11-NEXT: s_lshr_b32 s1, s0, 16266; GFX11-NEXT: s_sub_i32 s0, s0, 0xffc0ffc0267; GFX11-NEXT: s_sub_i32 s1, s1, 0xffc0268; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1269; GFX11-NEXT: ; return to shader part epilog270 %sub = sub <2 x i16> %a, <i16 -64, i16 -64>271 %cast = bitcast <2 x i16> %sub to i32272 ret i32 %cast273}274 275define amdgpu_ps i32 @s_sub_v2i16_neg_inline_imm_lo(<2 x i16> inreg %a) {276; GFX9-LABEL: s_sub_v2i16_neg_inline_imm_lo:277; GFX9: ; %bb.0:278; GFX9-NEXT: s_lshr_b32 s1, s0, 16279; GFX9-NEXT: s_sub_i32 s0, s0, 0x4ffc0280; GFX9-NEXT: s_sub_i32 s1, s1, 4281; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1282; GFX9-NEXT: ; return to shader part epilog283;284; GFX8-LABEL: s_sub_v2i16_neg_inline_imm_lo:285; GFX8: ; %bb.0:286; GFX8-NEXT: s_lshr_b32 s1, s0, 16287; GFX8-NEXT: s_add_i32 s1, s1, 0xfffc288; GFX8-NEXT: s_add_i32 s0, s0, 64289; GFX8-NEXT: s_and_b32 s1, 0xffff, s1290; GFX8-NEXT: s_and_b32 s0, 0xffff, s0291; GFX8-NEXT: s_lshl_b32 s1, s1, 16292; GFX8-NEXT: s_or_b32 s0, s0, s1293; GFX8-NEXT: ; return to shader part epilog294;295; GFX10-LABEL: s_sub_v2i16_neg_inline_imm_lo:296; GFX10: ; %bb.0:297; GFX10-NEXT: s_lshr_b32 s1, s0, 16298; GFX10-NEXT: s_sub_i32 s0, s0, 0x4ffc0299; GFX10-NEXT: s_sub_i32 s1, s1, 4300; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1301; GFX10-NEXT: ; return to shader part epilog302;303; GFX11-LABEL: s_sub_v2i16_neg_inline_imm_lo:304; GFX11: ; %bb.0:305; GFX11-NEXT: s_lshr_b32 s1, s0, 16306; GFX11-NEXT: s_sub_i32 s0, s0, 0x4ffc0307; GFX11-NEXT: s_sub_i32 s1, s1, 4308; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1309; GFX11-NEXT: ; return to shader part epilog310 %sub = sub <2 x i16> %a, <i16 -64, i16 4>311 %cast = bitcast <2 x i16> %sub to i32312 ret i32 %cast313}314 315define amdgpu_ps i32 @s_sub_v2i16_neg_inline_imm_hi(<2 x i16> inreg %a) {316; GFX9-LABEL: s_sub_v2i16_neg_inline_imm_hi:317; GFX9: ; %bb.0:318; GFX9-NEXT: s_lshr_b32 s1, s0, 16319; GFX9-NEXT: s_sub_i32 s0, s0, 0xffc00004320; GFX9-NEXT: s_sub_i32 s1, s1, 0xffc0321; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1322; GFX9-NEXT: ; return to shader part epilog323;324; GFX8-LABEL: s_sub_v2i16_neg_inline_imm_hi:325; GFX8: ; %bb.0:326; GFX8-NEXT: s_lshr_b32 s1, s0, 16327; GFX8-NEXT: s_add_i32 s1, s1, 64328; GFX8-NEXT: s_add_i32 s0, s0, 0xfffc329; GFX8-NEXT: s_and_b32 s1, 0xffff, s1330; GFX8-NEXT: s_and_b32 s0, 0xffff, s0331; GFX8-NEXT: s_lshl_b32 s1, s1, 16332; GFX8-NEXT: s_or_b32 s0, s0, s1333; GFX8-NEXT: ; return to shader part epilog334;335; GFX10-LABEL: s_sub_v2i16_neg_inline_imm_hi:336; GFX10: ; %bb.0:337; GFX10-NEXT: s_lshr_b32 s1, s0, 16338; GFX10-NEXT: s_sub_i32 s0, s0, 0xffc00004339; GFX10-NEXT: s_sub_i32 s1, s1, 0xffc0340; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1341; GFX10-NEXT: ; return to shader part epilog342;343; GFX11-LABEL: s_sub_v2i16_neg_inline_imm_hi:344; GFX11: ; %bb.0:345; GFX11-NEXT: s_lshr_b32 s1, s0, 16346; GFX11-NEXT: s_sub_i32 s0, s0, 0xffc00004347; GFX11-NEXT: s_sub_i32 s1, s1, 0xffc0348; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1349; GFX11-NEXT: ; return to shader part epilog350 %sub = sub <2 x i16> %a, <i16 4, i16 -64>351 %cast = bitcast <2 x i16> %sub to i32352 ret i32 %cast353}354 355define amdgpu_ps i32 @s_sub_v2i16(<2 x i16> inreg %a, <2 x i16> inreg %b) {356; GFX9-LABEL: s_sub_v2i16:357; GFX9: ; %bb.0:358; GFX9-NEXT: s_lshr_b32 s2, s0, 16359; GFX9-NEXT: s_lshr_b32 s3, s1, 16360; GFX9-NEXT: s_sub_i32 s0, s0, s1361; GFX9-NEXT: s_sub_i32 s1, s2, s3362; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1363; GFX9-NEXT: ; return to shader part epilog364;365; GFX8-LABEL: s_sub_v2i16:366; GFX8: ; %bb.0:367; GFX8-NEXT: s_lshr_b32 s2, s0, 16368; GFX8-NEXT: s_lshr_b32 s3, s1, 16369; GFX8-NEXT: s_sub_i32 s0, s0, s1370; GFX8-NEXT: s_sub_i32 s1, s2, s3371; GFX8-NEXT: s_and_b32 s1, 0xffff, s1372; GFX8-NEXT: s_and_b32 s0, 0xffff, s0373; GFX8-NEXT: s_lshl_b32 s1, s1, 16374; GFX8-NEXT: s_or_b32 s0, s0, s1375; GFX8-NEXT: ; return to shader part epilog376;377; GFX10-LABEL: s_sub_v2i16:378; GFX10: ; %bb.0:379; GFX10-NEXT: s_lshr_b32 s2, s0, 16380; GFX10-NEXT: s_lshr_b32 s3, s1, 16381; GFX10-NEXT: s_sub_i32 s0, s0, s1382; GFX10-NEXT: s_sub_i32 s1, s2, s3383; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1384; GFX10-NEXT: ; return to shader part epilog385;386; GFX11-LABEL: s_sub_v2i16:387; GFX11: ; %bb.0:388; GFX11-NEXT: s_lshr_b32 s2, s0, 16389; GFX11-NEXT: s_lshr_b32 s3, s1, 16390; GFX11-NEXT: s_sub_i32 s0, s0, s1391; GFX11-NEXT: s_sub_i32 s1, s2, s3392; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1393; GFX11-NEXT: ; return to shader part epilog394 %sub = sub <2 x i16> %a, %b395 %cast = bitcast <2 x i16> %sub to i32396 ret i32 %cast397}398 399define amdgpu_ps i32 @s_sub_v2i16_fneg_lhs(<2 x half> inreg %a, <2 x i16> inreg %b) {400; GFX9-LABEL: s_sub_v2i16_fneg_lhs:401; GFX9: ; %bb.0:402; GFX9-NEXT: s_xor_b32 s0, s0, 0x80008000403; GFX9-NEXT: s_lshr_b32 s2, s0, 16404; GFX9-NEXT: s_lshr_b32 s3, s1, 16405; GFX9-NEXT: s_sub_i32 s0, s0, s1406; GFX9-NEXT: s_sub_i32 s1, s2, s3407; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1408; GFX9-NEXT: ; return to shader part epilog409;410; GFX8-LABEL: s_sub_v2i16_fneg_lhs:411; GFX8: ; %bb.0:412; GFX8-NEXT: s_xor_b32 s0, s0, 0x80008000413; GFX8-NEXT: s_lshr_b32 s2, s0, 16414; GFX8-NEXT: s_lshr_b32 s3, s1, 16415; GFX8-NEXT: s_sub_i32 s0, s0, s1416; GFX8-NEXT: s_sub_i32 s1, s2, s3417; GFX8-NEXT: s_and_b32 s1, 0xffff, s1418; GFX8-NEXT: s_and_b32 s0, 0xffff, s0419; GFX8-NEXT: s_lshl_b32 s1, s1, 16420; GFX8-NEXT: s_or_b32 s0, s0, s1421; GFX8-NEXT: ; return to shader part epilog422;423; GFX10-LABEL: s_sub_v2i16_fneg_lhs:424; GFX10: ; %bb.0:425; GFX10-NEXT: s_xor_b32 s0, s0, 0x80008000426; GFX10-NEXT: s_lshr_b32 s3, s1, 16427; GFX10-NEXT: s_lshr_b32 s2, s0, 16428; GFX10-NEXT: s_sub_i32 s0, s0, s1429; GFX10-NEXT: s_sub_i32 s1, s2, s3430; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1431; GFX10-NEXT: ; return to shader part epilog432;433; GFX11-LABEL: s_sub_v2i16_fneg_lhs:434; GFX11: ; %bb.0:435; GFX11-NEXT: s_xor_b32 s0, s0, 0x80008000436; GFX11-NEXT: s_lshr_b32 s3, s1, 16437; GFX11-NEXT: s_lshr_b32 s2, s0, 16438; GFX11-NEXT: s_sub_i32 s0, s0, s1439; GFX11-NEXT: s_sub_i32 s1, s2, s3440; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1441; GFX11-NEXT: ; return to shader part epilog442 %neg.a = fneg <2 x half> %a443 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>444 %sub = sub <2 x i16> %cast.neg.a, %b445 %cast = bitcast <2 x i16> %sub to i32446 ret i32 %cast447}448 449define amdgpu_ps i32 @s_sub_v2i16_fneg_rhs(<2 x i16> inreg %a, <2 x half> inreg %b) {450; GFX9-LABEL: s_sub_v2i16_fneg_rhs:451; GFX9: ; %bb.0:452; GFX9-NEXT: s_xor_b32 s1, s1, 0x80008000453; GFX9-NEXT: s_lshr_b32 s2, s0, 16454; GFX9-NEXT: s_lshr_b32 s3, s1, 16455; GFX9-NEXT: s_sub_i32 s0, s0, s1456; GFX9-NEXT: s_sub_i32 s1, s2, s3457; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1458; GFX9-NEXT: ; return to shader part epilog459;460; GFX8-LABEL: s_sub_v2i16_fneg_rhs:461; GFX8: ; %bb.0:462; GFX8-NEXT: s_xor_b32 s1, s1, 0x80008000463; GFX8-NEXT: s_lshr_b32 s2, s0, 16464; GFX8-NEXT: s_lshr_b32 s3, s1, 16465; GFX8-NEXT: s_sub_i32 s0, s0, s1466; GFX8-NEXT: s_sub_i32 s1, s2, s3467; GFX8-NEXT: s_and_b32 s1, 0xffff, s1468; GFX8-NEXT: s_and_b32 s0, 0xffff, s0469; GFX8-NEXT: s_lshl_b32 s1, s1, 16470; GFX8-NEXT: s_or_b32 s0, s0, s1471; GFX8-NEXT: ; return to shader part epilog472;473; GFX10-LABEL: s_sub_v2i16_fneg_rhs:474; GFX10: ; %bb.0:475; GFX10-NEXT: s_xor_b32 s1, s1, 0x80008000476; GFX10-NEXT: s_lshr_b32 s2, s0, 16477; GFX10-NEXT: s_lshr_b32 s3, s1, 16478; GFX10-NEXT: s_sub_i32 s0, s0, s1479; GFX10-NEXT: s_sub_i32 s1, s2, s3480; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1481; GFX10-NEXT: ; return to shader part epilog482;483; GFX11-LABEL: s_sub_v2i16_fneg_rhs:484; GFX11: ; %bb.0:485; GFX11-NEXT: s_xor_b32 s1, s1, 0x80008000486; GFX11-NEXT: s_lshr_b32 s2, s0, 16487; GFX11-NEXT: s_lshr_b32 s3, s1, 16488; GFX11-NEXT: s_sub_i32 s0, s0, s1489; GFX11-NEXT: s_sub_i32 s1, s2, s3490; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1491; GFX11-NEXT: ; return to shader part epilog492 %neg.b = fneg <2 x half> %b493 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>494 %sub = sub <2 x i16> %a, %cast.neg.b495 %cast = bitcast <2 x i16> %sub to i32496 ret i32 %cast497}498 499define amdgpu_ps i32 @s_sub_v2i16_fneg_lhs_fneg_rhs(<2 x half> inreg %a, <2 x half> inreg %b) {500; GFX9-LABEL: s_sub_v2i16_fneg_lhs_fneg_rhs:501; GFX9: ; %bb.0:502; GFX9-NEXT: s_xor_b32 s0, s0, 0x80008000503; GFX9-NEXT: s_xor_b32 s1, s1, 0x80008000504; GFX9-NEXT: s_lshr_b32 s2, s0, 16505; GFX9-NEXT: s_lshr_b32 s3, s1, 16506; GFX9-NEXT: s_sub_i32 s0, s0, s1507; GFX9-NEXT: s_sub_i32 s1, s2, s3508; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s1509; GFX9-NEXT: ; return to shader part epilog510;511; GFX8-LABEL: s_sub_v2i16_fneg_lhs_fneg_rhs:512; GFX8: ; %bb.0:513; GFX8-NEXT: s_xor_b32 s0, s0, 0x80008000514; GFX8-NEXT: s_xor_b32 s1, s1, 0x80008000515; GFX8-NEXT: s_lshr_b32 s2, s0, 16516; GFX8-NEXT: s_lshr_b32 s3, s1, 16517; GFX8-NEXT: s_sub_i32 s0, s0, s1518; GFX8-NEXT: s_sub_i32 s1, s2, s3519; GFX8-NEXT: s_and_b32 s1, 0xffff, s1520; GFX8-NEXT: s_and_b32 s0, 0xffff, s0521; GFX8-NEXT: s_lshl_b32 s1, s1, 16522; GFX8-NEXT: s_or_b32 s0, s0, s1523; GFX8-NEXT: ; return to shader part epilog524;525; GFX10-LABEL: s_sub_v2i16_fneg_lhs_fneg_rhs:526; GFX10: ; %bb.0:527; GFX10-NEXT: s_xor_b32 s0, s0, 0x80008000528; GFX10-NEXT: s_xor_b32 s1, s1, 0x80008000529; GFX10-NEXT: s_lshr_b32 s2, s0, 16530; GFX10-NEXT: s_lshr_b32 s3, s1, 16531; GFX10-NEXT: s_sub_i32 s0, s0, s1532; GFX10-NEXT: s_sub_i32 s1, s2, s3533; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s1534; GFX10-NEXT: ; return to shader part epilog535;536; GFX11-LABEL: s_sub_v2i16_fneg_lhs_fneg_rhs:537; GFX11: ; %bb.0:538; GFX11-NEXT: s_xor_b32 s0, s0, 0x80008000539; GFX11-NEXT: s_xor_b32 s1, s1, 0x80008000540; GFX11-NEXT: s_lshr_b32 s2, s0, 16541; GFX11-NEXT: s_lshr_b32 s3, s1, 16542; GFX11-NEXT: s_sub_i32 s0, s0, s1543; GFX11-NEXT: s_sub_i32 s1, s2, s3544; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s1545; GFX11-NEXT: ; return to shader part epilog546 %neg.a = fneg <2 x half> %a547 %neg.b = fneg <2 x half> %b548 %cast.neg.a = bitcast <2 x half> %neg.a to <2 x i16>549 %cast.neg.b = bitcast <2 x half> %neg.b to <2 x i16>550 %sub = sub <2 x i16> %cast.neg.a, %cast.neg.b551 %cast = bitcast <2 x i16> %sub to i32552 ret i32 %cast553}554