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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s5 6define i32 @v_usubo_i32(i32 %a, i32 %b) {7; GFX7-LABEL: v_usubo_i32:8; GFX7: ; %bb.0:9; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v111; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc12; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v113; GFX7-NEXT: s_setpc_b64 s[30:31]14;15; GFX8-LABEL: v_usubo_i32:16; GFX8: ; %bb.0:17; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)18; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v119; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc20; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v121; GFX8-NEXT: s_setpc_b64 s[30:31]22;23; GFX9-LABEL: v_usubo_i32:24; GFX9: ; %bb.0:25; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)26; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v127; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc28; GFX9-NEXT: v_sub_u32_e32 v0, v0, v129; GFX9-NEXT: s_setpc_b64 s[30:31]30 %usubo = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)31 %sub = extractvalue {i32, i1} %usubo, 032 %of = extractvalue {i32, i1} %usubo, 133 %of.zext = zext i1 %of to i3234 %ret = sub i32 %sub, %of.zext35 ret i32 %ret36}37 38define i64 @v_usubo_i64(i64 %a, i64 %b) {39; GFX7-LABEL: v_usubo_i64:40; GFX7: ; %bb.0:41; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v243; GFX7-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc44; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc45; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v246; GFX7-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc47; GFX7-NEXT: s_setpc_b64 s[30:31]48;49; GFX8-LABEL: v_usubo_i64:50; GFX8: ; %bb.0:51; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v253; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc54; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc55; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v256; GFX8-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc57; GFX8-NEXT: s_setpc_b64 s[30:31]58;59; GFX9-LABEL: v_usubo_i64:60; GFX9: ; %bb.0:61; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)62; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v263; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc64; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc65; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v266; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v1, vcc67; GFX9-NEXT: s_setpc_b64 s[30:31]68 %usubo = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)69 %sub = extractvalue {i64, i1} %usubo, 070 %of = extractvalue {i64, i1} %usubo, 171 %of.zext = zext i1 %of to i6472 %ret = sub i64 %sub, %of.zext73 ret i64 %ret74}75 76define i8 @v_usubo_i8(i8 %a, i8 %b) {77; GFX7-LABEL: v_usubo_i8:78; GFX7: ; %bb.0:79; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)80; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v081; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v182; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v183; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v084; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v185; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc86; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v187; GFX7-NEXT: s_setpc_b64 s[30:31]88;89; GFX8-LABEL: v_usubo_i8:90; GFX8: ; %bb.0:91; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)92; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v093; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v194; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v195; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v096; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v197; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc98; GFX8-NEXT: v_sub_u16_e32 v0, v0, v199; GFX8-NEXT: s_setpc_b64 s[30:31]100;101; GFX9-LABEL: v_usubo_i8:102; GFX9: ; %bb.0:103; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)104; GFX9-NEXT: v_sub_u32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0105; GFX9-NEXT: v_cmp_ne_u32_sdwa s[4:5], v0, v0 src0_sel:DWORD src1_sel:BYTE_0106; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]107; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1108; GFX9-NEXT: s_setpc_b64 s[30:31]109 %usubo = call {i8, i1} @llvm.usub.with.overflow.i8(i8 %a, i8 %b)110 %sub = extractvalue {i8, i1} %usubo, 0111 %of = extractvalue {i8, i1} %usubo, 1112 %of.zext = zext i1 %of to i8113 %ret = sub i8 %sub, %of.zext114 ret i8 %ret115}116 117define i7 @v_usubo_i7(i7 %a, i7 %b) {118; GFX7-LABEL: v_usubo_i7:119; GFX7: ; %bb.0:120; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)121; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0122; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1123; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1124; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0125; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1126; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc127; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1128; GFX7-NEXT: s_setpc_b64 s[30:31]129;130; GFX8-LABEL: v_usubo_i7:131; GFX8: ; %bb.0:132; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)133; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0134; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1135; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1136; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0137; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1138; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc139; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1140; GFX8-NEXT: s_setpc_b64 s[30:31]141;142; GFX9-LABEL: v_usubo_i7:143; GFX9: ; %bb.0:144; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0146; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1147; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1148; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0149; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1150; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc151; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1152; GFX9-NEXT: s_setpc_b64 s[30:31]153 %usubo = call {i7, i1} @llvm.usub.with.overflow.i7(i7 %a, i7 %b)154 %sub = extractvalue {i7, i1} %usubo, 0155 %of = extractvalue {i7, i1} %usubo, 1156 %of.zext = zext i1 %of to i7157 %ret = sub i7 %sub, %of.zext158 ret i7 %ret159}160 161define <2 x i32> @v_usubo_v2i32(<2 x i32> %a, <2 x i32> %b) {162; GFX7-LABEL: v_usubo_v2i32:163; GFX7: ; %bb.0:164; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v2166; GFX7-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc167; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v1, v3168; GFX7-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc169; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v2170; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v1, v3171; GFX7-NEXT: s_setpc_b64 s[30:31]172;173; GFX8-LABEL: v_usubo_v2i32:174; GFX8: ; %bb.0:175; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)176; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2177; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc178; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3179; GFX8-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc180; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2181; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3182; GFX8-NEXT: s_setpc_b64 s[30:31]183;184; GFX9-LABEL: v_usubo_v2i32:185; GFX9: ; %bb.0:186; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)187; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2188; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc189; GFX9-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v3190; GFX9-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc191; GFX9-NEXT: v_sub_u32_e32 v0, v0, v2192; GFX9-NEXT: v_sub_u32_e32 v1, v1, v3193; GFX9-NEXT: s_setpc_b64 s[30:31]194 %usubo = call {<2 x i32>, <2 x i1>} @llvm.usub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)195 %sub = extractvalue {<2 x i32>, <2 x i1>} %usubo, 0196 %of = extractvalue {<2 x i32>, <2 x i1>} %usubo, 1197 %of.zext = zext <2 x i1> %of to <2 x i32>198 %ret = sub <2 x i32> %sub, %of.zext199 ret <2 x i32> %ret200}201 202define i32 @v_ssubo_i32(i32 %a, i32 %b) {203; GFX7-LABEL: v_ssubo_i32:204; GFX7: ; %bb.0:205; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)206; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1207; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0208; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1209; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc210; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]211; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0212; GFX7-NEXT: s_setpc_b64 s[30:31]213;214; GFX8-LABEL: v_ssubo_i32:215; GFX8: ; %bb.0:216; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)217; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1218; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0219; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1220; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc221; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]222; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v2, v0223; GFX8-NEXT: s_setpc_b64 s[30:31]224;225; GFX9-LABEL: v_ssubo_i32:226; GFX9: ; %bb.0:227; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)228; GFX9-NEXT: v_sub_u32_e32 v2, v0, v1229; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v2, v0230; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v1231; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc232; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]233; GFX9-NEXT: v_sub_u32_e32 v0, v2, v0234; GFX9-NEXT: s_setpc_b64 s[30:31]235 %ssubo = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)236 %sub = extractvalue {i32, i1} %ssubo, 0237 %of = extractvalue {i32, i1} %ssubo, 1238 %of.zext = zext i1 %of to i32239 %ret = sub i32 %sub, %of.zext240 ret i32 %ret241}242 243define i64 @v_ssubo_i64(i64 %a, i64 %b) {244; GFX7-LABEL: v_ssubo_i64:245; GFX7: ; %bb.0:246; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)247; GFX7-NEXT: v_sub_i32_e32 v4, vcc, v0, v2248; GFX7-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc249; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]250; GFX7-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]251; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc252; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]253; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v4, v0254; GFX7-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v5, vcc255; GFX7-NEXT: s_setpc_b64 s[30:31]256;257; GFX8-LABEL: v_ssubo_i64:258; GFX8: ; %bb.0:259; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)260; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2261; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc262; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]263; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]264; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc265; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]266; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v4, v0267; GFX8-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v5, vcc268; GFX8-NEXT: s_setpc_b64 s[30:31]269;270; GFX9-LABEL: v_ssubo_i64:271; GFX9: ; %bb.0:272; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)273; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2274; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc275; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]276; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]277; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc278; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]279; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v4, v0280; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v5, vcc281; GFX9-NEXT: s_setpc_b64 s[30:31]282 %ssubo = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)283 %sub = extractvalue {i64, i1} %ssubo, 0284 %of = extractvalue {i64, i1} %ssubo, 1285 %of.zext = zext i1 %of to i64286 %ret = sub i64 %sub, %of.zext287 ret i64 %ret288}289 290define <2 x i32> @v_ssubo_v2i32(<2 x i32> %a, <2 x i32> %b) {291; GFX7-LABEL: v_ssubo_v2i32:292; GFX7: ; %bb.0:293; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)294; GFX7-NEXT: v_sub_i32_e32 v4, vcc, v0, v2295; GFX7-NEXT: v_sub_i32_e32 v5, vcc, v1, v3296; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0297; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1298; GFX7-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2299; GFX7-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3300; GFX7-NEXT: s_xor_b64 s[6:7], s[6:7], vcc301; GFX7-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]302; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]303; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]304; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v4, v0305; GFX7-NEXT: v_sub_i32_e32 v1, vcc, v5, v1306; GFX7-NEXT: s_setpc_b64 s[30:31]307;308; GFX8-LABEL: v_ssubo_v2i32:309; GFX8: ; %bb.0:310; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)311; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2312; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v1, v3313; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0314; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1315; GFX8-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2316; GFX8-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3317; GFX8-NEXT: s_xor_b64 s[6:7], s[6:7], vcc318; GFX8-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]319; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]320; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]321; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v4, v0322; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v5, v1323; GFX8-NEXT: s_setpc_b64 s[30:31]324;325; GFX9-LABEL: v_ssubo_v2i32:326; GFX9: ; %bb.0:327; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)328; GFX9-NEXT: v_sub_u32_e32 v4, v0, v2329; GFX9-NEXT: v_sub_u32_e32 v5, v1, v3330; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v4, v0331; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], v5, v1332; GFX9-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v2333; GFX9-NEXT: v_cmp_lt_i32_e64 s[8:9], 0, v3334; GFX9-NEXT: s_xor_b64 s[6:7], s[6:7], vcc335; GFX9-NEXT: s_xor_b64 s[4:5], s[8:9], s[4:5]336; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[6:7]337; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]338; GFX9-NEXT: v_sub_u32_e32 v0, v4, v0339; GFX9-NEXT: v_sub_u32_e32 v1, v5, v1340; GFX9-NEXT: s_setpc_b64 s[30:31]341 %ssubo = call {<2 x i32>, <2 x i1>} @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)342 %sub = extractvalue {<2 x i32>, <2 x i1>} %ssubo, 0343 %of = extractvalue {<2 x i32>, <2 x i1>} %ssubo, 1344 %of.zext = zext <2 x i1> %of to <2 x i32>345 %ret = sub <2 x i32> %sub, %of.zext346 ret <2 x i32> %ret347}348 349define i8 @v_ssubo_i8(i8 %a, i8 %b) {350; GFX7-LABEL: v_ssubo_i8:351; GFX7: ; %bb.0:352; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)353; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1354; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8355; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 8356; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0357; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 8358; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0359; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc360; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]361; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0362; GFX7-NEXT: s_setpc_b64 s[30:31]363;364; GFX8-LABEL: v_ssubo_i8:365; GFX8: ; %bb.0:366; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)367; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1368; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 8369; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8370; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0371; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 8372; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0373; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc374; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]375; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0376; GFX8-NEXT: s_setpc_b64 s[30:31]377;378; GFX9-LABEL: v_ssubo_i8:379; GFX9: ; %bb.0:380; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)381; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1382; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v2), sext(v0) src0_sel:BYTE_0 src1_sel:BYTE_0383; GFX9-NEXT: v_mov_b32_e32 v0, 0384; GFX9-NEXT: v_cmp_gt_i32_sdwa s[6:7], sext(v1), v0 src0_sel:BYTE_0 src1_sel:DWORD385; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[4:5]386; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]387; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0388; GFX9-NEXT: s_setpc_b64 s[30:31]389 %ssubo = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 %a, i8 %b)390 %sub = extractvalue {i8, i1} %ssubo, 0391 %of = extractvalue {i8, i1} %ssubo, 1392 %of.zext = zext i1 %of to i8393 %ret = sub i8 %sub, %of.zext394 ret i8 %ret395}396 397define i7 @v_ssubo_i7(i7 %a, i7 %b) {398; GFX7-LABEL: v_ssubo_i7:399; GFX7: ; %bb.0:400; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1402; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 7403; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 7404; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0405; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 7406; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0407; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc408; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]409; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0410; GFX7-NEXT: s_setpc_b64 s[30:31]411;412; GFX8-LABEL: v_ssubo_i7:413; GFX8: ; %bb.0:414; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)415; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1416; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 7417; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 7418; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0419; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 7420; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0421; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc422; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]423; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0424; GFX8-NEXT: s_setpc_b64 s[30:31]425;426; GFX9-LABEL: v_ssubo_i7:427; GFX9: ; %bb.0:428; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)429; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1430; GFX9-NEXT: v_bfe_i32 v3, v2, 0, 7431; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 7432; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0433; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 7434; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0435; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc436; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]437; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0438; GFX9-NEXT: s_setpc_b64 s[30:31]439 %ssubo = call {i7, i1} @llvm.ssub.with.overflow.i7(i7 %a, i7 %b)440 %sub = extractvalue {i7, i1} %ssubo, 0441 %of = extractvalue {i7, i1} %ssubo, 1442 %of.zext = zext i1 %of to i7443 %ret = sub i7 %sub, %of.zext444 ret i7 %ret445}446 447define amdgpu_ps i32 @s_usubo_i32(i32 inreg %a, i32 inreg %b) {448; GFX7-LABEL: s_usubo_i32:449; GFX7: ; %bb.0:450; GFX7-NEXT: s_sub_u32 s0, s0, s1451; GFX7-NEXT: s_cselect_b32 s1, 1, 0452; GFX7-NEXT: s_sub_i32 s0, s0, s1453; GFX7-NEXT: ; return to shader part epilog454;455; GFX8-LABEL: s_usubo_i32:456; GFX8: ; %bb.0:457; GFX8-NEXT: s_sub_u32 s0, s0, s1458; GFX8-NEXT: s_cselect_b32 s1, 1, 0459; GFX8-NEXT: s_sub_i32 s0, s0, s1460; GFX8-NEXT: ; return to shader part epilog461;462; GFX9-LABEL: s_usubo_i32:463; GFX9: ; %bb.0:464; GFX9-NEXT: s_sub_u32 s0, s0, s1465; GFX9-NEXT: s_cselect_b32 s1, 1, 0466; GFX9-NEXT: s_sub_i32 s0, s0, s1467; GFX9-NEXT: ; return to shader part epilog468 %usubo = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)469 %sub = extractvalue {i32, i1} %usubo, 0470 %of = extractvalue {i32, i1} %usubo, 1471 %of.zext = zext i1 %of to i32472 %ret = sub i32 %sub, %of.zext473 ret i32 %ret474}475 476define amdgpu_ps i64 @s_usubo_i64(i64 inreg %a, i64 inreg %b) {477; GFX7-LABEL: s_usubo_i64:478; GFX7: ; %bb.0:479; GFX7-NEXT: s_sub_u32 s0, s0, s2480; GFX7-NEXT: s_subb_u32 s1, s1, s3481; GFX7-NEXT: s_cselect_b32 s2, 1, 0482; GFX7-NEXT: s_sub_u32 s0, s0, s2483; GFX7-NEXT: s_subb_u32 s1, s1, 0484; GFX7-NEXT: ; return to shader part epilog485;486; GFX8-LABEL: s_usubo_i64:487; GFX8: ; %bb.0:488; GFX8-NEXT: s_sub_u32 s0, s0, s2489; GFX8-NEXT: s_subb_u32 s1, s1, s3490; GFX8-NEXT: s_cselect_b32 s2, 1, 0491; GFX8-NEXT: s_sub_u32 s0, s0, s2492; GFX8-NEXT: s_subb_u32 s1, s1, 0493; GFX8-NEXT: ; return to shader part epilog494;495; GFX9-LABEL: s_usubo_i64:496; GFX9: ; %bb.0:497; GFX9-NEXT: s_sub_u32 s0, s0, s2498; GFX9-NEXT: s_subb_u32 s1, s1, s3499; GFX9-NEXT: s_cselect_b32 s2, 1, 0500; GFX9-NEXT: s_sub_u32 s0, s0, s2501; GFX9-NEXT: s_subb_u32 s1, s1, 0502; GFX9-NEXT: ; return to shader part epilog503 %usubo = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)504 %sub = extractvalue {i64, i1} %usubo, 0505 %of = extractvalue {i64, i1} %usubo, 1506 %of.zext = zext i1 %of to i64507 %ret = sub i64 %sub, %of.zext508 ret i64 %ret509}510 511define amdgpu_ps <2 x i32> @s_usubo_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b) {512; GFX7-LABEL: s_usubo_v2i32:513; GFX7: ; %bb.0:514; GFX7-NEXT: s_sub_u32 s0, s0, s2515; GFX7-NEXT: s_cselect_b32 s2, 1, 0516; GFX7-NEXT: s_sub_u32 s1, s1, s3517; GFX7-NEXT: s_cselect_b32 s3, 1, 0518; GFX7-NEXT: s_sub_i32 s0, s0, s2519; GFX7-NEXT: s_sub_i32 s1, s1, s3520; GFX7-NEXT: ; return to shader part epilog521;522; GFX8-LABEL: s_usubo_v2i32:523; GFX8: ; %bb.0:524; GFX8-NEXT: s_sub_u32 s0, s0, s2525; GFX8-NEXT: s_cselect_b32 s2, 1, 0526; GFX8-NEXT: s_sub_u32 s1, s1, s3527; GFX8-NEXT: s_cselect_b32 s3, 1, 0528; GFX8-NEXT: s_sub_i32 s0, s0, s2529; GFX8-NEXT: s_sub_i32 s1, s1, s3530; GFX8-NEXT: ; return to shader part epilog531;532; GFX9-LABEL: s_usubo_v2i32:533; GFX9: ; %bb.0:534; GFX9-NEXT: s_sub_u32 s0, s0, s2535; GFX9-NEXT: s_cselect_b32 s2, 1, 0536; GFX9-NEXT: s_sub_u32 s1, s1, s3537; GFX9-NEXT: s_cselect_b32 s3, 1, 0538; GFX9-NEXT: s_sub_i32 s0, s0, s2539; GFX9-NEXT: s_sub_i32 s1, s1, s3540; GFX9-NEXT: ; return to shader part epilog541 %usubo = call {<2 x i32>, <2 x i1>} @llvm.usub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)542 %sub = extractvalue {<2 x i32>, <2 x i1>} %usubo, 0543 %of = extractvalue {<2 x i32>, <2 x i1>} %usubo, 1544 %of.zext = zext <2 x i1> %of to <2 x i32>545 %ret = sub <2 x i32> %sub, %of.zext546 ret <2 x i32> %ret547}548 549define i8 @s_usubo_i8(i8 %a, i8 %b) {550; GFX7-LABEL: s_usubo_i8:551; GFX7: ; %bb.0:552; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)553; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0554; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v1555; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1556; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v0557; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1558; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc559; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1560; GFX7-NEXT: s_setpc_b64 s[30:31]561;562; GFX8-LABEL: s_usubo_i8:563; GFX8: ; %bb.0:564; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; GFX8-NEXT: v_and_b32_e32 v0, 0xff, v0566; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v1567; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1568; GFX8-NEXT: v_and_b32_e32 v1, 0xff, v0569; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1570; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc571; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1572; GFX8-NEXT: s_setpc_b64 s[30:31]573;574; GFX9-LABEL: s_usubo_i8:575; GFX9: ; %bb.0:576; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)577; GFX9-NEXT: v_sub_u32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_0578; GFX9-NEXT: v_cmp_ne_u32_sdwa s[4:5], v0, v0 src0_sel:DWORD src1_sel:BYTE_0579; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]580; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1581; GFX9-NEXT: s_setpc_b64 s[30:31]582 %usubo = call {i8, i1} @llvm.usub.with.overflow.i8(i8 %a, i8 %b)583 %sub = extractvalue {i8, i1} %usubo, 0584 %of = extractvalue {i8, i1} %usubo, 1585 %of.zext = zext i1 %of to i8586 %ret = sub i8 %sub, %of.zext587 ret i8 %ret588}589 590define i7 @s_usubo_i7(i7 %a, i7 %b) {591; GFX7-LABEL: s_usubo_i7:592; GFX7: ; %bb.0:593; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX7-NEXT: v_and_b32_e32 v0, 0x7f, v0595; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v1596; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1597; GFX7-NEXT: v_and_b32_e32 v1, 0x7f, v0598; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1599; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc600; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1601; GFX7-NEXT: s_setpc_b64 s[30:31]602;603; GFX8-LABEL: s_usubo_i7:604; GFX8: ; %bb.0:605; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)606; GFX8-NEXT: v_and_b32_e32 v0, 0x7f, v0607; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v1608; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1609; GFX8-NEXT: v_and_b32_e32 v1, 0x7f, v0610; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1611; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc612; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1613; GFX8-NEXT: s_setpc_b64 s[30:31]614;615; GFX9-LABEL: s_usubo_i7:616; GFX9: ; %bb.0:617; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)618; GFX9-NEXT: v_and_b32_e32 v0, 0x7f, v0619; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v1620; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1621; GFX9-NEXT: v_and_b32_e32 v1, 0x7f, v0622; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1623; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc624; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1625; GFX9-NEXT: s_setpc_b64 s[30:31]626 %usubo = call {i7, i1} @llvm.usub.with.overflow.i7(i7 %a, i7 %b)627 %sub = extractvalue {i7, i1} %usubo, 0628 %of = extractvalue {i7, i1} %usubo, 1629 %of.zext = zext i1 %of to i7630 %ret = sub i7 %sub, %of.zext631 ret i7 %ret632}633 634define amdgpu_ps i32 @s_ssubo_i32(i32 inreg %a, i32 inreg %b) {635; GFX7-LABEL: s_ssubo_i32:636; GFX7: ; %bb.0:637; GFX7-NEXT: s_sub_i32 s2, s0, s1638; GFX7-NEXT: s_cmp_lt_i32 s2, s0639; GFX7-NEXT: s_cselect_b32 s0, 1, 0640; GFX7-NEXT: s_cmp_gt_i32 s1, 0641; GFX7-NEXT: s_cselect_b32 s1, 1, 0642; GFX7-NEXT: s_xor_b32 s0, s1, s0643; GFX7-NEXT: s_sub_i32 s0, s2, s0644; GFX7-NEXT: ; return to shader part epilog645;646; GFX8-LABEL: s_ssubo_i32:647; GFX8: ; %bb.0:648; GFX8-NEXT: s_sub_i32 s2, s0, s1649; GFX8-NEXT: s_cmp_lt_i32 s2, s0650; GFX8-NEXT: s_cselect_b32 s0, 1, 0651; GFX8-NEXT: s_cmp_gt_i32 s1, 0652; GFX8-NEXT: s_cselect_b32 s1, 1, 0653; GFX8-NEXT: s_xor_b32 s0, s1, s0654; GFX8-NEXT: s_sub_i32 s0, s2, s0655; GFX8-NEXT: ; return to shader part epilog656;657; GFX9-LABEL: s_ssubo_i32:658; GFX9: ; %bb.0:659; GFX9-NEXT: s_sub_i32 s2, s0, s1660; GFX9-NEXT: s_cmp_lt_i32 s2, s0661; GFX9-NEXT: s_cselect_b32 s0, 1, 0662; GFX9-NEXT: s_cmp_gt_i32 s1, 0663; GFX9-NEXT: s_cselect_b32 s1, 1, 0664; GFX9-NEXT: s_xor_b32 s0, s1, s0665; GFX9-NEXT: s_sub_i32 s0, s2, s0666; GFX9-NEXT: ; return to shader part epilog667 %ssubo = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)668 %sub = extractvalue {i32, i1} %ssubo, 0669 %of = extractvalue {i32, i1} %ssubo, 1670 %of.zext = zext i1 %of to i32671 %ret = sub i32 %sub, %of.zext672 ret i32 %ret673}674 675define amdgpu_ps i64 @s_ssubo_i64(i64 inreg %a, i64 inreg %b) {676; GFX7-LABEL: s_ssubo_i64:677; GFX7: ; %bb.0:678; GFX7-NEXT: s_sub_u32 s4, s0, s2679; GFX7-NEXT: v_mov_b32_e32 v0, s0680; GFX7-NEXT: s_subb_u32 s5, s1, s3681; GFX7-NEXT: v_mov_b32_e32 v1, s1682; GFX7-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]683; GFX7-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0684; GFX7-NEXT: v_mov_b32_e32 v1, s5685; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], vcc686; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]687; GFX7-NEXT: v_sub_i32_e32 v0, vcc, s4, v0688; GFX7-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc689; GFX7-NEXT: v_readfirstlane_b32 s0, v0690; GFX7-NEXT: v_readfirstlane_b32 s1, v1691; GFX7-NEXT: ; return to shader part epilog692;693; GFX8-LABEL: s_ssubo_i64:694; GFX8: ; %bb.0:695; GFX8-NEXT: s_sub_u32 s4, s0, s2696; GFX8-NEXT: v_mov_b32_e32 v0, s0697; GFX8-NEXT: s_subb_u32 s5, s1, s3698; GFX8-NEXT: v_mov_b32_e32 v1, s1699; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]700; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0701; GFX8-NEXT: v_mov_b32_e32 v1, s5702; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], vcc703; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]704; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s4, v0705; GFX8-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc706; GFX8-NEXT: v_readfirstlane_b32 s0, v0707; GFX8-NEXT: v_readfirstlane_b32 s1, v1708; GFX8-NEXT: ; return to shader part epilog709;710; GFX9-LABEL: s_ssubo_i64:711; GFX9: ; %bb.0:712; GFX9-NEXT: s_sub_u32 s4, s0, s2713; GFX9-NEXT: v_mov_b32_e32 v0, s0714; GFX9-NEXT: s_subb_u32 s5, s1, s3715; GFX9-NEXT: v_mov_b32_e32 v1, s1716; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]717; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0718; GFX9-NEXT: v_mov_b32_e32 v1, s5719; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc720; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]721; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s4, v0722; GFX9-NEXT: v_subbrev_co_u32_e32 v1, vcc, 0, v1, vcc723; GFX9-NEXT: v_readfirstlane_b32 s0, v0724; GFX9-NEXT: v_readfirstlane_b32 s1, v1725; GFX9-NEXT: ; return to shader part epilog726 %ssubo = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)727 %sub = extractvalue {i64, i1} %ssubo, 0728 %of = extractvalue {i64, i1} %ssubo, 1729 %of.zext = zext i1 %of to i64730 %ret = sub i64 %sub, %of.zext731 ret i64 %ret732}733 734define amdgpu_ps <2 x i32> @s_ssubo_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b) {735; GFX7-LABEL: s_ssubo_v2i32:736; GFX7: ; %bb.0:737; GFX7-NEXT: s_sub_i32 s4, s0, s2738; GFX7-NEXT: s_sub_i32 s5, s1, s3739; GFX7-NEXT: s_cmp_lt_i32 s4, s0740; GFX7-NEXT: s_cselect_b32 s0, 1, 0741; GFX7-NEXT: s_cmp_lt_i32 s5, s1742; GFX7-NEXT: s_cselect_b32 s1, 1, 0743; GFX7-NEXT: s_cmp_gt_i32 s2, 0744; GFX7-NEXT: s_cselect_b32 s2, 1, 0745; GFX7-NEXT: s_cmp_gt_i32 s3, 0746; GFX7-NEXT: s_cselect_b32 s3, 1, 0747; GFX7-NEXT: s_xor_b32 s0, s2, s0748; GFX7-NEXT: s_xor_b32 s1, s3, s1749; GFX7-NEXT: s_sub_i32 s0, s4, s0750; GFX7-NEXT: s_sub_i32 s1, s5, s1751; GFX7-NEXT: ; return to shader part epilog752;753; GFX8-LABEL: s_ssubo_v2i32:754; GFX8: ; %bb.0:755; GFX8-NEXT: s_sub_i32 s4, s0, s2756; GFX8-NEXT: s_sub_i32 s5, s1, s3757; GFX8-NEXT: s_cmp_lt_i32 s4, s0758; GFX8-NEXT: s_cselect_b32 s0, 1, 0759; GFX8-NEXT: s_cmp_lt_i32 s5, s1760; GFX8-NEXT: s_cselect_b32 s1, 1, 0761; GFX8-NEXT: s_cmp_gt_i32 s2, 0762; GFX8-NEXT: s_cselect_b32 s2, 1, 0763; GFX8-NEXT: s_cmp_gt_i32 s3, 0764; GFX8-NEXT: s_cselect_b32 s3, 1, 0765; GFX8-NEXT: s_xor_b32 s0, s2, s0766; GFX8-NEXT: s_xor_b32 s1, s3, s1767; GFX8-NEXT: s_sub_i32 s0, s4, s0768; GFX8-NEXT: s_sub_i32 s1, s5, s1769; GFX8-NEXT: ; return to shader part epilog770;771; GFX9-LABEL: s_ssubo_v2i32:772; GFX9: ; %bb.0:773; GFX9-NEXT: s_sub_i32 s4, s0, s2774; GFX9-NEXT: s_sub_i32 s5, s1, s3775; GFX9-NEXT: s_cmp_lt_i32 s4, s0776; GFX9-NEXT: s_cselect_b32 s0, 1, 0777; GFX9-NEXT: s_cmp_lt_i32 s5, s1778; GFX9-NEXT: s_cselect_b32 s1, 1, 0779; GFX9-NEXT: s_cmp_gt_i32 s2, 0780; GFX9-NEXT: s_cselect_b32 s2, 1, 0781; GFX9-NEXT: s_cmp_gt_i32 s3, 0782; GFX9-NEXT: s_cselect_b32 s3, 1, 0783; GFX9-NEXT: s_xor_b32 s0, s2, s0784; GFX9-NEXT: s_xor_b32 s1, s3, s1785; GFX9-NEXT: s_sub_i32 s0, s4, s0786; GFX9-NEXT: s_sub_i32 s1, s5, s1787; GFX9-NEXT: ; return to shader part epilog788 %ssubo = call {<2 x i32>, <2 x i1>} @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)789 %sub = extractvalue {<2 x i32>, <2 x i1>} %ssubo, 0790 %of = extractvalue {<2 x i32>, <2 x i1>} %ssubo, 1791 %of.zext = zext <2 x i1> %of to <2 x i32>792 %ret = sub <2 x i32> %sub, %of.zext793 ret <2 x i32> %ret794}795 796define i8 @s_ssubo_i8(i8 %a, i8 %b) {797; GFX7-LABEL: s_ssubo_i8:798; GFX7: ; %bb.0:799; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)800; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1801; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 8802; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 8803; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0804; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 8805; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0806; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc807; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]808; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0809; GFX7-NEXT: s_setpc_b64 s[30:31]810;811; GFX8-LABEL: s_ssubo_i8:812; GFX8: ; %bb.0:813; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)814; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1815; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 8816; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 8817; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0818; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 8819; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0820; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc821; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]822; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0823; GFX8-NEXT: s_setpc_b64 s[30:31]824;825; GFX9-LABEL: s_ssubo_i8:826; GFX9: ; %bb.0:827; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)828; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1829; GFX9-NEXT: v_cmp_lt_i32_sdwa s[4:5], sext(v2), sext(v0) src0_sel:BYTE_0 src1_sel:BYTE_0830; GFX9-NEXT: v_mov_b32_e32 v0, 0831; GFX9-NEXT: v_cmp_gt_i32_sdwa s[6:7], sext(v1), v0 src0_sel:BYTE_0 src1_sel:DWORD832; GFX9-NEXT: s_xor_b64 s[4:5], s[6:7], s[4:5]833; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]834; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0835; GFX9-NEXT: s_setpc_b64 s[30:31]836 %ssubo = call {i8, i1} @llvm.ssub.with.overflow.i8(i8 %a, i8 %b)837 %sub = extractvalue {i8, i1} %ssubo, 0838 %of = extractvalue {i8, i1} %ssubo, 1839 %of.zext = zext i1 %of to i8840 %ret = sub i8 %sub, %of.zext841 ret i8 %ret842}843 844define i7 @s_ssubo_i7(i7 %a, i7 %b) {845; GFX7-LABEL: s_ssubo_i7:846; GFX7: ; %bb.0:847; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)848; GFX7-NEXT: v_sub_i32_e32 v2, vcc, v0, v1849; GFX7-NEXT: v_bfe_i32 v3, v2, 0, 7850; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 7851; GFX7-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0852; GFX7-NEXT: v_bfe_i32 v0, v1, 0, 7853; GFX7-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0854; GFX7-NEXT: s_xor_b64 s[4:5], s[4:5], vcc855; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]856; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v2, v0857; GFX7-NEXT: s_setpc_b64 s[30:31]858;859; GFX8-LABEL: s_ssubo_i7:860; GFX8: ; %bb.0:861; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)862; GFX8-NEXT: v_sub_u16_e32 v2, v0, v1863; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 7864; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 7865; GFX8-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0866; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 7867; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0868; GFX8-NEXT: s_xor_b64 s[4:5], s[4:5], vcc869; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]870; GFX8-NEXT: v_sub_u16_e32 v0, v2, v0871; GFX8-NEXT: s_setpc_b64 s[30:31]872;873; GFX9-LABEL: s_ssubo_i7:874; GFX9: ; %bb.0:875; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)876; GFX9-NEXT: v_sub_u16_e32 v2, v0, v1877; GFX9-NEXT: v_bfe_i32 v3, v2, 0, 7878; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 7879; GFX9-NEXT: v_cmp_lt_i32_e32 vcc, v3, v0880; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 7881; GFX9-NEXT: v_cmp_lt_i32_e64 s[4:5], 0, v0882; GFX9-NEXT: s_xor_b64 s[4:5], s[4:5], vcc883; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]884; GFX9-NEXT: v_sub_u16_e32 v0, v2, v0885; GFX9-NEXT: s_setpc_b64 s[30:31]886 %ssubo = call {i7, i1} @llvm.ssub.with.overflow.i7(i7 %a, i7 %b)887 %sub = extractvalue {i7, i1} %ssubo, 0888 %of = extractvalue {i7, i1} %ssubo, 1889 %of.zext = zext i1 %of to i7890 %ret = sub i7 %sub, %of.zext891 ret i7 %ret892}893 894define amdgpu_ps i32 @usubo_i32_sv(i32 inreg %a, i32 %b) {895; GFX7-LABEL: usubo_i32_sv:896; GFX7: ; %bb.0:897; GFX7-NEXT: v_sub_i32_e32 v0, vcc, s0, v0898; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc899; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1900; GFX7-NEXT: v_readfirstlane_b32 s0, v0901; GFX7-NEXT: ; return to shader part epilog902;903; GFX8-LABEL: usubo_i32_sv:904; GFX8: ; %bb.0:905; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0906; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc907; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1908; GFX8-NEXT: v_readfirstlane_b32 s0, v0909; GFX8-NEXT: ; return to shader part epilog910;911; GFX9-LABEL: usubo_i32_sv:912; GFX9: ; %bb.0:913; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v0914; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc915; GFX9-NEXT: v_sub_u32_e32 v0, v0, v1916; GFX9-NEXT: v_readfirstlane_b32 s0, v0917; GFX9-NEXT: ; return to shader part epilog918 %usubo = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)919 %sub = extractvalue {i32, i1} %usubo, 0920 %of = extractvalue {i32, i1} %usubo, 1921 %of.zext = zext i1 %of to i32922 %ret = sub i32 %sub, %of.zext923 ret i32 %ret924}925 926define amdgpu_ps i16 @usubo_i16_sv(i16 inreg %a, i16 %b) {927; GFX7-LABEL: usubo_i16_sv:928; GFX7: ; %bb.0:929; GFX7-NEXT: s_and_b32 s0, s0, 0xffff930; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0931; GFX7-NEXT: v_sub_i32_e32 v0, vcc, s0, v0932; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v0933; GFX7-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1934; GFX7-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc935; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v0, v1936; GFX7-NEXT: v_readfirstlane_b32 s0, v0937; GFX7-NEXT: ; return to shader part epilog938;939; GFX8-LABEL: usubo_i16_sv:940; GFX8: ; %bb.0:941; GFX8-NEXT: s_and_b32 s0, s0, 0xffff942; GFX8-NEXT: v_and_b32_e32 v0, 0xffff, v0943; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0944; GFX8-NEXT: v_and_b32_e32 v1, 0xffff, v0945; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1946; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc947; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1948; GFX8-NEXT: v_readfirstlane_b32 s0, v0949; GFX8-NEXT: ; return to shader part epilog950;951; GFX9-LABEL: usubo_i16_sv:952; GFX9: ; %bb.0:953; GFX9-NEXT: s_and_b32 s0, s0, 0xffff954; GFX9-NEXT: v_sub_u32_sdwa v0, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0955; GFX9-NEXT: v_cmp_ne_u32_sdwa s[0:1], v0, v0 src0_sel:DWORD src1_sel:WORD_0956; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]957; GFX9-NEXT: v_sub_u16_e32 v0, v0, v1958; GFX9-NEXT: v_readfirstlane_b32 s0, v0959; GFX9-NEXT: ; return to shader part epilog960 %usubo = call {i16, i1} @llvm.usub.with.overflow.i16(i16 %a, i16 %b)961 %sub = extractvalue {i16, i1} %usubo, 0962 %of = extractvalue {i16, i1} %usubo, 1963 %of.zext = zext i1 %of to i16964 %ret = sub i16 %sub, %of.zext965 ret i16 %ret966}967 968define amdgpu_ps i32 @ssubo_i32_sv(i32 inreg %a, i32 %b) {969; GFX7-LABEL: ssubo_i32_sv:970; GFX7: ; %bb.0:971; GFX7-NEXT: v_sub_i32_e32 v1, vcc, s0, v0972; GFX7-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1973; GFX7-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0974; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], vcc975; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]976; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v1, v0977; GFX7-NEXT: v_readfirstlane_b32 s0, v0978; GFX7-NEXT: ; return to shader part epilog979;980; GFX8-LABEL: ssubo_i32_sv:981; GFX8: ; %bb.0:982; GFX8-NEXT: v_sub_u32_e32 v1, vcc, s0, v0983; GFX8-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1984; GFX8-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0985; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], vcc986; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]987; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v1, v0988; GFX8-NEXT: v_readfirstlane_b32 s0, v0989; GFX8-NEXT: ; return to shader part epilog990;991; GFX9-LABEL: ssubo_i32_sv:992; GFX9: ; %bb.0:993; GFX9-NEXT: v_sub_u32_e32 v1, s0, v0994; GFX9-NEXT: v_cmp_gt_i32_e32 vcc, s0, v1995; GFX9-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v0996; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc997; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]998; GFX9-NEXT: v_sub_u32_e32 v0, v1, v0999; GFX9-NEXT: v_readfirstlane_b32 s0, v01000; GFX9-NEXT: ; return to shader part epilog1001 %ssubo = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)1002 %sub = extractvalue {i32, i1} %ssubo, 01003 %of = extractvalue {i32, i1} %ssubo, 11004 %of.zext = zext i1 %of to i321005 %ret = sub i32 %sub, %of.zext1006 ret i32 %ret1007}1008 1009define amdgpu_ps i16 @ssubo_i16_sv(i16 inreg %a, i16 %b) {1010; GFX7-LABEL: ssubo_i16_sv:1011; GFX7: ; %bb.0:1012; GFX7-NEXT: v_sub_i32_e32 v1, vcc, s0, v01013; GFX7-NEXT: v_bfe_i32 v2, v1, 0, 161014; GFX7-NEXT: s_sext_i32_i16 s0, s01015; GFX7-NEXT: v_bfe_i32 v0, v0, 0, 161016; GFX7-NEXT: v_cmp_gt_i32_e32 vcc, s0, v21017; GFX7-NEXT: v_cmp_lt_i32_e64 s[0:1], 0, v01018; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], vcc1019; GFX7-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]1020; GFX7-NEXT: v_sub_i32_e32 v0, vcc, v1, v01021; GFX7-NEXT: v_readfirstlane_b32 s0, v01022; GFX7-NEXT: ; return to shader part epilog1023;1024; GFX8-LABEL: ssubo_i16_sv:1025; GFX8: ; %bb.0:1026; GFX8-NEXT: v_sub_u16_e32 v1, s0, v01027; GFX8-NEXT: v_cmp_gt_i16_e32 vcc, s0, v11028; GFX8-NEXT: v_cmp_lt_i16_e64 s[0:1], 0, v01029; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], vcc1030; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]1031; GFX8-NEXT: v_sub_u16_e32 v0, v1, v01032; GFX8-NEXT: v_readfirstlane_b32 s0, v01033; GFX8-NEXT: ; return to shader part epilog1034;1035; GFX9-LABEL: ssubo_i16_sv:1036; GFX9: ; %bb.0:1037; GFX9-NEXT: v_sub_u16_e32 v1, s0, v01038; GFX9-NEXT: v_cmp_gt_i16_e32 vcc, s0, v11039; GFX9-NEXT: v_cmp_lt_i16_e64 s[0:1], 0, v01040; GFX9-NEXT: s_xor_b64 s[0:1], s[0:1], vcc1041; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]1042; GFX9-NEXT: v_sub_u16_e32 v0, v1, v01043; GFX9-NEXT: v_readfirstlane_b32 s0, v01044; GFX9-NEXT: ; return to shader part epilog1045 %ssubo = call {i16, i1} @llvm.ssub.with.overflow.i16(i16 %a, i16 %b)1046 %sub = extractvalue {i16, i1} %ssubo, 01047 %of = extractvalue {i16, i1} %ssubo, 11048 %of.zext = zext i1 %of to i161049 %ret = sub i16 %sub, %of.zext1050 ret i16 %ret1051}1052 1053declare {i7, i1} @llvm.usub.with.overflow.i7(i7 %a, i7 %b)1054declare {i8, i1} @llvm.usub.with.overflow.i8(i8 %a, i8 %b)1055declare {i16, i1} @llvm.usub.with.overflow.i16(i16 %a, i16 %b)1056declare {i32, i1} @llvm.usub.with.overflow.i32(i32 %a, i32 %b)1057declare {i64, i1} @llvm.usub.with.overflow.i64(i64 %a, i64 %b)1058declare {<2 x i32>, <2 x i1>} @llvm.usub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)1059 1060declare {i7, i1} @llvm.ssub.with.overflow.i7(i7 %a, i7 %b)1061declare {i8, i1} @llvm.ssub.with.overflow.i8(i8 %a, i8 %b)1062declare {i16, i1} @llvm.ssub.with.overflow.i16(i16 %a, i16 %b)1063declare {i32, i1} @llvm.ssub.with.overflow.i32(i32 %a, i32 %b)1064declare {i64, i1} @llvm.ssub.with.overflow.i64(i64 %a, i64 %b)1065declare {<2 x i32>, <2 x i1>} @llvm.ssub.with.overflow.v2i32(<2 x i32> %a, <2 x i32> %b)1066