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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=bonaire < %s | FileCheck -check-prefix=GFX7 %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=tonga < %s | FileCheck -check-prefix=GFX8 %s4 5define i16 @v_trunc_i32_to_i16(i32 %src) {6; GFX7-LABEL: v_trunc_i32_to_i16:7; GFX7: ; %bb.0:8; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; GFX7-NEXT: s_setpc_b64 s[30:31]10;11; GFX8-LABEL: v_trunc_i32_to_i16:12; GFX8: ; %bb.0:13; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; GFX8-NEXT: s_setpc_b64 s[30:31]15 %trunc = trunc i32 %src to i1616 ret i16 %trunc17}18 19define amdgpu_ps i16 @s_trunc_i32_to_i16(i32 inreg %src) {20; GFX7-LABEL: s_trunc_i32_to_i16:21; GFX7: ; %bb.0:22; GFX7-NEXT: ; return to shader part epilog23;24; GFX8-LABEL: s_trunc_i32_to_i16:25; GFX8: ; %bb.0:26; GFX8-NEXT: ; return to shader part epilog27 %trunc = trunc i32 %src to i1628 ret i16 %trunc29}30 31define i16 @v_trunc_i64_to_i16(i64 %src) {32; GFX7-LABEL: v_trunc_i64_to_i16:33; GFX7: ; %bb.0:34; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; GFX7-NEXT: s_setpc_b64 s[30:31]36;37; GFX8-LABEL: v_trunc_i64_to_i16:38; GFX8: ; %bb.0:39; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)40; GFX8-NEXT: s_setpc_b64 s[30:31]41 %trunc = trunc i64 %src to i1642 ret i16 %trunc43}44 45define amdgpu_ps i16 @s_trunc_i64_to_i16(i64 inreg %src) {46; GFX7-LABEL: s_trunc_i64_to_i16:47; GFX7: ; %bb.0:48; GFX7-NEXT: ; return to shader part epilog49;50; GFX8-LABEL: s_trunc_i64_to_i16:51; GFX8: ; %bb.0:52; GFX8-NEXT: ; return to shader part epilog53 %trunc = trunc i64 %src to i1654 ret i16 %trunc55}56 57define amdgpu_ps i16 @s_trunc_i128_to_i16(i128 inreg %src) {58; GFX7-LABEL: s_trunc_i128_to_i16:59; GFX7: ; %bb.0:60; GFX7-NEXT: ; return to shader part epilog61;62; GFX8-LABEL: s_trunc_i128_to_i16:63; GFX8: ; %bb.0:64; GFX8-NEXT: ; return to shader part epilog65 %trunc = trunc i128 %src to i1666 ret i16 %trunc67}68 69define i16 @v_trunc_i128_to_i16(i128 %src) {70; GFX7-LABEL: v_trunc_i128_to_i16:71; GFX7: ; %bb.0:72; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)73; GFX7-NEXT: s_setpc_b64 s[30:31]74;75; GFX8-LABEL: v_trunc_i128_to_i16:76; GFX8: ; %bb.0:77; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; GFX8-NEXT: s_setpc_b64 s[30:31]79 %trunc = trunc i128 %src to i1680 ret i16 %trunc81}82 83define i32 @v_trunc_v2i32_to_v2i16(<2 x i32> %src) {84; GFX7-LABEL: v_trunc_v2i32_to_v2i16:85; GFX7: ; %bb.0:86; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v188; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v089; GFX7-NEXT: v_or_b32_e32 v0, v1, v090; GFX7-NEXT: s_setpc_b64 s[30:31]91;92; GFX8-LABEL: v_trunc_v2i32_to_v2i16:93; GFX8: ; %bb.0:94; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)95; GFX8-NEXT: v_mov_b32_sdwa v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_096; GFX8-NEXT: s_setpc_b64 s[30:31]97 %trunc = trunc <2 x i32> %src to <2 x i16>98 %cast = bitcast <2 x i16> %trunc to i3299 ret i32 %cast100}101 102define amdgpu_ps i32 @s_trunc_v2i32_to_v2i16(<2 x i32> inreg %src) {103; GFX7-LABEL: s_trunc_v2i32_to_v2i16:104; GFX7: ; %bb.0:105; GFX7-NEXT: s_lshl_b32 s1, s1, 16106; GFX7-NEXT: s_and_b32 s0, s0, 0xffff107; GFX7-NEXT: s_or_b32 s0, s1, s0108; GFX7-NEXT: ; return to shader part epilog109;110; GFX8-LABEL: s_trunc_v2i32_to_v2i16:111; GFX8: ; %bb.0:112; GFX8-NEXT: s_lshl_b32 s1, s1, 16113; GFX8-NEXT: s_and_b32 s0, s0, 0xffff114; GFX8-NEXT: s_or_b32 s0, s1, s0115; GFX8-NEXT: ; return to shader part epilog116 %trunc = trunc <2 x i32> %src to <2 x i16>117 %cast = bitcast <2 x i16> %trunc to i32118 ret i32 %cast119}120 121; ; FIXME: G_INSERT mishandled122; define <2 x i32> @v_trunc_v3i32_to_v3i16(<3 x i32> %src) {123; %trunc = trunc <3 x i32> %src to <3 x i16>124; %ext = shufflevector <3 x i16> %trunc, <3 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>125; %cast = bitcast <4 x i16> %ext to <2 x i32>126; ret <2 x i32> %cast127; }128 129; ; FIXME: G_INSERT mishandled130; define amdgpu_ps <2 x i32> @s_trunc_v3i32_to_v3i16(<3 x i32> inreg %src) {131; %trunc = trunc <3 x i32> %src to <3 x i16>132; %ext = shufflevector <3 x i16> %trunc, <3 x i16> poison, <4 x i32> <i32 0, i32 1, i32 2, i32 3>133; %cast = bitcast <4 x i16> %ext to <2 x i32>134; ret <2 x i32> %cast135; }136 137define <2 x i32> @v_trunc_v4i32_to_v4i16(<4 x i32> %src) {138; GFX7-LABEL: v_trunc_v4i32_to_v4i16:139; GFX7: ; %bb.0:140; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1142; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0143; GFX7-NEXT: v_or_b32_e32 v0, v1, v0144; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v3145; GFX7-NEXT: v_and_b32_e32 v2, 0xffff, v2146; GFX7-NEXT: v_or_b32_e32 v1, v1, v2147; GFX7-NEXT: s_setpc_b64 s[30:31]148;149; GFX8-LABEL: v_trunc_v4i32_to_v4i16:150; GFX8: ; %bb.0:151; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)152; GFX8-NEXT: v_mov_b32_sdwa v2, v3 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0153; GFX8-NEXT: v_mov_b32_sdwa v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PRESERVE src0_sel:WORD_0154; GFX8-NEXT: v_mov_b32_e32 v1, v2155; GFX8-NEXT: s_setpc_b64 s[30:31]156 %trunc = trunc <4 x i32> %src to <4 x i16>157 %cast = bitcast <4 x i16> %trunc to <2 x i32>158 ret <2 x i32> %cast159}160 161define amdgpu_ps <2 x i32> @s_trunc_v4i32_to_v4i16(<4 x i32> inreg %src) {162; GFX7-LABEL: s_trunc_v4i32_to_v4i16:163; GFX7: ; %bb.0:164; GFX7-NEXT: s_lshl_b32 s1, s1, 16165; GFX7-NEXT: s_and_b32 s0, s0, 0xffff166; GFX7-NEXT: s_or_b32 s0, s1, s0167; GFX7-NEXT: s_lshl_b32 s1, s3, 16168; GFX7-NEXT: s_and_b32 s2, s2, 0xffff169; GFX7-NEXT: s_or_b32 s1, s1, s2170; GFX7-NEXT: ; return to shader part epilog171;172; GFX8-LABEL: s_trunc_v4i32_to_v4i16:173; GFX8: ; %bb.0:174; GFX8-NEXT: s_lshl_b32 s1, s1, 16175; GFX8-NEXT: s_and_b32 s0, s0, 0xffff176; GFX8-NEXT: s_or_b32 s0, s1, s0177; GFX8-NEXT: s_lshl_b32 s1, s3, 16178; GFX8-NEXT: s_and_b32 s2, s2, 0xffff179; GFX8-NEXT: s_or_b32 s1, s1, s2180; GFX8-NEXT: ; return to shader part epilog181 %trunc = trunc <4 x i32> %src to <4 x i16>182 %cast = bitcast <4 x i16> %trunc to <2 x i32>183 ret <2 x i32> %cast184}185