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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8 9define i7 @v_uaddsat_i7(i7 %lhs, i7 %rhs) {10; GFX6-LABEL: v_uaddsat_i7:11; GFX6:       ; %bb.0:12; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 25, v014; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 25, v115; GFX6-NEXT:    v_not_b32_e32 v2, v016; GFX6-NEXT:    v_min_u32_e32 v1, v2, v117; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v118; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 25, v019; GFX6-NEXT:    s_setpc_b64 s[30:31]20;21; GFX8-LABEL: v_uaddsat_i7:22; GFX8:       ; %bb.0:23; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 9, v025; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 9, v126; GFX8-NEXT:    v_add_u16_e64 v0, v0, v1 clamp27; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 9, v028; GFX8-NEXT:    s_setpc_b64 s[30:31]29;30; GFX9-LABEL: v_uaddsat_i7:31; GFX9:       ; %bb.0:32; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 9, v034; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 9, v135; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp36; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v037; GFX9-NEXT:    s_setpc_b64 s[30:31]38;39; GFX10-LABEL: v_uaddsat_i7:40; GFX10:       ; %bb.0:41; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)42; GFX10-NEXT:    v_lshlrev_b16 v0, 9, v043; GFX10-NEXT:    v_lshlrev_b16 v1, 9, v144; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp45; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v046; GFX10-NEXT:    s_setpc_b64 s[30:31]47;48; GFX11-TRUE16-LABEL: v_uaddsat_i7:49; GFX11-TRUE16:       ; %bb.0:50; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 9, v0.l52; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 9, v1.l53; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h clamp54; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 9, v0.l55; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]56;57; GFX11-FAKE16-LABEL: v_uaddsat_i7:58; GFX11-FAKE16:       ; %bb.0:59; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)60; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 9, v061; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 9, v162; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1 clamp63; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 9, v064; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]65  %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)66  ret i7 %result67}68 69define amdgpu_ps i7 @s_uaddsat_i7(i7 inreg %lhs, i7 inreg %rhs) {70; GFX6-LABEL: s_uaddsat_i7:71; GFX6:       ; %bb.0:72; GFX6-NEXT:    s_lshl_b32 s0, s0, 2573; GFX6-NEXT:    s_lshl_b32 s1, s1, 2574; GFX6-NEXT:    s_not_b32 s2, s075; GFX6-NEXT:    s_min_u32 s1, s2, s176; GFX6-NEXT:    s_add_i32 s0, s0, s177; GFX6-NEXT:    s_lshr_b32 s0, s0, 2578; GFX6-NEXT:    ; return to shader part epilog79;80; GFX8-LABEL: s_uaddsat_i7:81; GFX8:       ; %bb.0:82; GFX8-NEXT:    s_lshl_b32 s1, s1, 983; GFX8-NEXT:    s_lshl_b32 s0, s0, 984; GFX8-NEXT:    v_mov_b32_e32 v0, s185; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp86; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 9, v087; GFX8-NEXT:    v_readfirstlane_b32 s0, v088; GFX8-NEXT:    ; return to shader part epilog89;90; GFX9-LABEL: s_uaddsat_i7:91; GFX9:       ; %bb.0:92; GFX9-NEXT:    s_lshl_b32 s1, s1, 993; GFX9-NEXT:    s_lshl_b32 s0, s0, 994; GFX9-NEXT:    v_mov_b32_e32 v0, s195; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp96; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 9, v097; GFX9-NEXT:    v_readfirstlane_b32 s0, v098; GFX9-NEXT:    ; return to shader part epilog99;100; GFX10-LABEL: s_uaddsat_i7:101; GFX10:       ; %bb.0:102; GFX10-NEXT:    s_lshl_b32 s0, s0, 9103; GFX10-NEXT:    s_lshl_b32 s1, s1, 9104; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp105; GFX10-NEXT:    v_lshrrev_b16 v0, 9, v0106; GFX10-NEXT:    v_readfirstlane_b32 s0, v0107; GFX10-NEXT:    ; return to shader part epilog108;109; GFX11-TRUE16-LABEL: s_uaddsat_i7:110; GFX11-TRUE16:       ; %bb.0:111; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 9112; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 9113; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, s0, s1 clamp114; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 9, v0.l115; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0116; GFX11-TRUE16-NEXT:    ; return to shader part epilog117;118; GFX11-FAKE16-LABEL: s_uaddsat_i7:119; GFX11-FAKE16:       ; %bb.0:120; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 9121; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 9122; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, s0, s1 clamp123; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 9, v0124; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0125; GFX11-FAKE16-NEXT:    ; return to shader part epilog126  %result = call i7 @llvm.uadd.sat.i7(i7 %lhs, i7 %rhs)127  ret i7 %result128}129 130define i8 @v_uaddsat_i8(i8 %lhs, i8 %rhs) {131; GFX6-LABEL: v_uaddsat_i8:132; GFX6:       ; %bb.0:133; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)134; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 24, v0135; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1136; GFX6-NEXT:    v_not_b32_e32 v2, v0137; GFX6-NEXT:    v_min_u32_e32 v1, v2, v1138; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1139; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 24, v0140; GFX6-NEXT:    s_setpc_b64 s[30:31]141;142; GFX8-LABEL: v_uaddsat_i8:143; GFX8:       ; %bb.0:144; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v0146; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1147; GFX8-NEXT:    v_add_u16_e64 v0, v0, v1 clamp148; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 8, v0149; GFX8-NEXT:    s_setpc_b64 s[30:31]150;151; GFX9-LABEL: v_uaddsat_i8:152; GFX9:       ; %bb.0:153; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)154; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v0155; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v1156; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp157; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0158; GFX9-NEXT:    s_setpc_b64 s[30:31]159;160; GFX10-LABEL: v_uaddsat_i8:161; GFX10:       ; %bb.0:162; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)163; GFX10-NEXT:    v_lshlrev_b16 v0, 8, v0164; GFX10-NEXT:    v_lshlrev_b16 v1, 8, v1165; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp166; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0167; GFX10-NEXT:    s_setpc_b64 s[30:31]168;169; GFX11-TRUE16-LABEL: v_uaddsat_i8:170; GFX11-TRUE16:       ; %bb.0:171; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)172; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v0.l173; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.h, 8, v1.l174; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v0.h clamp175; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 8, v0.l176; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]177;178; GFX11-FAKE16-LABEL: v_uaddsat_i8:179; GFX11-FAKE16:       ; %bb.0:180; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)181; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v0, 8, v0182; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1183; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1 clamp184; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 8, v0185; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]186  %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)187  ret i8 %result188}189 190define amdgpu_ps i8 @s_uaddsat_i8(i8 inreg %lhs, i8 inreg %rhs) {191; GFX6-LABEL: s_uaddsat_i8:192; GFX6:       ; %bb.0:193; GFX6-NEXT:    s_lshl_b32 s0, s0, 24194; GFX6-NEXT:    s_lshl_b32 s1, s1, 24195; GFX6-NEXT:    s_not_b32 s2, s0196; GFX6-NEXT:    s_min_u32 s1, s2, s1197; GFX6-NEXT:    s_add_i32 s0, s0, s1198; GFX6-NEXT:    s_lshr_b32 s0, s0, 24199; GFX6-NEXT:    ; return to shader part epilog200;201; GFX8-LABEL: s_uaddsat_i8:202; GFX8:       ; %bb.0:203; GFX8-NEXT:    s_lshl_b32 s1, s1, 8204; GFX8-NEXT:    s_lshl_b32 s0, s0, 8205; GFX8-NEXT:    v_mov_b32_e32 v0, s1206; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp207; GFX8-NEXT:    v_lshrrev_b16_e32 v0, 8, v0208; GFX8-NEXT:    v_readfirstlane_b32 s0, v0209; GFX8-NEXT:    ; return to shader part epilog210;211; GFX9-LABEL: s_uaddsat_i8:212; GFX9:       ; %bb.0:213; GFX9-NEXT:    s_lshl_b32 s1, s1, 8214; GFX9-NEXT:    s_lshl_b32 s0, s0, 8215; GFX9-NEXT:    v_mov_b32_e32 v0, s1216; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp217; GFX9-NEXT:    v_lshrrev_b16_e32 v0, 8, v0218; GFX9-NEXT:    v_readfirstlane_b32 s0, v0219; GFX9-NEXT:    ; return to shader part epilog220;221; GFX10-LABEL: s_uaddsat_i8:222; GFX10:       ; %bb.0:223; GFX10-NEXT:    s_lshl_b32 s0, s0, 8224; GFX10-NEXT:    s_lshl_b32 s1, s1, 8225; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp226; GFX10-NEXT:    v_lshrrev_b16 v0, 8, v0227; GFX10-NEXT:    v_readfirstlane_b32 s0, v0228; GFX10-NEXT:    ; return to shader part epilog229;230; GFX11-TRUE16-LABEL: s_uaddsat_i8:231; GFX11-TRUE16:       ; %bb.0:232; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 8233; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 8234; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, s0, s1 clamp235; GFX11-TRUE16-NEXT:    v_lshrrev_b16 v0.l, 8, v0.l236; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0237; GFX11-TRUE16-NEXT:    ; return to shader part epilog238;239; GFX11-FAKE16-LABEL: s_uaddsat_i8:240; GFX11-FAKE16:       ; %bb.0:241; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 8242; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 8243; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, s0, s1 clamp244; GFX11-FAKE16-NEXT:    v_lshrrev_b16 v0, 8, v0245; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0246; GFX11-FAKE16-NEXT:    ; return to shader part epilog247  %result = call i8 @llvm.uadd.sat.i8(i8 %lhs, i8 %rhs)248  ret i8 %result249}250 251define i16 @v_uaddsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {252; GFX6-LABEL: v_uaddsat_v2i8:253; GFX6:       ; %bb.0:254; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)255; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 8, v0256; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 24, v0257; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 8, v1258; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1259; GFX6-NEXT:    v_not_b32_e32 v4, v0260; GFX6-NEXT:    v_min_u32_e32 v1, v4, v1261; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1262; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v2263; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 24, v3264; GFX6-NEXT:    v_not_b32_e32 v3, v1265; GFX6-NEXT:    v_min_u32_e32 v2, v3, v2266; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2267; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 24, v1268; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 24269; GFX6-NEXT:    s_setpc_b64 s[30:31]270;271; GFX8-LABEL: v_uaddsat_v2i8:272; GFX8:       ; %bb.0:273; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)274; GFX8-NEXT:    v_mov_b32_e32 v2, 8275; GFX8-NEXT:    v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD276; GFX8-NEXT:    v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD277; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v0278; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1279; GFX8-NEXT:    v_add_u16_e64 v0, v0, v1 clamp280; GFX8-NEXT:    v_add_u16_e64 v1, v3, v2 clamp281; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 8, v1282; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1283; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD284; GFX8-NEXT:    s_setpc_b64 s[30:31]285;286; GFX9-LABEL: v_uaddsat_v2i8:287; GFX9:       ; %bb.0:288; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)289; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 8, v0290; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 8, v1291; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v0292; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v1293; GFX9-NEXT:    v_lshl_or_b32 v0, v2, 16, v0294; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v1295; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]296; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]297; GFX9-NEXT:    v_pk_add_u16 v0, v0, v1 clamp298; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]299; GFX9-NEXT:    v_mov_b32_e32 v1, 0xff300; GFX9-NEXT:    v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD301; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD302; GFX9-NEXT:    s_setpc_b64 s[30:31]303;304; GFX10-LABEL: v_uaddsat_v2i8:305; GFX10:       ; %bb.0:306; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 8, v0308; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 8, v1309; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v0310; GFX10-NEXT:    v_and_b32_e32 v1, 0xffff, v1311; GFX10-NEXT:    v_lshl_or_b32 v0, v2, 16, v0312; GFX10-NEXT:    v_lshl_or_b32 v1, v3, 16, v1313; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]314; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]315; GFX10-NEXT:    v_pk_add_u16 v0, v0, v1 clamp316; GFX10-NEXT:    v_mov_b32_e32 v1, 0xff317; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]318; GFX10-NEXT:    v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD319; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD320; GFX10-NEXT:    s_setpc_b64 s[30:31]321;322; GFX11-TRUE16-LABEL: v_uaddsat_v2i8:323; GFX11-TRUE16:       ; %bb.0:324; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v0326; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v1327; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l328; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v3.l329; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]330; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]331; GFX11-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1 clamp332; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]333; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v1.h334; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l335; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]336;337; GFX11-FAKE16-LABEL: v_uaddsat_v2i8:338; GFX11-FAKE16:       ; %bb.0:339; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v0341; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v1342; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v0343; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v1344; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v2, 16, v0345; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v3, 16, v1346; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]347; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]348; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1 clamp349; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]350; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0351; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0352; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1353; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1354; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1355; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]356  %lhs = bitcast i16 %lhs.arg to <2 x i8>357  %rhs = bitcast i16 %rhs.arg to <2 x i8>358  %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)359  %cast.result = bitcast <2 x i8> %result to i16360  ret i16 %cast.result361}362 363define amdgpu_ps i16 @s_uaddsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {364; GFX6-LABEL: s_uaddsat_v2i8:365; GFX6:       ; %bb.0:366; GFX6-NEXT:    s_lshr_b32 s2, s0, 8367; GFX6-NEXT:    s_lshl_b32 s0, s0, 24368; GFX6-NEXT:    s_lshr_b32 s3, s1, 8369; GFX6-NEXT:    s_lshl_b32 s1, s1, 24370; GFX6-NEXT:    s_not_b32 s4, s0371; GFX6-NEXT:    s_min_u32 s1, s4, s1372; GFX6-NEXT:    s_add_i32 s0, s0, s1373; GFX6-NEXT:    s_lshl_b32 s1, s2, 24374; GFX6-NEXT:    s_lshl_b32 s2, s3, 24375; GFX6-NEXT:    s_not_b32 s3, s1376; GFX6-NEXT:    s_min_u32 s2, s3, s2377; GFX6-NEXT:    s_add_i32 s1, s1, s2378; GFX6-NEXT:    s_lshr_b32 s1, s1, 24379; GFX6-NEXT:    v_mov_b32_e32 v0, s0380; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 24381; GFX6-NEXT:    v_readfirstlane_b32 s0, v0382; GFX6-NEXT:    ; return to shader part epilog383;384; GFX8-LABEL: s_uaddsat_v2i8:385; GFX8:       ; %bb.0:386; GFX8-NEXT:    s_lshr_b32 s3, s1, 8387; GFX8-NEXT:    s_lshl_b32 s1, s1, 8388; GFX8-NEXT:    s_lshr_b32 s2, s0, 8389; GFX8-NEXT:    s_lshl_b32 s0, s0, 8390; GFX8-NEXT:    v_mov_b32_e32 v0, s1391; GFX8-NEXT:    s_lshl_b32 s1, s3, 8392; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp393; GFX8-NEXT:    s_lshl_b32 s0, s2, 8394; GFX8-NEXT:    v_mov_b32_e32 v1, s1395; GFX8-NEXT:    v_add_u16_e64 v1, s0, v1 clamp396; GFX8-NEXT:    v_lshrrev_b16_e32 v1, 8, v1397; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1398; GFX8-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD399; GFX8-NEXT:    v_readfirstlane_b32 s0, v0400; GFX8-NEXT:    ; return to shader part epilog401;402; GFX9-LABEL: s_uaddsat_v2i8:403; GFX9:       ; %bb.0:404; GFX9-NEXT:    s_lshr_b32 s2, s0, 8405; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2406; GFX9-NEXT:    s_lshr_b32 s3, s1, 8407; GFX9-NEXT:    s_lshr_b32 s2, s0, 16408; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s3409; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x80008410; GFX9-NEXT:    s_lshl_b32 s2, s2, 8411; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2412; GFX9-NEXT:    s_lshr_b32 s2, s1, 16413; GFX9-NEXT:    s_lshl_b32 s1, s1, 0x80008414; GFX9-NEXT:    s_lshl_b32 s2, s2, 8415; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s2416; GFX9-NEXT:    v_mov_b32_e32 v0, s1417; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp418; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]419; GFX9-NEXT:    v_mov_b32_e32 v1, 0xff420; GFX9-NEXT:    v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD421; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD422; GFX9-NEXT:    v_readfirstlane_b32 s0, v0423; GFX9-NEXT:    ; return to shader part epilog424;425; GFX10-LABEL: s_uaddsat_v2i8:426; GFX10:       ; %bb.0:427; GFX10-NEXT:    s_lshr_b32 s2, s0, 8428; GFX10-NEXT:    s_lshr_b32 s3, s1, 8429; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2430; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3431; GFX10-NEXT:    s_lshr_b32 s2, s0, 16432; GFX10-NEXT:    s_lshr_b32 s3, s1, 16433; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x80008434; GFX10-NEXT:    s_lshl_b32 s2, s2, 8435; GFX10-NEXT:    s_lshl_b32 s1, s1, 0x80008436; GFX10-NEXT:    s_lshl_b32 s3, s3, 8437; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2438; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s3439; GFX10-NEXT:    v_mov_b32_e32 v1, 0xff440; GFX10-NEXT:    v_pk_add_u16 v0, s0, s1 clamp441; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]442; GFX10-NEXT:    v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD443; GFX10-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD444; GFX10-NEXT:    v_readfirstlane_b32 s0, v0445; GFX10-NEXT:    ; return to shader part epilog446;447; GFX11-TRUE16-LABEL: s_uaddsat_v2i8:448; GFX11-TRUE16:       ; %bb.0:449; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s0, 8450; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s1, 8451; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s2452; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s3453; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s0, 16454; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s1, 16455; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 0x80008456; GFX11-TRUE16-NEXT:    s_lshl_b32 s2, s2, 8457; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 0x80008458; GFX11-TRUE16-NEXT:    s_lshl_b32 s3, s3, 8459; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s2460; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s3461; GFX11-TRUE16-NEXT:    v_pk_add_u16 v0, s0, s1 clamp462; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]463; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v0.l, 8, v1.h464; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l465; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0466; GFX11-TRUE16-NEXT:    ; return to shader part epilog467;468; GFX11-FAKE16-LABEL: s_uaddsat_v2i8:469; GFX11-FAKE16:       ; %bb.0:470; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s0, 8471; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s1, 8472; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s2473; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s3474; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s0, 16475; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s1, 16476; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 0x80008477; GFX11-FAKE16-NEXT:    s_lshl_b32 s2, s2, 8478; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 0x80008479; GFX11-FAKE16-NEXT:    s_lshl_b32 s3, s3, 8480; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s2481; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s3482; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, s0, s1 clamp483; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]484; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v0485; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v0486; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xff, v1487; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v1488; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v1489; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0490; GFX11-FAKE16-NEXT:    ; return to shader part epilog491  %lhs = bitcast i16 %lhs.arg to <2 x i8>492  %rhs = bitcast i16 %rhs.arg to <2 x i8>493  %result = call <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)494  %cast.result = bitcast <2 x i8> %result to i16495  ret i16 %cast.result496}497 498define i32 @v_uaddsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {499; GFX6-LABEL: v_uaddsat_v4i8:500; GFX6:       ; %bb.0:501; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)502; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 8, v0503; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v0504; GFX6-NEXT:    v_lshrrev_b32_e32 v4, 24, v0505; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 24, v0506; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 8, v1507; GFX6-NEXT:    v_lshrrev_b32_e32 v6, 16, v1508; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 24, v1509; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v1510; GFX6-NEXT:    v_not_b32_e32 v8, v0511; GFX6-NEXT:    v_min_u32_e32 v1, v8, v1512; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1513; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v2514; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 24, v5515; GFX6-NEXT:    v_not_b32_e32 v5, v1516; GFX6-NEXT:    v_min_u32_e32 v2, v5, v2517; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v2518; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 24, v3519; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 24, v6520; GFX6-NEXT:    v_not_b32_e32 v5, v2521; GFX6-NEXT:    v_min_u32_e32 v3, v5, v3522; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v3523; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 24, v4524; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 24, v7525; GFX6-NEXT:    v_not_b32_e32 v5, v3526; GFX6-NEXT:    v_min_u32_e32 v4, v5, v4527; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 24, v1528; GFX6-NEXT:    v_lshrrev_b32_e32 v2, 24, v2529; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v4530; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 24, v3531; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 24532; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v2533; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1534; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 24, v3535; GFX6-NEXT:    v_or_b32_e32 v0, v0, v1536; GFX6-NEXT:    s_setpc_b64 s[30:31]537;538; GFX8-LABEL: v_uaddsat_v4i8:539; GFX8:       ; %bb.0:540; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)541; GFX8-NEXT:    v_mov_b32_e32 v2, 8542; GFX8-NEXT:    v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD543; GFX8-NEXT:    v_lshrrev_b32_e32 v4, 16, v0544; GFX8-NEXT:    v_lshrrev_b32_e32 v5, 24, v0545; GFX8-NEXT:    v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD546; GFX8-NEXT:    v_lshrrev_b32_e32 v6, 16, v1547; GFX8-NEXT:    v_lshrrev_b32_e32 v7, 24, v1548; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v0549; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v1550; GFX8-NEXT:    v_add_u16_e64 v0, v0, v1 clamp551; GFX8-NEXT:    v_add_u16_e64 v1, v3, v2 clamp552; GFX8-NEXT:    v_lshlrev_b16_e32 v2, 8, v4553; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 8, v6554; GFX8-NEXT:    v_add_u16_e64 v2, v2, v3 clamp555; GFX8-NEXT:    v_lshlrev_b16_e32 v3, 8, v5556; GFX8-NEXT:    v_lshlrev_b16_e32 v4, 8, v7557; GFX8-NEXT:    v_add_u16_e64 v3, v3, v4 clamp558; GFX8-NEXT:    v_mov_b32_e32 v4, 0xff559; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD560; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD561; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 8, v1562; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1563; GFX8-NEXT:    v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD564; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1565; GFX8-NEXT:    v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD566; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1567; GFX8-NEXT:    s_setpc_b64 s[30:31]568;569; GFX9-LABEL: v_uaddsat_v4i8:570; GFX9:       ; %bb.0:571; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)572; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v0573; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 8, v0574; GFX9-NEXT:    v_lshrrev_b32_e32 v4, 8, v1575; GFX9-NEXT:    v_and_b32_e32 v6, 0xffff, v0576; GFX9-NEXT:    v_alignbit_b32 v0, v3, v0, 16577; GFX9-NEXT:    v_and_b32_e32 v3, 0xffff, v1578; GFX9-NEXT:    v_lshrrev_b32_e32 v5, 24, v1579; GFX9-NEXT:    v_lshl_or_b32 v2, v2, 16, v6580; GFX9-NEXT:    v_lshl_or_b32 v3, v4, 16, v3581; GFX9-NEXT:    v_alignbit_b32 v1, v5, v1, 16582; GFX9-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]583; GFX9-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]584; GFX9-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]585; GFX9-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]586; GFX9-NEXT:    v_pk_add_u16 v2, v2, v3 clamp587; GFX9-NEXT:    v_pk_add_u16 v0, v0, v1 clamp588; GFX9-NEXT:    v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]589; GFX9-NEXT:    v_mov_b32_e32 v3, 8590; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]591; GFX9-NEXT:    v_mov_b32_e32 v2, 0xff592; GFX9-NEXT:    v_lshlrev_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2593; GFX9-NEXT:    v_and_or_b32 v1, v1, v2, v3594; GFX9-NEXT:    v_and_b32_e32 v2, 0xff, v0595; GFX9-NEXT:    v_mov_b32_e32 v3, 24596; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2597; GFX9-NEXT:    v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2598; GFX9-NEXT:    v_or3_b32 v0, v1, v2, v0599; GFX9-NEXT:    s_setpc_b64 s[30:31]600;601; GFX10-LABEL: v_uaddsat_v4i8:602; GFX10:       ; %bb.0:603; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)604; GFX10-NEXT:    v_lshrrev_b32_e32 v2, 8, v0605; GFX10-NEXT:    v_lshrrev_b32_e32 v3, 24, v0606; GFX10-NEXT:    v_and_b32_e32 v4, 0xffff, v0607; GFX10-NEXT:    v_lshrrev_b32_e32 v5, 8, v1608; GFX10-NEXT:    v_and_b32_e32 v6, 0xffff, v1609; GFX10-NEXT:    v_lshrrev_b32_e32 v7, 24, v1610; GFX10-NEXT:    v_alignbit_b32 v0, v3, v0, 16611; GFX10-NEXT:    v_lshl_or_b32 v2, v2, 16, v4612; GFX10-NEXT:    v_mov_b32_e32 v4, 24613; GFX10-NEXT:    v_lshl_or_b32 v3, v5, 16, v6614; GFX10-NEXT:    v_alignbit_b32 v1, v7, v1, 16615; GFX10-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]616; GFX10-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]617; GFX10-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]618; GFX10-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]619; GFX10-NEXT:    v_pk_add_u16 v2, v2, v3 clamp620; GFX10-NEXT:    v_pk_add_u16 v0, v0, v1 clamp621; GFX10-NEXT:    v_mov_b32_e32 v1, 8622; GFX10-NEXT:    v_pk_lshrrev_b16 v2, 8, v2 op_sel_hi:[0,1]623; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]624; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2625; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v0626; GFX10-NEXT:    v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2627; GFX10-NEXT:    v_and_or_b32 v1, 0xff, v2, v1628; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3629; GFX10-NEXT:    v_or3_b32 v0, v1, v2, v0630; GFX10-NEXT:    s_setpc_b64 s[30:31]631;632; GFX11-TRUE16-LABEL: v_uaddsat_v4i8:633; GFX11-TRUE16:       ; %bb.0:634; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)635; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v0636; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v4, 8, v1637; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 16, v0638; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v5, 24, v0639; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v6, 16, v1640; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1641; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l642; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v4.l643; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.h, v5.l644; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v6.h, v7.l645; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]646; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]647; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]648; GFX11-TRUE16-NEXT:    v_pk_add_u16 v0, v0, v1 clamp649; GFX11-TRUE16-NEXT:    v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]650; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]651; GFX11-TRUE16-NEXT:    v_pk_add_u16 v1, v2, v1 clamp652; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h653; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]654; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff, v2655; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.h656; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff, v1657; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v2658; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xff, v3659; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1660; GFX11-TRUE16-NEXT:    v_and_or_b32 v0, 0xff, v0, v2661; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 24, v3662; GFX11-TRUE16-NEXT:    v_or3_b32 v0, v0, v1, v2663; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]664;665; GFX11-FAKE16-LABEL: v_uaddsat_v4i8:666; GFX11-FAKE16:       ; %bb.0:667; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)668; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 8, v0669; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 8, v1670; GFX11-FAKE16-NEXT:    v_and_b32_e32 v4, 0xffff, v0671; GFX11-FAKE16-NEXT:    v_and_b32_e32 v5, 0xffff, v1672; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v6, 24, v0673; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v7, 24, v1674; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v2, v2, 16, v4675; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v3, v3, 16, v5676; GFX11-FAKE16-NEXT:    v_alignbit_b32 v0, v6, v0, 16677; GFX11-FAKE16-NEXT:    v_alignbit_b32 v1, v7, v1, 16678; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]679; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]680; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]681; GFX11-FAKE16-NEXT:    v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]682; GFX11-FAKE16-NEXT:    v_pk_add_u16 v2, v2, v3 clamp683; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, v0, v1 clamp684; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]685; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]686; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 8687; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v0688; GFX11-FAKE16-NEXT:    v_bfe_u32 v0, v0, 16, 8689; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v2690; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v3, 16, v3691; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v0, 24, v0692; GFX11-FAKE16-NEXT:    v_and_or_b32 v1, 0xff, v1, v2693; GFX11-FAKE16-NEXT:    v_or3_b32 v0, v1, v3, v0694; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]695  %lhs = bitcast i32 %lhs.arg to <4 x i8>696  %rhs = bitcast i32 %rhs.arg to <4 x i8>697  %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)698  %cast.result = bitcast <4 x i8> %result to i32699  ret i32 %cast.result700}701 702define amdgpu_ps i32 @s_uaddsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {703; GFX6-LABEL: s_uaddsat_v4i8:704; GFX6:       ; %bb.0:705; GFX6-NEXT:    s_lshr_b32 s2, s0, 8706; GFX6-NEXT:    s_lshr_b32 s3, s0, 16707; GFX6-NEXT:    s_lshr_b32 s4, s0, 24708; GFX6-NEXT:    s_lshl_b32 s0, s0, 24709; GFX6-NEXT:    s_lshr_b32 s5, s1, 8710; GFX6-NEXT:    s_lshr_b32 s6, s1, 16711; GFX6-NEXT:    s_lshr_b32 s7, s1, 24712; GFX6-NEXT:    s_lshl_b32 s1, s1, 24713; GFX6-NEXT:    s_not_b32 s8, s0714; GFX6-NEXT:    s_min_u32 s1, s8, s1715; GFX6-NEXT:    s_add_i32 s0, s0, s1716; GFX6-NEXT:    s_lshl_b32 s1, s2, 24717; GFX6-NEXT:    s_lshl_b32 s2, s5, 24718; GFX6-NEXT:    s_not_b32 s5, s1719; GFX6-NEXT:    s_min_u32 s2, s5, s2720; GFX6-NEXT:    s_add_i32 s1, s1, s2721; GFX6-NEXT:    s_lshl_b32 s2, s3, 24722; GFX6-NEXT:    s_lshl_b32 s3, s6, 24723; GFX6-NEXT:    s_not_b32 s5, s2724; GFX6-NEXT:    s_min_u32 s3, s5, s3725; GFX6-NEXT:    s_add_i32 s2, s2, s3726; GFX6-NEXT:    s_lshl_b32 s3, s4, 24727; GFX6-NEXT:    s_lshl_b32 s4, s7, 24728; GFX6-NEXT:    s_not_b32 s5, s3729; GFX6-NEXT:    s_min_u32 s4, s5, s4730; GFX6-NEXT:    s_lshr_b32 s1, s1, 24731; GFX6-NEXT:    s_lshr_b32 s2, s2, 24732; GFX6-NEXT:    s_add_i32 s3, s3, s4733; GFX6-NEXT:    v_mov_b32_e32 v0, s0734; GFX6-NEXT:    s_lshr_b32 s3, s3, 24735; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 24736; GFX6-NEXT:    s_lshl_b32 s0, s2, 16737; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0738; GFX6-NEXT:    s_lshl_b32 s0, s3, 24739; GFX6-NEXT:    v_or_b32_e32 v0, s0, v0740; GFX6-NEXT:    v_readfirstlane_b32 s0, v0741; GFX6-NEXT:    ; return to shader part epilog742;743; GFX8-LABEL: s_uaddsat_v4i8:744; GFX8:       ; %bb.0:745; GFX8-NEXT:    s_lshr_b32 s5, s1, 8746; GFX8-NEXT:    s_lshr_b32 s6, s1, 16747; GFX8-NEXT:    s_lshr_b32 s7, s1, 24748; GFX8-NEXT:    s_lshl_b32 s1, s1, 8749; GFX8-NEXT:    s_lshr_b32 s2, s0, 8750; GFX8-NEXT:    s_lshr_b32 s3, s0, 16751; GFX8-NEXT:    s_lshr_b32 s4, s0, 24752; GFX8-NEXT:    s_lshl_b32 s0, s0, 8753; GFX8-NEXT:    v_mov_b32_e32 v0, s1754; GFX8-NEXT:    s_lshl_b32 s1, s5, 8755; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp756; GFX8-NEXT:    s_lshl_b32 s0, s2, 8757; GFX8-NEXT:    v_mov_b32_e32 v1, s1758; GFX8-NEXT:    v_add_u16_e64 v1, s0, v1 clamp759; GFX8-NEXT:    s_lshl_b32 s1, s6, 8760; GFX8-NEXT:    v_mov_b32_e32 v4, 0xff761; GFX8-NEXT:    s_lshl_b32 s0, s3, 8762; GFX8-NEXT:    v_mov_b32_e32 v2, s1763; GFX8-NEXT:    s_lshl_b32 s1, s7, 8764; GFX8-NEXT:    v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD765; GFX8-NEXT:    v_add_u16_e64 v2, s0, v2 clamp766; GFX8-NEXT:    s_lshl_b32 s0, s4, 8767; GFX8-NEXT:    v_mov_b32_e32 v3, s1768; GFX8-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD769; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 8, v1770; GFX8-NEXT:    v_add_u16_e64 v3, s0, v3 clamp771; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1772; GFX8-NEXT:    v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD773; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1774; GFX8-NEXT:    v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD775; GFX8-NEXT:    v_or_b32_e32 v0, v0, v1776; GFX8-NEXT:    v_readfirstlane_b32 s0, v0777; GFX8-NEXT:    ; return to shader part epilog778;779; GFX9-LABEL: s_uaddsat_v4i8:780; GFX9:       ; %bb.0:781; GFX9-NEXT:    s_lshr_b32 s2, s0, 8782; GFX9-NEXT:    s_lshr_b32 s3, s0, 16783; GFX9-NEXT:    s_lshr_b32 s4, s0, 24784; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s2785; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s3, s4786; GFX9-NEXT:    s_lshr_b32 s4, s0, 16787; GFX9-NEXT:    s_lshl_b32 s0, s0, 0x80008788; GFX9-NEXT:    s_lshl_b32 s4, s4, 8789; GFX9-NEXT:    s_lshr_b32 s5, s1, 8790; GFX9-NEXT:    s_pack_ll_b32_b16 s0, s0, s4791; GFX9-NEXT:    s_lshr_b32 s4, s2, 16792; GFX9-NEXT:    s_lshr_b32 s6, s1, 16793; GFX9-NEXT:    s_lshr_b32 s7, s1, 24794; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s5795; GFX9-NEXT:    s_lshl_b32 s2, s2, 0x80008796; GFX9-NEXT:    s_lshl_b32 s4, s4, 8797; GFX9-NEXT:    s_pack_ll_b32_b16 s2, s2, s4798; GFX9-NEXT:    s_lshr_b32 s4, s1, 16799; GFX9-NEXT:    s_pack_ll_b32_b16 s3, s6, s7800; GFX9-NEXT:    s_lshl_b32 s1, s1, 0x80008801; GFX9-NEXT:    s_lshl_b32 s4, s4, 8802; GFX9-NEXT:    s_pack_ll_b32_b16 s1, s1, s4803; GFX9-NEXT:    s_lshr_b32 s4, s3, 16804; GFX9-NEXT:    s_lshl_b32 s3, s3, 0x80008805; GFX9-NEXT:    s_lshl_b32 s4, s4, 8806; GFX9-NEXT:    s_pack_ll_b32_b16 s3, s3, s4807; GFX9-NEXT:    v_mov_b32_e32 v0, s1808; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp809; GFX9-NEXT:    v_mov_b32_e32 v1, s3810; GFX9-NEXT:    v_pk_add_u16 v1, s2, v1 clamp811; GFX9-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]812; GFX9-NEXT:    v_mov_b32_e32 v3, 8813; GFX9-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]814; GFX9-NEXT:    v_mov_b32_e32 v2, 0xff815; GFX9-NEXT:    v_lshlrev_b32_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2816; GFX9-NEXT:    v_and_or_b32 v0, v0, v2, v3817; GFX9-NEXT:    v_and_b32_e32 v2, 0xff, v1818; GFX9-NEXT:    v_mov_b32_e32 v3, 24819; GFX9-NEXT:    v_lshlrev_b32_e32 v2, 16, v2820; GFX9-NEXT:    v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2821; GFX9-NEXT:    v_or3_b32 v0, v0, v2, v1822; GFX9-NEXT:    v_readfirstlane_b32 s0, v0823; GFX9-NEXT:    ; return to shader part epilog824;825; GFX10-LABEL: s_uaddsat_v4i8:826; GFX10:       ; %bb.0:827; GFX10-NEXT:    s_lshr_b32 s2, s0, 8828; GFX10-NEXT:    s_lshr_b32 s3, s0, 16829; GFX10-NEXT:    s_lshr_b32 s4, s0, 24830; GFX10-NEXT:    s_lshr_b32 s5, s1, 8831; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s2832; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s3, s4833; GFX10-NEXT:    s_lshr_b32 s6, s1, 16834; GFX10-NEXT:    s_lshr_b32 s7, s1, 24835; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s5836; GFX10-NEXT:    s_lshr_b32 s4, s0, 16837; GFX10-NEXT:    s_lshr_b32 s5, s2, 16838; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s6, s7839; GFX10-NEXT:    s_lshl_b32 s0, s0, 0x80008840; GFX10-NEXT:    s_lshl_b32 s4, s4, 8841; GFX10-NEXT:    s_lshl_b32 s2, s2, 0x80008842; GFX10-NEXT:    s_lshl_b32 s5, s5, 8843; GFX10-NEXT:    s_pack_ll_b32_b16 s0, s0, s4844; GFX10-NEXT:    s_pack_ll_b32_b16 s2, s2, s5845; GFX10-NEXT:    s_lshr_b32 s4, s1, 16846; GFX10-NEXT:    s_lshr_b32 s5, s3, 16847; GFX10-NEXT:    s_lshl_b32 s1, s1, 0x80008848; GFX10-NEXT:    s_lshl_b32 s4, s4, 8849; GFX10-NEXT:    s_lshl_b32 s3, s3, 0x80008850; GFX10-NEXT:    s_lshl_b32 s5, s5, 8851; GFX10-NEXT:    s_pack_ll_b32_b16 s1, s1, s4852; GFX10-NEXT:    s_pack_ll_b32_b16 s3, s3, s5853; GFX10-NEXT:    v_pk_add_u16 v0, s0, s1 clamp854; GFX10-NEXT:    v_pk_add_u16 v1, s2, s3 clamp855; GFX10-NEXT:    v_mov_b32_e32 v2, 8856; GFX10-NEXT:    v_mov_b32_e32 v4, 24857; GFX10-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]858; GFX10-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]859; GFX10-NEXT:    v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2860; GFX10-NEXT:    v_and_b32_e32 v3, 0xff, v1861; GFX10-NEXT:    v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2862; GFX10-NEXT:    v_and_or_b32 v0, 0xff, v0, v2863; GFX10-NEXT:    v_lshlrev_b32_e32 v2, 16, v3864; GFX10-NEXT:    v_or3_b32 v0, v0, v2, v1865; GFX10-NEXT:    v_readfirstlane_b32 s0, v0866; GFX10-NEXT:    ; return to shader part epilog867;868; GFX11-TRUE16-LABEL: s_uaddsat_v4i8:869; GFX11-TRUE16:       ; %bb.0:870; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s0, 8871; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s0, 24872; GFX11-TRUE16-NEXT:    s_lshr_b32 s4, s1, 8873; GFX11-TRUE16-NEXT:    s_lshr_b32 s5, s1, 24874; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s0, s2875; GFX11-TRUE16-NEXT:    s_pack_hl_b32_b16 s0, s0, s3876; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s1, s4877; GFX11-TRUE16-NEXT:    s_lshr_b32 s4, s2, 16878; GFX11-TRUE16-NEXT:    s_pack_hl_b32_b16 s1, s1, s5879; GFX11-TRUE16-NEXT:    s_lshr_b32 s5, s3, 16880; GFX11-TRUE16-NEXT:    s_lshl_b32 s2, s2, 0x80008881; GFX11-TRUE16-NEXT:    s_lshl_b32 s4, s4, 8882; GFX11-TRUE16-NEXT:    s_lshl_b32 s3, s3, 0x80008883; GFX11-TRUE16-NEXT:    s_lshl_b32 s5, s5, 8884; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s4885; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s5886; GFX11-TRUE16-NEXT:    s_lshr_b32 s4, s0, 16887; GFX11-TRUE16-NEXT:    s_lshr_b32 s5, s1, 16888; GFX11-TRUE16-NEXT:    v_pk_add_u16 v0, s2, s3 clamp889; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 0x80008890; GFX11-TRUE16-NEXT:    s_lshl_b32 s4, s4, 8891; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s1, 0x80008892; GFX11-TRUE16-NEXT:    s_lshl_b32 s2, s5, 8893; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s4894; GFX11-TRUE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s2895; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]896; GFX11-TRUE16-NEXT:    v_pk_add_u16 v1, s0, s1 clamp897; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h898; GFX11-TRUE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]899; GFX11-TRUE16-NEXT:    v_and_b32_e32 v2, 0xff, v2900; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v3.l, v1.h901; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xff, v1902; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v2903; GFX11-TRUE16-NEXT:    v_and_b32_e32 v3, 0xff, v3904; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v1905; GFX11-TRUE16-NEXT:    v_and_or_b32 v0, 0xff, v0, v2906; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v2, 24, v3907; GFX11-TRUE16-NEXT:    v_or3_b32 v0, v0, v1, v2908; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s0, v0909; GFX11-TRUE16-NEXT:    ; return to shader part epilog910;911; GFX11-FAKE16-LABEL: s_uaddsat_v4i8:912; GFX11-FAKE16:       ; %bb.0:913; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s0, 8914; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s0, 24915; GFX11-FAKE16-NEXT:    s_lshr_b32 s4, s1, 8916; GFX11-FAKE16-NEXT:    s_lshr_b32 s5, s1, 24917; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s0, s2918; GFX11-FAKE16-NEXT:    s_pack_hl_b32_b16 s0, s0, s3919; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s1, s4920; GFX11-FAKE16-NEXT:    s_lshr_b32 s4, s2, 16921; GFX11-FAKE16-NEXT:    s_pack_hl_b32_b16 s1, s1, s5922; GFX11-FAKE16-NEXT:    s_lshr_b32 s5, s3, 16923; GFX11-FAKE16-NEXT:    s_lshl_b32 s2, s2, 0x80008924; GFX11-FAKE16-NEXT:    s_lshl_b32 s4, s4, 8925; GFX11-FAKE16-NEXT:    s_lshl_b32 s3, s3, 0x80008926; GFX11-FAKE16-NEXT:    s_lshl_b32 s5, s5, 8927; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s2, s2, s4928; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s3, s3, s5929; GFX11-FAKE16-NEXT:    s_lshr_b32 s4, s0, 16930; GFX11-FAKE16-NEXT:    s_lshr_b32 s5, s1, 16931; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, s2, s3 clamp932; GFX11-FAKE16-NEXT:    s_lshl_b32 s0, s0, 0x80008933; GFX11-FAKE16-NEXT:    s_lshl_b32 s4, s4, 8934; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s1, 0x80008935; GFX11-FAKE16-NEXT:    s_lshl_b32 s2, s5, 8936; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s0, s0, s4937; GFX11-FAKE16-NEXT:    s_pack_ll_b32_b16 s1, s1, s2938; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]939; GFX11-FAKE16-NEXT:    v_pk_add_u16 v1, s0, s1 clamp940; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 8941; GFX11-FAKE16-NEXT:    v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]942; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 8, v2943; GFX11-FAKE16-NEXT:    v_and_b32_e32 v3, 0xff, v1944; GFX11-FAKE16-NEXT:    v_bfe_u32 v1, v1, 16, 8945; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0xff, v0, v2946; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v2, 16, v3947; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 24, v1948; GFX11-FAKE16-NEXT:    v_or3_b32 v0, v0, v2, v1949; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v0950; GFX11-FAKE16-NEXT:    ; return to shader part epilog951  %lhs = bitcast i32 %lhs.arg to <4 x i8>952  %rhs = bitcast i32 %rhs.arg to <4 x i8>953  %result = call <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)954  %cast.result = bitcast <4 x i8> %result to i32955  ret i32 %cast.result956}957 958define i24 @v_uaddsat_i24(i24 %lhs, i24 %rhs) {959; GFX6-LABEL: v_uaddsat_i24:960; GFX6:       ; %bb.0:961; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)962; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 8, v0963; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 8, v1964; GFX6-NEXT:    v_not_b32_e32 v2, v0965; GFX6-NEXT:    v_min_u32_e32 v1, v2, v1966; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v1967; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 8, v0968; GFX6-NEXT:    s_setpc_b64 s[30:31]969;970; GFX8-LABEL: v_uaddsat_i24:971; GFX8:       ; %bb.0:972; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)973; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 8, v0974; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 8, v1975; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v1 clamp976; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 8, v0977; GFX8-NEXT:    s_setpc_b64 s[30:31]978;979; GFX9-LABEL: v_uaddsat_i24:980; GFX9:       ; %bb.0:981; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)982; GFX9-NEXT:    v_lshlrev_b32_e32 v0, 8, v0983; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 8, v1984; GFX9-NEXT:    v_add_u32_e64 v0, v0, v1 clamp985; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v0986; GFX9-NEXT:    s_setpc_b64 s[30:31]987;988; GFX10PLUS-LABEL: v_uaddsat_i24:989; GFX10PLUS:       ; %bb.0:990; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)991; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v0, 8, v0992; GFX10PLUS-NEXT:    v_lshlrev_b32_e32 v1, 8, v1993; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp994; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v0995; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]996  %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)997  ret i24 %result998}999 1000define amdgpu_ps i24 @s_uaddsat_i24(i24 inreg %lhs, i24 inreg %rhs) {1001; GFX6-LABEL: s_uaddsat_i24:1002; GFX6:       ; %bb.0:1003; GFX6-NEXT:    s_lshl_b32 s0, s0, 81004; GFX6-NEXT:    s_lshl_b32 s1, s1, 81005; GFX6-NEXT:    s_not_b32 s2, s01006; GFX6-NEXT:    s_min_u32 s1, s2, s11007; GFX6-NEXT:    s_add_i32 s0, s0, s11008; GFX6-NEXT:    s_lshr_b32 s0, s0, 81009; GFX6-NEXT:    ; return to shader part epilog1010;1011; GFX8-LABEL: s_uaddsat_i24:1012; GFX8:       ; %bb.0:1013; GFX8-NEXT:    s_lshl_b32 s1, s1, 81014; GFX8-NEXT:    s_lshl_b32 s0, s0, 81015; GFX8-NEXT:    v_mov_b32_e32 v0, s11016; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], s0, v0 clamp1017; GFX8-NEXT:    v_lshrrev_b32_e32 v0, 8, v01018; GFX8-NEXT:    v_readfirstlane_b32 s0, v01019; GFX8-NEXT:    ; return to shader part epilog1020;1021; GFX9-LABEL: s_uaddsat_i24:1022; GFX9:       ; %bb.0:1023; GFX9-NEXT:    s_lshl_b32 s1, s1, 81024; GFX9-NEXT:    s_lshl_b32 s0, s0, 81025; GFX9-NEXT:    v_mov_b32_e32 v0, s11026; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1027; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 8, v01028; GFX9-NEXT:    v_readfirstlane_b32 s0, v01029; GFX9-NEXT:    ; return to shader part epilog1030;1031; GFX10PLUS-LABEL: s_uaddsat_i24:1032; GFX10PLUS:       ; %bb.0:1033; GFX10PLUS-NEXT:    s_lshl_b32 s0, s0, 81034; GFX10PLUS-NEXT:    s_lshl_b32 s1, s1, 81035; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp1036; GFX10PLUS-NEXT:    v_lshrrev_b32_e32 v0, 8, v01037; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01038; GFX10PLUS-NEXT:    ; return to shader part epilog1039  %result = call i24 @llvm.uadd.sat.i24(i24 %lhs, i24 %rhs)1040  ret i24 %result1041}1042 1043define i32 @v_uaddsat_i32(i32 %lhs, i32 %rhs) {1044; GFX6-LABEL: v_uaddsat_i32:1045; GFX6:       ; %bb.0:1046; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1047; GFX6-NEXT:    v_not_b32_e32 v2, v01048; GFX6-NEXT:    v_min_u32_e32 v1, v2, v11049; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v11050; GFX6-NEXT:    s_setpc_b64 s[30:31]1051;1052; GFX8-LABEL: v_uaddsat_i32:1053; GFX8:       ; %bb.0:1054; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1055; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v1 clamp1056; GFX8-NEXT:    s_setpc_b64 s[30:31]1057;1058; GFX9-LABEL: v_uaddsat_i32:1059; GFX9:       ; %bb.0:1060; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1061; GFX9-NEXT:    v_add_u32_e64 v0, v0, v1 clamp1062; GFX9-NEXT:    s_setpc_b64 s[30:31]1063;1064; GFX10PLUS-LABEL: v_uaddsat_i32:1065; GFX10PLUS:       ; %bb.0:1066; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1067; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v1 clamp1068; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]1069  %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)1070  ret i32 %result1071}1072 1073define amdgpu_ps i32 @s_uaddsat_i32(i32 inreg %lhs, i32 inreg %rhs) {1074; GFX6-LABEL: s_uaddsat_i32:1075; GFX6:       ; %bb.0:1076; GFX6-NEXT:    s_not_b32 s2, s01077; GFX6-NEXT:    s_min_u32 s1, s2, s11078; GFX6-NEXT:    s_add_i32 s0, s0, s11079; GFX6-NEXT:    ; return to shader part epilog1080;1081; GFX8-LABEL: s_uaddsat_i32:1082; GFX8:       ; %bb.0:1083; GFX8-NEXT:    v_mov_b32_e32 v0, s11084; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], s0, v0 clamp1085; GFX8-NEXT:    v_readfirstlane_b32 s0, v01086; GFX8-NEXT:    ; return to shader part epilog1087;1088; GFX9-LABEL: s_uaddsat_i32:1089; GFX9:       ; %bb.0:1090; GFX9-NEXT:    v_mov_b32_e32 v0, s11091; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1092; GFX9-NEXT:    v_readfirstlane_b32 s0, v01093; GFX9-NEXT:    ; return to shader part epilog1094;1095; GFX10PLUS-LABEL: s_uaddsat_i32:1096; GFX10PLUS:       ; %bb.0:1097; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s1 clamp1098; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01099; GFX10PLUS-NEXT:    ; return to shader part epilog1100  %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)1101  ret i32 %result1102}1103 1104define amdgpu_ps float @uaddsat_i32_sv(i32 inreg %lhs, i32 %rhs) {1105; GFX6-LABEL: uaddsat_i32_sv:1106; GFX6:       ; %bb.0:1107; GFX6-NEXT:    s_not_b32 s1, s01108; GFX6-NEXT:    v_min_u32_e32 v0, s1, v01109; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v01110; GFX6-NEXT:    ; return to shader part epilog1111;1112; GFX8-LABEL: uaddsat_i32_sv:1113; GFX8:       ; %bb.0:1114; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], s0, v0 clamp1115; GFX8-NEXT:    ; return to shader part epilog1116;1117; GFX9-LABEL: uaddsat_i32_sv:1118; GFX9:       ; %bb.0:1119; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1120; GFX9-NEXT:    ; return to shader part epilog1121;1122; GFX10PLUS-LABEL: uaddsat_i32_sv:1123; GFX10PLUS:       ; %bb.0:1124; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, v0 clamp1125; GFX10PLUS-NEXT:    ; return to shader part epilog1126  %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)1127  %cast = bitcast i32 %result to float1128  ret float %cast1129}1130 1131define amdgpu_ps float @uaddsat_i32_vs(i32 %lhs, i32 inreg %rhs) {1132; GFX6-LABEL: uaddsat_i32_vs:1133; GFX6:       ; %bb.0:1134; GFX6-NEXT:    v_not_b32_e32 v1, v01135; GFX6-NEXT:    v_min_u32_e32 v1, s0, v11136; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v11137; GFX6-NEXT:    ; return to shader part epilog1138;1139; GFX8-LABEL: uaddsat_i32_vs:1140; GFX8:       ; %bb.0:1141; GFX8-NEXT:    v_add_u32_e64 v0, s[0:1], v0, s0 clamp1142; GFX8-NEXT:    ; return to shader part epilog1143;1144; GFX9-LABEL: uaddsat_i32_vs:1145; GFX9:       ; %bb.0:1146; GFX9-NEXT:    v_add_u32_e64 v0, v0, s0 clamp1147; GFX9-NEXT:    ; return to shader part epilog1148;1149; GFX10PLUS-LABEL: uaddsat_i32_vs:1150; GFX10PLUS:       ; %bb.0:1151; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, s0 clamp1152; GFX10PLUS-NEXT:    ; return to shader part epilog1153  %result = call i32 @llvm.uadd.sat.i32(i32 %lhs, i32 %rhs)1154  %cast = bitcast i32 %result to float1155  ret float %cast1156}1157 1158define <2 x i32> @v_uaddsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {1159; GFX6-LABEL: v_uaddsat_v2i32:1160; GFX6:       ; %bb.0:1161; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1162; GFX6-NEXT:    v_not_b32_e32 v4, v01163; GFX6-NEXT:    v_min_u32_e32 v2, v4, v21164; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v21165; GFX6-NEXT:    v_not_b32_e32 v2, v11166; GFX6-NEXT:    v_min_u32_e32 v2, v2, v31167; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v21168; GFX6-NEXT:    s_setpc_b64 s[30:31]1169;1170; GFX8-LABEL: v_uaddsat_v2i32:1171; GFX8:       ; %bb.0:1172; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1173; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v2 clamp1174; GFX8-NEXT:    v_add_u32_e64 v1, s[4:5], v1, v3 clamp1175; GFX8-NEXT:    s_setpc_b64 s[30:31]1176;1177; GFX9-LABEL: v_uaddsat_v2i32:1178; GFX9:       ; %bb.0:1179; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1180; GFX9-NEXT:    v_add_u32_e64 v0, v0, v2 clamp1181; GFX9-NEXT:    v_add_u32_e64 v1, v1, v3 clamp1182; GFX9-NEXT:    s_setpc_b64 s[30:31]1183;1184; GFX10PLUS-LABEL: v_uaddsat_v2i32:1185; GFX10PLUS:       ; %bb.0:1186; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1187; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v2 clamp1188; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v3 clamp1189; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]1190  %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1191  ret <2 x i32> %result1192}1193 1194define amdgpu_ps <2 x i32> @s_uaddsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {1195; GFX6-LABEL: s_uaddsat_v2i32:1196; GFX6:       ; %bb.0:1197; GFX6-NEXT:    s_not_b32 s4, s01198; GFX6-NEXT:    s_min_u32 s2, s4, s21199; GFX6-NEXT:    s_add_i32 s0, s0, s21200; GFX6-NEXT:    s_not_b32 s2, s11201; GFX6-NEXT:    s_min_u32 s2, s2, s31202; GFX6-NEXT:    s_add_i32 s1, s1, s21203; GFX6-NEXT:    ; return to shader part epilog1204;1205; GFX8-LABEL: s_uaddsat_v2i32:1206; GFX8:       ; %bb.0:1207; GFX8-NEXT:    v_mov_b32_e32 v0, s21208; GFX8-NEXT:    v_mov_b32_e32 v1, s31209; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], s0, v0 clamp1210; GFX8-NEXT:    v_add_u32_e64 v1, s[0:1], s1, v1 clamp1211; GFX8-NEXT:    v_readfirstlane_b32 s0, v01212; GFX8-NEXT:    v_readfirstlane_b32 s1, v11213; GFX8-NEXT:    ; return to shader part epilog1214;1215; GFX9-LABEL: s_uaddsat_v2i32:1216; GFX9:       ; %bb.0:1217; GFX9-NEXT:    v_mov_b32_e32 v0, s21218; GFX9-NEXT:    v_mov_b32_e32 v1, s31219; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1220; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp1221; GFX9-NEXT:    v_readfirstlane_b32 s0, v01222; GFX9-NEXT:    v_readfirstlane_b32 s1, v11223; GFX9-NEXT:    ; return to shader part epilog1224;1225; GFX10PLUS-LABEL: s_uaddsat_v2i32:1226; GFX10PLUS:       ; %bb.0:1227; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s2 clamp1228; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s3 clamp1229; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01230; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v11231; GFX10PLUS-NEXT:    ; return to shader part epilog1232  %result = call <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1233  ret <2 x i32> %result1234}1235 1236define <3 x i32> @v_uaddsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {1237; GFX6-LABEL: v_uaddsat_v3i32:1238; GFX6:       ; %bb.0:1239; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1240; GFX6-NEXT:    v_not_b32_e32 v6, v01241; GFX6-NEXT:    v_min_u32_e32 v3, v6, v31242; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v31243; GFX6-NEXT:    v_not_b32_e32 v3, v11244; GFX6-NEXT:    v_min_u32_e32 v3, v3, v41245; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v31246; GFX6-NEXT:    v_not_b32_e32 v3, v21247; GFX6-NEXT:    v_min_u32_e32 v3, v3, v51248; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v31249; GFX6-NEXT:    s_setpc_b64 s[30:31]1250;1251; GFX8-LABEL: v_uaddsat_v3i32:1252; GFX8:       ; %bb.0:1253; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1254; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v3 clamp1255; GFX8-NEXT:    v_add_u32_e64 v1, s[4:5], v1, v4 clamp1256; GFX8-NEXT:    v_add_u32_e64 v2, s[4:5], v2, v5 clamp1257; GFX8-NEXT:    s_setpc_b64 s[30:31]1258;1259; GFX9-LABEL: v_uaddsat_v3i32:1260; GFX9:       ; %bb.0:1261; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1262; GFX9-NEXT:    v_add_u32_e64 v0, v0, v3 clamp1263; GFX9-NEXT:    v_add_u32_e64 v1, v1, v4 clamp1264; GFX9-NEXT:    v_add_u32_e64 v2, v2, v5 clamp1265; GFX9-NEXT:    s_setpc_b64 s[30:31]1266;1267; GFX10PLUS-LABEL: v_uaddsat_v3i32:1268; GFX10PLUS:       ; %bb.0:1269; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1270; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v3 clamp1271; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v4 clamp1272; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v5 clamp1273; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]1274  %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1275  ret <3 x i32> %result1276}1277 1278define amdgpu_ps <3 x i32> @s_uaddsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {1279; GFX6-LABEL: s_uaddsat_v3i32:1280; GFX6:       ; %bb.0:1281; GFX6-NEXT:    s_not_b32 s6, s01282; GFX6-NEXT:    s_min_u32 s3, s6, s31283; GFX6-NEXT:    s_add_i32 s0, s0, s31284; GFX6-NEXT:    s_not_b32 s3, s11285; GFX6-NEXT:    s_min_u32 s3, s3, s41286; GFX6-NEXT:    s_add_i32 s1, s1, s31287; GFX6-NEXT:    s_not_b32 s3, s21288; GFX6-NEXT:    s_min_u32 s3, s3, s51289; GFX6-NEXT:    s_add_i32 s2, s2, s31290; GFX6-NEXT:    ; return to shader part epilog1291;1292; GFX8-LABEL: s_uaddsat_v3i32:1293; GFX8:       ; %bb.0:1294; GFX8-NEXT:    v_mov_b32_e32 v0, s31295; GFX8-NEXT:    v_mov_b32_e32 v1, s41296; GFX8-NEXT:    v_mov_b32_e32 v2, s51297; GFX8-NEXT:    v_add_u32_e64 v0, s[6:7], s0, v0 clamp1298; GFX8-NEXT:    v_add_u32_e64 v1, s[0:1], s1, v1 clamp1299; GFX8-NEXT:    v_add_u32_e64 v2, s[0:1], s2, v2 clamp1300; GFX8-NEXT:    v_readfirstlane_b32 s0, v01301; GFX8-NEXT:    v_readfirstlane_b32 s1, v11302; GFX8-NEXT:    v_readfirstlane_b32 s2, v21303; GFX8-NEXT:    ; return to shader part epilog1304;1305; GFX9-LABEL: s_uaddsat_v3i32:1306; GFX9:       ; %bb.0:1307; GFX9-NEXT:    v_mov_b32_e32 v0, s31308; GFX9-NEXT:    v_mov_b32_e32 v1, s41309; GFX9-NEXT:    v_mov_b32_e32 v2, s51310; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1311; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp1312; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp1313; GFX9-NEXT:    v_readfirstlane_b32 s0, v01314; GFX9-NEXT:    v_readfirstlane_b32 s1, v11315; GFX9-NEXT:    v_readfirstlane_b32 s2, v21316; GFX9-NEXT:    ; return to shader part epilog1317;1318; GFX10PLUS-LABEL: s_uaddsat_v3i32:1319; GFX10PLUS:       ; %bb.0:1320; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s3 clamp1321; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s4 clamp1322; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s5 clamp1323; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01324; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v11325; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v21326; GFX10PLUS-NEXT:    ; return to shader part epilog1327  %result = call <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1328  ret <3 x i32> %result1329}1330 1331define <4 x i32> @v_uaddsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {1332; GFX6-LABEL: v_uaddsat_v4i32:1333; GFX6:       ; %bb.0:1334; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1335; GFX6-NEXT:    v_not_b32_e32 v8, v01336; GFX6-NEXT:    v_min_u32_e32 v4, v8, v41337; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v41338; GFX6-NEXT:    v_not_b32_e32 v4, v11339; GFX6-NEXT:    v_min_u32_e32 v4, v4, v51340; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v41341; GFX6-NEXT:    v_not_b32_e32 v4, v21342; GFX6-NEXT:    v_min_u32_e32 v4, v4, v61343; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v41344; GFX6-NEXT:    v_not_b32_e32 v4, v31345; GFX6-NEXT:    v_min_u32_e32 v4, v4, v71346; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v41347; GFX6-NEXT:    s_setpc_b64 s[30:31]1348;1349; GFX8-LABEL: v_uaddsat_v4i32:1350; GFX8:       ; %bb.0:1351; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1352; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v4 clamp1353; GFX8-NEXT:    v_add_u32_e64 v1, s[4:5], v1, v5 clamp1354; GFX8-NEXT:    v_add_u32_e64 v2, s[4:5], v2, v6 clamp1355; GFX8-NEXT:    v_add_u32_e64 v3, s[4:5], v3, v7 clamp1356; GFX8-NEXT:    s_setpc_b64 s[30:31]1357;1358; GFX9-LABEL: v_uaddsat_v4i32:1359; GFX9:       ; %bb.0:1360; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1361; GFX9-NEXT:    v_add_u32_e64 v0, v0, v4 clamp1362; GFX9-NEXT:    v_add_u32_e64 v1, v1, v5 clamp1363; GFX9-NEXT:    v_add_u32_e64 v2, v2, v6 clamp1364; GFX9-NEXT:    v_add_u32_e64 v3, v3, v7 clamp1365; GFX9-NEXT:    s_setpc_b64 s[30:31]1366;1367; GFX10PLUS-LABEL: v_uaddsat_v4i32:1368; GFX10PLUS:       ; %bb.0:1369; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1370; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v4 clamp1371; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v5 clamp1372; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v6 clamp1373; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, v3, v7 clamp1374; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]1375  %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1376  ret <4 x i32> %result1377}1378 1379define amdgpu_ps <4 x i32> @s_uaddsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {1380; GFX6-LABEL: s_uaddsat_v4i32:1381; GFX6:       ; %bb.0:1382; GFX6-NEXT:    s_not_b32 s8, s01383; GFX6-NEXT:    s_min_u32 s4, s8, s41384; GFX6-NEXT:    s_add_i32 s0, s0, s41385; GFX6-NEXT:    s_not_b32 s4, s11386; GFX6-NEXT:    s_min_u32 s4, s4, s51387; GFX6-NEXT:    s_add_i32 s1, s1, s41388; GFX6-NEXT:    s_not_b32 s4, s21389; GFX6-NEXT:    s_min_u32 s4, s4, s61390; GFX6-NEXT:    s_add_i32 s2, s2, s41391; GFX6-NEXT:    s_not_b32 s4, s31392; GFX6-NEXT:    s_min_u32 s4, s4, s71393; GFX6-NEXT:    s_add_i32 s3, s3, s41394; GFX6-NEXT:    ; return to shader part epilog1395;1396; GFX8-LABEL: s_uaddsat_v4i32:1397; GFX8:       ; %bb.0:1398; GFX8-NEXT:    v_mov_b32_e32 v0, s41399; GFX8-NEXT:    v_mov_b32_e32 v1, s51400; GFX8-NEXT:    v_mov_b32_e32 v2, s61401; GFX8-NEXT:    v_mov_b32_e32 v3, s71402; GFX8-NEXT:    v_add_u32_e64 v0, s[8:9], s0, v0 clamp1403; GFX8-NEXT:    v_add_u32_e64 v1, s[0:1], s1, v1 clamp1404; GFX8-NEXT:    v_add_u32_e64 v2, s[0:1], s2, v2 clamp1405; GFX8-NEXT:    v_add_u32_e64 v3, s[0:1], s3, v3 clamp1406; GFX8-NEXT:    v_readfirstlane_b32 s0, v01407; GFX8-NEXT:    v_readfirstlane_b32 s1, v11408; GFX8-NEXT:    v_readfirstlane_b32 s2, v21409; GFX8-NEXT:    v_readfirstlane_b32 s3, v31410; GFX8-NEXT:    ; return to shader part epilog1411;1412; GFX9-LABEL: s_uaddsat_v4i32:1413; GFX9:       ; %bb.0:1414; GFX9-NEXT:    v_mov_b32_e32 v0, s41415; GFX9-NEXT:    v_mov_b32_e32 v1, s51416; GFX9-NEXT:    v_mov_b32_e32 v2, s61417; GFX9-NEXT:    v_mov_b32_e32 v3, s71418; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1419; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp1420; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp1421; GFX9-NEXT:    v_add_u32_e64 v3, s3, v3 clamp1422; GFX9-NEXT:    v_readfirstlane_b32 s0, v01423; GFX9-NEXT:    v_readfirstlane_b32 s1, v11424; GFX9-NEXT:    v_readfirstlane_b32 s2, v21425; GFX9-NEXT:    v_readfirstlane_b32 s3, v31426; GFX9-NEXT:    ; return to shader part epilog1427;1428; GFX10PLUS-LABEL: s_uaddsat_v4i32:1429; GFX10PLUS:       ; %bb.0:1430; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s4 clamp1431; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s5 clamp1432; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s6 clamp1433; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s7 clamp1434; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01435; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v11436; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v21437; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v31438; GFX10PLUS-NEXT:    ; return to shader part epilog1439  %result = call <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1440  ret <4 x i32> %result1441}1442 1443define <5 x i32> @v_uaddsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {1444; GFX6-LABEL: v_uaddsat_v5i32:1445; GFX6:       ; %bb.0:1446; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1447; GFX6-NEXT:    v_not_b32_e32 v10, v01448; GFX6-NEXT:    v_min_u32_e32 v5, v10, v51449; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v51450; GFX6-NEXT:    v_not_b32_e32 v5, v11451; GFX6-NEXT:    v_min_u32_e32 v5, v5, v61452; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v51453; GFX6-NEXT:    v_not_b32_e32 v5, v21454; GFX6-NEXT:    v_min_u32_e32 v5, v5, v71455; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v51456; GFX6-NEXT:    v_not_b32_e32 v5, v31457; GFX6-NEXT:    v_min_u32_e32 v5, v5, v81458; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v51459; GFX6-NEXT:    v_not_b32_e32 v5, v41460; GFX6-NEXT:    v_min_u32_e32 v5, v5, v91461; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v51462; GFX6-NEXT:    s_setpc_b64 s[30:31]1463;1464; GFX8-LABEL: v_uaddsat_v5i32:1465; GFX8:       ; %bb.0:1466; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1467; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v5 clamp1468; GFX8-NEXT:    v_add_u32_e64 v1, s[4:5], v1, v6 clamp1469; GFX8-NEXT:    v_add_u32_e64 v2, s[4:5], v2, v7 clamp1470; GFX8-NEXT:    v_add_u32_e64 v3, s[4:5], v3, v8 clamp1471; GFX8-NEXT:    v_add_u32_e64 v4, s[4:5], v4, v9 clamp1472; GFX8-NEXT:    s_setpc_b64 s[30:31]1473;1474; GFX9-LABEL: v_uaddsat_v5i32:1475; GFX9:       ; %bb.0:1476; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1477; GFX9-NEXT:    v_add_u32_e64 v0, v0, v5 clamp1478; GFX9-NEXT:    v_add_u32_e64 v1, v1, v6 clamp1479; GFX9-NEXT:    v_add_u32_e64 v2, v2, v7 clamp1480; GFX9-NEXT:    v_add_u32_e64 v3, v3, v8 clamp1481; GFX9-NEXT:    v_add_u32_e64 v4, v4, v9 clamp1482; GFX9-NEXT:    s_setpc_b64 s[30:31]1483;1484; GFX10PLUS-LABEL: v_uaddsat_v5i32:1485; GFX10PLUS:       ; %bb.0:1486; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1487; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, v0, v5 clamp1488; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, v1, v6 clamp1489; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, v2, v7 clamp1490; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, v3, v8 clamp1491; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, v4, v9 clamp1492; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]1493  %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1494  ret <5 x i32> %result1495}1496 1497define amdgpu_ps <5 x i32> @s_uaddsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {1498; GFX6-LABEL: s_uaddsat_v5i32:1499; GFX6:       ; %bb.0:1500; GFX6-NEXT:    s_not_b32 s10, s01501; GFX6-NEXT:    s_min_u32 s5, s10, s51502; GFX6-NEXT:    s_add_i32 s0, s0, s51503; GFX6-NEXT:    s_not_b32 s5, s11504; GFX6-NEXT:    s_min_u32 s5, s5, s61505; GFX6-NEXT:    s_add_i32 s1, s1, s51506; GFX6-NEXT:    s_not_b32 s5, s21507; GFX6-NEXT:    s_min_u32 s5, s5, s71508; GFX6-NEXT:    s_add_i32 s2, s2, s51509; GFX6-NEXT:    s_not_b32 s5, s31510; GFX6-NEXT:    s_min_u32 s5, s5, s81511; GFX6-NEXT:    s_add_i32 s3, s3, s51512; GFX6-NEXT:    s_not_b32 s5, s41513; GFX6-NEXT:    s_min_u32 s5, s5, s91514; GFX6-NEXT:    s_add_i32 s4, s4, s51515; GFX6-NEXT:    ; return to shader part epilog1516;1517; GFX8-LABEL: s_uaddsat_v5i32:1518; GFX8:       ; %bb.0:1519; GFX8-NEXT:    v_mov_b32_e32 v0, s51520; GFX8-NEXT:    v_mov_b32_e32 v1, s61521; GFX8-NEXT:    v_mov_b32_e32 v2, s71522; GFX8-NEXT:    v_mov_b32_e32 v3, s81523; GFX8-NEXT:    v_mov_b32_e32 v4, s91524; GFX8-NEXT:    v_add_u32_e64 v0, s[10:11], s0, v0 clamp1525; GFX8-NEXT:    v_add_u32_e64 v1, s[0:1], s1, v1 clamp1526; GFX8-NEXT:    v_add_u32_e64 v2, s[0:1], s2, v2 clamp1527; GFX8-NEXT:    v_add_u32_e64 v3, s[0:1], s3, v3 clamp1528; GFX8-NEXT:    v_add_u32_e64 v4, s[0:1], s4, v4 clamp1529; GFX8-NEXT:    v_readfirstlane_b32 s0, v01530; GFX8-NEXT:    v_readfirstlane_b32 s1, v11531; GFX8-NEXT:    v_readfirstlane_b32 s2, v21532; GFX8-NEXT:    v_readfirstlane_b32 s3, v31533; GFX8-NEXT:    v_readfirstlane_b32 s4, v41534; GFX8-NEXT:    ; return to shader part epilog1535;1536; GFX9-LABEL: s_uaddsat_v5i32:1537; GFX9:       ; %bb.0:1538; GFX9-NEXT:    v_mov_b32_e32 v0, s51539; GFX9-NEXT:    v_mov_b32_e32 v1, s61540; GFX9-NEXT:    v_mov_b32_e32 v2, s71541; GFX9-NEXT:    v_mov_b32_e32 v3, s81542; GFX9-NEXT:    v_mov_b32_e32 v4, s91543; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1544; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp1545; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp1546; GFX9-NEXT:    v_add_u32_e64 v3, s3, v3 clamp1547; GFX9-NEXT:    v_add_u32_e64 v4, s4, v4 clamp1548; GFX9-NEXT:    v_readfirstlane_b32 s0, v01549; GFX9-NEXT:    v_readfirstlane_b32 s1, v11550; GFX9-NEXT:    v_readfirstlane_b32 s2, v21551; GFX9-NEXT:    v_readfirstlane_b32 s3, v31552; GFX9-NEXT:    v_readfirstlane_b32 s4, v41553; GFX9-NEXT:    ; return to shader part epilog1554;1555; GFX10PLUS-LABEL: s_uaddsat_v5i32:1556; GFX10PLUS:       ; %bb.0:1557; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s5 clamp1558; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s6 clamp1559; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s7 clamp1560; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s8 clamp1561; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, s4, s9 clamp1562; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01563; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v11564; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v21565; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v31566; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v41567; GFX10PLUS-NEXT:    ; return to shader part epilog1568  %result = call <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1569  ret <5 x i32> %result1570}1571 1572define <16 x i32> @v_uaddsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {1573; GFX6-LABEL: v_uaddsat_v16i32:1574; GFX6:       ; %bb.0:1575; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1576; GFX6-NEXT:    v_not_b32_e32 v31, v01577; GFX6-NEXT:    v_min_u32_e32 v16, v31, v161578; GFX6-NEXT:    buffer_load_dword v31, off, s[0:3], s321579; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v161580; GFX6-NEXT:    v_not_b32_e32 v16, v11581; GFX6-NEXT:    v_min_u32_e32 v16, v16, v171582; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v161583; GFX6-NEXT:    v_not_b32_e32 v16, v21584; GFX6-NEXT:    v_min_u32_e32 v16, v16, v181585; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v161586; GFX6-NEXT:    v_not_b32_e32 v16, v31587; GFX6-NEXT:    v_min_u32_e32 v16, v16, v191588; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v161589; GFX6-NEXT:    v_not_b32_e32 v16, v41590; GFX6-NEXT:    v_min_u32_e32 v16, v16, v201591; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v161592; GFX6-NEXT:    v_not_b32_e32 v16, v51593; GFX6-NEXT:    v_min_u32_e32 v16, v16, v211594; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v161595; GFX6-NEXT:    v_not_b32_e32 v16, v61596; GFX6-NEXT:    v_min_u32_e32 v16, v16, v221597; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v161598; GFX6-NEXT:    v_not_b32_e32 v16, v71599; GFX6-NEXT:    v_min_u32_e32 v16, v16, v231600; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v161601; GFX6-NEXT:    v_not_b32_e32 v16, v81602; GFX6-NEXT:    v_min_u32_e32 v16, v16, v241603; GFX6-NEXT:    v_add_i32_e32 v8, vcc, v8, v161604; GFX6-NEXT:    v_not_b32_e32 v16, v91605; GFX6-NEXT:    v_min_u32_e32 v16, v16, v251606; GFX6-NEXT:    v_add_i32_e32 v9, vcc, v9, v161607; GFX6-NEXT:    v_not_b32_e32 v16, v101608; GFX6-NEXT:    v_min_u32_e32 v16, v16, v261609; GFX6-NEXT:    v_add_i32_e32 v10, vcc, v10, v161610; GFX6-NEXT:    v_not_b32_e32 v16, v111611; GFX6-NEXT:    v_min_u32_e32 v16, v16, v271612; GFX6-NEXT:    v_add_i32_e32 v11, vcc, v11, v161613; GFX6-NEXT:    v_not_b32_e32 v16, v121614; GFX6-NEXT:    v_min_u32_e32 v16, v16, v281615; GFX6-NEXT:    v_add_i32_e32 v12, vcc, v12, v161616; GFX6-NEXT:    v_not_b32_e32 v16, v131617; GFX6-NEXT:    v_min_u32_e32 v16, v16, v291618; GFX6-NEXT:    v_add_i32_e32 v13, vcc, v13, v161619; GFX6-NEXT:    v_not_b32_e32 v16, v141620; GFX6-NEXT:    v_min_u32_e32 v16, v16, v301621; GFX6-NEXT:    v_add_i32_e32 v14, vcc, v14, v161622; GFX6-NEXT:    v_not_b32_e32 v16, v151623; GFX6-NEXT:    s_waitcnt vmcnt(0)1624; GFX6-NEXT:    v_min_u32_e32 v16, v16, v311625; GFX6-NEXT:    v_add_i32_e32 v15, vcc, v15, v161626; GFX6-NEXT:    s_setpc_b64 s[30:31]1627;1628; GFX8-LABEL: v_uaddsat_v16i32:1629; GFX8:       ; %bb.0:1630; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1631; GFX8-NEXT:    v_add_u32_e64 v0, s[4:5], v0, v16 clamp1632; GFX8-NEXT:    buffer_load_dword v16, off, s[0:3], s321633; GFX8-NEXT:    v_add_u32_e64 v1, s[4:5], v1, v17 clamp1634; GFX8-NEXT:    v_add_u32_e64 v2, s[4:5], v2, v18 clamp1635; GFX8-NEXT:    v_add_u32_e64 v3, s[4:5], v3, v19 clamp1636; GFX8-NEXT:    v_add_u32_e64 v4, s[4:5], v4, v20 clamp1637; GFX8-NEXT:    v_add_u32_e64 v5, s[4:5], v5, v21 clamp1638; GFX8-NEXT:    v_add_u32_e64 v6, s[4:5], v6, v22 clamp1639; GFX8-NEXT:    v_add_u32_e64 v7, s[4:5], v7, v23 clamp1640; GFX8-NEXT:    v_add_u32_e64 v8, s[4:5], v8, v24 clamp1641; GFX8-NEXT:    v_add_u32_e64 v9, s[4:5], v9, v25 clamp1642; GFX8-NEXT:    v_add_u32_e64 v10, s[4:5], v10, v26 clamp1643; GFX8-NEXT:    v_add_u32_e64 v11, s[4:5], v11, v27 clamp1644; GFX8-NEXT:    v_add_u32_e64 v12, s[4:5], v12, v28 clamp1645; GFX8-NEXT:    v_add_u32_e64 v13, s[4:5], v13, v29 clamp1646; GFX8-NEXT:    v_add_u32_e64 v14, s[4:5], v14, v30 clamp1647; GFX8-NEXT:    s_waitcnt vmcnt(0)1648; GFX8-NEXT:    v_add_u32_e64 v15, s[4:5], v15, v16 clamp1649; GFX8-NEXT:    s_setpc_b64 s[30:31]1650;1651; GFX9-LABEL: v_uaddsat_v16i32:1652; GFX9:       ; %bb.0:1653; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1654; GFX9-NEXT:    v_add_u32_e64 v0, v0, v16 clamp1655; GFX9-NEXT:    buffer_load_dword v16, off, s[0:3], s321656; GFX9-NEXT:    v_add_u32_e64 v1, v1, v17 clamp1657; GFX9-NEXT:    v_add_u32_e64 v2, v2, v18 clamp1658; GFX9-NEXT:    v_add_u32_e64 v3, v3, v19 clamp1659; GFX9-NEXT:    v_add_u32_e64 v4, v4, v20 clamp1660; GFX9-NEXT:    v_add_u32_e64 v5, v5, v21 clamp1661; GFX9-NEXT:    v_add_u32_e64 v6, v6, v22 clamp1662; GFX9-NEXT:    v_add_u32_e64 v7, v7, v23 clamp1663; GFX9-NEXT:    v_add_u32_e64 v8, v8, v24 clamp1664; GFX9-NEXT:    v_add_u32_e64 v9, v9, v25 clamp1665; GFX9-NEXT:    v_add_u32_e64 v10, v10, v26 clamp1666; GFX9-NEXT:    v_add_u32_e64 v11, v11, v27 clamp1667; GFX9-NEXT:    v_add_u32_e64 v12, v12, v28 clamp1668; GFX9-NEXT:    v_add_u32_e64 v13, v13, v29 clamp1669; GFX9-NEXT:    v_add_u32_e64 v14, v14, v30 clamp1670; GFX9-NEXT:    s_waitcnt vmcnt(0)1671; GFX9-NEXT:    v_add_u32_e64 v15, v15, v16 clamp1672; GFX9-NEXT:    s_setpc_b64 s[30:31]1673;1674; GFX10-LABEL: v_uaddsat_v16i32:1675; GFX10:       ; %bb.0:1676; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1677; GFX10-NEXT:    buffer_load_dword v31, off, s[0:3], s321678; GFX10-NEXT:    v_add_nc_u32_e64 v0, v0, v16 clamp1679; GFX10-NEXT:    v_add_nc_u32_e64 v1, v1, v17 clamp1680; GFX10-NEXT:    v_add_nc_u32_e64 v2, v2, v18 clamp1681; GFX10-NEXT:    v_add_nc_u32_e64 v3, v3, v19 clamp1682; GFX10-NEXT:    v_add_nc_u32_e64 v4, v4, v20 clamp1683; GFX10-NEXT:    v_add_nc_u32_e64 v5, v5, v21 clamp1684; GFX10-NEXT:    v_add_nc_u32_e64 v6, v6, v22 clamp1685; GFX10-NEXT:    v_add_nc_u32_e64 v7, v7, v23 clamp1686; GFX10-NEXT:    v_add_nc_u32_e64 v8, v8, v24 clamp1687; GFX10-NEXT:    v_add_nc_u32_e64 v9, v9, v25 clamp1688; GFX10-NEXT:    v_add_nc_u32_e64 v10, v10, v26 clamp1689; GFX10-NEXT:    v_add_nc_u32_e64 v11, v11, v27 clamp1690; GFX10-NEXT:    v_add_nc_u32_e64 v12, v12, v28 clamp1691; GFX10-NEXT:    v_add_nc_u32_e64 v13, v13, v29 clamp1692; GFX10-NEXT:    v_add_nc_u32_e64 v14, v14, v30 clamp1693; GFX10-NEXT:    s_waitcnt vmcnt(0)1694; GFX10-NEXT:    v_add_nc_u32_e64 v15, v15, v31 clamp1695; GFX10-NEXT:    s_setpc_b64 s[30:31]1696;1697; GFX11-LABEL: v_uaddsat_v16i32:1698; GFX11:       ; %bb.0:1699; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1700; GFX11-NEXT:    scratch_load_b32 v31, off, s321701; GFX11-NEXT:    v_add_nc_u32_e64 v0, v0, v16 clamp1702; GFX11-NEXT:    v_add_nc_u32_e64 v1, v1, v17 clamp1703; GFX11-NEXT:    v_add_nc_u32_e64 v2, v2, v18 clamp1704; GFX11-NEXT:    v_add_nc_u32_e64 v3, v3, v19 clamp1705; GFX11-NEXT:    v_add_nc_u32_e64 v4, v4, v20 clamp1706; GFX11-NEXT:    v_add_nc_u32_e64 v5, v5, v21 clamp1707; GFX11-NEXT:    v_add_nc_u32_e64 v6, v6, v22 clamp1708; GFX11-NEXT:    v_add_nc_u32_e64 v7, v7, v23 clamp1709; GFX11-NEXT:    v_add_nc_u32_e64 v8, v8, v24 clamp1710; GFX11-NEXT:    v_add_nc_u32_e64 v9, v9, v25 clamp1711; GFX11-NEXT:    v_add_nc_u32_e64 v10, v10, v26 clamp1712; GFX11-NEXT:    v_add_nc_u32_e64 v11, v11, v27 clamp1713; GFX11-NEXT:    v_add_nc_u32_e64 v12, v12, v28 clamp1714; GFX11-NEXT:    v_add_nc_u32_e64 v13, v13, v29 clamp1715; GFX11-NEXT:    v_add_nc_u32_e64 v14, v14, v30 clamp1716; GFX11-NEXT:    s_waitcnt vmcnt(0)1717; GFX11-NEXT:    v_add_nc_u32_e64 v15, v15, v31 clamp1718; GFX11-NEXT:    s_setpc_b64 s[30:31]1719  %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)1720  ret <16 x i32> %result1721}1722 1723define amdgpu_ps <16 x i32> @s_uaddsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {1724; GFX6-LABEL: s_uaddsat_v16i32:1725; GFX6:       ; %bb.0:1726; GFX6-NEXT:    s_not_b32 s32, s01727; GFX6-NEXT:    s_min_u32 s16, s32, s161728; GFX6-NEXT:    s_add_i32 s0, s0, s161729; GFX6-NEXT:    s_not_b32 s16, s11730; GFX6-NEXT:    s_min_u32 s16, s16, s171731; GFX6-NEXT:    s_add_i32 s1, s1, s161732; GFX6-NEXT:    s_not_b32 s16, s21733; GFX6-NEXT:    s_min_u32 s16, s16, s181734; GFX6-NEXT:    s_add_i32 s2, s2, s161735; GFX6-NEXT:    s_not_b32 s16, s31736; GFX6-NEXT:    s_min_u32 s16, s16, s191737; GFX6-NEXT:    s_add_i32 s3, s3, s161738; GFX6-NEXT:    s_not_b32 s16, s41739; GFX6-NEXT:    s_min_u32 s16, s16, s201740; GFX6-NEXT:    s_add_i32 s4, s4, s161741; GFX6-NEXT:    s_not_b32 s16, s51742; GFX6-NEXT:    s_min_u32 s16, s16, s211743; GFX6-NEXT:    s_add_i32 s5, s5, s161744; GFX6-NEXT:    s_not_b32 s16, s61745; GFX6-NEXT:    s_min_u32 s16, s16, s221746; GFX6-NEXT:    s_add_i32 s6, s6, s161747; GFX6-NEXT:    s_not_b32 s16, s71748; GFX6-NEXT:    s_min_u32 s16, s16, s231749; GFX6-NEXT:    s_add_i32 s7, s7, s161750; GFX6-NEXT:    s_not_b32 s16, s81751; GFX6-NEXT:    s_min_u32 s16, s16, s241752; GFX6-NEXT:    s_add_i32 s8, s8, s161753; GFX6-NEXT:    s_not_b32 s16, s91754; GFX6-NEXT:    s_min_u32 s16, s16, s251755; GFX6-NEXT:    s_add_i32 s9, s9, s161756; GFX6-NEXT:    s_not_b32 s16, s101757; GFX6-NEXT:    s_min_u32 s16, s16, s261758; GFX6-NEXT:    s_add_i32 s10, s10, s161759; GFX6-NEXT:    s_not_b32 s16, s111760; GFX6-NEXT:    s_min_u32 s16, s16, s271761; GFX6-NEXT:    s_add_i32 s11, s11, s161762; GFX6-NEXT:    s_not_b32 s16, s121763; GFX6-NEXT:    s_min_u32 s16, s16, s281764; GFX6-NEXT:    s_add_i32 s12, s12, s161765; GFX6-NEXT:    s_not_b32 s16, s131766; GFX6-NEXT:    s_min_u32 s16, s16, s291767; GFX6-NEXT:    s_add_i32 s13, s13, s161768; GFX6-NEXT:    s_not_b32 s16, s141769; GFX6-NEXT:    s_min_u32 s16, s16, s301770; GFX6-NEXT:    s_add_i32 s14, s14, s161771; GFX6-NEXT:    s_not_b32 s16, s151772; GFX6-NEXT:    s_min_u32 s16, s16, s311773; GFX6-NEXT:    s_add_i32 s15, s15, s161774; GFX6-NEXT:    ; return to shader part epilog1775;1776; GFX8-LABEL: s_uaddsat_v16i32:1777; GFX8:       ; %bb.0:1778; GFX8-NEXT:    v_mov_b32_e32 v0, s161779; GFX8-NEXT:    v_mov_b32_e32 v1, s171780; GFX8-NEXT:    v_mov_b32_e32 v2, s181781; GFX8-NEXT:    v_mov_b32_e32 v3, s191782; GFX8-NEXT:    v_mov_b32_e32 v4, s201783; GFX8-NEXT:    v_mov_b32_e32 v5, s211784; GFX8-NEXT:    v_mov_b32_e32 v6, s221785; GFX8-NEXT:    v_mov_b32_e32 v7, s231786; GFX8-NEXT:    v_mov_b32_e32 v8, s241787; GFX8-NEXT:    v_mov_b32_e32 v9, s251788; GFX8-NEXT:    v_mov_b32_e32 v10, s261789; GFX8-NEXT:    v_mov_b32_e32 v11, s271790; GFX8-NEXT:    v_mov_b32_e32 v12, s281791; GFX8-NEXT:    v_mov_b32_e32 v13, s291792; GFX8-NEXT:    v_mov_b32_e32 v14, s301793; GFX8-NEXT:    v_mov_b32_e32 v15, s311794; GFX8-NEXT:    v_add_u32_e64 v0, s[32:33], s0, v0 clamp1795; GFX8-NEXT:    v_add_u32_e64 v1, s[16:17], s1, v1 clamp1796; GFX8-NEXT:    v_add_u32_e64 v2, s[16:17], s2, v2 clamp1797; GFX8-NEXT:    v_add_u32_e64 v3, s[2:3], s3, v3 clamp1798; GFX8-NEXT:    v_add_u32_e64 v4, s[2:3], s4, v4 clamp1799; GFX8-NEXT:    v_add_u32_e64 v5, s[2:3], s5, v5 clamp1800; GFX8-NEXT:    v_add_u32_e64 v6, s[2:3], s6, v6 clamp1801; GFX8-NEXT:    v_add_u32_e64 v7, s[2:3], s7, v7 clamp1802; GFX8-NEXT:    v_add_u32_e64 v8, s[2:3], s8, v8 clamp1803; GFX8-NEXT:    v_add_u32_e64 v9, s[2:3], s9, v9 clamp1804; GFX8-NEXT:    v_add_u32_e64 v10, s[2:3], s10, v10 clamp1805; GFX8-NEXT:    v_add_u32_e64 v11, s[2:3], s11, v11 clamp1806; GFX8-NEXT:    v_add_u32_e64 v12, s[2:3], s12, v12 clamp1807; GFX8-NEXT:    v_add_u32_e64 v13, s[2:3], s13, v13 clamp1808; GFX8-NEXT:    v_add_u32_e64 v14, s[2:3], s14, v14 clamp1809; GFX8-NEXT:    v_add_u32_e64 v15, s[2:3], s15, v15 clamp1810; GFX8-NEXT:    v_readfirstlane_b32 s0, v01811; GFX8-NEXT:    v_readfirstlane_b32 s1, v11812; GFX8-NEXT:    v_readfirstlane_b32 s2, v21813; GFX8-NEXT:    v_readfirstlane_b32 s3, v31814; GFX8-NEXT:    v_readfirstlane_b32 s4, v41815; GFX8-NEXT:    v_readfirstlane_b32 s5, v51816; GFX8-NEXT:    v_readfirstlane_b32 s6, v61817; GFX8-NEXT:    v_readfirstlane_b32 s7, v71818; GFX8-NEXT:    v_readfirstlane_b32 s8, v81819; GFX8-NEXT:    v_readfirstlane_b32 s9, v91820; GFX8-NEXT:    v_readfirstlane_b32 s10, v101821; GFX8-NEXT:    v_readfirstlane_b32 s11, v111822; GFX8-NEXT:    v_readfirstlane_b32 s12, v121823; GFX8-NEXT:    v_readfirstlane_b32 s13, v131824; GFX8-NEXT:    v_readfirstlane_b32 s14, v141825; GFX8-NEXT:    v_readfirstlane_b32 s15, v151826; GFX8-NEXT:    ; return to shader part epilog1827;1828; GFX9-LABEL: s_uaddsat_v16i32:1829; GFX9:       ; %bb.0:1830; GFX9-NEXT:    v_mov_b32_e32 v0, s161831; GFX9-NEXT:    v_mov_b32_e32 v1, s171832; GFX9-NEXT:    v_mov_b32_e32 v2, s181833; GFX9-NEXT:    v_mov_b32_e32 v3, s191834; GFX9-NEXT:    v_mov_b32_e32 v4, s201835; GFX9-NEXT:    v_mov_b32_e32 v5, s211836; GFX9-NEXT:    v_mov_b32_e32 v6, s221837; GFX9-NEXT:    v_mov_b32_e32 v7, s231838; GFX9-NEXT:    v_mov_b32_e32 v8, s241839; GFX9-NEXT:    v_mov_b32_e32 v9, s251840; GFX9-NEXT:    v_mov_b32_e32 v10, s261841; GFX9-NEXT:    v_mov_b32_e32 v11, s271842; GFX9-NEXT:    v_mov_b32_e32 v12, s281843; GFX9-NEXT:    v_mov_b32_e32 v13, s291844; GFX9-NEXT:    v_mov_b32_e32 v14, s301845; GFX9-NEXT:    v_mov_b32_e32 v15, s311846; GFX9-NEXT:    v_add_u32_e64 v0, s0, v0 clamp1847; GFX9-NEXT:    v_add_u32_e64 v1, s1, v1 clamp1848; GFX9-NEXT:    v_add_u32_e64 v2, s2, v2 clamp1849; GFX9-NEXT:    v_add_u32_e64 v3, s3, v3 clamp1850; GFX9-NEXT:    v_add_u32_e64 v4, s4, v4 clamp1851; GFX9-NEXT:    v_add_u32_e64 v5, s5, v5 clamp1852; GFX9-NEXT:    v_add_u32_e64 v6, s6, v6 clamp1853; GFX9-NEXT:    v_add_u32_e64 v7, s7, v7 clamp1854; GFX9-NEXT:    v_add_u32_e64 v8, s8, v8 clamp1855; GFX9-NEXT:    v_add_u32_e64 v9, s9, v9 clamp1856; GFX9-NEXT:    v_add_u32_e64 v10, s10, v10 clamp1857; GFX9-NEXT:    v_add_u32_e64 v11, s11, v11 clamp1858; GFX9-NEXT:    v_add_u32_e64 v12, s12, v12 clamp1859; GFX9-NEXT:    v_add_u32_e64 v13, s13, v13 clamp1860; GFX9-NEXT:    v_add_u32_e64 v14, s14, v14 clamp1861; GFX9-NEXT:    v_add_u32_e64 v15, s15, v15 clamp1862; GFX9-NEXT:    v_readfirstlane_b32 s0, v01863; GFX9-NEXT:    v_readfirstlane_b32 s1, v11864; GFX9-NEXT:    v_readfirstlane_b32 s2, v21865; GFX9-NEXT:    v_readfirstlane_b32 s3, v31866; GFX9-NEXT:    v_readfirstlane_b32 s4, v41867; GFX9-NEXT:    v_readfirstlane_b32 s5, v51868; GFX9-NEXT:    v_readfirstlane_b32 s6, v61869; GFX9-NEXT:    v_readfirstlane_b32 s7, v71870; GFX9-NEXT:    v_readfirstlane_b32 s8, v81871; GFX9-NEXT:    v_readfirstlane_b32 s9, v91872; GFX9-NEXT:    v_readfirstlane_b32 s10, v101873; GFX9-NEXT:    v_readfirstlane_b32 s11, v111874; GFX9-NEXT:    v_readfirstlane_b32 s12, v121875; GFX9-NEXT:    v_readfirstlane_b32 s13, v131876; GFX9-NEXT:    v_readfirstlane_b32 s14, v141877; GFX9-NEXT:    v_readfirstlane_b32 s15, v151878; GFX9-NEXT:    ; return to shader part epilog1879;1880; GFX10PLUS-LABEL: s_uaddsat_v16i32:1881; GFX10PLUS:       ; %bb.0:1882; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v0, s0, s16 clamp1883; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v1, s1, s17 clamp1884; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v2, s2, s18 clamp1885; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v3, s3, s19 clamp1886; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v4, s4, s20 clamp1887; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v5, s5, s21 clamp1888; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v6, s6, s22 clamp1889; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v7, s7, s23 clamp1890; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v8, s8, s24 clamp1891; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v9, s9, s25 clamp1892; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v10, s10, s26 clamp1893; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v11, s11, s27 clamp1894; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v12, s12, s28 clamp1895; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v13, s13, s29 clamp1896; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v14, s14, s30 clamp1897; GFX10PLUS-NEXT:    v_add_nc_u32_e64 v15, s15, s31 clamp1898; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v01899; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v11900; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v21901; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v31902; GFX10PLUS-NEXT:    v_readfirstlane_b32 s4, v41903; GFX10PLUS-NEXT:    v_readfirstlane_b32 s5, v51904; GFX10PLUS-NEXT:    v_readfirstlane_b32 s6, v61905; GFX10PLUS-NEXT:    v_readfirstlane_b32 s7, v71906; GFX10PLUS-NEXT:    v_readfirstlane_b32 s8, v81907; GFX10PLUS-NEXT:    v_readfirstlane_b32 s9, v91908; GFX10PLUS-NEXT:    v_readfirstlane_b32 s10, v101909; GFX10PLUS-NEXT:    v_readfirstlane_b32 s11, v111910; GFX10PLUS-NEXT:    v_readfirstlane_b32 s12, v121911; GFX10PLUS-NEXT:    v_readfirstlane_b32 s13, v131912; GFX10PLUS-NEXT:    v_readfirstlane_b32 s14, v141913; GFX10PLUS-NEXT:    v_readfirstlane_b32 s15, v151914; GFX10PLUS-NEXT:    ; return to shader part epilog1915  %result = call <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)1916  ret <16 x i32> %result1917}1918 1919define i16 @v_uaddsat_i16(i16 %lhs, i16 %rhs) {1920; GFX6-LABEL: v_uaddsat_i16:1921; GFX6:       ; %bb.0:1922; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1923; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v01924; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v11925; GFX6-NEXT:    v_not_b32_e32 v2, v01926; GFX6-NEXT:    v_min_u32_e32 v1, v2, v11927; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v11928; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v01929; GFX6-NEXT:    s_setpc_b64 s[30:31]1930;1931; GFX8-LABEL: v_uaddsat_i16:1932; GFX8:       ; %bb.0:1933; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1934; GFX8-NEXT:    v_add_u16_e64 v0, v0, v1 clamp1935; GFX8-NEXT:    s_setpc_b64 s[30:31]1936;1937; GFX9-LABEL: v_uaddsat_i16:1938; GFX9:       ; %bb.0:1939; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1940; GFX9-NEXT:    v_add_u16_e64 v0, v0, v1 clamp1941; GFX9-NEXT:    s_setpc_b64 s[30:31]1942;1943; GFX10-LABEL: v_uaddsat_i16:1944; GFX10:       ; %bb.0:1945; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1946; GFX10-NEXT:    v_add_nc_u16 v0, v0, v1 clamp1947; GFX10-NEXT:    s_setpc_b64 s[30:31]1948;1949; GFX11-TRUE16-LABEL: v_uaddsat_i16:1950; GFX11-TRUE16:       ; %bb.0:1951; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1952; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, v1.l clamp1953; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1954;1955; GFX11-FAKE16-LABEL: v_uaddsat_i16:1956; GFX11-FAKE16:       ; %bb.0:1957; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1958; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, v1 clamp1959; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1960  %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)1961  ret i16 %result1962}1963 1964define amdgpu_ps i16 @s_uaddsat_i16(i16 inreg %lhs, i16 inreg %rhs) {1965; GFX6-LABEL: s_uaddsat_i16:1966; GFX6:       ; %bb.0:1967; GFX6-NEXT:    s_lshl_b32 s0, s0, 161968; GFX6-NEXT:    s_lshl_b32 s1, s1, 161969; GFX6-NEXT:    s_not_b32 s2, s01970; GFX6-NEXT:    s_min_u32 s1, s2, s11971; GFX6-NEXT:    s_add_i32 s0, s0, s11972; GFX6-NEXT:    s_lshr_b32 s0, s0, 161973; GFX6-NEXT:    ; return to shader part epilog1974;1975; GFX8-LABEL: s_uaddsat_i16:1976; GFX8:       ; %bb.0:1977; GFX8-NEXT:    v_mov_b32_e32 v0, s11978; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp1979; GFX8-NEXT:    v_readfirstlane_b32 s0, v01980; GFX8-NEXT:    ; return to shader part epilog1981;1982; GFX9-LABEL: s_uaddsat_i16:1983; GFX9:       ; %bb.0:1984; GFX9-NEXT:    v_mov_b32_e32 v0, s11985; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp1986; GFX9-NEXT:    v_readfirstlane_b32 s0, v01987; GFX9-NEXT:    ; return to shader part epilog1988;1989; GFX10-LABEL: s_uaddsat_i16:1990; GFX10:       ; %bb.0:1991; GFX10-NEXT:    v_add_nc_u16 v0, s0, s1 clamp1992; GFX10-NEXT:    v_readfirstlane_b32 s0, v01993; GFX10-NEXT:    ; return to shader part epilog1994;1995; GFX11-TRUE16-LABEL: s_uaddsat_i16:1996; GFX11-TRUE16:       ; %bb.0:1997; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, s0, s1 clamp1998; GFX11-TRUE16-NEXT:    v_readfirstlane_b32 s0, v01999; GFX11-TRUE16-NEXT:    ; return to shader part epilog2000;2001; GFX11-FAKE16-LABEL: s_uaddsat_i16:2002; GFX11-FAKE16:       ; %bb.0:2003; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, s0, s1 clamp2004; GFX11-FAKE16-NEXT:    v_readfirstlane_b32 s0, v02005; GFX11-FAKE16-NEXT:    ; return to shader part epilog2006  %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)2007  ret i16 %result2008}2009 2010define amdgpu_ps half @uaddsat_i16_sv(i16 inreg %lhs, i16 %rhs) {2011; GFX6-LABEL: uaddsat_i16_sv:2012; GFX6:       ; %bb.0:2013; GFX6-NEXT:    s_lshl_b32 s0, s0, 162014; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02015; GFX6-NEXT:    s_not_b32 s1, s02016; GFX6-NEXT:    v_min_u32_e32 v0, s1, v02017; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v02018; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v02019; GFX6-NEXT:    ; return to shader part epilog2020;2021; GFX8-LABEL: uaddsat_i16_sv:2022; GFX8:       ; %bb.0:2023; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2024; GFX8-NEXT:    ; return to shader part epilog2025;2026; GFX9-LABEL: uaddsat_i16_sv:2027; GFX9:       ; %bb.0:2028; GFX9-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2029; GFX9-NEXT:    ; return to shader part epilog2030;2031; GFX10-LABEL: uaddsat_i16_sv:2032; GFX10:       ; %bb.0:2033; GFX10-NEXT:    v_add_nc_u16 v0, s0, v0 clamp2034; GFX10-NEXT:    ; return to shader part epilog2035;2036; GFX11-TRUE16-LABEL: uaddsat_i16_sv:2037; GFX11-TRUE16:       ; %bb.0:2038; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, s0, v0.l clamp2039; GFX11-TRUE16-NEXT:    ; return to shader part epilog2040;2041; GFX11-FAKE16-LABEL: uaddsat_i16_sv:2042; GFX11-FAKE16:       ; %bb.0:2043; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, s0, v0 clamp2044; GFX11-FAKE16-NEXT:    ; return to shader part epilog2045  %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)2046  %cast = bitcast i16 %result to half2047  ret half %cast2048}2049 2050define amdgpu_ps half @uaddsat_i16_vs(i16 %lhs, i16 inreg %rhs) {2051; GFX6-LABEL: uaddsat_i16_vs:2052; GFX6:       ; %bb.0:2053; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02054; GFX6-NEXT:    s_lshl_b32 s0, s0, 162055; GFX6-NEXT:    v_not_b32_e32 v1, v02056; GFX6-NEXT:    v_min_u32_e32 v1, s0, v12057; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v12058; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v02059; GFX6-NEXT:    ; return to shader part epilog2060;2061; GFX8-LABEL: uaddsat_i16_vs:2062; GFX8:       ; %bb.0:2063; GFX8-NEXT:    v_add_u16_e64 v0, v0, s0 clamp2064; GFX8-NEXT:    ; return to shader part epilog2065;2066; GFX9-LABEL: uaddsat_i16_vs:2067; GFX9:       ; %bb.0:2068; GFX9-NEXT:    v_add_u16_e64 v0, v0, s0 clamp2069; GFX9-NEXT:    ; return to shader part epilog2070;2071; GFX10-LABEL: uaddsat_i16_vs:2072; GFX10:       ; %bb.0:2073; GFX10-NEXT:    v_add_nc_u16 v0, v0, s0 clamp2074; GFX10-NEXT:    ; return to shader part epilog2075;2076; GFX11-TRUE16-LABEL: uaddsat_i16_vs:2077; GFX11-TRUE16:       ; %bb.0:2078; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v0.l, s0 clamp2079; GFX11-TRUE16-NEXT:    ; return to shader part epilog2080;2081; GFX11-FAKE16-LABEL: uaddsat_i16_vs:2082; GFX11-FAKE16:       ; %bb.0:2083; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v0, s0 clamp2084; GFX11-FAKE16-NEXT:    ; return to shader part epilog2085  %result = call i16 @llvm.uadd.sat.i16(i16 %lhs, i16 %rhs)2086  %cast = bitcast i16 %result to half2087  ret half %cast2088}2089 2090define <2 x i16> @v_uaddsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {2091; GFX6-LABEL: v_uaddsat_v2i16:2092; GFX6:       ; %bb.0:2093; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2094; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02095; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v22096; GFX6-NEXT:    v_not_b32_e32 v4, v02097; GFX6-NEXT:    v_min_u32_e32 v2, v4, v22098; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12099; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v22100; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v32101; GFX6-NEXT:    v_not_b32_e32 v3, v12102; GFX6-NEXT:    v_min_u32_e32 v2, v3, v22103; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v22104; GFX6-NEXT:    v_lshrrev_b32_e32 v0, 16, v02105; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12106; GFX6-NEXT:    s_setpc_b64 s[30:31]2107;2108; GFX8-LABEL: v_uaddsat_v2i16:2109; GFX8:       ; %bb.0:2110; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2111; GFX8-NEXT:    v_add_u16_e64 v2, v0, v1 clamp2112; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12113; GFX8-NEXT:    v_or_b32_e32 v0, v2, v02114; GFX8-NEXT:    s_setpc_b64 s[30:31]2115;2116; GFX9-LABEL: v_uaddsat_v2i16:2117; GFX9:       ; %bb.0:2118; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2119; GFX9-NEXT:    v_pk_add_u16 v0, v0, v1 clamp2120; GFX9-NEXT:    s_setpc_b64 s[30:31]2121;2122; GFX10PLUS-LABEL: v_uaddsat_v2i16:2123; GFX10PLUS:       ; %bb.0:2124; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2125; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v1 clamp2126; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]2127  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2128  ret <2 x i16> %result2129}2130 2131define amdgpu_ps i32 @s_uaddsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {2132; GFX6-LABEL: s_uaddsat_v2i16:2133; GFX6:       ; %bb.0:2134; GFX6-NEXT:    s_lshl_b32 s0, s0, 162135; GFX6-NEXT:    s_lshl_b32 s2, s2, 162136; GFX6-NEXT:    s_not_b32 s4, s02137; GFX6-NEXT:    s_min_u32 s2, s4, s22138; GFX6-NEXT:    s_lshl_b32 s1, s1, 162139; GFX6-NEXT:    s_add_i32 s0, s0, s22140; GFX6-NEXT:    s_lshl_b32 s2, s3, 162141; GFX6-NEXT:    s_not_b32 s3, s12142; GFX6-NEXT:    s_min_u32 s2, s3, s22143; GFX6-NEXT:    s_add_i32 s1, s1, s22144; GFX6-NEXT:    s_lshr_b32 s1, s1, 162145; GFX6-NEXT:    v_mov_b32_e32 v0, s02146; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 162147; GFX6-NEXT:    v_readfirstlane_b32 s0, v02148; GFX6-NEXT:    ; return to shader part epilog2149;2150; GFX8-LABEL: s_uaddsat_v2i16:2151; GFX8:       ; %bb.0:2152; GFX8-NEXT:    s_lshr_b32 s2, s0, 162153; GFX8-NEXT:    s_lshr_b32 s3, s1, 162154; GFX8-NEXT:    v_mov_b32_e32 v0, s12155; GFX8-NEXT:    v_mov_b32_e32 v1, s32156; GFX8-NEXT:    v_mov_b32_e32 v2, s22157; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2158; GFX8-NEXT:    v_add_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2159; GFX8-NEXT:    v_or_b32_e32 v0, v0, v12160; GFX8-NEXT:    v_readfirstlane_b32 s0, v02161; GFX8-NEXT:    ; return to shader part epilog2162;2163; GFX9-LABEL: s_uaddsat_v2i16:2164; GFX9:       ; %bb.0:2165; GFX9-NEXT:    v_mov_b32_e32 v0, s12166; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2167; GFX9-NEXT:    v_readfirstlane_b32 s0, v02168; GFX9-NEXT:    ; return to shader part epilog2169;2170; GFX10PLUS-LABEL: s_uaddsat_v2i16:2171; GFX10PLUS:       ; %bb.0:2172; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s1 clamp2173; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v02174; GFX10PLUS-NEXT:    ; return to shader part epilog2175  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2176  %cast = bitcast <2 x i16> %result to i322177  ret i32 %cast2178}2179 2180define amdgpu_ps float @uaddsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {2181; GFX6-LABEL: uaddsat_v2i16_sv:2182; GFX6:       ; %bb.0:2183; GFX6-NEXT:    s_lshl_b32 s0, s0, 162184; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02185; GFX6-NEXT:    s_not_b32 s2, s02186; GFX6-NEXT:    v_min_u32_e32 v0, s2, v02187; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v02188; GFX6-NEXT:    s_lshl_b32 s0, s1, 162189; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12190; GFX6-NEXT:    s_not_b32 s1, s02191; GFX6-NEXT:    v_min_u32_e32 v1, s1, v12192; GFX6-NEXT:    v_add_i32_e32 v1, vcc, s0, v12193; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12194; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 162195; GFX6-NEXT:    ; return to shader part epilog2196;2197; GFX8-LABEL: uaddsat_v2i16_sv:2198; GFX8:       ; %bb.0:2199; GFX8-NEXT:    s_lshr_b32 s1, s0, 162200; GFX8-NEXT:    v_mov_b32_e32 v2, s12201; GFX8-NEXT:    v_add_u16_e64 v1, s0, v0 clamp2202; GFX8-NEXT:    v_add_u16_sdwa v0, v2, v0 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12203; GFX8-NEXT:    v_or_b32_e32 v0, v1, v02204; GFX8-NEXT:    ; return to shader part epilog2205;2206; GFX9-LABEL: uaddsat_v2i16_sv:2207; GFX9:       ; %bb.0:2208; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2209; GFX9-NEXT:    ; return to shader part epilog2210;2211; GFX10PLUS-LABEL: uaddsat_v2i16_sv:2212; GFX10PLUS:       ; %bb.0:2213; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2214; GFX10PLUS-NEXT:    ; return to shader part epilog2215  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2216  %cast = bitcast <2 x i16> %result to float2217  ret float %cast2218}2219 2220define amdgpu_ps float @uaddsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {2221; GFX6-LABEL: uaddsat_v2i16_vs:2222; GFX6:       ; %bb.0:2223; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02224; GFX6-NEXT:    s_lshl_b32 s0, s0, 162225; GFX6-NEXT:    v_not_b32_e32 v2, v02226; GFX6-NEXT:    v_min_u32_e32 v2, s0, v22227; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12228; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v22229; GFX6-NEXT:    s_lshl_b32 s0, s1, 162230; GFX6-NEXT:    v_not_b32_e32 v2, v12231; GFX6-NEXT:    v_min_u32_e32 v2, s0, v22232; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v22233; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12234; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 162235; GFX6-NEXT:    ; return to shader part epilog2236;2237; GFX8-LABEL: uaddsat_v2i16_vs:2238; GFX8:       ; %bb.0:2239; GFX8-NEXT:    s_lshr_b32 s1, s0, 162240; GFX8-NEXT:    v_mov_b32_e32 v2, s12241; GFX8-NEXT:    v_add_u16_e64 v1, v0, s0 clamp2242; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2243; GFX8-NEXT:    v_or_b32_e32 v0, v1, v02244; GFX8-NEXT:    ; return to shader part epilog2245;2246; GFX9-LABEL: uaddsat_v2i16_vs:2247; GFX9:       ; %bb.0:2248; GFX9-NEXT:    v_pk_add_u16 v0, v0, s0 clamp2249; GFX9-NEXT:    ; return to shader part epilog2250;2251; GFX10PLUS-LABEL: uaddsat_v2i16_vs:2252; GFX10PLUS:       ; %bb.0:2253; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, s0 clamp2254; GFX10PLUS-NEXT:    ; return to shader part epilog2255  %result = call <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2256  %cast = bitcast <2 x i16> %result to float2257  ret float %cast2258}2259 2260; FIXME: v3i16 insert/extract2261; define <3 x i16> @v_uaddsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {2262;   %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)2263;   ret <3 x i16> %result2264; }2265 2266; define amdgpu_ps <3 x i16> @s_uaddsat_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs) {2267;   %result = call <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)2268;   ret <3 x i16> %result2269; }2270 2271define <2 x float> @v_uaddsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {2272; GFX6-LABEL: v_uaddsat_v4i16:2273; GFX6:       ; %bb.0:2274; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02276; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v42277; GFX6-NEXT:    v_not_b32_e32 v8, v02278; GFX6-NEXT:    v_min_u32_e32 v4, v8, v42279; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12280; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v42281; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v52282; GFX6-NEXT:    v_not_b32_e32 v5, v12283; GFX6-NEXT:    v_min_u32_e32 v4, v5, v42284; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v22285; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v42286; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v62287; GFX6-NEXT:    v_not_b32_e32 v5, v22288; GFX6-NEXT:    v_min_u32_e32 v4, v5, v42289; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v32290; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v42291; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v72292; GFX6-NEXT:    v_not_b32_e32 v5, v32293; GFX6-NEXT:    v_min_u32_e32 v4, v5, v42294; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v42295; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12296; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v32297; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 162298; GFX6-NEXT:    v_alignbit_b32 v1, v3, v2, 162299; GFX6-NEXT:    s_setpc_b64 s[30:31]2300;2301; GFX8-LABEL: v_uaddsat_v4i16:2302; GFX8:       ; %bb.0:2303; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2304; GFX8-NEXT:    v_add_u16_e64 v4, v0, v2 clamp2305; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12306; GFX8-NEXT:    v_add_u16_e64 v2, v1, v3 clamp2307; GFX8-NEXT:    v_add_u16_sdwa v1, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12308; GFX8-NEXT:    v_or_b32_e32 v0, v4, v02309; GFX8-NEXT:    v_or_b32_e32 v1, v2, v12310; GFX8-NEXT:    s_setpc_b64 s[30:31]2311;2312; GFX9-LABEL: v_uaddsat_v4i16:2313; GFX9:       ; %bb.0:2314; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2315; GFX9-NEXT:    v_pk_add_u16 v0, v0, v2 clamp2316; GFX9-NEXT:    v_pk_add_u16 v1, v1, v3 clamp2317; GFX9-NEXT:    s_setpc_b64 s[30:31]2318;2319; GFX10PLUS-LABEL: v_uaddsat_v4i16:2320; GFX10PLUS:       ; %bb.0:2321; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2322; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v2 clamp2323; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v3 clamp2324; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]2325  %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)2326  %cast = bitcast <4 x i16> %result to <2 x float>2327  ret <2 x float> %cast2328}2329 2330define amdgpu_ps <2 x i32> @s_uaddsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {2331; GFX6-LABEL: s_uaddsat_v4i16:2332; GFX6:       ; %bb.0:2333; GFX6-NEXT:    s_lshl_b32 s0, s0, 162334; GFX6-NEXT:    s_lshl_b32 s4, s4, 162335; GFX6-NEXT:    s_not_b32 s8, s02336; GFX6-NEXT:    s_min_u32 s4, s8, s42337; GFX6-NEXT:    s_lshl_b32 s1, s1, 162338; GFX6-NEXT:    s_add_i32 s0, s0, s42339; GFX6-NEXT:    s_lshl_b32 s4, s5, 162340; GFX6-NEXT:    s_not_b32 s5, s12341; GFX6-NEXT:    s_min_u32 s4, s5, s42342; GFX6-NEXT:    s_lshl_b32 s2, s2, 162343; GFX6-NEXT:    s_add_i32 s1, s1, s42344; GFX6-NEXT:    s_lshl_b32 s4, s6, 162345; GFX6-NEXT:    s_not_b32 s5, s22346; GFX6-NEXT:    s_min_u32 s4, s5, s42347; GFX6-NEXT:    s_lshl_b32 s3, s3, 162348; GFX6-NEXT:    s_add_i32 s2, s2, s42349; GFX6-NEXT:    s_lshl_b32 s4, s7, 162350; GFX6-NEXT:    s_not_b32 s5, s32351; GFX6-NEXT:    s_min_u32 s4, s5, s42352; GFX6-NEXT:    s_add_i32 s3, s3, s42353; GFX6-NEXT:    s_lshr_b32 s1, s1, 162354; GFX6-NEXT:    s_lshr_b32 s3, s3, 162355; GFX6-NEXT:    v_mov_b32_e32 v0, s02356; GFX6-NEXT:    v_mov_b32_e32 v1, s22357; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 162358; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 162359; GFX6-NEXT:    v_readfirstlane_b32 s0, v02360; GFX6-NEXT:    v_readfirstlane_b32 s1, v12361; GFX6-NEXT:    ; return to shader part epilog2362;2363; GFX8-LABEL: s_uaddsat_v4i16:2364; GFX8:       ; %bb.0:2365; GFX8-NEXT:    s_lshr_b32 s4, s0, 162366; GFX8-NEXT:    s_lshr_b32 s6, s2, 162367; GFX8-NEXT:    s_lshr_b32 s5, s1, 162368; GFX8-NEXT:    s_lshr_b32 s7, s3, 162369; GFX8-NEXT:    v_mov_b32_e32 v1, s62370; GFX8-NEXT:    v_mov_b32_e32 v2, s42371; GFX8-NEXT:    v_mov_b32_e32 v0, s22372; GFX8-NEXT:    v_add_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2373; GFX8-NEXT:    v_mov_b32_e32 v2, s32374; GFX8-NEXT:    v_mov_b32_e32 v3, s72375; GFX8-NEXT:    v_mov_b32_e32 v4, s52376; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2377; GFX8-NEXT:    v_add_u16_e64 v2, s1, v2 clamp2378; GFX8-NEXT:    v_add_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2379; GFX8-NEXT:    v_or_b32_e32 v0, v0, v12380; GFX8-NEXT:    v_or_b32_e32 v1, v2, v32381; GFX8-NEXT:    v_readfirstlane_b32 s0, v02382; GFX8-NEXT:    v_readfirstlane_b32 s1, v12383; GFX8-NEXT:    ; return to shader part epilog2384;2385; GFX9-LABEL: s_uaddsat_v4i16:2386; GFX9:       ; %bb.0:2387; GFX9-NEXT:    v_mov_b32_e32 v0, s22388; GFX9-NEXT:    v_mov_b32_e32 v1, s32389; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2390; GFX9-NEXT:    v_pk_add_u16 v1, s1, v1 clamp2391; GFX9-NEXT:    v_readfirstlane_b32 s0, v02392; GFX9-NEXT:    v_readfirstlane_b32 s1, v12393; GFX9-NEXT:    ; return to shader part epilog2394;2395; GFX10PLUS-LABEL: s_uaddsat_v4i16:2396; GFX10PLUS:       ; %bb.0:2397; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s2 clamp2398; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s3 clamp2399; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v02400; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v12401; GFX10PLUS-NEXT:    ; return to shader part epilog2402  %result = call <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)2403  %cast = bitcast <4 x i16> %result to <2 x i32>2404  ret <2 x i32> %cast2405}2406 2407; FIXME2408; define <5 x i16> @v_uaddsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {2409;   %result = call <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)2410;   ret <5 x i16> %result2411; }2412 2413; define amdgpu_ps <5 x i16> @s_uaddsat_v5i16(<5 x i16> inreg %lhs, <5 x i16> inreg %rhs) {2414;   %result = call <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)2415;   ret <5 x i16> %result2416; }2417 2418define <3 x float> @v_uaddsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {2419; GFX6-LABEL: v_uaddsat_v6i16:2420; GFX6:       ; %bb.0:2421; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2422; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02423; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v62424; GFX6-NEXT:    v_not_b32_e32 v12, v02425; GFX6-NEXT:    v_min_u32_e32 v6, v12, v62426; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12427; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v62428; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v72429; GFX6-NEXT:    v_not_b32_e32 v7, v12430; GFX6-NEXT:    v_min_u32_e32 v6, v7, v62431; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v22432; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v62433; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v82434; GFX6-NEXT:    v_not_b32_e32 v7, v22435; GFX6-NEXT:    v_min_u32_e32 v6, v7, v62436; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v32437; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v62438; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v92439; GFX6-NEXT:    v_not_b32_e32 v7, v32440; GFX6-NEXT:    v_min_u32_e32 v6, v7, v62441; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v42442; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v62443; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v102444; GFX6-NEXT:    v_not_b32_e32 v7, v42445; GFX6-NEXT:    v_min_u32_e32 v6, v7, v62446; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 16, v52447; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v62448; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v112449; GFX6-NEXT:    v_not_b32_e32 v7, v52450; GFX6-NEXT:    v_min_u32_e32 v6, v7, v62451; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v62452; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12453; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v32454; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v52455; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 162456; GFX6-NEXT:    v_alignbit_b32 v1, v3, v2, 162457; GFX6-NEXT:    v_alignbit_b32 v2, v5, v4, 162458; GFX6-NEXT:    s_setpc_b64 s[30:31]2459;2460; GFX8-LABEL: v_uaddsat_v6i16:2461; GFX8:       ; %bb.0:2462; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2463; GFX8-NEXT:    v_add_u16_e64 v6, v0, v3 clamp2464; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12465; GFX8-NEXT:    v_add_u16_e64 v3, v1, v4 clamp2466; GFX8-NEXT:    v_add_u16_sdwa v1, v1, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12467; GFX8-NEXT:    v_add_u16_e64 v4, v2, v5 clamp2468; GFX8-NEXT:    v_add_u16_sdwa v2, v2, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12469; GFX8-NEXT:    v_or_b32_e32 v0, v6, v02470; GFX8-NEXT:    v_or_b32_e32 v1, v3, v12471; GFX8-NEXT:    v_or_b32_e32 v2, v4, v22472; GFX8-NEXT:    s_setpc_b64 s[30:31]2473;2474; GFX9-LABEL: v_uaddsat_v6i16:2475; GFX9:       ; %bb.0:2476; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2477; GFX9-NEXT:    v_pk_add_u16 v0, v0, v3 clamp2478; GFX9-NEXT:    v_pk_add_u16 v1, v1, v4 clamp2479; GFX9-NEXT:    v_pk_add_u16 v2, v2, v5 clamp2480; GFX9-NEXT:    s_setpc_b64 s[30:31]2481;2482; GFX10PLUS-LABEL: v_uaddsat_v6i16:2483; GFX10PLUS:       ; %bb.0:2484; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2485; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v3 clamp2486; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v4 clamp2487; GFX10PLUS-NEXT:    v_pk_add_u16 v2, v2, v5 clamp2488; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]2489  %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)2490  %cast = bitcast <6 x i16> %result to <3 x float>2491  ret <3 x float> %cast2492}2493 2494define amdgpu_ps <3 x i32> @s_uaddsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {2495; GFX6-LABEL: s_uaddsat_v6i16:2496; GFX6:       ; %bb.0:2497; GFX6-NEXT:    s_lshl_b32 s0, s0, 162498; GFX6-NEXT:    s_lshl_b32 s6, s6, 162499; GFX6-NEXT:    s_not_b32 s12, s02500; GFX6-NEXT:    s_min_u32 s6, s12, s62501; GFX6-NEXT:    s_lshl_b32 s1, s1, 162502; GFX6-NEXT:    s_add_i32 s0, s0, s62503; GFX6-NEXT:    s_lshl_b32 s6, s7, 162504; GFX6-NEXT:    s_not_b32 s7, s12505; GFX6-NEXT:    s_min_u32 s6, s7, s62506; GFX6-NEXT:    s_lshl_b32 s2, s2, 162507; GFX6-NEXT:    s_add_i32 s1, s1, s62508; GFX6-NEXT:    s_lshl_b32 s6, s8, 162509; GFX6-NEXT:    s_not_b32 s7, s22510; GFX6-NEXT:    s_min_u32 s6, s7, s62511; GFX6-NEXT:    s_lshl_b32 s3, s3, 162512; GFX6-NEXT:    s_add_i32 s2, s2, s62513; GFX6-NEXT:    s_lshl_b32 s6, s9, 162514; GFX6-NEXT:    s_not_b32 s7, s32515; GFX6-NEXT:    s_min_u32 s6, s7, s62516; GFX6-NEXT:    s_lshl_b32 s4, s4, 162517; GFX6-NEXT:    s_add_i32 s3, s3, s62518; GFX6-NEXT:    s_lshl_b32 s6, s10, 162519; GFX6-NEXT:    s_not_b32 s7, s42520; GFX6-NEXT:    s_min_u32 s6, s7, s62521; GFX6-NEXT:    s_lshl_b32 s5, s5, 162522; GFX6-NEXT:    s_add_i32 s4, s4, s62523; GFX6-NEXT:    s_lshl_b32 s6, s11, 162524; GFX6-NEXT:    s_not_b32 s7, s52525; GFX6-NEXT:    s_min_u32 s6, s7, s62526; GFX6-NEXT:    s_add_i32 s5, s5, s62527; GFX6-NEXT:    s_lshr_b32 s1, s1, 162528; GFX6-NEXT:    s_lshr_b32 s3, s3, 162529; GFX6-NEXT:    s_lshr_b32 s5, s5, 162530; GFX6-NEXT:    v_mov_b32_e32 v0, s02531; GFX6-NEXT:    v_mov_b32_e32 v1, s22532; GFX6-NEXT:    v_mov_b32_e32 v2, s42533; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 162534; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 162535; GFX6-NEXT:    v_alignbit_b32 v2, s5, v2, 162536; GFX6-NEXT:    v_readfirstlane_b32 s0, v02537; GFX6-NEXT:    v_readfirstlane_b32 s1, v12538; GFX6-NEXT:    v_readfirstlane_b32 s2, v22539; GFX6-NEXT:    ; return to shader part epilog2540;2541; GFX8-LABEL: s_uaddsat_v6i16:2542; GFX8:       ; %bb.0:2543; GFX8-NEXT:    s_lshr_b32 s6, s0, 162544; GFX8-NEXT:    s_lshr_b32 s7, s1, 162545; GFX8-NEXT:    s_lshr_b32 s9, s3, 162546; GFX8-NEXT:    s_lshr_b32 s10, s4, 162547; GFX8-NEXT:    s_lshr_b32 s8, s2, 162548; GFX8-NEXT:    s_lshr_b32 s11, s5, 162549; GFX8-NEXT:    v_mov_b32_e32 v1, s92550; GFX8-NEXT:    v_mov_b32_e32 v2, s62551; GFX8-NEXT:    v_mov_b32_e32 v3, s102552; GFX8-NEXT:    v_mov_b32_e32 v4, s72553; GFX8-NEXT:    v_mov_b32_e32 v0, s32554; GFX8-NEXT:    v_add_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2555; GFX8-NEXT:    v_mov_b32_e32 v2, s42556; GFX8-NEXT:    v_add_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2557; GFX8-NEXT:    v_mov_b32_e32 v4, s52558; GFX8-NEXT:    v_mov_b32_e32 v5, s112559; GFX8-NEXT:    v_mov_b32_e32 v6, s82560; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2561; GFX8-NEXT:    v_add_u16_e64 v2, s1, v2 clamp2562; GFX8-NEXT:    v_add_u16_e64 v4, s2, v4 clamp2563; GFX8-NEXT:    v_add_u16_sdwa v5, v6, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2564; GFX8-NEXT:    v_or_b32_e32 v0, v0, v12565; GFX8-NEXT:    v_or_b32_e32 v1, v2, v32566; GFX8-NEXT:    v_or_b32_e32 v2, v4, v52567; GFX8-NEXT:    v_readfirstlane_b32 s0, v02568; GFX8-NEXT:    v_readfirstlane_b32 s1, v12569; GFX8-NEXT:    v_readfirstlane_b32 s2, v22570; GFX8-NEXT:    ; return to shader part epilog2571;2572; GFX9-LABEL: s_uaddsat_v6i16:2573; GFX9:       ; %bb.0:2574; GFX9-NEXT:    v_mov_b32_e32 v0, s32575; GFX9-NEXT:    v_mov_b32_e32 v1, s42576; GFX9-NEXT:    v_mov_b32_e32 v2, s52577; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2578; GFX9-NEXT:    v_pk_add_u16 v1, s1, v1 clamp2579; GFX9-NEXT:    v_pk_add_u16 v2, s2, v2 clamp2580; GFX9-NEXT:    v_readfirstlane_b32 s0, v02581; GFX9-NEXT:    v_readfirstlane_b32 s1, v12582; GFX9-NEXT:    v_readfirstlane_b32 s2, v22583; GFX9-NEXT:    ; return to shader part epilog2584;2585; GFX10PLUS-LABEL: s_uaddsat_v6i16:2586; GFX10PLUS:       ; %bb.0:2587; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s3 clamp2588; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s4 clamp2589; GFX10PLUS-NEXT:    v_pk_add_u16 v2, s2, s5 clamp2590; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v02591; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v12592; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v22593; GFX10PLUS-NEXT:    ; return to shader part epilog2594  %result = call <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)2595  %cast = bitcast <6 x i16> %result to <3 x i32>2596  ret <3 x i32> %cast2597}2598 2599define <4 x float> @v_uaddsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {2600; GFX6-LABEL: v_uaddsat_v8i16:2601; GFX6:       ; %bb.0:2602; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2603; GFX6-NEXT:    v_lshlrev_b32_e32 v0, 16, v02604; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v82605; GFX6-NEXT:    v_not_b32_e32 v16, v02606; GFX6-NEXT:    v_min_u32_e32 v8, v16, v82607; GFX6-NEXT:    v_lshlrev_b32_e32 v1, 16, v12608; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v82609; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v92610; GFX6-NEXT:    v_not_b32_e32 v9, v12611; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82612; GFX6-NEXT:    v_lshlrev_b32_e32 v2, 16, v22613; GFX6-NEXT:    v_add_i32_e32 v1, vcc, v1, v82614; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v102615; GFX6-NEXT:    v_not_b32_e32 v9, v22616; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82617; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v32618; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v82619; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v112620; GFX6-NEXT:    v_not_b32_e32 v9, v32621; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82622; GFX6-NEXT:    v_lshlrev_b32_e32 v4, 16, v42623; GFX6-NEXT:    v_add_i32_e32 v3, vcc, v3, v82624; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v122625; GFX6-NEXT:    v_not_b32_e32 v9, v42626; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82627; GFX6-NEXT:    v_lshlrev_b32_e32 v5, 16, v52628; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v82629; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v132630; GFX6-NEXT:    v_not_b32_e32 v9, v52631; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82632; GFX6-NEXT:    v_lshlrev_b32_e32 v6, 16, v62633; GFX6-NEXT:    v_add_i32_e32 v5, vcc, v5, v82634; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v142635; GFX6-NEXT:    v_not_b32_e32 v9, v62636; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82637; GFX6-NEXT:    v_lshlrev_b32_e32 v7, 16, v72638; GFX6-NEXT:    v_add_i32_e32 v6, vcc, v6, v82639; GFX6-NEXT:    v_lshlrev_b32_e32 v8, 16, v152640; GFX6-NEXT:    v_not_b32_e32 v9, v72641; GFX6-NEXT:    v_min_u32_e32 v8, v9, v82642; GFX6-NEXT:    v_add_i32_e32 v7, vcc, v7, v82643; GFX6-NEXT:    v_lshrrev_b32_e32 v1, 16, v12644; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v32645; GFX6-NEXT:    v_lshrrev_b32_e32 v5, 16, v52646; GFX6-NEXT:    v_lshrrev_b32_e32 v7, 16, v72647; GFX6-NEXT:    v_alignbit_b32 v0, v1, v0, 162648; GFX6-NEXT:    v_alignbit_b32 v1, v3, v2, 162649; GFX6-NEXT:    v_alignbit_b32 v2, v5, v4, 162650; GFX6-NEXT:    v_alignbit_b32 v3, v7, v6, 162651; GFX6-NEXT:    s_setpc_b64 s[30:31]2652;2653; GFX8-LABEL: v_uaddsat_v8i16:2654; GFX8:       ; %bb.0:2655; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2656; GFX8-NEXT:    v_add_u16_e64 v8, v0, v4 clamp2657; GFX8-NEXT:    v_add_u16_sdwa v0, v0, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12658; GFX8-NEXT:    v_add_u16_e64 v4, v1, v5 clamp2659; GFX8-NEXT:    v_add_u16_sdwa v1, v1, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12660; GFX8-NEXT:    v_add_u16_e64 v5, v2, v6 clamp2661; GFX8-NEXT:    v_add_u16_sdwa v2, v2, v6 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12662; GFX8-NEXT:    v_add_u16_e64 v6, v3, v7 clamp2663; GFX8-NEXT:    v_add_u16_sdwa v3, v3, v7 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12664; GFX8-NEXT:    v_or_b32_e32 v0, v8, v02665; GFX8-NEXT:    v_or_b32_e32 v1, v4, v12666; GFX8-NEXT:    v_or_b32_e32 v2, v5, v22667; GFX8-NEXT:    v_or_b32_e32 v3, v6, v32668; GFX8-NEXT:    s_setpc_b64 s[30:31]2669;2670; GFX9-LABEL: v_uaddsat_v8i16:2671; GFX9:       ; %bb.0:2672; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2673; GFX9-NEXT:    v_pk_add_u16 v0, v0, v4 clamp2674; GFX9-NEXT:    v_pk_add_u16 v1, v1, v5 clamp2675; GFX9-NEXT:    v_pk_add_u16 v2, v2, v6 clamp2676; GFX9-NEXT:    v_pk_add_u16 v3, v3, v7 clamp2677; GFX9-NEXT:    s_setpc_b64 s[30:31]2678;2679; GFX10PLUS-LABEL: v_uaddsat_v8i16:2680; GFX10PLUS:       ; %bb.0:2681; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2682; GFX10PLUS-NEXT:    v_pk_add_u16 v0, v0, v4 clamp2683; GFX10PLUS-NEXT:    v_pk_add_u16 v1, v1, v5 clamp2684; GFX10PLUS-NEXT:    v_pk_add_u16 v2, v2, v6 clamp2685; GFX10PLUS-NEXT:    v_pk_add_u16 v3, v3, v7 clamp2686; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]2687  %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)2688  %cast = bitcast <8 x i16> %result to <4 x float>2689  ret <4 x float> %cast2690}2691 2692define amdgpu_ps <4 x i32> @s_uaddsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {2693; GFX6-LABEL: s_uaddsat_v8i16:2694; GFX6:       ; %bb.0:2695; GFX6-NEXT:    s_lshl_b32 s0, s0, 162696; GFX6-NEXT:    s_lshl_b32 s8, s8, 162697; GFX6-NEXT:    s_not_b32 s16, s02698; GFX6-NEXT:    s_min_u32 s8, s16, s82699; GFX6-NEXT:    s_lshl_b32 s1, s1, 162700; GFX6-NEXT:    s_add_i32 s0, s0, s82701; GFX6-NEXT:    s_lshl_b32 s8, s9, 162702; GFX6-NEXT:    s_not_b32 s9, s12703; GFX6-NEXT:    s_min_u32 s8, s9, s82704; GFX6-NEXT:    s_lshl_b32 s2, s2, 162705; GFX6-NEXT:    s_add_i32 s1, s1, s82706; GFX6-NEXT:    s_lshl_b32 s8, s10, 162707; GFX6-NEXT:    s_not_b32 s9, s22708; GFX6-NEXT:    s_min_u32 s8, s9, s82709; GFX6-NEXT:    s_lshl_b32 s3, s3, 162710; GFX6-NEXT:    s_add_i32 s2, s2, s82711; GFX6-NEXT:    s_lshl_b32 s8, s11, 162712; GFX6-NEXT:    s_not_b32 s9, s32713; GFX6-NEXT:    s_min_u32 s8, s9, s82714; GFX6-NEXT:    s_lshl_b32 s4, s4, 162715; GFX6-NEXT:    s_add_i32 s3, s3, s82716; GFX6-NEXT:    s_lshl_b32 s8, s12, 162717; GFX6-NEXT:    s_not_b32 s9, s42718; GFX6-NEXT:    s_min_u32 s8, s9, s82719; GFX6-NEXT:    s_lshl_b32 s5, s5, 162720; GFX6-NEXT:    s_add_i32 s4, s4, s82721; GFX6-NEXT:    s_lshl_b32 s8, s13, 162722; GFX6-NEXT:    s_not_b32 s9, s52723; GFX6-NEXT:    s_min_u32 s8, s9, s82724; GFX6-NEXT:    s_lshl_b32 s6, s6, 162725; GFX6-NEXT:    s_add_i32 s5, s5, s82726; GFX6-NEXT:    s_lshl_b32 s8, s14, 162727; GFX6-NEXT:    s_not_b32 s9, s62728; GFX6-NEXT:    s_min_u32 s8, s9, s82729; GFX6-NEXT:    s_lshl_b32 s7, s7, 162730; GFX6-NEXT:    s_add_i32 s6, s6, s82731; GFX6-NEXT:    s_lshl_b32 s8, s15, 162732; GFX6-NEXT:    s_not_b32 s9, s72733; GFX6-NEXT:    s_min_u32 s8, s9, s82734; GFX6-NEXT:    s_add_i32 s7, s7, s82735; GFX6-NEXT:    s_lshr_b32 s1, s1, 162736; GFX6-NEXT:    s_lshr_b32 s3, s3, 162737; GFX6-NEXT:    s_lshr_b32 s5, s5, 162738; GFX6-NEXT:    s_lshr_b32 s7, s7, 162739; GFX6-NEXT:    v_mov_b32_e32 v0, s02740; GFX6-NEXT:    v_mov_b32_e32 v1, s22741; GFX6-NEXT:    v_mov_b32_e32 v2, s42742; GFX6-NEXT:    v_mov_b32_e32 v3, s62743; GFX6-NEXT:    v_alignbit_b32 v0, s1, v0, 162744; GFX6-NEXT:    v_alignbit_b32 v1, s3, v1, 162745; GFX6-NEXT:    v_alignbit_b32 v2, s5, v2, 162746; GFX6-NEXT:    v_alignbit_b32 v3, s7, v3, 162747; GFX6-NEXT:    v_readfirstlane_b32 s0, v02748; GFX6-NEXT:    v_readfirstlane_b32 s1, v12749; GFX6-NEXT:    v_readfirstlane_b32 s2, v22750; GFX6-NEXT:    v_readfirstlane_b32 s3, v32751; GFX6-NEXT:    ; return to shader part epilog2752;2753; GFX8-LABEL: s_uaddsat_v8i16:2754; GFX8:       ; %bb.0:2755; GFX8-NEXT:    s_lshr_b32 s8, s0, 162756; GFX8-NEXT:    s_lshr_b32 s9, s1, 162757; GFX8-NEXT:    s_lshr_b32 s10, s2, 162758; GFX8-NEXT:    s_lshr_b32 s12, s4, 162759; GFX8-NEXT:    s_lshr_b32 s13, s5, 162760; GFX8-NEXT:    s_lshr_b32 s14, s6, 162761; GFX8-NEXT:    s_lshr_b32 s11, s3, 162762; GFX8-NEXT:    s_lshr_b32 s15, s7, 162763; GFX8-NEXT:    v_mov_b32_e32 v1, s122764; GFX8-NEXT:    v_mov_b32_e32 v2, s82765; GFX8-NEXT:    v_mov_b32_e32 v3, s132766; GFX8-NEXT:    v_mov_b32_e32 v4, s92767; GFX8-NEXT:    v_mov_b32_e32 v5, s142768; GFX8-NEXT:    v_mov_b32_e32 v6, s102769; GFX8-NEXT:    v_mov_b32_e32 v0, s42770; GFX8-NEXT:    v_add_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2771; GFX8-NEXT:    v_mov_b32_e32 v2, s52772; GFX8-NEXT:    v_add_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2773; GFX8-NEXT:    v_mov_b32_e32 v4, s62774; GFX8-NEXT:    v_add_u16_sdwa v5, v6, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2775; GFX8-NEXT:    v_mov_b32_e32 v6, s72776; GFX8-NEXT:    v_mov_b32_e32 v7, s152777; GFX8-NEXT:    v_mov_b32_e32 v8, s112778; GFX8-NEXT:    v_add_u16_e64 v0, s0, v0 clamp2779; GFX8-NEXT:    v_add_u16_e64 v2, s1, v2 clamp2780; GFX8-NEXT:    v_add_u16_e64 v4, s2, v4 clamp2781; GFX8-NEXT:    v_add_u16_e64 v6, s3, v6 clamp2782; GFX8-NEXT:    v_add_u16_sdwa v7, v8, v7 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2783; GFX8-NEXT:    v_or_b32_e32 v0, v0, v12784; GFX8-NEXT:    v_or_b32_e32 v1, v2, v32785; GFX8-NEXT:    v_or_b32_e32 v2, v4, v52786; GFX8-NEXT:    v_or_b32_e32 v3, v6, v72787; GFX8-NEXT:    v_readfirstlane_b32 s0, v02788; GFX8-NEXT:    v_readfirstlane_b32 s1, v12789; GFX8-NEXT:    v_readfirstlane_b32 s2, v22790; GFX8-NEXT:    v_readfirstlane_b32 s3, v32791; GFX8-NEXT:    ; return to shader part epilog2792;2793; GFX9-LABEL: s_uaddsat_v8i16:2794; GFX9:       ; %bb.0:2795; GFX9-NEXT:    v_mov_b32_e32 v0, s42796; GFX9-NEXT:    v_mov_b32_e32 v1, s52797; GFX9-NEXT:    v_mov_b32_e32 v2, s62798; GFX9-NEXT:    v_mov_b32_e32 v3, s72799; GFX9-NEXT:    v_pk_add_u16 v0, s0, v0 clamp2800; GFX9-NEXT:    v_pk_add_u16 v1, s1, v1 clamp2801; GFX9-NEXT:    v_pk_add_u16 v2, s2, v2 clamp2802; GFX9-NEXT:    v_pk_add_u16 v3, s3, v3 clamp2803; GFX9-NEXT:    v_readfirstlane_b32 s0, v02804; GFX9-NEXT:    v_readfirstlane_b32 s1, v12805; GFX9-NEXT:    v_readfirstlane_b32 s2, v22806; GFX9-NEXT:    v_readfirstlane_b32 s3, v32807; GFX9-NEXT:    ; return to shader part epilog2808;2809; GFX10PLUS-LABEL: s_uaddsat_v8i16:2810; GFX10PLUS:       ; %bb.0:2811; GFX10PLUS-NEXT:    v_pk_add_u16 v0, s0, s4 clamp2812; GFX10PLUS-NEXT:    v_pk_add_u16 v1, s1, s5 clamp2813; GFX10PLUS-NEXT:    v_pk_add_u16 v2, s2, s6 clamp2814; GFX10PLUS-NEXT:    v_pk_add_u16 v3, s3, s7 clamp2815; GFX10PLUS-NEXT:    v_readfirstlane_b32 s0, v02816; GFX10PLUS-NEXT:    v_readfirstlane_b32 s1, v12817; GFX10PLUS-NEXT:    v_readfirstlane_b32 s2, v22818; GFX10PLUS-NEXT:    v_readfirstlane_b32 s3, v32819; GFX10PLUS-NEXT:    ; return to shader part epilog2820  %result = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)2821  %cast = bitcast <8 x i16> %result to <4 x i32>2822  ret <4 x i32> %cast2823}2824 2825define i48 @v_uaddsat_i48(i48 %lhs, i48 %rhs) {2826; GFX6-LABEL: v_uaddsat_i48:2827; GFX6:       ; %bb.0:2828; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2829; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v12830; GFX6-NEXT:    v_and_b32_e32 v3, 0xffff, v32831; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v22832; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc2833; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v02834; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v12835; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v02836; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v32837; GFX6-NEXT:    v_or_b32_e32 v0, v0, v32838; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, v1, v22839; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2840; GFX6-NEXT:    v_cndmask_b32_e64 v1, v2, -1, vcc2841; GFX6-NEXT:    s_setpc_b64 s[30:31]2842;2843; GFX8-LABEL: v_uaddsat_i48:2844; GFX8:       ; %bb.0:2845; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2846; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2847; GFX8-NEXT:    v_lshlrev_b64 v[2:3], 16, v[2:3]2848; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v22849; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc2850; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2851; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc2852; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2853; GFX8-NEXT:    s_setpc_b64 s[30:31]2854;2855; GFX9-LABEL: v_uaddsat_i48:2856; GFX9:       ; %bb.0:2857; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2858; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2859; GFX9-NEXT:    v_lshlrev_b64 v[2:3], 16, v[2:3]2860; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v22861; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc2862; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2863; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc2864; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2865; GFX9-NEXT:    s_setpc_b64 s[30:31]2866;2867; GFX10PLUS-LABEL: v_uaddsat_i48:2868; GFX10PLUS:       ; %bb.0:2869; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2870; GFX10PLUS-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2871; GFX10PLUS-NEXT:    v_lshlrev_b64 v[2:3], 16, v[2:3]2872; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v22873; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo2874; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo2875; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo2876; GFX10PLUS-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2877; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]2878  %result = call i48 @llvm.uadd.sat.i48(i48 %lhs, i48 %rhs)2879  ret i48 %result2880}2881 2882define amdgpu_ps i48 @s_uaddsat_i48(i48 inreg %lhs, i48 inreg %rhs) {2883; GFX6-LABEL: s_uaddsat_i48:2884; GFX6:       ; %bb.0:2885; GFX6-NEXT:    s_add_u32 s0, s0, s22886; GFX6-NEXT:    s_cselect_b32 s2, 1, 02887; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff2888; GFX6-NEXT:    s_and_b32 s3, s3, 0xffff2889; GFX6-NEXT:    s_cmp_lg_u32 s2, 02890; GFX6-NEXT:    s_addc_u32 s2, s1, s32891; GFX6-NEXT:    s_and_b32 s1, s2, 0xffff2892; GFX6-NEXT:    s_cmp_lg_u32 s2, s12893; GFX6-NEXT:    s_cselect_b32 s2, 1, 02894; GFX6-NEXT:    s_lshr_b32 s3, s0, 162895; GFX6-NEXT:    s_and_b32 s0, s0, 0xffff2896; GFX6-NEXT:    s_lshl_b32 s3, s3, 162897; GFX6-NEXT:    s_or_b32 s0, s0, s32898; GFX6-NEXT:    s_cmp_lg_u32 s2, 02899; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]2900; GFX6-NEXT:    ; return to shader part epilog2901;2902; GFX8-LABEL: s_uaddsat_i48:2903; GFX8:       ; %bb.0:2904; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162905; GFX8-NEXT:    s_lshl_b64 s[2:3], s[2:3], 162906; GFX8-NEXT:    s_add_u32 s0, s0, s22907; GFX8-NEXT:    s_addc_u32 s1, s1, s32908; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]2909; GFX8-NEXT:    s_lshr_b64 s[0:1], s[0:1], 162910; GFX8-NEXT:    ; return to shader part epilog2911;2912; GFX9-LABEL: s_uaddsat_i48:2913; GFX9:       ; %bb.0:2914; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162915; GFX9-NEXT:    s_lshl_b64 s[2:3], s[2:3], 162916; GFX9-NEXT:    s_add_u32 s0, s0, s22917; GFX9-NEXT:    s_addc_u32 s1, s1, s32918; GFX9-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]2919; GFX9-NEXT:    s_lshr_b64 s[0:1], s[0:1], 162920; GFX9-NEXT:    ; return to shader part epilog2921;2922; GFX10PLUS-LABEL: s_uaddsat_i48:2923; GFX10PLUS:       ; %bb.0:2924; GFX10PLUS-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162925; GFX10PLUS-NEXT:    s_lshl_b64 s[2:3], s[2:3], 162926; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s22927; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s32928; GFX10PLUS-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]2929; GFX10PLUS-NEXT:    s_lshr_b64 s[0:1], s[0:1], 162930; GFX10PLUS-NEXT:    ; return to shader part epilog2931  %result = call i48 @llvm.uadd.sat.i48(i48 %lhs, i48 %rhs)2932  ret i48 %result2933}2934 2935define amdgpu_ps <2 x float> @uaddsat_i48_sv(i48 inreg %lhs, i48 %rhs) {2936; GFX6-LABEL: uaddsat_i48_sv:2937; GFX6:       ; %bb.0:2938; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff2939; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v12940; GFX6-NEXT:    v_mov_b32_e32 v2, s12941; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v02942; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc2943; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v12944; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v02945; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v02946; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v32947; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, v1, v22948; GFX6-NEXT:    v_or_b32_e32 v0, v0, v32949; GFX6-NEXT:    v_cndmask_b32_e64 v1, v2, -1, vcc2950; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2951; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v12952; GFX6-NEXT:    ; return to shader part epilog2953;2954; GFX8-LABEL: uaddsat_i48_sv:2955; GFX8:       ; %bb.0:2956; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2957; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162958; GFX8-NEXT:    v_mov_b32_e32 v2, s12959; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v02960; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc2961; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2962; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc2963; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2964; GFX8-NEXT:    ; return to shader part epilog2965;2966; GFX9-LABEL: uaddsat_i48_sv:2967; GFX9:       ; %bb.0:2968; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2969; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162970; GFX9-NEXT:    v_mov_b32_e32 v2, s12971; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v02972; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v2, v1, vcc2973; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc2974; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc2975; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2976; GFX9-NEXT:    ; return to shader part epilog2977;2978; GFX10PLUS-LABEL: uaddsat_i48_sv:2979; GFX10PLUS:       ; %bb.0:2980; GFX10PLUS-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]2981; GFX10PLUS-NEXT:    s_lshl_b64 s[0:1], s[0:1], 162982; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v02983; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo2984; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo2985; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo2986; GFX10PLUS-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]2987; GFX10PLUS-NEXT:    ; return to shader part epilog2988  %result = call i48 @llvm.uadd.sat.i48(i48 %lhs, i48 %rhs)2989  %ext.result = zext i48 %result to i642990  %cast = bitcast i64 %ext.result to <2 x float>2991  ret <2 x float> %cast2992}2993 2994define amdgpu_ps <2 x float> @uaddsat_i48_vs(i48 %lhs, i48 inreg %rhs) {2995; GFX6-LABEL: uaddsat_i48_vs:2996; GFX6:       ; %bb.0:2997; GFX6-NEXT:    s_and_b32 s1, s1, 0xffff2998; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v12999; GFX6-NEXT:    v_mov_b32_e32 v2, s13000; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v03001; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc3002; GFX6-NEXT:    v_and_b32_e32 v2, 0xffff, v13003; GFX6-NEXT:    v_lshrrev_b32_e32 v3, 16, v03004; GFX6-NEXT:    v_and_b32_e32 v0, 0xffff, v03005; GFX6-NEXT:    v_lshlrev_b32_e32 v3, 16, v33006; GFX6-NEXT:    v_cmp_ne_u32_e32 vcc, v1, v23007; GFX6-NEXT:    v_or_b32_e32 v0, v0, v33008; GFX6-NEXT:    v_cndmask_b32_e64 v1, v2, -1, vcc3009; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3010; GFX6-NEXT:    v_and_b32_e32 v1, 0xffff, v13011; GFX6-NEXT:    ; return to shader part epilog3012;3013; GFX8-LABEL: uaddsat_i48_vs:3014; GFX8:       ; %bb.0:3015; GFX8-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]3016; GFX8-NEXT:    s_lshl_b64 s[0:1], s[0:1], 163017; GFX8-NEXT:    v_mov_b32_e32 v2, s13018; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v03019; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc3020; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3021; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3022; GFX8-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]3023; GFX8-NEXT:    ; return to shader part epilog3024;3025; GFX9-LABEL: uaddsat_i48_vs:3026; GFX9:       ; %bb.0:3027; GFX9-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]3028; GFX9-NEXT:    s_lshl_b64 s[0:1], s[0:1], 163029; GFX9-NEXT:    v_mov_b32_e32 v2, s13030; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v03031; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc3032; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3033; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3034; GFX9-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]3035; GFX9-NEXT:    ; return to shader part epilog3036;3037; GFX10PLUS-LABEL: uaddsat_i48_vs:3038; GFX10PLUS:       ; %bb.0:3039; GFX10PLUS-NEXT:    v_lshlrev_b64 v[0:1], 16, v[0:1]3040; GFX10PLUS-NEXT:    s_lshl_b64 s[0:1], s[0:1], 163041; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s03042; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3043; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3044; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3045; GFX10PLUS-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]3046; GFX10PLUS-NEXT:    ; return to shader part epilog3047  %result = call i48 @llvm.uadd.sat.i48(i48 %lhs, i48 %rhs)3048  %ext.result = zext i48 %result to i643049  %cast = bitcast i64 %ext.result to <2 x float>3050  ret <2 x float> %cast3051}3052 3053define i64 @v_uaddsat_i64(i64 %lhs, i64 %rhs) {3054; GFX6-LABEL: v_uaddsat_i64:3055; GFX6:       ; %bb.0:3056; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3057; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v23058; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc3059; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3060; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3061; GFX6-NEXT:    s_setpc_b64 s[30:31]3062;3063; GFX8-LABEL: v_uaddsat_i64:3064; GFX8:       ; %bb.0:3065; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3066; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v23067; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v3, vcc3068; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3069; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3070; GFX8-NEXT:    s_setpc_b64 s[30:31]3071;3072; GFX9-LABEL: v_uaddsat_i64:3073; GFX9:       ; %bb.0:3074; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3075; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v23076; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v3, vcc3077; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3078; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3079; GFX9-NEXT:    s_setpc_b64 s[30:31]3080;3081; GFX10PLUS-LABEL: v_uaddsat_i64:3082; GFX10PLUS:       ; %bb.0:3083; GFX10PLUS-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3084; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v23085; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo3086; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3087; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3088; GFX10PLUS-NEXT:    s_setpc_b64 s[30:31]3089  %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)3090  ret i64 %result3091}3092 3093define amdgpu_ps i64 @s_uaddsat_i64(i64 inreg %lhs, i64 inreg %rhs) {3094; GFX6-LABEL: s_uaddsat_i64:3095; GFX6:       ; %bb.0:3096; GFX6-NEXT:    s_add_u32 s0, s0, s23097; GFX6-NEXT:    s_addc_u32 s1, s1, s33098; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3099; GFX6-NEXT:    ; return to shader part epilog3100;3101; GFX8-LABEL: s_uaddsat_i64:3102; GFX8:       ; %bb.0:3103; GFX8-NEXT:    s_add_u32 s0, s0, s23104; GFX8-NEXT:    s_addc_u32 s1, s1, s33105; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3106; GFX8-NEXT:    ; return to shader part epilog3107;3108; GFX9-LABEL: s_uaddsat_i64:3109; GFX9:       ; %bb.0:3110; GFX9-NEXT:    s_add_u32 s0, s0, s23111; GFX9-NEXT:    s_addc_u32 s1, s1, s33112; GFX9-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3113; GFX9-NEXT:    ; return to shader part epilog3114;3115; GFX10PLUS-LABEL: s_uaddsat_i64:3116; GFX10PLUS:       ; %bb.0:3117; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s23118; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s33119; GFX10PLUS-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3120; GFX10PLUS-NEXT:    ; return to shader part epilog3121  %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)3122  ret i64 %result3123}3124 3125define amdgpu_ps <2 x float> @uaddsat_i64_sv(i64 inreg %lhs, i64 %rhs) {3126; GFX6-LABEL: uaddsat_i64_sv:3127; GFX6:       ; %bb.0:3128; GFX6-NEXT:    v_mov_b32_e32 v2, s13129; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v03130; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc3131; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3132; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3133; GFX6-NEXT:    ; return to shader part epilog3134;3135; GFX8-LABEL: uaddsat_i64_sv:3136; GFX8:       ; %bb.0:3137; GFX8-NEXT:    v_mov_b32_e32 v2, s13138; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v03139; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v2, v1, vcc3140; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3141; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3142; GFX8-NEXT:    ; return to shader part epilog3143;3144; GFX9-LABEL: uaddsat_i64_sv:3145; GFX9:       ; %bb.0:3146; GFX9-NEXT:    v_mov_b32_e32 v2, s13147; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v03148; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v2, v1, vcc3149; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3150; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3151; GFX9-NEXT:    ; return to shader part epilog3152;3153; GFX10PLUS-LABEL: uaddsat_i64_sv:3154; GFX10PLUS:       ; %bb.0:3155; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v03156; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3157; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3158; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3159; GFX10PLUS-NEXT:    ; return to shader part epilog3160  %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)3161  %cast = bitcast i64 %result to <2 x float>3162  ret <2 x float> %cast3163}3164 3165define amdgpu_ps <2 x float> @uaddsat_i64_vs(i64 %lhs, i64 inreg %rhs) {3166; GFX6-LABEL: uaddsat_i64_vs:3167; GFX6:       ; %bb.0:3168; GFX6-NEXT:    v_mov_b32_e32 v2, s13169; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v03170; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc3171; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3172; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3173; GFX6-NEXT:    ; return to shader part epilog3174;3175; GFX8-LABEL: uaddsat_i64_vs:3176; GFX8:       ; %bb.0:3177; GFX8-NEXT:    v_mov_b32_e32 v2, s13178; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v03179; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v2, vcc3180; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3181; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3182; GFX8-NEXT:    ; return to shader part epilog3183;3184; GFX9-LABEL: uaddsat_i64_vs:3185; GFX9:       ; %bb.0:3186; GFX9-NEXT:    v_mov_b32_e32 v2, s13187; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v03188; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v2, vcc3189; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3190; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3191; GFX9-NEXT:    ; return to shader part epilog3192;3193; GFX10PLUS-LABEL: uaddsat_i64_vs:3194; GFX10PLUS:       ; %bb.0:3195; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s03196; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3197; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3198; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3199; GFX10PLUS-NEXT:    ; return to shader part epilog3200  %result = call i64 @llvm.uadd.sat.i64(i64 %lhs, i64 %rhs)3201  %cast = bitcast i64 %result to <2 x float>3202  ret <2 x float> %cast3203}3204 3205define <2 x i64> @v_uaddsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {3206; GFX6-LABEL: v_uaddsat_v2i64:3207; GFX6:       ; %bb.0:3208; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3209; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v43210; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc3211; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3212; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3213; GFX6-NEXT:    v_add_i32_e32 v2, vcc, v2, v63214; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc3215; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3216; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3217; GFX6-NEXT:    s_setpc_b64 s[30:31]3218;3219; GFX8-LABEL: v_uaddsat_v2i64:3220; GFX8:       ; %bb.0:3221; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3222; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v43223; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v5, vcc3224; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3225; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3226; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v63227; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, v3, v7, vcc3228; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3229; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3230; GFX8-NEXT:    s_setpc_b64 s[30:31]3231;3232; GFX9-LABEL: v_uaddsat_v2i64:3233; GFX9:       ; %bb.0:3234; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3235; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v43236; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v5, vcc3237; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3238; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3239; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v63240; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v7, vcc3241; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3242; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3243; GFX9-NEXT:    s_setpc_b64 s[30:31]3244;3245; GFX10-LABEL: v_uaddsat_v2i64:3246; GFX10:       ; %bb.0:3247; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3248; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v43249; GFX10-NEXT:    v_add_co_u32 v2, s4, v2, v63250; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo3251; GFX10-NEXT:    v_add_co_ci_u32_e64 v3, s4, v3, v7, s43252; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3253; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3254; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s43255; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, -1, s43256; GFX10-NEXT:    s_setpc_b64 s[30:31]3257;3258; GFX11-LABEL: v_uaddsat_v2i64:3259; GFX11:       ; %bb.0:3260; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3261; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v43262; GFX11-NEXT:    v_add_co_u32 v2, s0, v2, v63263; GFX11-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo3264; GFX11-NEXT:    v_add_co_ci_u32_e64 v3, s0, v3, v7, s03265; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3266; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3267; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -1, s03268; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, -1, s03269; GFX11-NEXT:    s_setpc_b64 s[30:31]3270  %result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)3271  ret <2 x i64> %result3272}3273 3274define amdgpu_ps <2 x i64> @s_uaddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {3275; GFX6-LABEL: s_uaddsat_v2i64:3276; GFX6:       ; %bb.0:3277; GFX6-NEXT:    s_add_u32 s0, s0, s43278; GFX6-NEXT:    s_addc_u32 s1, s1, s53279; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3280; GFX6-NEXT:    s_add_u32 s2, s2, s63281; GFX6-NEXT:    s_addc_u32 s3, s3, s73282; GFX6-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3283; GFX6-NEXT:    ; return to shader part epilog3284;3285; GFX8-LABEL: s_uaddsat_v2i64:3286; GFX8:       ; %bb.0:3287; GFX8-NEXT:    s_add_u32 s0, s0, s43288; GFX8-NEXT:    s_addc_u32 s1, s1, s53289; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3290; GFX8-NEXT:    s_add_u32 s2, s2, s63291; GFX8-NEXT:    s_addc_u32 s3, s3, s73292; GFX8-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3293; GFX8-NEXT:    ; return to shader part epilog3294;3295; GFX9-LABEL: s_uaddsat_v2i64:3296; GFX9:       ; %bb.0:3297; GFX9-NEXT:    s_add_u32 s0, s0, s43298; GFX9-NEXT:    s_addc_u32 s1, s1, s53299; GFX9-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3300; GFX9-NEXT:    s_add_u32 s2, s2, s63301; GFX9-NEXT:    s_addc_u32 s3, s3, s73302; GFX9-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3303; GFX9-NEXT:    ; return to shader part epilog3304;3305; GFX10PLUS-LABEL: s_uaddsat_v2i64:3306; GFX10PLUS:       ; %bb.0:3307; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s43308; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s53309; GFX10PLUS-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3310; GFX10PLUS-NEXT:    s_add_u32 s2, s2, s63311; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s73312; GFX10PLUS-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3313; GFX10PLUS-NEXT:    ; return to shader part epilog3314  %result = call <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)3315  ret <2 x i64> %result3316}3317 3318define amdgpu_ps i128 @s_uaddsat_i128(i128 inreg %lhs, i128 inreg %rhs) {3319; GFX6-LABEL: s_uaddsat_i128:3320; GFX6:       ; %bb.0:3321; GFX6-NEXT:    s_add_u32 s0, s0, s43322; GFX6-NEXT:    s_addc_u32 s1, s1, s53323; GFX6-NEXT:    s_addc_u32 s2, s2, s63324; GFX6-NEXT:    s_addc_u32 s3, s3, s73325; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3326; GFX6-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3327; GFX6-NEXT:    ; return to shader part epilog3328;3329; GFX8-LABEL: s_uaddsat_i128:3330; GFX8:       ; %bb.0:3331; GFX8-NEXT:    s_add_u32 s0, s0, s43332; GFX8-NEXT:    s_addc_u32 s1, s1, s53333; GFX8-NEXT:    s_addc_u32 s2, s2, s63334; GFX8-NEXT:    s_addc_u32 s3, s3, s73335; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3336; GFX8-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3337; GFX8-NEXT:    ; return to shader part epilog3338;3339; GFX9-LABEL: s_uaddsat_i128:3340; GFX9:       ; %bb.0:3341; GFX9-NEXT:    s_add_u32 s0, s0, s43342; GFX9-NEXT:    s_addc_u32 s1, s1, s53343; GFX9-NEXT:    s_addc_u32 s2, s2, s63344; GFX9-NEXT:    s_addc_u32 s3, s3, s73345; GFX9-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3346; GFX9-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3347; GFX9-NEXT:    ; return to shader part epilog3348;3349; GFX10PLUS-LABEL: s_uaddsat_i128:3350; GFX10PLUS:       ; %bb.0:3351; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s43352; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s53353; GFX10PLUS-NEXT:    s_addc_u32 s2, s2, s63354; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s73355; GFX10PLUS-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3356; GFX10PLUS-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3357; GFX10PLUS-NEXT:    ; return to shader part epilog3358  %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)3359  ret i128 %result3360}3361 3362define amdgpu_ps <4 x float> @uaddsat_i128_sv(i128 inreg %lhs, i128 %rhs) {3363; GFX6-LABEL: uaddsat_i128_sv:3364; GFX6:       ; %bb.0:3365; GFX6-NEXT:    v_mov_b32_e32 v4, s13366; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v03367; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v4, v1, vcc3368; GFX6-NEXT:    v_mov_b32_e32 v4, s23369; GFX6-NEXT:    v_mov_b32_e32 v5, s33370; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc3371; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc3372; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3373; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3374; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3375; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3376; GFX6-NEXT:    ; return to shader part epilog3377;3378; GFX8-LABEL: uaddsat_i128_sv:3379; GFX8:       ; %bb.0:3380; GFX8-NEXT:    v_mov_b32_e32 v4, s13381; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v03382; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v4, v1, vcc3383; GFX8-NEXT:    v_mov_b32_e32 v4, s23384; GFX8-NEXT:    v_mov_b32_e32 v5, s33385; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, v4, v2, vcc3386; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, v5, v3, vcc3387; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3388; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3389; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3390; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3391; GFX8-NEXT:    ; return to shader part epilog3392;3393; GFX9-LABEL: uaddsat_i128_sv:3394; GFX9:       ; %bb.0:3395; GFX9-NEXT:    v_mov_b32_e32 v4, s13396; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v03397; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v4, v1, vcc3398; GFX9-NEXT:    v_mov_b32_e32 v4, s23399; GFX9-NEXT:    v_mov_b32_e32 v5, s33400; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v4, v2, vcc3401; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v5, v3, vcc3402; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3403; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3404; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3405; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3406; GFX9-NEXT:    ; return to shader part epilog3407;3408; GFX10PLUS-LABEL: uaddsat_i128_sv:3409; GFX10PLUS:       ; %bb.0:3410; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, s0, v03411; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3412; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo3413; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo3414; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3415; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3416; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo3417; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo3418; GFX10PLUS-NEXT:    ; return to shader part epilog3419  %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)3420  %cast = bitcast i128 %result to <4 x float>3421  ret <4 x float> %cast3422}3423 3424define amdgpu_ps <4 x float> @uaddsat_i128_vs(i128 %lhs, i128 inreg %rhs) {3425; GFX6-LABEL: uaddsat_i128_vs:3426; GFX6:       ; %bb.0:3427; GFX6-NEXT:    v_mov_b32_e32 v4, s13428; GFX6-NEXT:    v_add_i32_e32 v0, vcc, s0, v03429; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc3430; GFX6-NEXT:    v_mov_b32_e32 v4, s23431; GFX6-NEXT:    v_mov_b32_e32 v5, s33432; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc3433; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc3434; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3435; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3436; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3437; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3438; GFX6-NEXT:    ; return to shader part epilog3439;3440; GFX8-LABEL: uaddsat_i128_vs:3441; GFX8:       ; %bb.0:3442; GFX8-NEXT:    v_mov_b32_e32 v4, s13443; GFX8-NEXT:    v_add_u32_e32 v0, vcc, s0, v03444; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v4, vcc3445; GFX8-NEXT:    v_mov_b32_e32 v4, s23446; GFX8-NEXT:    v_mov_b32_e32 v5, s33447; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, v2, v4, vcc3448; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, v3, v5, vcc3449; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3450; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3451; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3452; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3453; GFX8-NEXT:    ; return to shader part epilog3454;3455; GFX9-LABEL: uaddsat_i128_vs:3456; GFX9:       ; %bb.0:3457; GFX9-NEXT:    v_mov_b32_e32 v4, s13458; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, s0, v03459; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v4, vcc3460; GFX9-NEXT:    v_mov_b32_e32 v4, s23461; GFX9-NEXT:    v_mov_b32_e32 v5, s33462; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v2, v4, vcc3463; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v5, vcc3464; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3465; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3466; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3467; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3468; GFX9-NEXT:    ; return to shader part epilog3469;3470; GFX10PLUS-LABEL: uaddsat_i128_vs:3471; GFX10PLUS:       ; %bb.0:3472; GFX10PLUS-NEXT:    v_add_co_u32 v0, vcc_lo, v0, s03473; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3474; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo3475; GFX10PLUS-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo3476; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3477; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3478; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo3479; GFX10PLUS-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo3480; GFX10PLUS-NEXT:    ; return to shader part epilog3481  %result = call i128 @llvm.uadd.sat.i128(i128 %lhs, i128 %rhs)3482  %cast = bitcast i128 %result to <4 x float>3483  ret <4 x float> %cast3484}3485 3486define <2 x i128> @v_uaddsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {3487; GFX6-LABEL: v_uaddsat_v2i128:3488; GFX6:       ; %bb.0:3489; GFX6-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3490; GFX6-NEXT:    v_add_i32_e32 v0, vcc, v0, v83491; GFX6-NEXT:    v_addc_u32_e32 v1, vcc, v1, v9, vcc3492; GFX6-NEXT:    v_addc_u32_e32 v2, vcc, v2, v10, vcc3493; GFX6-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc3494; GFX6-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3495; GFX6-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3496; GFX6-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3497; GFX6-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3498; GFX6-NEXT:    v_add_i32_e32 v4, vcc, v4, v123499; GFX6-NEXT:    v_addc_u32_e32 v5, vcc, v5, v13, vcc3500; GFX6-NEXT:    v_addc_u32_e32 v6, vcc, v6, v14, vcc3501; GFX6-NEXT:    v_addc_u32_e32 v7, vcc, v7, v15, vcc3502; GFX6-NEXT:    v_cndmask_b32_e64 v4, v4, -1, vcc3503; GFX6-NEXT:    v_cndmask_b32_e64 v5, v5, -1, vcc3504; GFX6-NEXT:    v_cndmask_b32_e64 v6, v6, -1, vcc3505; GFX6-NEXT:    v_cndmask_b32_e64 v7, v7, -1, vcc3506; GFX6-NEXT:    s_setpc_b64 s[30:31]3507;3508; GFX8-LABEL: v_uaddsat_v2i128:3509; GFX8:       ; %bb.0:3510; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3511; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v83512; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v1, v9, vcc3513; GFX8-NEXT:    v_addc_u32_e32 v2, vcc, v2, v10, vcc3514; GFX8-NEXT:    v_addc_u32_e32 v3, vcc, v3, v11, vcc3515; GFX8-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3516; GFX8-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3517; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3518; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3519; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v123520; GFX8-NEXT:    v_addc_u32_e32 v5, vcc, v5, v13, vcc3521; GFX8-NEXT:    v_addc_u32_e32 v6, vcc, v6, v14, vcc3522; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v7, v15, vcc3523; GFX8-NEXT:    v_cndmask_b32_e64 v4, v4, -1, vcc3524; GFX8-NEXT:    v_cndmask_b32_e64 v5, v5, -1, vcc3525; GFX8-NEXT:    v_cndmask_b32_e64 v6, v6, -1, vcc3526; GFX8-NEXT:    v_cndmask_b32_e64 v7, v7, -1, vcc3527; GFX8-NEXT:    s_setpc_b64 s[30:31]3528;3529; GFX9-LABEL: v_uaddsat_v2i128:3530; GFX9:       ; %bb.0:3531; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3532; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v83533; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v1, v9, vcc3534; GFX9-NEXT:    v_addc_co_u32_e32 v2, vcc, v2, v10, vcc3535; GFX9-NEXT:    v_addc_co_u32_e32 v3, vcc, v3, v11, vcc3536; GFX9-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc3537; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc3538; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc3539; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc3540; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v123541; GFX9-NEXT:    v_addc_co_u32_e32 v5, vcc, v5, v13, vcc3542; GFX9-NEXT:    v_addc_co_u32_e32 v6, vcc, v6, v14, vcc3543; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v15, vcc3544; GFX9-NEXT:    v_cndmask_b32_e64 v4, v4, -1, vcc3545; GFX9-NEXT:    v_cndmask_b32_e64 v5, v5, -1, vcc3546; GFX9-NEXT:    v_cndmask_b32_e64 v6, v6, -1, vcc3547; GFX9-NEXT:    v_cndmask_b32_e64 v7, v7, -1, vcc3548; GFX9-NEXT:    s_setpc_b64 s[30:31]3549;3550; GFX10-LABEL: v_uaddsat_v2i128:3551; GFX10:       ; %bb.0:3552; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3553; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v83554; GFX10-NEXT:    v_add_co_u32 v4, s4, v4, v123555; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo3556; GFX10-NEXT:    v_add_co_ci_u32_e64 v5, s4, v5, v13, s43557; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo3558; GFX10-NEXT:    v_add_co_ci_u32_e64 v6, s4, v6, v14, s43559; GFX10-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo3560; GFX10-NEXT:    v_add_co_ci_u32_e64 v7, s4, v7, v15, s43561; GFX10-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3562; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3563; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo3564; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo3565; GFX10-NEXT:    v_cndmask_b32_e64 v4, v4, -1, s43566; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, -1, s43567; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, -1, s43568; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, -1, s43569; GFX10-NEXT:    s_setpc_b64 s[30:31]3570;3571; GFX11-LABEL: v_uaddsat_v2i128:3572; GFX11:       ; %bb.0:3573; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3574; GFX11-NEXT:    v_add_co_u32 v0, vcc_lo, v0, v83575; GFX11-NEXT:    v_add_co_u32 v4, s0, v4, v123576; GFX11-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo3577; GFX11-NEXT:    v_add_co_ci_u32_e64 v5, s0, v5, v13, s03578; GFX11-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo3579; GFX11-NEXT:    v_add_co_ci_u32_e64 v6, s0, v6, v14, s03580; GFX11-NEXT:    v_add_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo3581; GFX11-NEXT:    v_add_co_ci_u32_e64 v7, s0, v7, v15, s03582; GFX11-NEXT:    v_cndmask_b32_e64 v0, v0, -1, vcc_lo3583; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, -1, vcc_lo3584; GFX11-NEXT:    v_cndmask_b32_e64 v2, v2, -1, vcc_lo3585; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, -1, vcc_lo3586; GFX11-NEXT:    v_cndmask_b32_e64 v4, v4, -1, s03587; GFX11-NEXT:    v_cndmask_b32_e64 v5, v5, -1, s03588; GFX11-NEXT:    v_cndmask_b32_e64 v6, v6, -1, s03589; GFX11-NEXT:    v_cndmask_b32_e64 v7, v7, -1, s03590; GFX11-NEXT:    s_setpc_b64 s[30:31]3591  %result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)3592  ret <2 x i128> %result3593}3594 3595define amdgpu_ps <2 x i128> @s_uaddsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {3596; GFX6-LABEL: s_uaddsat_v2i128:3597; GFX6:       ; %bb.0:3598; GFX6-NEXT:    s_add_u32 s0, s0, s83599; GFX6-NEXT:    s_addc_u32 s1, s1, s93600; GFX6-NEXT:    s_addc_u32 s2, s2, s103601; GFX6-NEXT:    s_addc_u32 s3, s3, s113602; GFX6-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3603; GFX6-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3604; GFX6-NEXT:    s_add_u32 s4, s4, s123605; GFX6-NEXT:    s_addc_u32 s5, s5, s133606; GFX6-NEXT:    s_addc_u32 s6, s6, s143607; GFX6-NEXT:    s_addc_u32 s7, s7, s153608; GFX6-NEXT:    s_cselect_b64 s[4:5], -1, s[4:5]3609; GFX6-NEXT:    s_cselect_b64 s[6:7], -1, s[6:7]3610; GFX6-NEXT:    ; return to shader part epilog3611;3612; GFX8-LABEL: s_uaddsat_v2i128:3613; GFX8:       ; %bb.0:3614; GFX8-NEXT:    s_add_u32 s0, s0, s83615; GFX8-NEXT:    s_addc_u32 s1, s1, s93616; GFX8-NEXT:    s_addc_u32 s2, s2, s103617; GFX8-NEXT:    s_addc_u32 s3, s3, s113618; GFX8-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3619; GFX8-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3620; GFX8-NEXT:    s_add_u32 s4, s4, s123621; GFX8-NEXT:    s_addc_u32 s5, s5, s133622; GFX8-NEXT:    s_addc_u32 s6, s6, s143623; GFX8-NEXT:    s_addc_u32 s7, s7, s153624; GFX8-NEXT:    s_cselect_b64 s[4:5], -1, s[4:5]3625; GFX8-NEXT:    s_cselect_b64 s[6:7], -1, s[6:7]3626; GFX8-NEXT:    ; return to shader part epilog3627;3628; GFX9-LABEL: s_uaddsat_v2i128:3629; GFX9:       ; %bb.0:3630; GFX9-NEXT:    s_add_u32 s0, s0, s83631; GFX9-NEXT:    s_addc_u32 s1, s1, s93632; GFX9-NEXT:    s_addc_u32 s2, s2, s103633; GFX9-NEXT:    s_addc_u32 s3, s3, s113634; GFX9-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3635; GFX9-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3636; GFX9-NEXT:    s_add_u32 s4, s4, s123637; GFX9-NEXT:    s_addc_u32 s5, s5, s133638; GFX9-NEXT:    s_addc_u32 s6, s6, s143639; GFX9-NEXT:    s_addc_u32 s7, s7, s153640; GFX9-NEXT:    s_cselect_b64 s[4:5], -1, s[4:5]3641; GFX9-NEXT:    s_cselect_b64 s[6:7], -1, s[6:7]3642; GFX9-NEXT:    ; return to shader part epilog3643;3644; GFX10PLUS-LABEL: s_uaddsat_v2i128:3645; GFX10PLUS:       ; %bb.0:3646; GFX10PLUS-NEXT:    s_add_u32 s0, s0, s83647; GFX10PLUS-NEXT:    s_addc_u32 s1, s1, s93648; GFX10PLUS-NEXT:    s_addc_u32 s2, s2, s103649; GFX10PLUS-NEXT:    s_addc_u32 s3, s3, s113650; GFX10PLUS-NEXT:    s_cselect_b64 s[0:1], -1, s[0:1]3651; GFX10PLUS-NEXT:    s_cselect_b64 s[2:3], -1, s[2:3]3652; GFX10PLUS-NEXT:    s_add_u32 s4, s4, s123653; GFX10PLUS-NEXT:    s_addc_u32 s5, s5, s133654; GFX10PLUS-NEXT:    s_addc_u32 s6, s6, s143655; GFX10PLUS-NEXT:    s_addc_u32 s7, s7, s153656; GFX10PLUS-NEXT:    s_cselect_b64 s[4:5], -1, s[4:5]3657; GFX10PLUS-NEXT:    s_cselect_b64 s[6:7], -1, s[6:7]3658; GFX10PLUS-NEXT:    ; return to shader part epilog3659  %result = call <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)3660  ret <2 x i128> %result3661}3662 3663declare i7 @llvm.uadd.sat.i7(i7, i7) #03664declare i8 @llvm.uadd.sat.i8(i8, i8) #03665declare <2 x i8> @llvm.uadd.sat.v2i8(<2 x i8>, <2 x i8>) #03666declare <4 x i8> @llvm.uadd.sat.v4i8(<4 x i8>, <4 x i8>) #03667 3668declare i16 @llvm.uadd.sat.i16(i16, i16) #03669declare <2 x i16> @llvm.uadd.sat.v2i16(<2 x i16>, <2 x i16>) #03670declare <3 x i16> @llvm.uadd.sat.v3i16(<3 x i16>, <3 x i16>) #03671declare <4 x i16> @llvm.uadd.sat.v4i16(<4 x i16>, <4 x i16>) #03672declare <5 x i16> @llvm.uadd.sat.v5i16(<5 x i16>, <5 x i16>) #03673declare <6 x i16> @llvm.uadd.sat.v6i16(<6 x i16>, <6 x i16>) #03674declare <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16>, <8 x i16>) #03675 3676declare i24 @llvm.uadd.sat.i24(i24, i24) #03677 3678declare i32 @llvm.uadd.sat.i32(i32, i32) #03679declare <2 x i32> @llvm.uadd.sat.v2i32(<2 x i32>, <2 x i32>) #03680declare <3 x i32> @llvm.uadd.sat.v3i32(<3 x i32>, <3 x i32>) #03681declare <4 x i32> @llvm.uadd.sat.v4i32(<4 x i32>, <4 x i32>) #03682declare <5 x i32> @llvm.uadd.sat.v5i32(<5 x i32>, <5 x i32>) #03683declare <16 x i32> @llvm.uadd.sat.v16i32(<16 x i32>, <16 x i32>) #03684 3685declare i48 @llvm.uadd.sat.i48(i48, i48) #03686 3687declare i64 @llvm.uadd.sat.i64(i64, i64) #03688declare <2 x i64> @llvm.uadd.sat.v2i64(<2 x i64>, <2 x i64>) #03689 3690declare i128 @llvm.uadd.sat.i128(i128, i128) #03691declare <2 x i128> @llvm.uadd.sat.v2i128(<2 x i128>, <2 x i128>) #03692 3693attributes #0 = { nounwind readnone speculatable willreturn }3694