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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - < %s | FileCheck --check-prefixes=GCN %s3; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - < %s | FileCheck --check-prefixes=GCN %s4; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - < %s | FileCheck --check-prefixes=GCN %s5 6; Test vector bitfield extract.7define i32 @v_srl_mask_i32(i32 %value) {8; GCN-LABEL: v_srl_mask_i32:9; GCN: ; %bb.0:10; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GCN-NEXT: v_bfe_u32 v0, v0, 8, 512; GCN-NEXT: s_setpc_b64 s[30:31]13 %1 = lshr i32 %value, 814 %2 = and i32 %1, 3115 ret i32 %216}17 18; Test scalar bitfield extract.19define amdgpu_ps i32 @s_srl_mask_i32(i32 inreg %value) {20; GCN-LABEL: s_srl_mask_i32:21; GCN: ; %bb.0:22; GCN-NEXT: s_bfe_u32 s0, s0, 0x5000823; GCN-NEXT: ; return to shader part epilog24 %1 = lshr i32 %value, 825 %2 = and i32 %1, 3126 ret i32 %227}28 29; Don't generate G_UBFX if the offset + width is too big.30define amdgpu_ps i32 @s_srl_big_mask_i32(i32 inreg %value) {31; GCN-LABEL: s_srl_big_mask_i32:32; GCN: ; %bb.0:33; GCN-NEXT: s_lshr_b32 s0, s0, 3034; GCN-NEXT: ; return to shader part epilog35 %1 = lshr i32 %value, 3036 %2 = and i32 %1, 3137 ret i32 %238}39 40; Test vector bitfield extract.41define i32 @v_mask_srl_i32(i32 %value) {42; GCN-LABEL: v_mask_srl_i32:43; GCN: ; %bb.0:44; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)45; GCN-NEXT: v_bfe_u32 v0, v0, 8, 546; GCN-NEXT: s_setpc_b64 s[30:31]47 %1 = and i32 %value, 7936 ; 31 << 848 %2 = lshr i32 %1, 849 ret i32 %250}51 52; Test scalar bitfield extract.53define amdgpu_ps i32 @s_mask_srl_i32(i32 inreg %value) {54; GCN-LABEL: s_mask_srl_i32:55; GCN: ; %bb.0:56; GCN-NEXT: s_bfe_u32 s0, s0, 0x5000857; GCN-NEXT: ; return to shader part epilog58 %1 = and i32 %value, 7936 ; 31 << 859 %2 = lshr i32 %1, 860 ret i32 %261}62 63; Test vector bitfield extract for 64-bits.64define i64 @v_srl_mask_i64(i64 %value) {65; GCN-LABEL: v_srl_mask_i64:66; GCN: ; %bb.0:67; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)68; GCN-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]69; GCN-NEXT: v_mov_b32_e32 v1, 070; GCN-NEXT: v_bfe_u32 v0, v0, 0, 1071; GCN-NEXT: s_setpc_b64 s[30:31]72 %1 = lshr i64 %value, 2573 %2 = and i64 %1, 102374 ret i64 %275}76 77; Test scalar bitfield extract for 64-bits.78define amdgpu_ps i64 @s_srl_mask_i64(i64 inreg %value) {79; GCN-LABEL: s_srl_mask_i64:80; GCN: ; %bb.0:81; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa001982; GCN-NEXT: ; return to shader part epilog83 %1 = lshr i64 %value, 2584 %2 = and i64 %1, 102385 ret i64 %286}87 88; Don't generate G_UBFX if the offset + width is too big.89define amdgpu_ps i64 @s_srl_big_mask_i64(i64 inreg %value) {90; GCN-LABEL: s_srl_big_mask_i64:91; GCN: ; %bb.0:92; GCN-NEXT: s_lshr_b32 s0, s1, 2893; GCN-NEXT: s_mov_b32 s1, 094; GCN-NEXT: ; return to shader part epilog95 %1 = lshr i64 %value, 6096 %2 = and i64 %1, 6397 ret i64 %298}99 100; Test vector bitfield extract for 64-bits.101; TODO: No need for a 64-bit shift instruction when the extracted value is102; entirely contained within the upper or lower half.103define i64 @v_mask_srl_i64(i64 %value) {104; GCN-LABEL: v_mask_srl_i64:105; GCN: ; %bb.0:106; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)107; GCN-NEXT: v_lshrrev_b64 v[0:1], 25, v[0:1]108; GCN-NEXT: v_mov_b32_e32 v1, 0109; GCN-NEXT: v_bfe_u32 v0, v0, 0, 10110; GCN-NEXT: s_setpc_b64 s[30:31]111 %1 = and i64 %value, 34326183936 ; 1023 << 25112 %2 = lshr i64 %1, 25113 ret i64 %2114}115 116; Test scalar bitfield extract for 64-bits.117define amdgpu_ps i64 @s_mask_srl_i64(i64 inreg %value) {118; GCN-LABEL: s_mask_srl_i64:119; GCN: ; %bb.0:120; GCN-NEXT: s_bfe_u64 s[0:1], s[0:1], 0xa0019121; GCN-NEXT: ; return to shader part epilog122 %1 = and i64 %value, 34326183936 ; 1023 << 25123 %2 = lshr i64 %1, 25124 ret i64 %2125}126