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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s4 5; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.6 7define i32 @v_udiv_i32(i32 %num, i32 %den) {8; GISEL-LABEL: v_udiv_i32:9; GISEL: ; %bb.0:10; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v112; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v113; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v214; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v215; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v216; GISEL-NEXT: v_mul_lo_u32 v3, v3, v217; GISEL-NEXT: v_mul_hi_u32 v3, v2, v318; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v319; GISEL-NEXT: v_mul_hi_u32 v2, v0, v220; GISEL-NEXT: v_mul_lo_u32 v3, v2, v121; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v222; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v323; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v124; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc25; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v126; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc27; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v228; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v129; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc30; GISEL-NEXT: s_setpc_b64 s[30:31]31;32; CGP-LABEL: v_udiv_i32:33; CGP: ; %bb.0:34; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)35; CGP-NEXT: v_cvt_f32_u32_e32 v2, v136; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v137; CGP-NEXT: v_rcp_f32_e32 v2, v238; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v239; CGP-NEXT: v_cvt_u32_f32_e32 v2, v240; CGP-NEXT: v_mul_lo_u32 v3, v3, v241; CGP-NEXT: v_mul_hi_u32 v3, v2, v342; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v343; CGP-NEXT: v_mul_hi_u32 v2, v0, v244; CGP-NEXT: v_mul_lo_u32 v3, v2, v145; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v246; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v347; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v148; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc49; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v150; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc51; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v252; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v153; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc54; CGP-NEXT: s_setpc_b64 s[30:31]55 %result = udiv i32 %num, %den56 ret i32 %result57}58 59; FIXME: This is a workaround for not handling uniform VGPR case.60declare i32 @llvm.amdgcn.readfirstlane(i32)61 62define amdgpu_ps i32 @s_udiv_i32(i32 inreg %num, i32 inreg %den) {63; GISEL-LABEL: s_udiv_i32:64; GISEL: ; %bb.0:65; GISEL-NEXT: v_cvt_f32_u32_e32 v0, s166; GISEL-NEXT: s_sub_i32 s2, 0, s167; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v068; GISEL-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v069; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v070; GISEL-NEXT: v_mul_lo_u32 v1, s2, v071; GISEL-NEXT: v_mul_hi_u32 v1, v0, v172; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v173; GISEL-NEXT: v_mul_hi_u32 v0, s0, v074; GISEL-NEXT: v_mul_lo_u32 v1, v0, s175; GISEL-NEXT: v_add_i32_e32 v2, vcc, 1, v076; GISEL-NEXT: v_sub_i32_e32 v1, vcc, s0, v177; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v178; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc79; GISEL-NEXT: v_subrev_i32_e64 v2, s[2:3], s1, v180; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc81; GISEL-NEXT: v_add_i32_e32 v2, vcc, 1, v082; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v183; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc84; GISEL-NEXT: v_readfirstlane_b32 s0, v085; GISEL-NEXT: ; return to shader part epilog86;87; CGP-LABEL: s_udiv_i32:88; CGP: ; %bb.0:89; CGP-NEXT: v_cvt_f32_u32_e32 v0, s190; CGP-NEXT: s_sub_i32 s2, 0, s191; CGP-NEXT: v_rcp_f32_e32 v0, v092; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v093; CGP-NEXT: v_cvt_u32_f32_e32 v0, v094; CGP-NEXT: v_mul_lo_u32 v1, s2, v095; CGP-NEXT: v_mul_hi_u32 v1, v0, v196; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v197; CGP-NEXT: v_mul_hi_u32 v0, s0, v098; CGP-NEXT: v_mul_lo_u32 v1, v0, s199; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0100; CGP-NEXT: v_sub_i32_e32 v1, vcc, s0, v1101; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v1102; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc103; CGP-NEXT: v_subrev_i32_e64 v2, s[2:3], s1, v1104; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc105; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0106; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v1107; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc108; CGP-NEXT: v_readfirstlane_b32 s0, v0109; CGP-NEXT: ; return to shader part epilog110 %result = udiv i32 %num, %den111 %readlane = call i32 @llvm.amdgcn.readfirstlane(i32 %result)112 ret i32 %readlane113}114 115define <2 x i32> @v_udiv_v2i32(<2 x i32> %num, <2 x i32> %den) {116; GISEL-LABEL: v_udiv_v2i32:117; GISEL: ; %bb.0:118; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)119; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2120; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2121; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3122; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3123; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4124; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6125; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4126; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6127; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4128; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6129; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4130; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6131; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5132; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7133; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5134; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7135; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4136; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5137; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2138; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4139; GISEL-NEXT: v_mul_lo_u32 v8, v5, v3140; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v5141; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6142; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8143; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2144; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc145; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2146; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3147; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]148; GISEL-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3149; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc150; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4151; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]152; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5153; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2154; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc155; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3156; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc157; GISEL-NEXT: s_setpc_b64 s[30:31]158;159; CGP-LABEL: v_udiv_v2i32:160; CGP: ; %bb.0:161; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2163; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2164; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3165; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3166; CGP-NEXT: v_rcp_f32_e32 v4, v4167; CGP-NEXT: v_rcp_f32_e32 v6, v6168; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4169; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6170; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4171; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6172; CGP-NEXT: v_mul_lo_u32 v5, v5, v4173; CGP-NEXT: v_mul_lo_u32 v7, v7, v6174; CGP-NEXT: v_mul_hi_u32 v5, v4, v5175; CGP-NEXT: v_mul_hi_u32 v7, v6, v7176; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5177; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7178; CGP-NEXT: v_mul_hi_u32 v4, v0, v4179; CGP-NEXT: v_mul_hi_u32 v5, v1, v5180; CGP-NEXT: v_mul_lo_u32 v6, v4, v2181; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4182; CGP-NEXT: v_mul_lo_u32 v8, v5, v3183; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5184; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6185; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8186; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2187; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc188; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2189; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3190; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]191; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3192; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc193; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4194; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]195; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5196; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2197; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc198; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3199; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc200; CGP-NEXT: s_setpc_b64 s[30:31]201 %result = udiv <2 x i32> %num, %den202 ret <2 x i32> %result203}204 205define i32 @v_udiv_i32_pow2k_denom(i32 %num) {206; CHECK-LABEL: v_udiv_i32_pow2k_denom:207; CHECK: ; %bb.0:208; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; CHECK-NEXT: v_lshrrev_b32_e32 v0, 12, v0210; CHECK-NEXT: s_setpc_b64 s[30:31]211 %result = udiv i32 %num, 4096212 ret i32 %result213}214 215define <2 x i32> @v_udiv_v2i32_pow2k_denom(<2 x i32> %num) {216; CHECK-LABEL: v_udiv_v2i32_pow2k_denom:217; CHECK: ; %bb.0:218; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)219; CHECK-NEXT: v_lshrrev_b32_e32 v0, 12, v0220; CHECK-NEXT: v_lshrrev_b32_e32 v1, 12, v1221; CHECK-NEXT: s_setpc_b64 s[30:31]222 %result = udiv <2 x i32> %num, <i32 4096, i32 4096>223 ret <2 x i32> %result224}225 226define i32 @v_udiv_i32_oddk_denom(i32 %num) {227; CHECK-LABEL: v_udiv_i32_oddk_denom:228; CHECK: ; %bb.0:229; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)230; CHECK-NEXT: v_mov_b32_e32 v1, 0xb2a50881231; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1232; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1233; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0234; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v1235; CHECK-NEXT: v_lshrrev_b32_e32 v0, 20, v0236; CHECK-NEXT: s_setpc_b64 s[30:31]237 %result = udiv i32 %num, 1235195238 ret i32 %result239}240 241define <2 x i32> @v_udiv_v2i32_oddk_denom(<2 x i32> %num) {242; CHECK-LABEL: v_udiv_v2i32_oddk_denom:243; CHECK: ; %bb.0:244; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; CHECK-NEXT: v_mov_b32_e32 v2, 0xb2a50881246; CHECK-NEXT: v_mul_hi_u32 v3, v0, v2247; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2248; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3249; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v2250; CHECK-NEXT: v_lshrrev_b32_e32 v0, 1, v0251; CHECK-NEXT: v_lshrrev_b32_e32 v1, 1, v1252; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3253; CHECK-NEXT: v_add_i32_e32 v1, vcc, v1, v2254; CHECK-NEXT: v_lshrrev_b32_e32 v0, 20, v0255; CHECK-NEXT: v_lshrrev_b32_e32 v1, 20, v1256; CHECK-NEXT: s_setpc_b64 s[30:31]257 %result = udiv <2 x i32> %num, <i32 1235195, i32 1235195>258 ret <2 x i32> %result259}260 261define i32 @v_udiv_i32_pow2_shl_denom(i32 %x, i32 %y) {262; CHECK-LABEL: v_udiv_i32_pow2_shl_denom:263; CHECK: ; %bb.0:264; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; CHECK-NEXT: v_lshl_b32_e32 v1, 0x1000, v1266; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1267; CHECK-NEXT: v_sub_i32_e32 v3, vcc, 0, v1268; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2269; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2270; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2271; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2272; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3273; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3274; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2275; CHECK-NEXT: v_mul_lo_u32 v3, v2, v1276; CHECK-NEXT: v_add_i32_e32 v4, vcc, 1, v2277; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v3278; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1279; CHECK-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc280; CHECK-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1281; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc282; CHECK-NEXT: v_add_i32_e32 v3, vcc, 1, v2283; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1284; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc285; CHECK-NEXT: s_setpc_b64 s[30:31]286 %shl.y = shl i32 4096, %y287 %r = udiv i32 %x, %shl.y288 ret i32 %r289}290 291define <2 x i32> @v_udiv_v2i32_pow2_shl_denom(<2 x i32> %x, <2 x i32> %y) {292; GISEL-LABEL: v_udiv_v2i32_pow2_shl_denom:293; GISEL: ; %bb.0:294; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)295; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2296; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3297; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2298; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2299; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3300; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3301; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4302; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6303; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4304; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6305; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4306; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6307; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4308; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6309; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5310; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7311; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5312; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7313; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4314; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5315; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2316; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4317; GISEL-NEXT: v_mul_lo_u32 v8, v5, v3318; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v5319; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6320; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8321; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2322; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc323; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2324; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3325; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]326; GISEL-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3327; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc328; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4329; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]330; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5331; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2332; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc333; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3334; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc335; GISEL-NEXT: s_setpc_b64 s[30:31]336;337; CGP-LABEL: v_udiv_v2i32_pow2_shl_denom:338; CGP: ; %bb.0:339; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)340; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2341; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3342; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2343; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2344; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3345; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3346; CGP-NEXT: v_rcp_f32_e32 v4, v4347; CGP-NEXT: v_rcp_f32_e32 v6, v6348; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4349; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6350; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4351; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6352; CGP-NEXT: v_mul_lo_u32 v5, v5, v4353; CGP-NEXT: v_mul_lo_u32 v7, v7, v6354; CGP-NEXT: v_mul_hi_u32 v5, v4, v5355; CGP-NEXT: v_mul_hi_u32 v7, v6, v7356; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5357; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7358; CGP-NEXT: v_mul_hi_u32 v4, v0, v4359; CGP-NEXT: v_mul_hi_u32 v5, v1, v5360; CGP-NEXT: v_mul_lo_u32 v6, v4, v2361; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4362; CGP-NEXT: v_mul_lo_u32 v8, v5, v3363; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5364; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6365; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8366; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2367; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc368; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2369; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3370; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]371; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3372; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc373; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4374; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]375; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5376; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2377; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc378; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3379; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc380; CGP-NEXT: s_setpc_b64 s[30:31]381 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y382 %r = udiv <2 x i32> %x, %shl.y383 ret <2 x i32> %r384}385 386define i32 @v_udiv_i32_24bit(i32 %num, i32 %den) {387; GISEL-LABEL: v_udiv_i32_24bit:388; GISEL: ; %bb.0:389; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)390; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0391; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1392; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1393; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1394; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2395; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2396; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2397; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2398; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3399; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3400; GISEL-NEXT: v_mul_hi_u32 v2, v0, v2401; GISEL-NEXT: v_mul_lo_u32 v3, v2, v1402; GISEL-NEXT: v_add_i32_e32 v4, vcc, 1, v2403; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v3404; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1405; GISEL-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc406; GISEL-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1407; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc408; GISEL-NEXT: v_add_i32_e32 v3, vcc, 1, v2409; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1410; GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc411; GISEL-NEXT: s_setpc_b64 s[30:31]412;413; CGP-LABEL: v_udiv_i32_24bit:414; CGP: ; %bb.0:415; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0417; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1418; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0419; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1420; CGP-NEXT: v_rcp_f32_e32 v2, v1421; CGP-NEXT: v_mul_f32_e32 v2, v0, v2422; CGP-NEXT: v_trunc_f32_e32 v2, v2423; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0424; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2425; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v1426; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]427; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0428; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0429; CGP-NEXT: s_setpc_b64 s[30:31]430 %num.mask = and i32 %num, 16777215431 %den.mask = and i32 %den, 16777215432 %result = udiv i32 %num.mask, %den.mask433 ret i32 %result434}435 436define <2 x i32> @v_udiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {437; GISEL-LABEL: v_udiv_v2i32_24bit:438; GISEL: ; %bb.0:439; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)440; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0441; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1442; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2443; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3444; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2445; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2446; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3447; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3448; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4449; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6450; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4451; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6452; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4453; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6454; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4455; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6456; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5457; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7458; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5459; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7460; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4461; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5462; GISEL-NEXT: v_mul_lo_u32 v6, v4, v2463; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v4464; GISEL-NEXT: v_mul_lo_u32 v8, v5, v3465; GISEL-NEXT: v_add_i32_e32 v9, vcc, 1, v5466; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v6467; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v8468; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2469; GISEL-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc470; GISEL-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2471; GISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3472; GISEL-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5]473; GISEL-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3474; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc475; GISEL-NEXT: v_add_i32_e32 v6, vcc, 1, v4476; GISEL-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5]477; GISEL-NEXT: v_add_i32_e32 v7, vcc, 1, v5478; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2479; GISEL-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc480; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3481; GISEL-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc482; GISEL-NEXT: s_setpc_b64 s[30:31]483;484; CGP-LABEL: v_udiv_v2i32_24bit:485; CGP: ; %bb.0:486; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)487; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0488; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1489; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2490; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3491; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0492; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2493; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1494; CGP-NEXT: v_cvt_f32_u32_e32 v3, v3495; CGP-NEXT: v_rcp_f32_e32 v4, v2496; CGP-NEXT: v_rcp_f32_e32 v5, v3497; CGP-NEXT: v_mul_f32_e32 v4, v0, v4498; CGP-NEXT: v_mul_f32_e32 v5, v1, v5499; CGP-NEXT: v_trunc_f32_e32 v4, v4500; CGP-NEXT: v_trunc_f32_e32 v5, v5501; CGP-NEXT: v_fma_f32 v0, -v4, v2, v0502; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4503; CGP-NEXT: v_fma_f32 v1, -v5, v3, v1504; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5505; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v2506; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]507; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, v3508; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]509; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0510; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1511; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0512; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1513; CGP-NEXT: s_setpc_b64 s[30:31]514 %num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>515 %den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>516 %result = udiv <2 x i32> %num.mask, %den.mask517 ret <2 x i32> %result518}519