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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=tonga < %s | FileCheck --check-prefix=GFX8 %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s4; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -amdgpu-bypass-slow-div=0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefix=GFX10 %s5 6define amdgpu_kernel void @udivrem_i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i32 %x, i32 %y) {7; GFX8-LABEL: udivrem_i32:8; GFX8:       ; %bb.0:9; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x1010; GFX8-NEXT:    s_add_i32 s12, s12, s1711; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s1312; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 813; GFX8-NEXT:    s_waitcnt lgkmcnt(0)14; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s515; GFX8-NEXT:    s_sub_i32 s0, 0, s516; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v017; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v018; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v019; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v020; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x021; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v122; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v123; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v024; GFX8-NEXT:    s_waitcnt lgkmcnt(0)25; GFX8-NEXT:    v_mov_b32_e32 v0, s026; GFX8-NEXT:    v_mov_b32_e32 v1, s127; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s528; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v229; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v330; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v331; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc32; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v333; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc34; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v235; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v336; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc37; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v338; GFX8-NEXT:    flat_store_dword v[0:1], v239; GFX8-NEXT:    v_mov_b32_e32 v0, s240; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc41; GFX8-NEXT:    v_mov_b32_e32 v1, s342; GFX8-NEXT:    flat_store_dword v[0:1], v343; GFX8-NEXT:    s_endpgm44;45; GFX9-LABEL: udivrem_i32:46; GFX9:       ; %bb.0:47; GFX9-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x1048; GFX9-NEXT:    v_mov_b32_e32 v2, 049; GFX9-NEXT:    s_waitcnt lgkmcnt(0)50; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s551; GFX9-NEXT:    s_sub_i32 s0, 0, s552; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v053; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v054; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v055; GFX9-NEXT:    v_mul_lo_u32 v1, s0, v056; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x057; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v158; GFX9-NEXT:    v_add_u32_e32 v0, v0, v159; GFX9-NEXT:    v_mul_hi_u32 v0, s4, v060; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s561; GFX9-NEXT:    v_add_u32_e32 v3, 1, v062; GFX9-NEXT:    v_sub_u32_e32 v1, s4, v163; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v164; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc65; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v166; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc67; GFX9-NEXT:    v_add_u32_e32 v3, 1, v068; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v169; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc70; GFX9-NEXT:    v_subrev_u32_e32 v3, s5, v171; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc72; GFX9-NEXT:    s_waitcnt lgkmcnt(0)73; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]74; GFX9-NEXT:    global_store_dword v2, v1, s[2:3]75; GFX9-NEXT:    s_endpgm76;77; GFX10-LABEL: udivrem_i32:78; GFX10:       ; %bb.0:79; GFX10-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x1080; GFX10-NEXT:    s_waitcnt lgkmcnt(0)81; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s582; GFX10-NEXT:    s_sub_i32 s0, 0, s583; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v084; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v085; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v086; GFX10-NEXT:    v_mul_lo_u32 v1, s0, v087; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x088; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v189; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v190; GFX10-NEXT:    v_mul_hi_u32 v0, s4, v091; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s592; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v093; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s4, v194; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v195; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v196; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo97; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo98; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v099; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s5, v1100; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s5, v1101; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo102; GFX10-NEXT:    v_mov_b32_e32 v2, 0103; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo104; GFX10-NEXT:    s_waitcnt lgkmcnt(0)105; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]106; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]107; GFX10-NEXT:    s_endpgm108  %div = udiv i32 %x, %y109  store i32 %div, ptr addrspace(1) %out0110  %rem = urem i32 %x, %y111  store i32 %rem, ptr addrspace(1) %out1112  ret void113}114 115define amdgpu_kernel void @udivrem_i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i64 %x, i64 %y) {116; GFX8-LABEL: udivrem_i64:117; GFX8:       ; %bb.0:118; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[8:9], 0x0119; GFX8-NEXT:    s_add_i32 s12, s12, s17120; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8121; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13122; GFX8-NEXT:    s_waitcnt lgkmcnt(0)123; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s11124; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s10125; GFX8-NEXT:    s_sub_u32 s2, 0, s10126; GFX8-NEXT:    s_subb_u32 s3, 0, s11127; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0128; GFX8-NEXT:    v_add_f32_e32 v0, v0, v1129; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0130; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0131; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0132; GFX8-NEXT:    v_trunc_f32_e32 v1, v1133; GFX8-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v1134; GFX8-NEXT:    v_add_f32_e32 v0, v2, v0135; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v0136; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v1137; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 0138; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]139; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v0140; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]141; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v0142; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v0143; GFX8-NEXT:    v_mul_lo_u32 v3, v6, v4144; GFX8-NEXT:    v_mul_lo_u32 v5, v7, v4145; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v4146; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3147; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc148; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v5, v0149; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc150; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2151; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc152; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v8153; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc154; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1155; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v2156; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v4157; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1158; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc159; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1160; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1161; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v0162; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc163; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 0164; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]165; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v0166; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]167; GFX8-NEXT:    v_mul_hi_u32 v3, v6, v0168; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v0169; GFX8-NEXT:    v_mul_lo_u32 v2, v6, v4170; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v2171; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc172; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3173; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc174; GFX8-NEXT:    v_mul_lo_u32 v3, v7, v4175; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1176; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v4177; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v0178; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc179; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2180; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc181; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2182; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v4183; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v1184; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc185; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v1186; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v1187; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v0188; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc189; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v0190; GFX8-NEXT:    v_mul_lo_u32 v3, s8, v1191; GFX8-NEXT:    v_mul_hi_u32 v4, s8, v0192; GFX8-NEXT:    v_mul_hi_u32 v0, s9, v0193; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v3194; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc195; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v4196; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc197; GFX8-NEXT:    v_mul_lo_u32 v4, s9, v1198; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v2199; GFX8-NEXT:    v_mul_hi_u32 v3, s8, v1200; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v0201; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc202; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v3203; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc204; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v3205; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v0, v2206; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc207; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v0208; GFX8-NEXT:    v_mul_hi_u32 v3, s9, v1209; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s10, v6, 0210; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v3, v2211; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s10, v7, v[1:2]212; GFX8-NEXT:    v_mov_b32_e32 v1, s11213; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s11, v6, v[2:3]214; GFX8-NEXT:    v_mov_b32_e32 v2, s9215; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s8, v0216; GFX8-NEXT:    v_subb_u32_e64 v5, s[0:1], v2, v4, vcc217; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], s9, v4218; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v5219; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]220; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v3221; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]222; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v5223; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v1, vcc224; GFX8-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]225; GFX8-NEXT:    v_subrev_u32_e32 v4, vcc, s10, v3226; GFX8-NEXT:    v_subbrev_u32_e64 v8, s[0:1], 0, v0, vcc227; GFX8-NEXT:    v_add_u32_e64 v9, s[0:1], 1, v6228; GFX8-NEXT:    v_addc_u32_e64 v10, s[0:1], 0, v7, s[0:1]229; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s11, v8230; GFX8-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s[0:1]231; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s10, v4232; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v1, vcc233; GFX8-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]234; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s11, v8235; GFX8-NEXT:    v_subrev_u32_e32 v14, vcc, s10, v4236; GFX8-NEXT:    v_cndmask_b32_e64 v11, v11, v12, s[0:1]237; GFX8-NEXT:    v_add_u32_e64 v12, s[0:1], 1, v9238; GFX8-NEXT:    v_subbrev_u32_e32 v15, vcc, 0, v0, vcc239; GFX8-NEXT:    v_addc_u32_e64 v13, s[0:1], 0, v10, s[0:1]240; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11241; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2242; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v14, vcc243; GFX8-NEXT:    v_cndmask_b32_e32 v4, v8, v15, vcc244; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v12, vcc245; GFX8-NEXT:    v_cndmask_b32_e32 v1, v10, v13, vcc246; GFX8-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[0:1]247; GFX8-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]248; GFX8-NEXT:    v_mov_b32_e32 v4, s4249; GFX8-NEXT:    v_cndmask_b32_e64 v0, v6, v0, s[0:1]250; GFX8-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s[0:1]251; GFX8-NEXT:    v_mov_b32_e32 v5, s5252; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]253; GFX8-NEXT:    v_mov_b32_e32 v0, s6254; GFX8-NEXT:    v_mov_b32_e32 v1, s7255; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]256; GFX8-NEXT:    s_endpgm257;258; GFX9-LABEL: udivrem_i64:259; GFX9:       ; %bb.0:260; GFX9-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0261; GFX9-NEXT:    s_waitcnt lgkmcnt(0)262; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s19263; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s18264; GFX9-NEXT:    s_sub_u32 s2, 0, s18265; GFX9-NEXT:    s_subb_u32 s3, 0, s19266; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0267; GFX9-NEXT:    v_add_f32_e32 v0, v0, v1268; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0269; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0270; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0271; GFX9-NEXT:    v_trunc_f32_e32 v1, v1272; GFX9-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v1273; GFX9-NEXT:    v_add_f32_e32 v0, v2, v0274; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v0275; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v1276; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 0277; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]278; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v0279; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]280; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v0281; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v0282; GFX9-NEXT:    v_mul_lo_u32 v3, v6, v4283; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v4284; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v4285; GFX9-NEXT:    v_mul_hi_u32 v4, v7, v4286; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v3287; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc288; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v5, v0289; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc290; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v2291; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc292; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v8293; GFX9-NEXT:    v_add_u32_e32 v1, v3, v1294; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc295; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1296; GFX9-NEXT:    v_add_u32_e32 v2, v5, v2297; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc298; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v4299; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v0300; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v1, vcc301; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 0302; GFX9-NEXT:    v_mov_b32_e32 v8, 0303; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]304; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v0305; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]306; GFX9-NEXT:    v_mul_hi_u32 v3, v6, v0307; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v0308; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v4309; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v2310; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc311; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v3312; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc313; GFX9-NEXT:    v_mul_lo_u32 v3, v7, v4314; GFX9-NEXT:    v_add_u32_e32 v1, v2, v1315; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v4316; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v0317; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc318; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v2319; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc320; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2321; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v4322; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v1323; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc324; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v3325; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v0326; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v1, vcc327; GFX9-NEXT:    v_mul_lo_u32 v2, s17, v0328; GFX9-NEXT:    v_mul_lo_u32 v3, s16, v1329; GFX9-NEXT:    v_mul_hi_u32 v4, s16, v0330; GFX9-NEXT:    v_mul_hi_u32 v0, s17, v0331; GFX9-NEXT:    v_mul_hi_u32 v5, s17, v1332; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v3333; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc334; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v4335; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc336; GFX9-NEXT:    v_mul_lo_u32 v4, s17, v1337; GFX9-NEXT:    v_add_u32_e32 v2, v3, v2338; GFX9-NEXT:    v_mul_hi_u32 v3, s16, v1339; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v0340; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc341; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v3342; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc343; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v0, v2344; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s18, v6, 0345; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc346; GFX9-NEXT:    v_add_u32_e32 v3, v4, v3347; GFX9-NEXT:    v_add3_u32 v7, v3, v2, v5348; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s18, v7, v[1:2]349; GFX9-NEXT:    v_mov_b32_e32 v1, s19350; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s19, v6, v[2:3]351; GFX9-NEXT:    v_mov_b32_e32 v2, s17352; GFX9-NEXT:    v_sub_co_u32_e32 v3, vcc, s16, v0353; GFX9-NEXT:    v_subb_co_u32_e64 v5, s[0:1], v2, v4, vcc354; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s19, v5355; GFX9-NEXT:    v_sub_u32_e32 v0, s17, v4356; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s[0:1]357; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s18, v3358; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]359; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s19, v5360; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v1, vcc361; GFX9-NEXT:    v_cndmask_b32_e64 v2, v2, v4, s[0:1]362; GFX9-NEXT:    v_subrev_co_u32_e32 v4, vcc, s18, v3363; GFX9-NEXT:    v_subbrev_co_u32_e64 v9, s[0:1], 0, v0, vcc364; GFX9-NEXT:    v_add_co_u32_e64 v10, s[0:1], 1, v6365; GFX9-NEXT:    v_addc_co_u32_e64 v11, s[0:1], 0, v7, s[0:1]366; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s19, v9367; GFX9-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s[0:1]368; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s18, v4369; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v1, vcc370; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]371; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s19, v9372; GFX9-NEXT:    v_subrev_co_u32_e32 v15, vcc, s18, v4373; GFX9-NEXT:    v_cndmask_b32_e64 v12, v12, v13, s[0:1]374; GFX9-NEXT:    v_add_co_u32_e64 v13, s[0:1], 1, v10375; GFX9-NEXT:    v_subbrev_co_u32_e32 v16, vcc, 0, v0, vcc376; GFX9-NEXT:    v_addc_co_u32_e64 v14, s[0:1], 0, v11, s[0:1]377; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12378; GFX9-NEXT:    v_cndmask_b32_e32 v0, v10, v13, vcc379; GFX9-NEXT:    v_cndmask_b32_e32 v1, v11, v14, vcc380; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v2381; GFX9-NEXT:    v_cndmask_b32_e64 v0, v6, v0, s[0:1]382; GFX9-NEXT:    v_cndmask_b32_e64 v1, v7, v1, s[0:1]383; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v15, vcc384; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v16, vcc385; GFX9-NEXT:    v_cndmask_b32_e64 v2, v3, v2, s[0:1]386; GFX9-NEXT:    v_cndmask_b32_e64 v3, v5, v4, s[0:1]387; GFX9-NEXT:    global_store_dwordx2 v8, v[0:1], s[12:13]388; GFX9-NEXT:    global_store_dwordx2 v8, v[2:3], s[14:15]389; GFX9-NEXT:    s_endpgm390;391; GFX10-LABEL: udivrem_i64:392; GFX10:       ; %bb.0:393; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0394; GFX10-NEXT:    s_waitcnt lgkmcnt(0)395; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s19396; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s18397; GFX10-NEXT:    s_sub_u32 s0, 0, s18398; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v0399; GFX10-NEXT:    v_add_f32_e32 v0, v0, v1400; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0401; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v0402; GFX10-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v0403; GFX10-NEXT:    v_trunc_f32_e32 v2, v1404; GFX10-NEXT:    v_mul_f32_e32 v1, 0xcf800000, v2405; GFX10-NEXT:    v_cvt_u32_f32_e32 v4, v2406; GFX10-NEXT:    v_add_f32_e32 v0, v1, v0407; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v0408; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s1, s0, v3, 0409; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s1, s0, v4, v[1:2]410; GFX10-NEXT:    s_subb_u32 s1, 0, s19411; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v0412; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s2, s1, v3, v[1:2]413; GFX10-NEXT:    v_mul_lo_u32 v2, v4, v0414; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0415; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1416; GFX10-NEXT:    v_mul_lo_u32 v7, v4, v1417; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1418; GFX10-NEXT:    v_mul_hi_u32 v1, v4, v1419; GFX10-NEXT:    v_add_co_u32 v2, s2, v2, v5420; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s2421; GFX10-NEXT:    v_add_co_u32 v6, s2, v7, v6422; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s2423; GFX10-NEXT:    v_add_co_u32 v0, s2, v2, v0424; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s2425; GFX10-NEXT:    v_add_co_u32 v2, s2, v6, v8426; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s2427; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0428; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6429; GFX10-NEXT:    v_add_co_u32 v0, s2, v2, v0430; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s2431; GFX10-NEXT:    v_add_co_u32 v3, vcc_lo, v3, v0432; GFX10-NEXT:    v_add3_u32 v1, v5, v2, v1433; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, v4, v1, vcc_lo434; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s2, s0, v3, 0435; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s0, s0, v4, v[1:2]436; GFX10-NEXT:    v_mul_hi_u32 v6, v4, v0437; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s0, s1, v3, v[1:2]438; GFX10-NEXT:    v_mul_lo_u32 v2, v4, v0439; GFX10-NEXT:    v_mul_hi_u32 v0, v3, v0440; GFX10-NEXT:    v_mul_lo_u32 v5, v3, v1441; GFX10-NEXT:    v_mul_lo_u32 v7, v4, v1442; GFX10-NEXT:    v_mul_hi_u32 v8, v3, v1443; GFX10-NEXT:    v_mul_hi_u32 v1, v4, v1444; GFX10-NEXT:    v_add_co_u32 v2, s0, v2, v5445; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s0446; GFX10-NEXT:    v_add_co_u32 v6, s0, v7, v6447; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s0448; GFX10-NEXT:    v_add_co_u32 v0, s0, v2, v0449; GFX10-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0450; GFX10-NEXT:    v_add_co_u32 v2, s0, v6, v8451; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s0452; GFX10-NEXT:    v_add_nc_u32_e32 v0, v5, v0453; GFX10-NEXT:    v_add_nc_u32_e32 v5, v7, v6454; GFX10-NEXT:    v_add_co_u32 v0, s0, v2, v0455; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0456; GFX10-NEXT:    v_add_co_u32 v0, vcc_lo, v3, v0457; GFX10-NEXT:    v_add3_u32 v1, v5, v2, v1458; GFX10-NEXT:    v_mul_lo_u32 v2, s17, v0459; GFX10-NEXT:    v_add_co_ci_u32_e32 v1, vcc_lo, v4, v1, vcc_lo460; GFX10-NEXT:    v_mul_hi_u32 v4, s16, v0461; GFX10-NEXT:    v_mul_hi_u32 v0, s17, v0462; GFX10-NEXT:    v_mul_lo_u32 v3, s16, v1463; GFX10-NEXT:    v_mul_lo_u32 v5, s17, v1464; GFX10-NEXT:    v_add_co_u32 v2, s0, v2, v3465; GFX10-NEXT:    v_mul_hi_u32 v3, s16, v1466; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s0467; GFX10-NEXT:    v_add_co_u32 v2, s0, v2, v4468; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s0469; GFX10-NEXT:    v_add_co_u32 v0, s0, v5, v0470; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s0471; GFX10-NEXT:    v_mul_hi_u32 v5, s17, v1472; GFX10-NEXT:    v_add_nc_u32_e32 v2, v6, v2473; GFX10-NEXT:    v_add_co_u32 v0, s0, v0, v3474; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s0475; GFX10-NEXT:    v_add_co_u32 v6, s0, v0, v2476; GFX10-NEXT:    v_add_nc_u32_e32 v2, v4, v3477; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s0478; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s18, v6, 0479; GFX10-NEXT:    v_add3_u32 v3, v2, v3, v5480; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s0, s18, v3, v[1:2]481; GFX10-NEXT:    v_mad_u64_u32 v[1:2], s0, s19, v6, v[1:2]482; GFX10-NEXT:    v_add_co_u32 v2, vcc_lo, v6, 1483; GFX10-NEXT:    v_add_co_ci_u32_e32 v4, vcc_lo, 0, v3, vcc_lo484; GFX10-NEXT:    v_sub_co_u32 v7, vcc_lo, s16, v0485; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s17, v1486; GFX10-NEXT:    v_sub_co_ci_u32_e64 v8, s0, s17, v1, vcc_lo487; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s19, v5, vcc_lo488; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s18, v7489; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, -1, vcc_lo490; GFX10-NEXT:    v_sub_co_u32 v5, vcc_lo, v7, s18491; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v9, s0, 0, v0, vcc_lo492; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s19, v8493; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s19, v0, vcc_lo494; GFX10-NEXT:    v_cndmask_b32_e64 v10, 0, -1, s0495; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s18, v5496; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, -1, s0497; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s19, v9498; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, -1, s0499; GFX10-NEXT:    v_add_co_u32 v13, s0, v2, 1500; GFX10-NEXT:    v_add_co_ci_u32_e64 v14, s0, 0, v4, s0501; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s19, v9502; GFX10-NEXT:    v_cndmask_b32_e64 v11, v12, v11, s0503; GFX10-NEXT:    v_cmp_eq_u32_e64 s0, s19, v8504; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11505; GFX10-NEXT:    v_cndmask_b32_e64 v1, v10, v1, s0506; GFX10-NEXT:    v_sub_co_u32 v10, s0, v5, s18507; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v0, s0, 0, v0, s0508; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v13, vcc_lo509; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v1510; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v14, vcc_lo511; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v10, vcc_lo512; GFX10-NEXT:    v_cndmask_b32_e32 v5, v9, v0, vcc_lo513; GFX10-NEXT:    v_mov_b32_e32 v9, 0514; GFX10-NEXT:    v_cndmask_b32_e64 v0, v6, v2, s0515; GFX10-NEXT:    v_cndmask_b32_e64 v1, v3, v1, s0516; GFX10-NEXT:    v_cndmask_b32_e64 v2, v7, v4, s0517; GFX10-NEXT:    v_cndmask_b32_e64 v3, v8, v5, s0518; GFX10-NEXT:    global_store_dwordx2 v9, v[0:1], s[12:13]519; GFX10-NEXT:    global_store_dwordx2 v9, v[2:3], s[14:15]520; GFX10-NEXT:    s_endpgm521  %div = udiv i64 %x, %y522  store i64 %div, ptr addrspace(1) %out0523  %rem = urem i64 %x, %y524  store i64 %rem, ptr addrspace(1) %out1525  ret void526}527 528define amdgpu_kernel void @udivrem_v2i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i32> %x, <2 x i32> %y) {529; GFX8-LABEL: udivrem_v2i32:530; GFX8:       ; %bb.0:531; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[8:9], 0x0532; GFX8-NEXT:    s_add_i32 s12, s12, s17533; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13534; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8535; GFX8-NEXT:    s_waitcnt lgkmcnt(0)536; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s10537; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s11538; GFX8-NEXT:    s_sub_i32 s0, 0, s10539; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0540; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1541; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0542; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0543; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1544; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1545; GFX8-NEXT:    v_mul_lo_u32 v2, s0, v0546; GFX8-NEXT:    s_sub_i32 s0, 0, s11547; GFX8-NEXT:    v_mul_lo_u32 v3, s0, v1548; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2549; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3550; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2551; GFX8-NEXT:    v_mul_hi_u32 v0, s8, v0552; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3553; GFX8-NEXT:    v_mul_hi_u32 v1, s9, v1554; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s10555; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0556; GFX8-NEXT:    v_mul_lo_u32 v4, v1, s11557; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s8, v2558; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2559; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc560; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s10, v2561; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc562; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0563; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s10, v2564; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc565; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s10, v2566; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc567; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s9, v4568; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1569; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3570; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc571; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3572; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc573; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v1574; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s11, v3575; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc576; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s11, v3577; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc578; GFX8-NEXT:    v_mov_b32_e32 v4, s4579; GFX8-NEXT:    v_mov_b32_e32 v5, s5580; GFX8-NEXT:    flat_store_dwordx2 v[4:5], v[0:1]581; GFX8-NEXT:    v_mov_b32_e32 v0, s6582; GFX8-NEXT:    v_mov_b32_e32 v1, s7583; GFX8-NEXT:    flat_store_dwordx2 v[0:1], v[2:3]584; GFX8-NEXT:    s_endpgm585;586; GFX9-LABEL: udivrem_v2i32:587; GFX9:       ; %bb.0:588; GFX9-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0589; GFX9-NEXT:    s_waitcnt lgkmcnt(0)590; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s18591; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s19592; GFX9-NEXT:    s_sub_i32 s0, 0, s18593; GFX9-NEXT:    s_sub_i32 s1, 0, s19594; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0595; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1596; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0597; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0598; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1599; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1600; GFX9-NEXT:    v_mul_lo_u32 v2, s0, v0601; GFX9-NEXT:    v_mul_lo_u32 v3, s1, v1602; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2603; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3604; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2605; GFX9-NEXT:    v_mul_hi_u32 v0, s16, v0606; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3607; GFX9-NEXT:    v_mul_hi_u32 v1, s17, v1608; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s18609; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0610; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s19611; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1612; GFX9-NEXT:    v_sub_u32_e32 v2, s16, v2613; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s18, v2614; GFX9-NEXT:    v_sub_u32_e32 v3, s17, v3615; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc616; GFX9-NEXT:    v_subrev_u32_e32 v4, s18, v2617; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s19, v3618; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc619; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]620; GFX9-NEXT:    v_subrev_u32_e32 v5, s19, v3621; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0622; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s18, v2623; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v5, s[0:1]624; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc625; GFX9-NEXT:    v_subrev_u32_e32 v4, s18, v2626; GFX9-NEXT:    v_add_u32_e32 v5, 1, v1627; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc628; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s19, v3629; GFX9-NEXT:    v_subrev_u32_e32 v4, s19, v3630; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc631; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc632; GFX9-NEXT:    v_mov_b32_e32 v4, 0633; GFX9-NEXT:    global_store_dwordx2 v4, v[0:1], s[12:13]634; GFX9-NEXT:    global_store_dwordx2 v4, v[2:3], s[14:15]635; GFX9-NEXT:    s_endpgm636;637; GFX10-LABEL: udivrem_v2i32:638; GFX10:       ; %bb.0:639; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x0640; GFX10-NEXT:    v_mov_b32_e32 v8, 0641; GFX10-NEXT:    s_waitcnt lgkmcnt(0)642; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s18643; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s19644; GFX10-NEXT:    s_sub_i32 s0, 0, s18645; GFX10-NEXT:    s_sub_i32 s1, 0, s19646; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0647; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1648; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0649; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1650; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0651; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1652; GFX10-NEXT:    v_mul_lo_u32 v2, s0, v0653; GFX10-NEXT:    v_mul_lo_u32 v3, s1, v1654; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v2655; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v3656; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v2657; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v3658; GFX10-NEXT:    v_mul_hi_u32 v0, s16, v0659; GFX10-NEXT:    v_mul_hi_u32 v1, s17, v1660; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s18661; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s19662; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0663; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1664; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s16, v2665; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s17, v3666; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s18, v2667; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s18, v2668; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s19, v3669; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s19, v3670; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo671; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo672; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0673; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0674; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v0675; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s18, v2676; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v1677; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s19, v3678; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s18, v2679; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s19, v3680; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo681; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s0682; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo683; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s0684; GFX10-NEXT:    global_store_dwordx2 v8, v[0:1], s[12:13]685; GFX10-NEXT:    global_store_dwordx2 v8, v[2:3], s[14:15]686; GFX10-NEXT:    s_endpgm687  %div = udiv <2 x i32> %x, %y688  store <2 x i32> %div, ptr addrspace(1) %out0689  %rem = urem <2 x i32> %x, %y690  store <2 x i32> %rem, ptr addrspace(1) %out1691  ret void692}693 694define amdgpu_kernel void @udivrem_v4i32(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <4 x i32> %x, <4 x i32> %y) {695; GFX8-LABEL: udivrem_v4i32:696; GFX8:       ; %bb.0:697; GFX8-NEXT:    s_add_i32 s12, s12, s17698; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13699; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8700; GFX8-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x10701; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x0702; GFX8-NEXT:    s_waitcnt lgkmcnt(0)703; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s16704; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s17705; GFX8-NEXT:    s_sub_i32 s0, 0, s16706; GFX8-NEXT:    v_cvt_f32_u32_e32 v6, s18707; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v0708; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v1709; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0710; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v0711; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1712; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v1713; GFX8-NEXT:    v_mul_lo_u32 v2, s0, v0714; GFX8-NEXT:    s_sub_i32 s0, 0, s17715; GFX8-NEXT:    v_mul_lo_u32 v3, s0, v1716; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v2717; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v3718; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v2719; GFX8-NEXT:    v_mul_hi_u32 v0, s12, v0720; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v3721; GFX8-NEXT:    v_mul_hi_u32 v1, s13, v1722; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s16723; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0724; GFX8-NEXT:    v_mul_lo_u32 v5, v1, s17725; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s12, v2726; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s16, v2727; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc728; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s16, v2729; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc730; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v0731; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s16, v2732; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc733; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s16, v2734; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v3, vcc735; GFX8-NEXT:    v_rcp_iflag_f32_e32 v3, v6736; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s13, v5737; GFX8-NEXT:    v_add_u32_e32 v5, vcc, 1, v1738; GFX8-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3739; GFX8-NEXT:    v_cvt_u32_f32_e32 v3, v3740; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s17, v2741; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc742; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s17, v2743; GFX8-NEXT:    s_sub_i32 s0, 0, s18744; GFX8-NEXT:    v_mul_lo_u32 v6, s0, v3745; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc746; GFX8-NEXT:    v_add_u32_e32 v5, vcc, 1, v1747; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s17, v2748; GFX8-NEXT:    v_mul_hi_u32 v6, v3, v6749; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc750; GFX8-NEXT:    v_cvt_f32_u32_e32 v5, s19751; GFX8-NEXT:    v_add_u32_e64 v3, s[0:1], v3, v6752; GFX8-NEXT:    v_rcp_iflag_f32_e32 v6, v5753; GFX8-NEXT:    v_mul_hi_u32 v3, s14, v3754; GFX8-NEXT:    v_subrev_u32_e64 v5, s[0:1], s17, v2755; GFX8-NEXT:    v_mul_f32_e32 v6, 0x4f7ffffe, v6756; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v6757; GFX8-NEXT:    s_sub_i32 s0, 0, s19758; GFX8-NEXT:    v_cndmask_b32_e32 v5, v2, v5, vcc759; GFX8-NEXT:    v_mul_lo_u32 v2, v3, s18760; GFX8-NEXT:    v_mul_lo_u32 v7, s0, v6761; GFX8-NEXT:    v_add_u32_e32 v8, vcc, 1, v3762; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s14, v2763; GFX8-NEXT:    v_mul_hi_u32 v7, v6, v7764; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s18, v2765; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc766; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s18, v2767; GFX8-NEXT:    v_cndmask_b32_e32 v8, v2, v8, vcc768; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v6, v7769; GFX8-NEXT:    v_mul_hi_u32 v7, s15, v2770; GFX8-NEXT:    v_add_u32_e32 v2, vcc, 1, v3771; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s18, v8772; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc773; GFX8-NEXT:    v_mul_lo_u32 v3, v7, s19774; GFX8-NEXT:    v_subrev_u32_e64 v6, s[0:1], s18, v8775; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc776; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s15, v3777; GFX8-NEXT:    v_add_u32_e32 v8, vcc, 1, v7778; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s19, v3779; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc780; GFX8-NEXT:    v_subrev_u32_e64 v8, s[0:1], s19, v3781; GFX8-NEXT:    v_cndmask_b32_e32 v8, v3, v8, vcc782; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v7783; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s19, v8784; GFX8-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc785; GFX8-NEXT:    v_subrev_u32_e64 v7, s[0:1], s19, v8786; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc787; GFX8-NEXT:    v_mov_b32_e32 v9, s5788; GFX8-NEXT:    v_mov_b32_e32 v8, s4789; GFX8-NEXT:    flat_store_dwordx4 v[8:9], v[0:3]790; GFX8-NEXT:    s_nop 0791; GFX8-NEXT:    v_mov_b32_e32 v0, s6792; GFX8-NEXT:    v_mov_b32_e32 v1, s7793; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[4:7]794; GFX8-NEXT:    s_endpgm795;796; GFX9-LABEL: udivrem_v4i32:797; GFX9:       ; %bb.0:798; GFX9-NEXT:    s_load_dwordx8 s[0:7], s[8:9], 0x10799; GFX9-NEXT:    s_waitcnt lgkmcnt(0)800; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s4801; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s5802; GFX9-NEXT:    s_sub_i32 s10, 0, s4803; GFX9-NEXT:    s_sub_i32 s11, 0, s5804; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v0805; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v1806; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s6807; GFX9-NEXT:    s_sub_i32 s12, 0, s6808; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0809; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1810; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v0811; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v1812; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v4813; GFX9-NEXT:    v_mul_lo_u32 v2, s10, v0814; GFX9-NEXT:    v_mul_lo_u32 v3, s11, v1815; GFX9-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x0816; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v2817; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v3818; GFX9-NEXT:    v_add_u32_e32 v0, v0, v2819; GFX9-NEXT:    v_add_u32_e32 v1, v1, v3820; GFX9-NEXT:    v_mul_hi_u32 v0, s0, v0821; GFX9-NEXT:    v_mul_hi_u32 v1, s1, v1822; GFX9-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v4823; GFX9-NEXT:    v_cvt_u32_f32_e32 v2, v2824; GFX9-NEXT:    v_mul_lo_u32 v3, v0, s4825; GFX9-NEXT:    v_mul_lo_u32 v4, v1, s5826; GFX9-NEXT:    v_add_u32_e32 v5, 1, v0827; GFX9-NEXT:    v_add_u32_e32 v6, 1, v1828; GFX9-NEXT:    v_sub_u32_e32 v3, s0, v3829; GFX9-NEXT:    v_sub_u32_e32 v7, s1, v4830; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3831; GFX9-NEXT:    v_subrev_u32_e32 v4, s4, v3832; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc833; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc834; GFX9-NEXT:    v_add_u32_e32 v4, 1, v0835; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v3836; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc837; GFX9-NEXT:    v_subrev_u32_e32 v4, s4, v3838; GFX9-NEXT:    v_cndmask_b32_e32 v4, v3, v4, vcc839; GFX9-NEXT:    v_mul_lo_u32 v3, s12, v2840; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s7841; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v7842; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc843; GFX9-NEXT:    v_mul_hi_u32 v3, v2, v3844; GFX9-NEXT:    v_rcp_iflag_f32_e32 v5, v5845; GFX9-NEXT:    v_subrev_u32_e32 v6, s5, v7846; GFX9-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc847; GFX9-NEXT:    v_add_u32_e32 v2, v2, v3848; GFX9-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v5849; GFX9-NEXT:    v_mul_hi_u32 v2, s2, v2850; GFX9-NEXT:    v_cvt_u32_f32_e32 v3, v3851; GFX9-NEXT:    v_add_u32_e32 v7, 1, v1852; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v6853; GFX9-NEXT:    s_sub_i32 s0, 0, s7854; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v7, vcc855; GFX9-NEXT:    v_mul_lo_u32 v7, v2, s6856; GFX9-NEXT:    v_mul_lo_u32 v8, s0, v3857; GFX9-NEXT:    v_subrev_u32_e32 v5, s5, v6858; GFX9-NEXT:    v_cndmask_b32_e32 v5, v6, v5, vcc859; GFX9-NEXT:    v_sub_u32_e32 v6, s2, v7860; GFX9-NEXT:    v_mul_hi_u32 v7, v3, v8861; GFX9-NEXT:    v_add_u32_e32 v8, 1, v2862; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v6863; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v8, vcc864; GFX9-NEXT:    v_add_u32_e32 v3, v3, v7865; GFX9-NEXT:    v_mul_hi_u32 v3, s3, v3866; GFX9-NEXT:    v_subrev_u32_e32 v7, s6, v6867; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc868; GFX9-NEXT:    v_add_u32_e32 v7, 1, v2869; GFX9-NEXT:    v_mul_lo_u32 v8, v3, s7870; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s6, v6871; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v7, vcc872; GFX9-NEXT:    v_subrev_u32_e32 v7, s6, v6873; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v7, vcc874; GFX9-NEXT:    v_sub_u32_e32 v7, s3, v8875; GFX9-NEXT:    v_add_u32_e32 v8, 1, v3876; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7877; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc878; GFX9-NEXT:    v_subrev_u32_e32 v8, s7, v7879; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc880; GFX9-NEXT:    v_add_u32_e32 v8, 1, v3881; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s7, v7882; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v8, vcc883; GFX9-NEXT:    v_subrev_u32_e32 v8, s7, v7884; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v8, vcc885; GFX9-NEXT:    v_mov_b32_e32 v8, 0886; GFX9-NEXT:    s_waitcnt lgkmcnt(0)887; GFX9-NEXT:    global_store_dwordx4 v8, v[0:3], s[8:9]888; GFX9-NEXT:    global_store_dwordx4 v8, v[4:7], s[10:11]889; GFX9-NEXT:    s_endpgm890;891; GFX10-LABEL: udivrem_v4i32:892; GFX10:       ; %bb.0:893; GFX10-NEXT:    s_load_dwordx8 s[0:7], s[8:9], 0x10894; GFX10-NEXT:    v_mov_b32_e32 v8, 0895; GFX10-NEXT:    s_waitcnt lgkmcnt(0)896; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s4897; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s5898; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s6899; GFX10-NEXT:    v_cvt_f32_u32_e32 v3, s7900; GFX10-NEXT:    s_sub_i32 s10, 0, s4901; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v0902; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v1903; GFX10-NEXT:    v_rcp_iflag_f32_e32 v2, v2904; GFX10-NEXT:    v_rcp_iflag_f32_e32 v3, v3905; GFX10-NEXT:    s_sub_i32 s11, 0, s5906; GFX10-NEXT:    s_sub_i32 s12, 0, s6907; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v0908; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v1909; GFX10-NEXT:    v_mul_f32_e32 v2, 0x4f7ffffe, v2910; GFX10-NEXT:    v_mul_f32_e32 v3, 0x4f7ffffe, v3911; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v0912; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v1913; GFX10-NEXT:    v_cvt_u32_f32_e32 v2, v2914; GFX10-NEXT:    v_cvt_u32_f32_e32 v3, v3915; GFX10-NEXT:    v_mul_lo_u32 v4, s10, v0916; GFX10-NEXT:    v_mul_lo_u32 v5, s11, v1917; GFX10-NEXT:    v_mul_lo_u32 v6, s12, v2918; GFX10-NEXT:    s_sub_i32 s10, 0, s7919; GFX10-NEXT:    v_mul_lo_u32 v7, s10, v3920; GFX10-NEXT:    s_load_dwordx4 s[8:11], s[8:9], 0x0921; GFX10-NEXT:    v_mul_hi_u32 v4, v0, v4922; GFX10-NEXT:    v_mul_hi_u32 v5, v1, v5923; GFX10-NEXT:    v_mul_hi_u32 v6, v2, v6924; GFX10-NEXT:    v_mul_hi_u32 v7, v3, v7925; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v4926; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v5927; GFX10-NEXT:    v_add_nc_u32_e32 v2, v2, v6928; GFX10-NEXT:    v_add_nc_u32_e32 v3, v3, v7929; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v0930; GFX10-NEXT:    v_mul_hi_u32 v1, s1, v1931; GFX10-NEXT:    v_mul_hi_u32 v2, s2, v2932; GFX10-NEXT:    v_mul_hi_u32 v3, s3, v3933; GFX10-NEXT:    v_mul_lo_u32 v4, v0, s4934; GFX10-NEXT:    v_mul_lo_u32 v5, v1, s5935; GFX10-NEXT:    v_mul_lo_u32 v6, v2, s6936; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v0937; GFX10-NEXT:    v_mul_lo_u32 v7, v3, s7938; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v1939; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v2940; GFX10-NEXT:    v_add_nc_u32_e32 v12, 1, v3941; GFX10-NEXT:    v_sub_nc_u32_e32 v4, s0, v4942; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s1, v5943; GFX10-NEXT:    v_sub_nc_u32_e32 v6, s2, v6944; GFX10-NEXT:    v_sub_nc_u32_e32 v7, s3, v7945; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v4946; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s5, v5947; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s6, v6948; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s7, v7949; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc_lo950; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s4, v4951; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v10, s0952; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s5, v5953; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v11, s1954; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s6, v6955; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v12, s2956; GFX10-NEXT:    v_subrev_nc_u32_e32 v12, s7, v7957; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo958; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v10, s0959; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v11, s1960; GFX10-NEXT:    v_add_nc_u32_e32 v9, 1, v0961; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v12, s2962; GFX10-NEXT:    v_add_nc_u32_e32 v10, 1, v1963; GFX10-NEXT:    v_add_nc_u32_e32 v11, 1, v2964; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v4965; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s5, v5966; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s6, v6967; GFX10-NEXT:    v_add_nc_u32_e32 v12, 1, v3968; GFX10-NEXT:    v_cmp_le_u32_e64 s2, s7, v7969; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v9, vcc_lo970; GFX10-NEXT:    v_subrev_nc_u32_e32 v9, s4, v4971; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v10, s0972; GFX10-NEXT:    v_subrev_nc_u32_e32 v10, s5, v5973; GFX10-NEXT:    v_cndmask_b32_e64 v2, v2, v11, s1974; GFX10-NEXT:    v_subrev_nc_u32_e32 v11, s6, v6975; GFX10-NEXT:    v_subrev_nc_u32_e32 v13, s7, v7976; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v12, s2977; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v9, vcc_lo978; GFX10-NEXT:    v_cndmask_b32_e64 v5, v5, v10, s0979; GFX10-NEXT:    v_cndmask_b32_e64 v6, v6, v11, s1980; GFX10-NEXT:    v_cndmask_b32_e64 v7, v7, v13, s2981; GFX10-NEXT:    s_waitcnt lgkmcnt(0)982; GFX10-NEXT:    global_store_dwordx4 v8, v[0:3], s[8:9]983; GFX10-NEXT:    global_store_dwordx4 v8, v[4:7], s[10:11]984; GFX10-NEXT:    s_endpgm985  %div = udiv <4 x i32> %x, %y986  store <4 x i32> %div, ptr addrspace(1) %out0987  %rem = urem <4 x i32> %x, %y988  store <4 x i32> %rem, ptr addrspace(1) %out1989  ret void990}991 992define amdgpu_kernel void @udivrem_v2i64(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i64> %x, <2 x i64> %y) {993; GFX8-LABEL: udivrem_v2i64:994; GFX8:       ; %bb.0:995; GFX8-NEXT:    s_add_i32 s12, s12, s17996; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s13997; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 8998; GFX8-NEXT:    s_load_dwordx4 s[12:15], s[8:9], 0x20999; GFX8-NEXT:    s_load_dwordx8 s[4:11], s[8:9], 0x01000; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1001; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s131002; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s121003; GFX8-NEXT:    s_sub_u32 s2, 0, s121004; GFX8-NEXT:    s_subb_u32 s3, 0, s131005; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v01006; GFX8-NEXT:    v_add_f32_e32 v0, v0, v11007; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v01008; GFX8-NEXT:    v_mov_b32_e32 v9, s131009; GFX8-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01010; GFX8-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01011; GFX8-NEXT:    v_trunc_f32_e32 v1, v11012; GFX8-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11013; GFX8-NEXT:    v_add_f32_e32 v0, v2, v01014; GFX8-NEXT:    v_cvt_u32_f32_e32 v6, v01015; GFX8-NEXT:    v_cvt_u32_f32_e32 v7, v11016; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 01017; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]1018; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v01019; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]1020; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v01021; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v01022; GFX8-NEXT:    v_mul_lo_u32 v3, v6, v41023; GFX8-NEXT:    v_mul_lo_u32 v5, v7, v41024; GFX8-NEXT:    v_mul_hi_u32 v8, v6, v41025; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31026; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1027; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v5, v01028; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc1029; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v21030; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1031; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v81032; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1033; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11034; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v5, v21035; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v41036; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11037; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1038; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11039; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11040; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v01041; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v7, v1, vcc1042; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 01043; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]1044; GFX8-NEXT:    v_mul_lo_u32 v1, v7, v01045; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]1046; GFX8-NEXT:    v_mul_hi_u32 v3, v6, v01047; GFX8-NEXT:    v_mul_hi_u32 v0, v7, v01048; GFX8-NEXT:    v_mul_lo_u32 v2, v6, v41049; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v21050; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1051; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31052; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1053; GFX8-NEXT:    v_mul_lo_u32 v3, v7, v41054; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11055; GFX8-NEXT:    v_mul_hi_u32 v2, v6, v41056; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v3, v01057; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1058; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v21059; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1060; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v21061; GFX8-NEXT:    v_mul_hi_u32 v3, v7, v41062; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11063; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1064; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v2, v11065; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v3, v11066; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v6, v01067; GFX8-NEXT:    v_addc_u32_e32 v1, vcc, v7, v1, vcc1068; GFX8-NEXT:    v_mul_lo_u32 v2, s9, v01069; GFX8-NEXT:    v_mul_lo_u32 v3, s8, v11070; GFX8-NEXT:    v_mul_hi_u32 v4, s8, v01071; GFX8-NEXT:    v_mul_hi_u32 v0, s9, v01072; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v31073; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1074; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v41075; GFX8-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1076; GFX8-NEXT:    v_mul_lo_u32 v4, s9, v11077; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v21078; GFX8-NEXT:    v_mul_hi_u32 v3, s8, v11079; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v4, v01080; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1081; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v31082; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1083; GFX8-NEXT:    v_add_u32_e32 v3, vcc, v4, v31084; GFX8-NEXT:    v_add_u32_e32 v8, vcc, v0, v21085; GFX8-NEXT:    v_cndmask_b32_e64 v0, 0, 1, vcc1086; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v3, v01087; GFX8-NEXT:    v_mul_hi_u32 v3, s9, v11088; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s12, v8, 01089; GFX8-NEXT:    v_add_u32_e64 v17, s[2:3], 1, v81090; GFX8-NEXT:    v_add_u32_e32 v10, vcc, v3, v21091; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s12, v10, v[1:2]1092; GFX8-NEXT:    v_sub_u32_e32 v1, vcc, s8, v01093; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s13, v8, v[2:3]1094; GFX8-NEXT:    v_mov_b32_e32 v2, s91095; GFX8-NEXT:    v_cvt_f32_u32_e32 v5, s141096; GFX8-NEXT:    v_subb_u32_e64 v0, s[0:1], v2, v4, vcc1097; GFX8-NEXT:    v_sub_u32_e64 v2, s[0:1], s9, v41098; GFX8-NEXT:    v_cvt_f32_u32_e32 v4, s151099; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v01100; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1101; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v11102; GFX8-NEXT:    v_mul_f32_e32 v4, 0x4f800000, v41103; GFX8-NEXT:    v_add_f32_e32 v4, v4, v51104; GFX8-NEXT:    v_rcp_iflag_f32_e32 v4, v41105; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]1106; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v01107; GFX8-NEXT:    v_subb_u32_e32 v12, vcc, v2, v9, vcc1108; GFX8-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v41109; GFX8-NEXT:    v_cndmask_b32_e64 v11, v3, v6, s[0:1]1110; GFX8-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v21111; GFX8-NEXT:    v_trunc_f32_e32 v3, v31112; GFX8-NEXT:    v_mul_f32_e32 v4, 0xcf800000, v31113; GFX8-NEXT:    v_add_f32_e32 v2, v4, v21114; GFX8-NEXT:    v_cvt_u32_f32_e32 v13, v21115; GFX8-NEXT:    s_sub_u32 s8, 0, s141116; GFX8-NEXT:    v_cvt_u32_f32_e32 v14, v31117; GFX8-NEXT:    v_subrev_u32_e32 v15, vcc, s12, v11118; GFX8-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s8, v13, 01119; GFX8-NEXT:    v_subbrev_u32_e64 v16, s[0:1], 0, v12, vcc1120; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s8, v14, v[3:4]1121; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s13, v161122; GFX8-NEXT:    s_subb_u32 s9, 0, s151123; GFX8-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1124; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s9, v13, v[4:5]1125; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s12, v151126; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]1127; GFX8-NEXT:    v_mul_lo_u32 v5, v14, v21128; GFX8-NEXT:    v_mul_lo_u32 v7, v13, v61129; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s13, v161130; GFX8-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]1131; GFX8-NEXT:    v_mul_hi_u32 v4, v13, v21132; GFX8-NEXT:    v_add_u32_e64 v5, s[0:1], v5, v71133; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]1134; GFX8-NEXT:    v_add_u32_e64 v4, s[0:1], v5, v41135; GFX8-NEXT:    v_subb_u32_e32 v4, vcc, v12, v9, vcc1136; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]1137; GFX8-NEXT:    v_mul_hi_u32 v2, v14, v21138; GFX8-NEXT:    v_mul_lo_u32 v9, v14, v61139; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v7, v51140; GFX8-NEXT:    v_mul_hi_u32 v7, v13, v61141; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v9, v21142; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1143; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v71144; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1145; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v9, v71146; GFX8-NEXT:    v_addc_u32_e64 v18, s[2:3], 0, v10, s[2:3]1147; GFX8-NEXT:    v_add_u32_e32 v9, vcc, 1, v171148; GFX8-NEXT:    v_addc_u32_e32 v12, vcc, 0, v18, vcc1149; GFX8-NEXT:    v_subrev_u32_e32 v19, vcc, s12, v151150; GFX8-NEXT:    v_mul_hi_u32 v6, v14, v61151; GFX8-NEXT:    v_subbrev_u32_e32 v20, vcc, 0, v4, vcc1152; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v2, v51153; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1154; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v7, v41155; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v6, v41156; GFX8-NEXT:    v_add_u32_e32 v13, vcc, v13, v21157; GFX8-NEXT:    v_addc_u32_e32 v14, vcc, v14, v4, vcc1158; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s8, v13, 01159; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v31160; GFX8-NEXT:    v_cndmask_b32_e32 v2, v17, v9, vcc1161; GFX8-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s8, v14, v[5:6]1162; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v111163; GFX8-NEXT:    v_cndmask_b32_e64 v2, v8, v2, s[0:1]1164; GFX8-NEXT:    v_mad_u64_u32 v[8:9], s[2:3], s9, v13, v[6:7]1165; GFX8-NEXT:    v_mul_lo_u32 v6, v14, v41166; GFX8-NEXT:    v_mul_hi_u32 v9, v13, v41167; GFX8-NEXT:    v_mul_lo_u32 v7, v13, v81168; GFX8-NEXT:    v_cndmask_b32_e32 v3, v18, v12, vcc1169; GFX8-NEXT:    v_cndmask_b32_e64 v3, v10, v3, s[0:1]1170; GFX8-NEXT:    v_cndmask_b32_e32 v5, v15, v19, vcc1171; GFX8-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc1172; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v71173; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1174; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v6, v91175; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc1176; GFX8-NEXT:    v_mul_lo_u32 v9, v14, v81177; GFX8-NEXT:    v_mul_hi_u32 v4, v14, v41178; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v61179; GFX8-NEXT:    v_mul_hi_u32 v7, v13, v81180; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v9, v41181; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1182; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v71183; GFX8-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1184; GFX8-NEXT:    v_add_u32_e32 v7, vcc, v9, v71185; GFX8-NEXT:    v_mul_hi_u32 v8, v14, v81186; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v61187; GFX8-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc1188; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v7, v61189; GFX8-NEXT:    v_add_u32_e32 v6, vcc, v8, v61190; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v13, v41191; GFX8-NEXT:    v_addc_u32_e32 v7, vcc, v14, v6, vcc1192; GFX8-NEXT:    v_mul_lo_u32 v8, s11, v41193; GFX8-NEXT:    v_mul_lo_u32 v9, s10, v71194; GFX8-NEXT:    v_cndmask_b32_e64 v6, v1, v5, s[0:1]1195; GFX8-NEXT:    v_mul_hi_u32 v1, s10, v41196; GFX8-NEXT:    v_mul_hi_u32 v4, s11, v41197; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v8, v91198; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1199; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v5, v11200; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1201; GFX8-NEXT:    v_mul_lo_u32 v5, s11, v71202; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v8, v11203; GFX8-NEXT:    v_mul_hi_u32 v8, s10, v71204; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v5, v41205; GFX8-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc1206; GFX8-NEXT:    v_add_u32_e32 v4, vcc, v4, v81207; GFX8-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1208; GFX8-NEXT:    v_add_u32_e32 v5, vcc, v5, v81209; GFX8-NEXT:    v_add_u32_e32 v11, vcc, v4, v11210; GFX8-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1211; GFX8-NEXT:    v_mul_hi_u32 v7, s11, v71212; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v5, v11213; GFX8-NEXT:    v_mad_u64_u32 v[4:5], s[2:3], s14, v11, 01214; GFX8-NEXT:    v_add_u32_e32 v12, vcc, v7, v11215; GFX8-NEXT:    v_mad_u64_u32 v[8:9], s[2:3], s14, v12, v[5:6]1216; GFX8-NEXT:    v_cndmask_b32_e64 v7, v0, v10, s[0:1]1217; GFX8-NEXT:    v_mov_b32_e32 v5, s151218; GFX8-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s15, v11, v[8:9]1219; GFX8-NEXT:    v_mov_b32_e32 v1, s111220; GFX8-NEXT:    v_sub_u32_e32 v8, vcc, s10, v41221; GFX8-NEXT:    v_subb_u32_e64 v1, s[0:1], v1, v0, vcc1222; GFX8-NEXT:    v_sub_u32_e64 v0, s[0:1], s11, v01223; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s15, v11224; GFX8-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]1225; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s14, v81226; GFX8-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]1227; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s15, v11228; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v5, vcc1229; GFX8-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[0:1]1230; GFX8-NEXT:    v_subrev_u32_e32 v9, vcc, s14, v81231; GFX8-NEXT:    v_subbrev_u32_e64 v10, s[0:1], 0, v0, vcc1232; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s15, v101233; GFX8-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]1234; GFX8-NEXT:    v_cmp_le_u32_e64 s[0:1], s14, v91235; GFX8-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]1236; GFX8-NEXT:    v_cmp_eq_u32_e64 s[0:1], s15, v101237; GFX8-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]1238; GFX8-NEXT:    v_add_u32_e64 v14, s[0:1], 1, v111239; GFX8-NEXT:    v_subb_u32_e32 v0, vcc, v0, v5, vcc1240; GFX8-NEXT:    v_addc_u32_e64 v15, s[0:1], 0, v12, s[0:1]1241; GFX8-NEXT:    v_add_u32_e32 v5, vcc, 1, v141242; GFX8-NEXT:    v_addc_u32_e32 v16, vcc, 0, v15, vcc1243; GFX8-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v131244; GFX8-NEXT:    v_subrev_u32_e64 v13, s[0:1], s14, v91245; GFX8-NEXT:    v_subbrev_u32_e64 v0, s[0:1], 0, v0, s[0:1]1246; GFX8-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v41247; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v13, vcc1248; GFX8-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc1249; GFX8-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc1250; GFX8-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc1251; GFX8-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]1252; GFX8-NEXT:    v_cndmask_b32_e64 v9, v1, v0, s[0:1]1253; GFX8-NEXT:    v_mov_b32_e32 v0, s41254; GFX8-NEXT:    v_cndmask_b32_e64 v4, v11, v5, s[0:1]1255; GFX8-NEXT:    v_cndmask_b32_e64 v5, v12, v14, s[0:1]1256; GFX8-NEXT:    v_mov_b32_e32 v1, s51257; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[2:5]1258; GFX8-NEXT:    v_mov_b32_e32 v0, s61259; GFX8-NEXT:    v_mov_b32_e32 v1, s71260; GFX8-NEXT:    flat_store_dwordx4 v[0:1], v[6:9]1261; GFX8-NEXT:    s_endpgm1262;1263; GFX9-LABEL: udivrem_v2i64:1264; GFX9:       ; %bb.0:1265; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x201266; GFX9-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x01267; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1268; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s51269; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s41270; GFX9-NEXT:    s_sub_u32 s2, 0, s41271; GFX9-NEXT:    s_subb_u32 s3, 0, s51272; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v01273; GFX9-NEXT:    v_add_f32_e32 v0, v0, v11274; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01275; GFX9-NEXT:    v_mov_b32_e32 v9, s51276; GFX9-NEXT:    s_sub_u32 s8, 0, s61277; GFX9-NEXT:    s_subb_u32 s9, 0, s71278; GFX9-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01279; GFX9-NEXT:    v_mul_f32_e32 v1, 0x2f800000, v01280; GFX9-NEXT:    v_trunc_f32_e32 v1, v11281; GFX9-NEXT:    v_mul_f32_e32 v2, 0xcf800000, v11282; GFX9-NEXT:    v_add_f32_e32 v0, v2, v01283; GFX9-NEXT:    v_cvt_u32_f32_e32 v6, v01284; GFX9-NEXT:    v_cvt_u32_f32_e32 v7, v11285; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 01286; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]1287; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v01288; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]1289; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v01290; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v01291; GFX9-NEXT:    v_mul_lo_u32 v3, v6, v41292; GFX9-NEXT:    v_mul_lo_u32 v5, v7, v41293; GFX9-NEXT:    v_mul_hi_u32 v8, v6, v41294; GFX9-NEXT:    v_mul_hi_u32 v4, v7, v41295; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v31296; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1297; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v5, v01298; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, vcc1299; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v21300; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1301; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v81302; GFX9-NEXT:    v_add_u32_e32 v1, v3, v11303; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1304; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v11305; GFX9-NEXT:    v_add_u32_e32 v2, v5, v21306; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1307; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v41308; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v01309; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v7, v1, vcc1310; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s2, v6, 01311; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s2, v7, v[1:2]1312; GFX9-NEXT:    v_mul_lo_u32 v1, v7, v01313; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s3, v6, v[2:3]1314; GFX9-NEXT:    v_mul_hi_u32 v3, v6, v01315; GFX9-NEXT:    v_mul_hi_u32 v0, v7, v01316; GFX9-NEXT:    v_mul_lo_u32 v2, v6, v41317; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v21318; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1319; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v1, v31320; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1321; GFX9-NEXT:    v_mul_lo_u32 v3, v7, v41322; GFX9-NEXT:    v_add_u32_e32 v1, v2, v11323; GFX9-NEXT:    v_mul_hi_u32 v2, v6, v41324; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v3, v01325; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1326; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v21327; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1328; GFX9-NEXT:    v_add_u32_e32 v2, v3, v21329; GFX9-NEXT:    v_mul_hi_u32 v3, v7, v41330; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v11331; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1332; GFX9-NEXT:    v_add3_u32 v1, v2, v1, v31333; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v6, v01334; GFX9-NEXT:    v_addc_co_u32_e32 v1, vcc, v7, v1, vcc1335; GFX9-NEXT:    v_mul_lo_u32 v2, s17, v01336; GFX9-NEXT:    v_mul_lo_u32 v3, s16, v11337; GFX9-NEXT:    v_mul_hi_u32 v4, s16, v01338; GFX9-NEXT:    v_mul_hi_u32 v0, s17, v01339; GFX9-NEXT:    v_mul_hi_u32 v5, s17, v11340; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v31341; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1342; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v41343; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1344; GFX9-NEXT:    v_mul_lo_u32 v4, s17, v11345; GFX9-NEXT:    v_add_u32_e32 v2, v3, v21346; GFX9-NEXT:    v_mul_hi_u32 v3, s16, v11347; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v4, v01348; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1349; GFX9-NEXT:    v_add_co_u32_e32 v0, vcc, v0, v31350; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, 1, vcc1351; GFX9-NEXT:    v_add_co_u32_e32 v8, vcc, v0, v21352; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s4, v8, 01353; GFX9-NEXT:    v_cndmask_b32_e64 v2, 0, 1, vcc1354; GFX9-NEXT:    v_add_u32_e32 v3, v4, v31355; GFX9-NEXT:    v_add3_u32 v10, v3, v2, v51356; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s4, v10, v[1:2]1357; GFX9-NEXT:    v_sub_co_u32_e32 v1, vcc, s16, v01358; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s5, v8, v[2:3]1359; GFX9-NEXT:    v_mov_b32_e32 v2, s171360; GFX9-NEXT:    v_cvt_f32_u32_e32 v5, s61361; GFX9-NEXT:    v_subb_co_u32_e64 v0, s[0:1], v2, v4, vcc1362; GFX9-NEXT:    v_sub_u32_e32 v2, s17, v41363; GFX9-NEXT:    v_cvt_f32_u32_e32 v4, s71364; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s5, v01365; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1366; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s4, v11367; GFX9-NEXT:    v_mul_f32_e32 v4, 0x4f800000, v41368; GFX9-NEXT:    v_add_f32_e32 v4, v4, v51369; GFX9-NEXT:    v_rcp_iflag_f32_e32 v4, v41370; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, -1, s[0:1]1371; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s5, v01372; GFX9-NEXT:    v_subb_co_u32_e32 v12, vcc, v2, v9, vcc1373; GFX9-NEXT:    v_mul_f32_e32 v2, 0x5f7ffffc, v41374; GFX9-NEXT:    v_cndmask_b32_e64 v11, v3, v6, s[0:1]1375; GFX9-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v21376; GFX9-NEXT:    v_trunc_f32_e32 v3, v31377; GFX9-NEXT:    v_mul_f32_e32 v4, 0xcf800000, v31378; GFX9-NEXT:    v_add_f32_e32 v2, v4, v21379; GFX9-NEXT:    v_cvt_u32_f32_e32 v13, v21380; GFX9-NEXT:    v_cvt_u32_f32_e32 v14, v31381; GFX9-NEXT:    v_subrev_co_u32_e32 v15, vcc, s4, v11382; GFX9-NEXT:    v_mad_u64_u32 v[2:3], s[0:1], s8, v13, 01383; GFX9-NEXT:    v_subbrev_co_u32_e64 v16, s[0:1], 0, v12, vcc1384; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s8, v14, v[3:4]1385; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s5, v161386; GFX9-NEXT:    v_cndmask_b32_e64 v3, 0, -1, s[0:1]1387; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s9, v13, v[4:5]1388; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s4, v151389; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]1390; GFX9-NEXT:    v_mul_lo_u32 v5, v14, v21391; GFX9-NEXT:    v_mul_lo_u32 v7, v13, v61392; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s5, v161393; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]1394; GFX9-NEXT:    v_mul_hi_u32 v4, v13, v21395; GFX9-NEXT:    v_add_co_u32_e64 v5, s[0:1], v5, v71396; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s[0:1]1397; GFX9-NEXT:    v_add_co_u32_e64 v4, s[0:1], v5, v41398; GFX9-NEXT:    v_subb_co_u32_e32 v4, vcc, v12, v9, vcc1399; GFX9-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s[0:1]1400; GFX9-NEXT:    v_mul_hi_u32 v2, v14, v21401; GFX9-NEXT:    v_mul_lo_u32 v9, v14, v61402; GFX9-NEXT:    v_add_u32_e32 v5, v7, v51403; GFX9-NEXT:    v_mul_hi_u32 v7, v13, v61404; GFX9-NEXT:    v_add_co_u32_e64 v17, s[2:3], 1, v81405; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v9, v21406; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1407; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v71408; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1409; GFX9-NEXT:    v_addc_co_u32_e64 v18, s[2:3], 0, v10, s[2:3]1410; GFX9-NEXT:    v_add_u32_e32 v7, v9, v71411; GFX9-NEXT:    v_add_co_u32_e32 v9, vcc, 1, v171412; GFX9-NEXT:    v_addc_co_u32_e32 v12, vcc, 0, v18, vcc1413; GFX9-NEXT:    v_mul_hi_u32 v6, v14, v61414; GFX9-NEXT:    v_subrev_co_u32_e32 v19, vcc, s4, v151415; GFX9-NEXT:    v_subbrev_co_u32_e32 v20, vcc, 0, v4, vcc1416; GFX9-NEXT:    v_add_co_u32_e32 v2, vcc, v2, v51417; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, 1, vcc1418; GFX9-NEXT:    v_add3_u32 v4, v7, v4, v61419; GFX9-NEXT:    v_add_co_u32_e32 v13, vcc, v13, v21420; GFX9-NEXT:    v_addc_co_u32_e32 v14, vcc, v14, v4, vcc1421; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[0:1], s8, v13, 01422; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v31423; GFX9-NEXT:    v_cndmask_b32_e32 v2, v17, v9, vcc1424; GFX9-NEXT:    v_mad_u64_u32 v[6:7], s[0:1], s8, v14, v[5:6]1425; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v111426; GFX9-NEXT:    v_cndmask_b32_e64 v2, v8, v2, s[0:1]1427; GFX9-NEXT:    v_mad_u64_u32 v[8:9], s[2:3], s9, v13, v[6:7]1428; GFX9-NEXT:    v_mul_lo_u32 v6, v14, v41429; GFX9-NEXT:    v_mul_hi_u32 v9, v13, v41430; GFX9-NEXT:    v_mul_lo_u32 v7, v13, v81431; GFX9-NEXT:    v_cndmask_b32_e32 v3, v18, v12, vcc1432; GFX9-NEXT:    v_cndmask_b32_e64 v3, v10, v3, s[0:1]1433; GFX9-NEXT:    v_cndmask_b32_e32 v5, v15, v19, vcc1434; GFX9-NEXT:    v_cndmask_b32_e32 v10, v16, v20, vcc1435; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v71436; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1437; GFX9-NEXT:    v_add_co_u32_e32 v6, vcc, v6, v91438; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc1439; GFX9-NEXT:    v_mul_lo_u32 v9, v14, v81440; GFX9-NEXT:    v_mul_hi_u32 v4, v14, v41441; GFX9-NEXT:    v_add_u32_e32 v6, v7, v61442; GFX9-NEXT:    v_mul_hi_u32 v7, v13, v81443; GFX9-NEXT:    v_mul_hi_u32 v8, v14, v81444; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v9, v41445; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1446; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v71447; GFX9-NEXT:    v_cndmask_b32_e64 v7, 0, 1, vcc1448; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v61449; GFX9-NEXT:    v_add_u32_e32 v7, v9, v71450; GFX9-NEXT:    v_cndmask_b32_e64 v6, 0, 1, vcc1451; GFX9-NEXT:    v_add3_u32 v6, v7, v6, v81452; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v13, v41453; GFX9-NEXT:    v_addc_co_u32_e32 v7, vcc, v14, v6, vcc1454; GFX9-NEXT:    v_mul_lo_u32 v8, s19, v41455; GFX9-NEXT:    v_mul_lo_u32 v9, s18, v71456; GFX9-NEXT:    v_cndmask_b32_e64 v6, v1, v5, s[0:1]1457; GFX9-NEXT:    v_mul_hi_u32 v1, s18, v41458; GFX9-NEXT:    v_mul_hi_u32 v4, s19, v41459; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, v8, v91460; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1461; GFX9-NEXT:    v_add_co_u32_e32 v1, vcc, v5, v11462; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1463; GFX9-NEXT:    v_mul_lo_u32 v5, s19, v71464; GFX9-NEXT:    v_add_u32_e32 v1, v8, v11465; GFX9-NEXT:    v_mul_hi_u32 v8, s18, v71466; GFX9-NEXT:    v_mul_hi_u32 v7, s19, v71467; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v5, v41468; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, 1, vcc1469; GFX9-NEXT:    v_add_co_u32_e32 v4, vcc, v4, v81470; GFX9-NEXT:    v_cndmask_b32_e64 v8, 0, 1, vcc1471; GFX9-NEXT:    v_add_co_u32_e32 v11, vcc, v4, v11472; GFX9-NEXT:    v_mad_u64_u32 v[4:5], s[2:3], s6, v11, 01473; GFX9-NEXT:    v_cndmask_b32_e64 v1, 0, 1, vcc1474; GFX9-NEXT:    v_add_u32_e32 v8, v9, v81475; GFX9-NEXT:    v_add3_u32 v12, v8, v1, v71476; GFX9-NEXT:    v_mad_u64_u32 v[8:9], s[2:3], s6, v12, v[5:6]1477; GFX9-NEXT:    v_cndmask_b32_e64 v7, v0, v10, s[0:1]1478; GFX9-NEXT:    v_mov_b32_e32 v5, s71479; GFX9-NEXT:    v_mad_u64_u32 v[0:1], s[0:1], s7, v11, v[8:9]1480; GFX9-NEXT:    v_mov_b32_e32 v1, s191481; GFX9-NEXT:    v_sub_co_u32_e32 v8, vcc, s18, v41482; GFX9-NEXT:    v_subb_co_u32_e64 v1, s[0:1], v1, v0, vcc1483; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v11484; GFX9-NEXT:    v_sub_u32_e32 v0, s19, v01485; GFX9-NEXT:    v_cndmask_b32_e64 v4, 0, -1, s[0:1]1486; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v81487; GFX9-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s[0:1]1488; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v11489; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v5, vcc1490; GFX9-NEXT:    v_cndmask_b32_e64 v4, v4, v9, s[0:1]1491; GFX9-NEXT:    v_subrev_co_u32_e32 v9, vcc, s6, v81492; GFX9-NEXT:    v_subbrev_co_u32_e64 v10, s[0:1], 0, v0, vcc1493; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s7, v101494; GFX9-NEXT:    v_cndmask_b32_e64 v13, 0, -1, s[0:1]1495; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s6, v91496; GFX9-NEXT:    v_cndmask_b32_e64 v14, 0, -1, s[0:1]1497; GFX9-NEXT:    v_cmp_eq_u32_e64 s[0:1], s7, v101498; GFX9-NEXT:    v_cndmask_b32_e64 v13, v13, v14, s[0:1]1499; GFX9-NEXT:    v_add_co_u32_e64 v14, s[0:1], 1, v111500; GFX9-NEXT:    v_subb_co_u32_e32 v0, vcc, v0, v5, vcc1501; GFX9-NEXT:    v_addc_co_u32_e64 v15, s[0:1], 0, v12, s[0:1]1502; GFX9-NEXT:    v_add_co_u32_e32 v5, vcc, 1, v141503; GFX9-NEXT:    v_addc_co_u32_e32 v16, vcc, 0, v15, vcc1504; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v131505; GFX9-NEXT:    v_cndmask_b32_e32 v5, v14, v5, vcc1506; GFX9-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc1507; GFX9-NEXT:    v_subrev_co_u32_e64 v15, s[0:1], s6, v91508; GFX9-NEXT:    v_subbrev_co_u32_e64 v0, s[0:1], 0, v0, s[0:1]1509; GFX9-NEXT:    v_cmp_ne_u32_e64 s[0:1], 0, v41510; GFX9-NEXT:    v_mov_b32_e32 v13, 01511; GFX9-NEXT:    v_cndmask_b32_e64 v4, v11, v5, s[0:1]1512; GFX9-NEXT:    v_cndmask_b32_e64 v5, v12, v14, s[0:1]1513; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v15, vcc1514; GFX9-NEXT:    v_cndmask_b32_e32 v0, v10, v0, vcc1515; GFX9-NEXT:    v_cndmask_b32_e64 v8, v8, v9, s[0:1]1516; GFX9-NEXT:    v_cndmask_b32_e64 v9, v1, v0, s[0:1]1517; GFX9-NEXT:    global_store_dwordx4 v13, v[2:5], s[12:13]1518; GFX9-NEXT:    global_store_dwordx4 v13, v[6:9], s[14:15]1519; GFX9-NEXT:    s_endpgm1520;1521; GFX10-LABEL: udivrem_v2i64:1522; GFX10:       ; %bb.0:1523; GFX10-NEXT:    s_clause 0x11524; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x201525; GFX10-NEXT:    s_load_dwordx8 s[12:19], s[8:9], 0x01526; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1527; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s51528; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s71529; GFX10-NEXT:    v_cvt_f32_u32_e32 v2, s41530; GFX10-NEXT:    v_cvt_f32_u32_e32 v3, s61531; GFX10-NEXT:    s_sub_u32 s1, 0, s41532; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f800000, v01533; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f800000, v11534; GFX10-NEXT:    s_subb_u32 s2, 0, s51535; GFX10-NEXT:    s_sub_u32 s3, 0, s61536; GFX10-NEXT:    s_subb_u32 s10, 0, s71537; GFX10-NEXT:    v_add_f32_e32 v0, v0, v21538; GFX10-NEXT:    v_add_f32_e32 v1, v1, v31539; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v01540; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v11541; GFX10-NEXT:    v_mul_f32_e32 v0, 0x5f7ffffc, v01542; GFX10-NEXT:    v_mul_f32_e32 v1, 0x5f7ffffc, v11543; GFX10-NEXT:    v_mul_f32_e32 v2, 0x2f800000, v01544; GFX10-NEXT:    v_mul_f32_e32 v3, 0x2f800000, v11545; GFX10-NEXT:    v_trunc_f32_e32 v2, v21546; GFX10-NEXT:    v_trunc_f32_e32 v4, v31547; GFX10-NEXT:    v_mul_f32_e32 v3, 0xcf800000, v21548; GFX10-NEXT:    v_mul_f32_e32 v5, 0xcf800000, v41549; GFX10-NEXT:    v_cvt_u32_f32_e32 v9, v21550; GFX10-NEXT:    v_cvt_u32_f32_e32 v10, v41551; GFX10-NEXT:    v_add_f32_e32 v0, v3, v01552; GFX10-NEXT:    v_add_f32_e32 v1, v5, v11553; GFX10-NEXT:    v_cvt_u32_f32_e32 v7, v01554; GFX10-NEXT:    v_cvt_u32_f32_e32 v8, v11555; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s1, v7, 01556; GFX10-NEXT:    v_mad_u64_u32 v[2:3], s0, s3, v8, 01557; GFX10-NEXT:    v_mul_hi_u32 v11, v9, v01558; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, s1, v9, v[1:2]1559; GFX10-NEXT:    v_mad_u64_u32 v[5:6], s0, s3, v10, v[3:4]1560; GFX10-NEXT:    v_mul_lo_u32 v6, v9, v01561; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s0, s2, v7, v[4:5]1562; GFX10-NEXT:    v_mul_hi_u32 v4, v7, v01563; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s10, v8, v[5:6]1564; GFX10-NEXT:    v_mul_lo_u32 v1, v10, v21565; GFX10-NEXT:    v_mul_hi_u32 v5, v8, v21566; GFX10-NEXT:    v_mul_hi_u32 v2, v10, v21567; GFX10-NEXT:    v_mul_lo_u32 v12, v7, v31568; GFX10-NEXT:    v_mul_lo_u32 v13, v9, v31569; GFX10-NEXT:    v_mul_hi_u32 v14, v7, v31570; GFX10-NEXT:    v_mul_lo_u32 v15, v8, v01571; GFX10-NEXT:    v_mul_lo_u32 v16, v10, v01572; GFX10-NEXT:    v_mul_hi_u32 v17, v8, v01573; GFX10-NEXT:    v_mul_hi_u32 v3, v9, v31574; GFX10-NEXT:    v_mul_hi_u32 v0, v10, v01575; GFX10-NEXT:    v_add_co_u32 v6, s0, v6, v121576; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s01577; GFX10-NEXT:    v_add_co_u32 v11, s0, v13, v111578; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s01579; GFX10-NEXT:    v_add_co_u32 v1, s0, v1, v151580; GFX10-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s01581; GFX10-NEXT:    v_add_co_u32 v2, s0, v16, v21582; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s01583; GFX10-NEXT:    v_add_co_u32 v4, s0, v6, v41584; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s01585; GFX10-NEXT:    v_add_co_u32 v6, s0, v11, v141586; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s01587; GFX10-NEXT:    v_add_co_u32 v1, s0, v1, v51588; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s01589; GFX10-NEXT:    v_add_nc_u32_e32 v4, v12, v41590; GFX10-NEXT:    v_add_co_u32 v2, s0, v2, v171591; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s01592; GFX10-NEXT:    v_add_nc_u32_e32 v1, v15, v11593; GFX10-NEXT:    v_add_co_u32 v4, s0, v6, v41594; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s01595; GFX10-NEXT:    v_add_nc_u32_e32 v11, v13, v111596; GFX10-NEXT:    v_add_co_u32 v1, s0, v2, v11597; GFX10-NEXT:    v_add_nc_u32_e32 v5, v16, v51598; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s01599; GFX10-NEXT:    v_add3_u32 v3, v11, v6, v31600; GFX10-NEXT:    v_add_co_u32 v7, vcc_lo, v7, v41601; GFX10-NEXT:    v_add_co_u32 v8, s0, v8, v11602; GFX10-NEXT:    v_add3_u32 v2, v5, v2, v01603; GFX10-NEXT:    v_add_co_ci_u32_e32 v9, vcc_lo, v9, v3, vcc_lo1604; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s11, s1, v7, 01605; GFX10-NEXT:    v_add_co_ci_u32_e64 v10, vcc_lo, v10, v2, s01606; GFX10-NEXT:    v_mad_u64_u32 v[2:3], s0, s3, v8, 01607; GFX10-NEXT:    v_mul_hi_u32 v11, v9, v01608; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, s1, v9, v[1:2]1609; GFX10-NEXT:    v_mad_u64_u32 v[5:6], s0, s3, v10, v[3:4]1610; GFX10-NEXT:    v_mul_lo_u32 v6, v9, v01611; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s0, s2, v7, v[4:5]1612; GFX10-NEXT:    v_mul_hi_u32 v4, v7, v01613; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s10, v8, v[5:6]1614; GFX10-NEXT:    v_mul_lo_u32 v1, v10, v21615; GFX10-NEXT:    v_mul_hi_u32 v5, v8, v21616; GFX10-NEXT:    v_mul_hi_u32 v2, v10, v21617; GFX10-NEXT:    v_mul_lo_u32 v12, v7, v31618; GFX10-NEXT:    v_mul_lo_u32 v13, v9, v31619; GFX10-NEXT:    v_mul_hi_u32 v14, v7, v31620; GFX10-NEXT:    v_mul_lo_u32 v15, v8, v01621; GFX10-NEXT:    v_mul_lo_u32 v16, v10, v01622; GFX10-NEXT:    v_mul_hi_u32 v17, v8, v01623; GFX10-NEXT:    v_mul_hi_u32 v3, v9, v31624; GFX10-NEXT:    v_mul_hi_u32 v0, v10, v01625; GFX10-NEXT:    v_add_co_u32 v6, s0, v6, v121626; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s01627; GFX10-NEXT:    v_add_co_u32 v11, s0, v13, v111628; GFX10-NEXT:    v_cndmask_b32_e64 v13, 0, 1, s01629; GFX10-NEXT:    v_add_co_u32 v1, s0, v1, v151630; GFX10-NEXT:    v_cndmask_b32_e64 v15, 0, 1, s01631; GFX10-NEXT:    v_add_co_u32 v2, s0, v16, v21632; GFX10-NEXT:    v_cndmask_b32_e64 v16, 0, 1, s01633; GFX10-NEXT:    v_add_co_u32 v4, s0, v6, v41634; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s01635; GFX10-NEXT:    v_add_co_u32 v6, s0, v11, v141636; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s01637; GFX10-NEXT:    v_add_co_u32 v1, s0, v1, v51638; GFX10-NEXT:    v_cndmask_b32_e64 v1, 0, 1, s01639; GFX10-NEXT:    v_add_nc_u32_e32 v4, v12, v41640; GFX10-NEXT:    v_add_co_u32 v2, s0, v2, v171641; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s01642; GFX10-NEXT:    v_add_nc_u32_e32 v1, v15, v11643; GFX10-NEXT:    v_add_co_u32 v4, s0, v6, v41644; GFX10-NEXT:    v_add_nc_u32_e32 v11, v13, v111645; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s01646; GFX10-NEXT:    v_add_co_u32 v1, s0, v2, v11647; GFX10-NEXT:    v_add_nc_u32_e32 v5, v16, v51648; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, 1, s01649; GFX10-NEXT:    v_add3_u32 v3, v11, v6, v31650; GFX10-NEXT:    v_add_co_u32 v4, vcc_lo, v7, v41651; GFX10-NEXT:    v_add_co_u32 v1, s0, v8, v11652; GFX10-NEXT:    v_add3_u32 v0, v5, v2, v01653; GFX10-NEXT:    v_add_co_ci_u32_e32 v2, vcc_lo, v9, v3, vcc_lo1654; GFX10-NEXT:    v_mul_lo_u32 v3, s17, v41655; GFX10-NEXT:    v_mul_hi_u32 v5, s16, v41656; GFX10-NEXT:    v_add_co_ci_u32_e64 v0, vcc_lo, v10, v0, s01657; GFX10-NEXT:    v_mul_lo_u32 v8, s16, v21658; GFX10-NEXT:    v_mul_hi_u32 v4, s17, v41659; GFX10-NEXT:    v_mul_lo_u32 v9, s17, v21660; GFX10-NEXT:    v_mul_lo_u32 v6, s19, v11661; GFX10-NEXT:    v_mul_lo_u32 v11, s18, v01662; GFX10-NEXT:    v_mul_hi_u32 v7, s18, v11663; GFX10-NEXT:    v_mul_hi_u32 v1, s19, v11664; GFX10-NEXT:    v_mul_lo_u32 v12, s19, v01665; GFX10-NEXT:    v_add_co_u32 v3, s0, v3, v81666; GFX10-NEXT:    v_mul_hi_u32 v10, s16, v21667; GFX10-NEXT:    v_cndmask_b32_e64 v8, 0, 1, s01668; GFX10-NEXT:    v_add_co_u32 v4, s0, v9, v41669; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, 1, s01670; GFX10-NEXT:    v_add_co_u32 v6, s0, v6, v111671; GFX10-NEXT:    v_cndmask_b32_e64 v11, 0, 1, s01672; GFX10-NEXT:    v_add_co_u32 v1, s0, v12, v11673; GFX10-NEXT:    v_mul_hi_u32 v13, s18, v01674; GFX10-NEXT:    v_cndmask_b32_e64 v12, 0, 1, s01675; GFX10-NEXT:    v_add_co_u32 v3, s0, v3, v51676; GFX10-NEXT:    v_cndmask_b32_e64 v3, 0, 1, s01677; GFX10-NEXT:    v_add_co_u32 v4, s0, v4, v101678; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s01679; GFX10-NEXT:    v_add_co_u32 v6, s0, v6, v71680; GFX10-NEXT:    v_cndmask_b32_e64 v6, 0, 1, s01681; GFX10-NEXT:    v_add_co_u32 v1, s0, v1, v131682; GFX10-NEXT:    v_cndmask_b32_e64 v7, 0, 1, s01683; GFX10-NEXT:    v_mul_hi_u32 v10, s19, v01684; GFX10-NEXT:    v_add_nc_u32_e32 v0, v8, v31685; GFX10-NEXT:    v_add_nc_u32_e32 v3, v9, v51686; GFX10-NEXT:    v_add_nc_u32_e32 v5, v11, v61687; GFX10-NEXT:    v_mul_hi_u32 v2, s17, v21688; GFX10-NEXT:    v_add_nc_u32_e32 v6, v12, v71689; GFX10-NEXT:    v_add_co_u32 v7, s0, v4, v01690; GFX10-NEXT:    v_cndmask_b32_e64 v4, 0, 1, s01691; GFX10-NEXT:    v_add_co_u32 v8, s0, v1, v51692; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, 1, s01693; GFX10-NEXT:    v_mad_u64_u32 v[0:1], s0, s4, v7, 01694; GFX10-NEXT:    v_add3_u32 v9, v3, v4, v21695; GFX10-NEXT:    v_mad_u64_u32 v[2:3], s0, s6, v8, 01696; GFX10-NEXT:    v_add3_u32 v10, v6, v5, v101697; GFX10-NEXT:    v_mov_b32_e32 v12, 01698; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, s4, v9, v[1:2]1699; GFX10-NEXT:    v_add_co_u32 v1, vcc_lo, v7, 11700; GFX10-NEXT:    v_add_co_ci_u32_e32 v11, vcc_lo, 0, v9, vcc_lo1701; GFX10-NEXT:    v_mad_u64_u32 v[5:6], s0, s6, v10, v[3:4]1702; GFX10-NEXT:    v_add_co_u32 v6, vcc_lo, v1, 11703; GFX10-NEXT:    v_add_co_ci_u32_e32 v13, vcc_lo, 0, v11, vcc_lo1704; GFX10-NEXT:    v_sub_co_u32 v14, vcc_lo, s16, v01705; GFX10-NEXT:    v_mad_u64_u32 v[3:4], s0, s5, v7, v[4:5]1706; GFX10-NEXT:    v_mad_u64_u32 v[4:5], s0, s7, v8, v[5:6]1707; GFX10-NEXT:    v_sub_nc_u32_e32 v5, s17, v31708; GFX10-NEXT:    v_sub_co_ci_u32_e64 v3, s0, s17, v3, vcc_lo1709; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s5, v5, vcc_lo1710; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v141711; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc_lo1712; GFX10-NEXT:    v_sub_co_u32 v15, vcc_lo, v14, s41713; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v16, s0, 0, v0, vcc_lo1714; GFX10-NEXT:    v_sub_co_u32 v17, s0, s18, v21715; GFX10-NEXT:    v_sub_co_ci_u32_e64 v18, s1, s19, v4, s01716; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s4, v151717; GFX10-NEXT:    v_subrev_co_ci_u32_e32 v0, vcc_lo, s5, v0, vcc_lo1718; GFX10-NEXT:    v_sub_nc_u32_e32 v4, s19, v41719; GFX10-NEXT:    v_cndmask_b32_e64 v2, 0, -1, s11720; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s5, v161721; GFX10-NEXT:    v_cndmask_b32_e64 v19, 0, -1, s11722; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s5, v31723; GFX10-NEXT:    v_cndmask_b32_e64 v20, 0, -1, s11724; GFX10-NEXT:    v_cmp_eq_u32_e64 s1, s5, v161725; GFX10-NEXT:    v_cndmask_b32_e64 v2, v19, v2, s11726; GFX10-NEXT:    v_cmp_eq_u32_e64 s1, s5, v31727; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v21728; GFX10-NEXT:    v_cndmask_b32_e64 v5, v20, v5, s11729; GFX10-NEXT:    v_sub_co_u32 v2, s1, v15, s41730; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v6, vcc_lo1731; GFX10-NEXT:    v_cmp_ne_u32_e64 s2, 0, v51732; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v6, s1, 0, v0, s11733; GFX10-NEXT:    v_cndmask_b32_e32 v5, v11, v13, vcc_lo1734; GFX10-NEXT:    v_cmp_le_u32_e64 s1, s7, v181735; GFX10-NEXT:    v_cndmask_b32_e64 v0, v7, v1, s21736; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v7, s0, s7, v4, s01737; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s6, v171738; GFX10-NEXT:    v_cndmask_b32_e64 v1, v9, v5, s21739; GFX10-NEXT:    v_cndmask_b32_e32 v2, v15, v2, vcc_lo1740; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, -1, s11741; GFX10-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc_lo1742; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, -1, s01743; GFX10-NEXT:    v_sub_co_u32 v11, s0, v17, s61744; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v13, s1, 0, v7, s01745; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, s7, v181746; GFX10-NEXT:    v_cndmask_b32_e64 v4, v14, v2, s21747; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v9, vcc_lo1748; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s7, v131749; GFX10-NEXT:    v_cndmask_b32_e64 v5, 0, -1, vcc_lo1750; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s6, v111751; GFX10-NEXT:    v_cndmask_b32_e64 v9, 0, -1, vcc_lo1752; GFX10-NEXT:    v_add_co_u32 v14, vcc_lo, v8, 11753; GFX10-NEXT:    v_add_co_ci_u32_e32 v15, vcc_lo, 0, v10, vcc_lo1754; GFX10-NEXT:    v_cmp_eq_u32_e32 vcc_lo, s7, v131755; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v9, vcc_lo1756; GFX10-NEXT:    v_add_co_u32 v9, vcc_lo, v14, 11757; GFX10-NEXT:    v_add_co_ci_u32_e32 v16, vcc_lo, 0, v15, vcc_lo1758; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v7, vcc_lo, s7, v7, s01759; GFX10-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v51760; GFX10-NEXT:    v_sub_co_u32 v5, s0, v11, s61761; GFX10-NEXT:    v_subrev_co_ci_u32_e64 v7, s0, 0, v7, s01762; GFX10-NEXT:    v_cndmask_b32_e32 v9, v14, v9, vcc_lo1763; GFX10-NEXT:    v_cndmask_b32_e32 v14, v15, v16, vcc_lo1764; GFX10-NEXT:    v_cmp_ne_u32_e64 s0, 0, v21765; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v5, vcc_lo1766; GFX10-NEXT:    v_cndmask_b32_e32 v7, v13, v7, vcc_lo1767; GFX10-NEXT:    v_cndmask_b32_e64 v5, v3, v6, s21768; GFX10-NEXT:    v_cndmask_b32_e64 v2, v8, v9, s01769; GFX10-NEXT:    v_cndmask_b32_e64 v3, v10, v14, s01770; GFX10-NEXT:    v_cndmask_b32_e64 v6, v17, v11, s01771; GFX10-NEXT:    v_cndmask_b32_e64 v7, v18, v7, s01772; GFX10-NEXT:    global_store_dwordx4 v12, v[0:3], s[12:13]1773; GFX10-NEXT:    global_store_dwordx4 v12, v[4:7], s[14:15]1774; GFX10-NEXT:    s_endpgm1775  %div = udiv <2 x i64> %x, %y1776  store <2 x i64> %div, ptr addrspace(1) %out01777  %rem = urem <2 x i64> %x, %y1778  store <2 x i64> %rem, ptr addrspace(1) %out11779  ret void1780}1781 1782define amdgpu_kernel void @udiv_i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i8 %x, i8 %y) {1783; GFX8-LABEL: udiv_i8:1784; GFX8:       ; %bb.0:1785; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x101786; GFX8-NEXT:    s_add_i32 s12, s12, s171787; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s131788; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81789; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1790; GFX8-NEXT:    s_bfe_u32 s5, s4, 0x800081791; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, s51792; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v01793; GFX8-NEXT:    s_sub_i32 s0, 0, s51794; GFX8-NEXT:    s_and_b32 s4, s4, 0xff1795; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01796; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v01797; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v01798; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01799; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v11800; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v11801; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v01802; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1803; GFX8-NEXT:    v_mov_b32_e32 v0, s01804; GFX8-NEXT:    v_mov_b32_e32 v1, s11805; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s51806; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v21807; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v31808; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v31809; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc1810; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v31811; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1812; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v21813; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v31814; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc1815; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v31816; GFX8-NEXT:    flat_store_byte v[0:1], v21817; GFX8-NEXT:    v_mov_b32_e32 v0, s21818; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1819; GFX8-NEXT:    v_mov_b32_e32 v1, s31820; GFX8-NEXT:    flat_store_byte v[0:1], v31821; GFX8-NEXT:    s_endpgm1822;1823; GFX9-LABEL: udiv_i8:1824; GFX9:       ; %bb.0:1825; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x101826; GFX9-NEXT:    v_mov_b32_e32 v2, 01827; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1828; GFX9-NEXT:    s_bfe_u32 s4, s0, 0x800081829; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s41830; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01831; GFX9-NEXT:    s_sub_i32 s1, 0, s41832; GFX9-NEXT:    s_and_b32 s5, s0, 0xff1833; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01834; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v01835; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v01836; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01837; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v11838; GFX9-NEXT:    v_add_u32_e32 v0, v0, v11839; GFX9-NEXT:    v_mul_hi_u32 v0, s5, v01840; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s41841; GFX9-NEXT:    v_add_u32_e32 v3, 1, v01842; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v11843; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v11844; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc1845; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v11846; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1847; GFX9-NEXT:    v_add_u32_e32 v3, 1, v01848; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v11849; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc1850; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v11851; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc1852; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1853; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]1854; GFX9-NEXT:    global_store_byte v2, v1, s[2:3]1855; GFX9-NEXT:    s_endpgm1856;1857; GFX10-LABEL: udiv_i8:1858; GFX10:       ; %bb.0:1859; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x101860; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1861; GFX10-NEXT:    s_bfe_u32 s4, s0, 0x800081862; GFX10-NEXT:    s_and_b32 s0, s0, 0xff1863; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, s41864; GFX10-NEXT:    s_sub_i32 s1, 0, s41865; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v01866; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01867; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v01868; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v01869; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v11870; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v11871; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v01872; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s41873; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v01874; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v11875; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01876; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v11877; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v11878; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1879; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1880; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v01881; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v11882; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v11883; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo1884; GFX10-NEXT:    v_mov_b32_e32 v2, 01885; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo1886; GFX10-NEXT:    s_waitcnt lgkmcnt(0)1887; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]1888; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]1889; GFX10-NEXT:    s_endpgm1890  %div = udiv i8 %x, %y1891  store i8 %div, ptr addrspace(1) %out01892  %rem = urem i8 %x, %y1893  store i8 %rem, ptr addrspace(1) %out11894  ret void1895}1896 1897define amdgpu_kernel void @udivrem_v2i8(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i8> %x, <2 x i8> %y) {1898; GFX8-LABEL: udivrem_v2i8:1899; GFX8:       ; %bb.0:1900; GFX8-NEXT:    s_load_dword s0, s[8:9], 0x101901; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x01902; GFX8-NEXT:    s_add_i32 s12, s12, s171903; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s131904; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 81905; GFX8-NEXT:    s_waitcnt lgkmcnt(0)1906; GFX8-NEXT:    s_bfe_u32 s2, s0, 0x800101907; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, s21908; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v01909; GFX8-NEXT:    v_cvt_f32_ubyte3_e32 v1, s01910; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v11911; GFX8-NEXT:    s_sub_i32 s1, 0, s21912; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01913; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v01914; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v11915; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v11916; GFX8-NEXT:    s_lshr_b32 s3, s0, 241917; GFX8-NEXT:    v_mul_lo_u32 v2, s1, v01918; GFX8-NEXT:    s_sub_i32 s1, 0, s31919; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v11920; GFX8-NEXT:    s_and_b32 s1, s0, 0xff1921; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v21922; GFX8-NEXT:    s_bfe_u32 s8, s0, 0x800081923; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v31924; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v21925; GFX8-NEXT:    v_mul_hi_u32 v0, s1, v01926; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v31927; GFX8-NEXT:    v_mul_hi_u32 v1, s8, v11928; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s21929; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v01930; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s1, v21931; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s2, v21932; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc1933; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s2, v21934; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc1935; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v01936; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s2, v21937; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc1938; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s31939; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s2, v21940; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc1941; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s8, v31942; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v11943; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v31944; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc1945; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v31946; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1947; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v11948; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v31949; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc1950; GFX8-NEXT:    v_and_b32_e32 v1, 0xff, v11951; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v31952; GFX8-NEXT:    v_lshlrev_b16_e32 v1, 8, v11953; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc1954; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD1955; GFX8-NEXT:    v_mov_b32_e32 v0, s41956; GFX8-NEXT:    v_mov_b32_e32 v1, s51957; GFX8-NEXT:    flat_store_short v[0:1], v41958; GFX8-NEXT:    v_and_b32_e32 v0, 0xff, v31959; GFX8-NEXT:    v_lshlrev_b16_e32 v0, 8, v01960; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD1961; GFX8-NEXT:    v_mov_b32_e32 v0, s61962; GFX8-NEXT:    v_mov_b32_e32 v1, s71963; GFX8-NEXT:    flat_store_short v[0:1], v21964; GFX8-NEXT:    s_endpgm1965;1966; GFX9-LABEL: udivrem_v2i8:1967; GFX9:       ; %bb.0:1968; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x101969; GFX9-NEXT:    s_waitcnt lgkmcnt(0)1970; GFX9-NEXT:    s_bfe_u32 s4, s0, 0x800101971; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v1, s41972; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v11973; GFX9-NEXT:    v_cvt_f32_ubyte3_e32 v0, s01974; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v01975; GFX9-NEXT:    s_sub_i32 s1, 0, s41976; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v11977; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v11978; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v01979; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v01980; GFX9-NEXT:    s_lshr_b32 s5, s0, 241981; GFX9-NEXT:    v_mul_lo_u32 v3, s1, v11982; GFX9-NEXT:    s_sub_i32 s2, 0, s51983; GFX9-NEXT:    v_mul_lo_u32 v2, s2, v01984; GFX9-NEXT:    s_and_b32 s6, s0, 0xff1985; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v31986; GFX9-NEXT:    s_bfe_u32 s7, s0, 0x800081987; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v21988; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x01989; GFX9-NEXT:    v_add_u32_e32 v1, v1, v31990; GFX9-NEXT:    v_mul_hi_u32 v1, s6, v11991; GFX9-NEXT:    v_add_u32_e32 v0, v0, v21992; GFX9-NEXT:    v_mul_hi_u32 v0, s7, v01993; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s41994; GFX9-NEXT:    v_add_u32_e32 v4, 1, v11995; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s51996; GFX9-NEXT:    v_sub_u32_e32 v3, s6, v31997; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v31998; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc1999; GFX9-NEXT:    v_subrev_u32_e32 v4, s4, v32000; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2001; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12002; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v32003; GFX9-NEXT:    v_sub_u32_e32 v2, s7, v22004; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2005; GFX9-NEXT:    v_subrev_u32_e32 v4, s4, v32006; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2007; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02008; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v22009; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2010; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v22011; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2012; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02013; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s5, v22014; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2015; GFX9-NEXT:    v_and_b32_e32 v0, 0xff, v02016; GFX9-NEXT:    v_subrev_u32_e32 v4, s5, v22017; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v02018; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2019; GFX9-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2020; GFX9-NEXT:    v_mov_b32_e32 v1, 02021; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2022; GFX9-NEXT:    global_store_short v1, v0, s[0:1]2023; GFX9-NEXT:    v_and_b32_e32 v0, 0xff, v22024; GFX9-NEXT:    v_lshlrev_b16_e32 v0, 8, v02025; GFX9-NEXT:    v_or_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2026; GFX9-NEXT:    global_store_short v1, v0, s[2:3]2027; GFX9-NEXT:    s_endpgm2028;2029; GFX10-LABEL: udivrem_v2i8:2030; GFX10:       ; %bb.0:2031; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102032; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2033; GFX10-NEXT:    v_cvt_f32_ubyte3_e32 v0, s02034; GFX10-NEXT:    s_bfe_u32 s1, s0, 0x800102035; GFX10-NEXT:    s_lshr_b32 s2, s0, 242036; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v1, s12037; GFX10-NEXT:    s_sub_i32 s3, 0, s22038; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02039; GFX10-NEXT:    s_sub_i32 s4, 0, s12040; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v12041; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02042; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12043; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02044; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v12045; GFX10-NEXT:    v_mul_lo_u32 v2, s3, v02046; GFX10-NEXT:    s_bfe_u32 s3, s0, 0x800082047; GFX10-NEXT:    s_and_b32 s0, s0, 0xff2048; GFX10-NEXT:    v_mul_lo_u32 v3, s4, v12049; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02050; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v22051; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v32052; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v22053; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v32054; GFX10-NEXT:    v_mul_hi_u32 v0, s3, v02055; GFX10-NEXT:    v_mul_hi_u32 v1, s0, v12056; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s22057; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02058; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s12059; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v12060; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s3, v22061; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s0, v32062; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22063; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v22064; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32065; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s1, v32066; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2067; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo2068; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s02069; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s02070; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02071; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22072; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s2, v22073; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v12074; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32075; GFX10-NEXT:    v_subrev_nc_u32_e32 v7, s1, v32076; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2077; GFX10-NEXT:    v_mov_b32_e32 v4, 0xff2078; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo2079; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s02080; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v7, s02081; GFX10-NEXT:    v_and_b32_sdwa v0, v0, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2082; GFX10-NEXT:    v_and_b32_sdwa v2, v2, v4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2083; GFX10-NEXT:    v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2084; GFX10-NEXT:    v_mov_b32_e32 v1, 02085; GFX10-NEXT:    v_or_b32_sdwa v2, v3, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2086; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2087; GFX10-NEXT:    global_store_short v1, v0, s[4:5]2088; GFX10-NEXT:    global_store_short v1, v2, s[6:7]2089; GFX10-NEXT:    s_endpgm2090  %div = udiv <2 x i8> %x, %y2091  store <2 x i8> %div, ptr addrspace(1) %out02092  %rem = urem <2 x i8> %x, %y2093  store <2 x i8> %rem, ptr addrspace(1) %out12094  ret void2095}2096 2097define amdgpu_kernel void @udiv_i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i16 %x, i16 %y) {2098; GFX8-LABEL: udiv_i16:2099; GFX8:       ; %bb.0:2100; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x102101; GFX8-NEXT:    s_add_i32 s12, s12, s172102; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132103; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82104; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2105; GFX8-NEXT:    s_lshr_b32 s5, s4, 162106; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s52107; GFX8-NEXT:    s_sub_i32 s0, 0, s52108; GFX8-NEXT:    s_and_b32 s4, s4, 0xffff2109; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02110; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02111; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02112; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v02113; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02114; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12115; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12116; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v02117; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2118; GFX8-NEXT:    v_mov_b32_e32 v0, s02119; GFX8-NEXT:    v_mov_b32_e32 v1, s12120; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s52121; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22122; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v32123; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32124; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2125; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32126; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2127; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22128; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32129; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2130; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32131; GFX8-NEXT:    flat_store_short v[0:1], v22132; GFX8-NEXT:    v_mov_b32_e32 v0, s22133; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2134; GFX8-NEXT:    v_mov_b32_e32 v1, s32135; GFX8-NEXT:    flat_store_short v[0:1], v32136; GFX8-NEXT:    s_endpgm2137;2138; GFX9-LABEL: udiv_i16:2139; GFX9:       ; %bb.0:2140; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x102141; GFX9-NEXT:    v_mov_b32_e32 v2, 02142; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2143; GFX9-NEXT:    s_lshr_b32 s4, s0, 162144; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s42145; GFX9-NEXT:    s_sub_i32 s1, 0, s42146; GFX9-NEXT:    s_and_b32 s5, s0, 0xffff2147; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02148; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02149; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02150; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v02151; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02152; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v12153; GFX9-NEXT:    v_add_u32_e32 v0, v0, v12154; GFX9-NEXT:    v_mul_hi_u32 v0, s5, v02155; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s42156; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02157; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v12158; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12159; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2160; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12161; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2162; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02163; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12164; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2165; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12166; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2167; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2168; GFX9-NEXT:    global_store_short v2, v0, s[0:1]2169; GFX9-NEXT:    global_store_short v2, v1, s[2:3]2170; GFX9-NEXT:    s_endpgm2171;2172; GFX10-LABEL: udiv_i16:2173; GFX10:       ; %bb.0:2174; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102175; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2176; GFX10-NEXT:    s_lshr_b32 s4, s0, 162177; GFX10-NEXT:    s_and_b32 s0, s0, 0xffff2178; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s42179; GFX10-NEXT:    s_sub_i32 s1, 0, s42180; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02181; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02182; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02183; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v02184; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v12185; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v12186; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v02187; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s42188; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02189; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v12190; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02191; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12192; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12193; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2194; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2195; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02196; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12197; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12198; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2199; GFX10-NEXT:    v_mov_b32_e32 v2, 02200; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2201; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2202; GFX10-NEXT:    global_store_short v2, v0, s[0:1]2203; GFX10-NEXT:    global_store_short v2, v1, s[2:3]2204; GFX10-NEXT:    s_endpgm2205  %div = udiv i16 %x, %y2206  store i16 %div, ptr addrspace(1) %out02207  %rem = urem i16 %x, %y2208  store i16 %rem, ptr addrspace(1) %out12209  ret void2210}2211 2212define amdgpu_kernel void @udivrem_v2i16(ptr addrspace(1) %out0, ptr addrspace(1) %out1, <2 x i16> %x, <2 x i16> %y) {2213; GFX8-LABEL: udivrem_v2i16:2214; GFX8:       ; %bb.0:2215; GFX8-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102216; GFX8-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02217; GFX8-NEXT:    s_add_i32 s12, s12, s172218; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132219; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82220; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2221; GFX8-NEXT:    s_and_b32 s2, s1, 0xffff2222; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s22223; GFX8-NEXT:    s_lshr_b32 s3, s1, 162224; GFX8-NEXT:    v_cvt_f32_u32_e32 v1, s32225; GFX8-NEXT:    s_sub_i32 s1, 0, s22226; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02227; GFX8-NEXT:    s_lshr_b32 s8, s0, 162228; GFX8-NEXT:    v_rcp_iflag_f32_e32 v1, v12229; GFX8-NEXT:    s_and_b32 s0, s0, 0xffff2230; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02231; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02232; GFX8-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12233; GFX8-NEXT:    v_cvt_u32_f32_e32 v1, v12234; GFX8-NEXT:    v_mul_lo_u32 v2, s1, v02235; GFX8-NEXT:    s_sub_i32 s1, 0, s32236; GFX8-NEXT:    v_mul_lo_u32 v3, s1, v12237; GFX8-NEXT:    v_mul_hi_u32 v2, v0, v22238; GFX8-NEXT:    v_mul_hi_u32 v3, v1, v32239; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v22240; GFX8-NEXT:    v_mul_hi_u32 v0, s0, v02241; GFX8-NEXT:    v_add_u32_e32 v1, vcc, v1, v32242; GFX8-NEXT:    v_mul_hi_u32 v1, s8, v12243; GFX8-NEXT:    v_mul_lo_u32 v2, v0, s22244; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02245; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, s0, v22246; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s2, v22247; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2248; GFX8-NEXT:    v_subrev_u32_e64 v3, s[0:1], s2, v22249; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc2250; GFX8-NEXT:    v_add_u32_e32 v3, vcc, 1, v02251; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s2, v22252; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2253; GFX8-NEXT:    v_mul_lo_u32 v3, v1, s32254; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s2, v22255; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2256; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s8, v32257; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12258; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v32259; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2260; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v32261; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2262; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v12263; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s3, v32264; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2265; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s3, v32266; GFX8-NEXT:    v_and_b32_e32 v1, 0xffff, v12267; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2268; GFX8-NEXT:    v_lshlrev_b32_e32 v1, 16, v12269; GFX8-NEXT:    v_or_b32_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2270; GFX8-NEXT:    v_and_b32_e32 v0, 0xffff, v32271; GFX8-NEXT:    v_lshlrev_b32_e32 v0, 16, v02272; GFX8-NEXT:    v_or_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2273; GFX8-NEXT:    v_mov_b32_e32 v0, s42274; GFX8-NEXT:    v_mov_b32_e32 v1, s52275; GFX8-NEXT:    flat_store_dword v[0:1], v42276; GFX8-NEXT:    v_mov_b32_e32 v0, s62277; GFX8-NEXT:    v_mov_b32_e32 v1, s72278; GFX8-NEXT:    flat_store_dword v[0:1], v22279; GFX8-NEXT:    s_endpgm2280;2281; GFX9-LABEL: udivrem_v2i16:2282; GFX9:       ; %bb.0:2283; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102284; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2285; GFX9-NEXT:    s_and_b32 s3, s1, 0xffff2286; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s32287; GFX9-NEXT:    s_lshr_b32 s2, s1, 162288; GFX9-NEXT:    v_cvt_f32_u32_e32 v1, s22289; GFX9-NEXT:    s_sub_i32 s1, 0, s32290; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02291; GFX9-NEXT:    s_sub_i32 s4, 0, s22292; GFX9-NEXT:    v_rcp_iflag_f32_e32 v1, v12293; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02294; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02295; GFX9-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12296; GFX9-NEXT:    v_cvt_u32_f32_e32 v1, v12297; GFX9-NEXT:    v_mul_lo_u32 v2, s1, v02298; GFX9-NEXT:    s_lshr_b32 s1, s0, 162299; GFX9-NEXT:    v_mul_lo_u32 v3, s4, v12300; GFX9-NEXT:    s_and_b32 s0, s0, 0xffff2301; GFX9-NEXT:    v_mul_hi_u32 v2, v0, v22302; GFX9-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02303; GFX9-NEXT:    v_mul_hi_u32 v3, v1, v32304; GFX9-NEXT:    v_add_u32_e32 v0, v0, v22305; GFX9-NEXT:    v_mul_hi_u32 v0, s0, v02306; GFX9-NEXT:    v_add_u32_e32 v1, v1, v32307; GFX9-NEXT:    v_mul_hi_u32 v1, s1, v12308; GFX9-NEXT:    v_mul_lo_u32 v2, v0, s32309; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02310; GFX9-NEXT:    v_mul_lo_u32 v3, v1, s22311; GFX9-NEXT:    v_add_u32_e32 v5, 1, v12312; GFX9-NEXT:    v_sub_u32_e32 v2, s0, v22313; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v22314; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2315; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v22316; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2317; GFX9-NEXT:    v_add_u32_e32 v4, 1, v02318; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s3, v22319; GFX9-NEXT:    v_sub_u32_e32 v3, s1, v32320; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc2321; GFX9-NEXT:    v_subrev_u32_e32 v4, s3, v22322; GFX9-NEXT:    v_cmp_le_u32_e64 s[0:1], s2, v32323; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2324; GFX9-NEXT:    v_subrev_u32_e32 v4, s2, v32325; GFX9-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s[0:1]2326; GFX9-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s[0:1]2327; GFX9-NEXT:    v_add_u32_e32 v4, 1, v12328; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s2, v32329; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc2330; GFX9-NEXT:    v_subrev_u32_e32 v4, s2, v32331; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff, v02332; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2333; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v02334; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v22335; GFX9-NEXT:    v_mov_b32_e32 v2, 02336; GFX9-NEXT:    v_lshl_or_b32 v1, v3, 16, v12337; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2338; GFX9-NEXT:    global_store_dword v2, v0, s[4:5]2339; GFX9-NEXT:    global_store_dword v2, v1, s[6:7]2340; GFX9-NEXT:    s_endpgm2341;2342; GFX10-LABEL: udivrem_v2i16:2343; GFX10:       ; %bb.0:2344; GFX10-NEXT:    s_clause 0x12345; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102346; GFX10-NEXT:    s_load_dwordx4 s[4:7], s[8:9], 0x02347; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2348; GFX10-NEXT:    s_and_b32 s2, s1, 0xffff2349; GFX10-NEXT:    s_lshr_b32 s1, s1, 162350; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s22351; GFX10-NEXT:    v_cvt_f32_u32_e32 v1, s12352; GFX10-NEXT:    s_sub_i32 s3, 0, s22353; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02354; GFX10-NEXT:    v_rcp_iflag_f32_e32 v1, v12355; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02356; GFX10-NEXT:    v_mul_f32_e32 v1, 0x4f7ffffe, v12357; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02358; GFX10-NEXT:    v_cvt_u32_f32_e32 v1, v12359; GFX10-NEXT:    v_mul_lo_u32 v2, s3, v02360; GFX10-NEXT:    s_sub_i32 s3, 0, s12361; GFX10-NEXT:    v_mul_lo_u32 v3, s3, v12362; GFX10-NEXT:    s_and_b32 s3, s0, 0xffff2363; GFX10-NEXT:    s_lshr_b32 s0, s0, 162364; GFX10-NEXT:    v_mul_hi_u32 v2, v0, v22365; GFX10-NEXT:    v_mul_hi_u32 v3, v1, v32366; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v22367; GFX10-NEXT:    v_add_nc_u32_e32 v1, v1, v32368; GFX10-NEXT:    v_mul_hi_u32 v0, s3, v02369; GFX10-NEXT:    v_mul_hi_u32 v1, s0, v12370; GFX10-NEXT:    v_mul_lo_u32 v2, v0, s22371; GFX10-NEXT:    v_add_nc_u32_e32 v4, 1, v02372; GFX10-NEXT:    v_mul_lo_u32 v3, v1, s12373; GFX10-NEXT:    v_add_nc_u32_e32 v6, 1, v12374; GFX10-NEXT:    v_sub_nc_u32_e32 v2, s3, v22375; GFX10-NEXT:    v_sub_nc_u32_e32 v3, s0, v32376; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22377; GFX10-NEXT:    v_subrev_nc_u32_e32 v5, s2, v22378; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32379; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo2380; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s1, v32381; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo2382; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v6, s02383; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v02384; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v4, s02385; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s2, v22386; GFX10-NEXT:    v_subrev_nc_u32_e32 v4, s2, v22387; GFX10-NEXT:    v_cmp_le_u32_e64 s0, s1, v32388; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v5, vcc_lo2389; GFX10-NEXT:    v_add_nc_u32_e32 v5, 1, v12390; GFX10-NEXT:    v_subrev_nc_u32_e32 v6, s1, v32391; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo2392; GFX10-NEXT:    v_and_b32_e32 v0, 0xffff, v02393; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, v5, s02394; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, v6, s02395; GFX10-NEXT:    v_and_b32_e32 v2, 0xffff, v22396; GFX10-NEXT:    v_lshl_or_b32 v0, v1, 16, v02397; GFX10-NEXT:    v_mov_b32_e32 v1, 02398; GFX10-NEXT:    v_lshl_or_b32 v2, v3, 16, v22399; GFX10-NEXT:    global_store_dword v1, v0, s[4:5]2400; GFX10-NEXT:    global_store_dword v1, v2, s[6:7]2401; GFX10-NEXT:    s_endpgm2402  %div = udiv <2 x i16> %x, %y2403  store <2 x i16> %div, ptr addrspace(1) %out02404  %rem = urem <2 x i16> %x, %y2405  store <2 x i16> %rem, ptr addrspace(1) %out12406  ret void2407}2408 2409define amdgpu_kernel void @udivrem_i3(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i3 %x, i3 %y) {2410; GFX8-LABEL: udivrem_i3:2411; GFX8:       ; %bb.0:2412; GFX8-NEXT:    s_load_dword s4, s[8:9], 0x102413; GFX8-NEXT:    s_add_i32 s12, s12, s172414; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132415; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82416; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2417; GFX8-NEXT:    s_bfe_u32 s5, s4, 0x300082418; GFX8-NEXT:    v_cvt_f32_ubyte0_e32 v0, s52419; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02420; GFX8-NEXT:    s_sub_i32 s0, 0, s52421; GFX8-NEXT:    s_and_b32 s4, s4, 72422; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02423; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02424; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v02425; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02426; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12427; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12428; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v02429; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2430; GFX8-NEXT:    v_mov_b32_e32 v0, s02431; GFX8-NEXT:    v_mov_b32_e32 v1, s12432; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s52433; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22434; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v32435; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32436; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2437; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32438; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2439; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22440; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32441; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2442; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32443; GFX8-NEXT:    v_and_b32_e32 v2, 7, v22444; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2445; GFX8-NEXT:    flat_store_byte v[0:1], v22446; GFX8-NEXT:    v_mov_b32_e32 v0, s22447; GFX8-NEXT:    v_and_b32_e32 v2, 7, v32448; GFX8-NEXT:    v_mov_b32_e32 v1, s32449; GFX8-NEXT:    flat_store_byte v[0:1], v22450; GFX8-NEXT:    s_endpgm2451;2452; GFX9-LABEL: udivrem_i3:2453; GFX9:       ; %bb.0:2454; GFX9-NEXT:    s_load_dword s0, s[8:9], 0x102455; GFX9-NEXT:    v_mov_b32_e32 v2, 02456; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2457; GFX9-NEXT:    s_bfe_u32 s4, s0, 0x300082458; GFX9-NEXT:    v_cvt_f32_ubyte0_e32 v0, s42459; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02460; GFX9-NEXT:    s_sub_i32 s1, 0, s42461; GFX9-NEXT:    s_and_b32 s5, s0, 72462; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02463; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02464; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v02465; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02466; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v12467; GFX9-NEXT:    v_add_u32_e32 v0, v0, v12468; GFX9-NEXT:    v_mul_hi_u32 v0, s5, v02469; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s42470; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02471; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v12472; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12473; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2474; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12475; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2476; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02477; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12478; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2479; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12480; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2481; GFX9-NEXT:    v_and_b32_e32 v0, 7, v02482; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2483; GFX9-NEXT:    global_store_byte v2, v0, s[0:1]2484; GFX9-NEXT:    v_and_b32_e32 v0, 7, v12485; GFX9-NEXT:    global_store_byte v2, v0, s[2:3]2486; GFX9-NEXT:    s_endpgm2487;2488; GFX10-LABEL: udivrem_i3:2489; GFX10:       ; %bb.0:2490; GFX10-NEXT:    s_load_dword s0, s[8:9], 0x102491; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2492; GFX10-NEXT:    s_bfe_u32 s4, s0, 0x300082493; GFX10-NEXT:    s_and_b32 s0, s0, 72494; GFX10-NEXT:    v_cvt_f32_ubyte0_e32 v0, s42495; GFX10-NEXT:    s_sub_i32 s1, 0, s42496; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02497; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02498; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02499; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v02500; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v12501; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v12502; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v02503; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s42504; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02505; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v12506; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02507; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12508; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12509; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2510; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2511; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02512; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12513; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12514; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2515; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2516; GFX10-NEXT:    v_mov_b32_e32 v2, 02517; GFX10-NEXT:    v_and_b32_e32 v0, 7, v02518; GFX10-NEXT:    v_and_b32_e32 v1, 7, v12519; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2520; GFX10-NEXT:    global_store_byte v2, v0, s[0:1]2521; GFX10-NEXT:    global_store_byte v2, v1, s[2:3]2522; GFX10-NEXT:    s_endpgm2523  %div = udiv i3 %x, %y2524  store i3 %div, ptr addrspace(1) %out02525  %rem = urem i3 %x, %y2526  store i3 %rem, ptr addrspace(1) %out12527  ret void2528}2529 2530define amdgpu_kernel void @udivrem_i27(ptr addrspace(1) %out0, ptr addrspace(1) %out1, i27 %x, i27 %y) {2531; GFX8-LABEL: udivrem_i27:2532; GFX8:       ; %bb.0:2533; GFX8-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x102534; GFX8-NEXT:    s_add_i32 s12, s12, s172535; GFX8-NEXT:    s_mov_b32 flat_scratch_lo, s132536; GFX8-NEXT:    s_lshr_b32 flat_scratch_hi, s12, 82537; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2538; GFX8-NEXT:    s_and_b32 s5, s5, 0x7ffffff2539; GFX8-NEXT:    v_cvt_f32_u32_e32 v0, s52540; GFX8-NEXT:    s_sub_i32 s0, 0, s52541; GFX8-NEXT:    s_and_b32 s4, s4, 0x7ffffff2542; GFX8-NEXT:    v_rcp_iflag_f32_e32 v0, v02543; GFX8-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02544; GFX8-NEXT:    v_cvt_u32_f32_e32 v0, v02545; GFX8-NEXT:    v_mul_lo_u32 v1, s0, v02546; GFX8-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02547; GFX8-NEXT:    v_mul_hi_u32 v1, v0, v12548; GFX8-NEXT:    v_add_u32_e32 v0, vcc, v0, v12549; GFX8-NEXT:    v_mul_hi_u32 v2, s4, v02550; GFX8-NEXT:    s_waitcnt lgkmcnt(0)2551; GFX8-NEXT:    v_mov_b32_e32 v0, s02552; GFX8-NEXT:    v_mov_b32_e32 v1, s12553; GFX8-NEXT:    v_mul_lo_u32 v3, v2, s52554; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22555; GFX8-NEXT:    v_sub_u32_e32 v3, vcc, s4, v32556; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32557; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2558; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32559; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2560; GFX8-NEXT:    v_add_u32_e32 v4, vcc, 1, v22561; GFX8-NEXT:    v_cmp_le_u32_e32 vcc, s5, v32562; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc2563; GFX8-NEXT:    v_subrev_u32_e64 v4, s[0:1], s5, v32564; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v22565; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc2566; GFX8-NEXT:    flat_store_dword v[0:1], v22567; GFX8-NEXT:    v_mov_b32_e32 v0, s22568; GFX8-NEXT:    v_and_b32_e32 v2, 0x7ffffff, v32569; GFX8-NEXT:    v_mov_b32_e32 v1, s32570; GFX8-NEXT:    flat_store_dword v[0:1], v22571; GFX8-NEXT:    s_endpgm2572;2573; GFX9-LABEL: udivrem_i27:2574; GFX9:       ; %bb.0:2575; GFX9-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102576; GFX9-NEXT:    v_mov_b32_e32 v2, 02577; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2578; GFX9-NEXT:    s_and_b32 s4, s1, 0x7ffffff2579; GFX9-NEXT:    v_cvt_f32_u32_e32 v0, s42580; GFX9-NEXT:    s_sub_i32 s1, 0, s42581; GFX9-NEXT:    s_and_b32 s5, s0, 0x7ffffff2582; GFX9-NEXT:    v_rcp_iflag_f32_e32 v0, v02583; GFX9-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02584; GFX9-NEXT:    v_cvt_u32_f32_e32 v0, v02585; GFX9-NEXT:    v_mul_lo_u32 v1, s1, v02586; GFX9-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02587; GFX9-NEXT:    v_mul_hi_u32 v1, v0, v12588; GFX9-NEXT:    v_add_u32_e32 v0, v0, v12589; GFX9-NEXT:    v_mul_hi_u32 v0, s5, v02590; GFX9-NEXT:    v_mul_lo_u32 v1, v0, s42591; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02592; GFX9-NEXT:    v_sub_u32_e32 v1, s5, v12593; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12594; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2595; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12596; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2597; GFX9-NEXT:    v_add_u32_e32 v3, 1, v02598; GFX9-NEXT:    v_cmp_le_u32_e32 vcc, s4, v12599; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc2600; GFX9-NEXT:    v_subrev_u32_e32 v3, s4, v12601; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc2602; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v02603; GFX9-NEXT:    s_waitcnt lgkmcnt(0)2604; GFX9-NEXT:    global_store_dword v2, v0, s[0:1]2605; GFX9-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v12606; GFX9-NEXT:    global_store_dword v2, v0, s[2:3]2607; GFX9-NEXT:    s_endpgm2608;2609; GFX10-LABEL: udivrem_i27:2610; GFX10:       ; %bb.0:2611; GFX10-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x102612; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2613; GFX10-NEXT:    s_and_b32 s4, s1, 0x7ffffff2614; GFX10-NEXT:    s_and_b32 s0, s0, 0x7ffffff2615; GFX10-NEXT:    v_cvt_f32_u32_e32 v0, s42616; GFX10-NEXT:    s_sub_i32 s1, 0, s42617; GFX10-NEXT:    v_rcp_iflag_f32_e32 v0, v02618; GFX10-NEXT:    v_mul_f32_e32 v0, 0x4f7ffffe, v02619; GFX10-NEXT:    v_cvt_u32_f32_e32 v0, v02620; GFX10-NEXT:    v_mul_lo_u32 v1, s1, v02621; GFX10-NEXT:    v_mul_hi_u32 v1, v0, v12622; GFX10-NEXT:    v_add_nc_u32_e32 v0, v0, v12623; GFX10-NEXT:    v_mul_hi_u32 v0, s0, v02624; GFX10-NEXT:    v_mul_lo_u32 v1, v0, s42625; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02626; GFX10-NEXT:    v_sub_nc_u32_e32 v1, s0, v12627; GFX10-NEXT:    s_load_dwordx4 s[0:3], s[8:9], 0x02628; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12629; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12630; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2631; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2632; GFX10-NEXT:    v_add_nc_u32_e32 v2, 1, v02633; GFX10-NEXT:    v_cmp_le_u32_e32 vcc_lo, s4, v12634; GFX10-NEXT:    v_subrev_nc_u32_e32 v3, s4, v12635; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo2636; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo2637; GFX10-NEXT:    v_mov_b32_e32 v2, 02638; GFX10-NEXT:    v_and_b32_e32 v0, 0x7ffffff, v02639; GFX10-NEXT:    v_and_b32_e32 v1, 0x7ffffff, v12640; GFX10-NEXT:    s_waitcnt lgkmcnt(0)2641; GFX10-NEXT:    global_store_dword v2, v0, s[0:1]2642; GFX10-NEXT:    global_store_dword v2, v1, s[2:3]2643; GFX10-NEXT:    s_endpgm2644  %div = udiv i27 %x, %y2645  store i27 %div, ptr addrspace(1) %out02646  %rem = urem i27 %x, %y2647  store i27 %rem, ptr addrspace(1) %out12648  ret void2649}2650