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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=1 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,GISEL %s3; RUN: llc -global-isel -amdgpu-codegenprepare-disable-idiv-expansion=0 -mtriple=amdgcn-amd-amdpal < %s | FileCheck -check-prefixes=CHECK,CGP %s4 5; The same 32-bit expansion is implemented in the legalizer and in AMDGPUCodeGenPrepare.6 7define i32 @v_urem_i32(i32 %num, i32 %den) {8; GISEL-LABEL: v_urem_i32:9; GISEL: ; %bb.0:10; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v112; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v113; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v214; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v215; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v216; GISEL-NEXT: v_mul_lo_u32 v3, v3, v217; GISEL-NEXT: v_mul_hi_u32 v3, v2, v318; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v319; GISEL-NEXT: v_mul_hi_u32 v2, v0, v220; GISEL-NEXT: v_mul_lo_u32 v2, v2, v121; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v222; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v123; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v124; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc25; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v126; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v127; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc28; GISEL-NEXT: s_setpc_b64 s[30:31]29;30; CGP-LABEL: v_urem_i32:31; CGP: ; %bb.0:32; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; CGP-NEXT: v_cvt_f32_u32_e32 v2, v134; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v135; CGP-NEXT: v_rcp_f32_e32 v2, v236; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v237; CGP-NEXT: v_cvt_u32_f32_e32 v2, v238; CGP-NEXT: v_mul_lo_u32 v3, v3, v239; CGP-NEXT: v_mul_hi_u32 v3, v2, v340; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v341; CGP-NEXT: v_mul_hi_u32 v2, v0, v242; CGP-NEXT: v_mul_lo_u32 v2, v2, v143; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v244; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v145; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v146; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc47; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v148; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v149; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc50; CGP-NEXT: s_setpc_b64 s[30:31]51 %result = urem i32 %num, %den52 ret i32 %result53}54 55; FIXME: This is a workaround for not handling uniform VGPR case.56declare i32 @llvm.amdgcn.readfirstlane(i32)57 58define amdgpu_ps i32 @s_urem_i32(i32 inreg %num, i32 inreg %den) {59; GISEL-LABEL: s_urem_i32:60; GISEL: ; %bb.0:61; GISEL-NEXT: v_cvt_f32_u32_e32 v0, s162; GISEL-NEXT: s_sub_i32 s2, 0, s163; GISEL-NEXT: v_rcp_iflag_f32_e32 v0, v064; GISEL-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v065; GISEL-NEXT: v_cvt_u32_f32_e32 v0, v066; GISEL-NEXT: v_mul_lo_u32 v1, s2, v067; GISEL-NEXT: v_mul_hi_u32 v1, v0, v168; GISEL-NEXT: v_add_i32_e32 v0, vcc, v0, v169; GISEL-NEXT: v_mul_hi_u32 v0, s0, v070; GISEL-NEXT: v_mul_lo_u32 v0, v0, s171; GISEL-NEXT: v_sub_i32_e32 v0, vcc, s0, v072; GISEL-NEXT: v_subrev_i32_e32 v1, vcc, s1, v073; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v074; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc75; GISEL-NEXT: v_subrev_i32_e32 v1, vcc, s1, v076; GISEL-NEXT: v_cmp_le_u32_e32 vcc, s1, v077; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc78; GISEL-NEXT: v_readfirstlane_b32 s0, v079; GISEL-NEXT: ; return to shader part epilog80;81; CGP-LABEL: s_urem_i32:82; CGP: ; %bb.0:83; CGP-NEXT: v_cvt_f32_u32_e32 v0, s184; CGP-NEXT: s_sub_i32 s2, 0, s185; CGP-NEXT: v_rcp_f32_e32 v0, v086; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v087; CGP-NEXT: v_cvt_u32_f32_e32 v0, v088; CGP-NEXT: v_mul_lo_u32 v1, s2, v089; CGP-NEXT: v_mul_hi_u32 v1, v0, v190; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v191; CGP-NEXT: v_mul_hi_u32 v0, s0, v092; CGP-NEXT: v_mul_lo_u32 v0, v0, s193; CGP-NEXT: v_sub_i32_e32 v0, vcc, s0, v094; CGP-NEXT: v_subrev_i32_e32 v1, vcc, s1, v095; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v096; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc97; CGP-NEXT: v_subrev_i32_e32 v1, vcc, s1, v098; CGP-NEXT: v_cmp_le_u32_e32 vcc, s1, v099; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc100; CGP-NEXT: v_readfirstlane_b32 s0, v0101; CGP-NEXT: ; return to shader part epilog102 %result = urem i32 %num, %den103 %readlane = call i32 @llvm.amdgcn.readfirstlane(i32 %result)104 ret i32 %readlane105}106 107define <2 x i32> @v_urem_v2i32(<2 x i32> %num, <2 x i32> %den) {108; GISEL-LABEL: v_urem_v2i32:109; GISEL: ; %bb.0:110; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)111; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2112; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2113; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3114; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3115; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4116; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6117; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4118; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6119; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4120; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6121; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4122; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6123; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5124; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7125; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5126; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7127; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4128; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5129; GISEL-NEXT: v_mul_lo_u32 v4, v4, v2130; GISEL-NEXT: v_mul_lo_u32 v5, v5, v3131; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4132; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5133; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2134; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3135; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2136; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc137; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3138; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc139; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2140; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3141; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2142; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc143; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3144; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc145; GISEL-NEXT: s_setpc_b64 s[30:31]146;147; CGP-LABEL: v_urem_v2i32:148; CGP: ; %bb.0:149; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)150; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2151; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2152; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3153; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3154; CGP-NEXT: v_rcp_f32_e32 v4, v4155; CGP-NEXT: v_rcp_f32_e32 v6, v6156; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4157; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6158; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4159; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6160; CGP-NEXT: v_mul_lo_u32 v5, v5, v4161; CGP-NEXT: v_mul_lo_u32 v7, v7, v6162; CGP-NEXT: v_mul_hi_u32 v5, v4, v5163; CGP-NEXT: v_mul_hi_u32 v7, v6, v7164; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5165; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7166; CGP-NEXT: v_mul_hi_u32 v4, v0, v4167; CGP-NEXT: v_mul_hi_u32 v5, v1, v5168; CGP-NEXT: v_mul_lo_u32 v4, v4, v2169; CGP-NEXT: v_mul_lo_u32 v5, v5, v3170; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4171; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5172; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2173; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3174; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2175; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc176; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3177; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc178; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2179; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3180; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2181; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc182; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3183; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc184; CGP-NEXT: s_setpc_b64 s[30:31]185 %result = urem <2 x i32> %num, %den186 ret <2 x i32> %result187}188 189define i32 @v_urem_i32_pow2k_denom(i32 %num) {190; CHECK-LABEL: v_urem_i32_pow2k_denom:191; CHECK: ; %bb.0:192; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)193; CHECK-NEXT: v_and_b32_e32 v0, 0xfff, v0194; CHECK-NEXT: s_setpc_b64 s[30:31]195 %result = urem i32 %num, 4096196 ret i32 %result197}198 199define <2 x i32> @v_urem_v2i32_pow2k_denom(<2 x i32> %num) {200; CHECK-LABEL: v_urem_v2i32_pow2k_denom:201; CHECK: ; %bb.0:202; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; CHECK-NEXT: v_and_b32_e32 v0, 0xfff, v0204; CHECK-NEXT: v_and_b32_e32 v1, 0xfff, v1205; CHECK-NEXT: s_setpc_b64 s[30:31]206 %result = urem <2 x i32> %num, <i32 4096, i32 4096>207 ret <2 x i32> %result208}209 210define i32 @v_urem_i32_oddk_denom(i32 %num) {211; CHECK-LABEL: v_urem_i32_oddk_denom:212; CHECK: ; %bb.0:213; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)214; CHECK-NEXT: v_mov_b32_e32 v1, 0xb2a50881215; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1216; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v0, v1217; CHECK-NEXT: v_lshrrev_b32_e32 v2, 1, v2218; CHECK-NEXT: v_add_i32_e32 v1, vcc, v2, v1219; CHECK-NEXT: v_lshrrev_b32_e32 v1, 20, v1220; CHECK-NEXT: v_mov_b32_e32 v2, 0x12d8fb221; CHECK-NEXT: v_mul_lo_u32 v1, v1, v2222; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v1223; CHECK-NEXT: s_setpc_b64 s[30:31]224 %result = urem i32 %num, 1235195225 ret i32 %result226}227 228define <2 x i32> @v_urem_v2i32_oddk_denom(<2 x i32> %num) {229; CHECK-LABEL: v_urem_v2i32_oddk_denom:230; CHECK: ; %bb.0:231; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)232; CHECK-NEXT: v_mov_b32_e32 v2, 0xb2a50881233; CHECK-NEXT: v_mov_b32_e32 v3, 0x12d8fb234; CHECK-NEXT: v_mul_hi_u32 v4, v0, v2235; CHECK-NEXT: v_mul_hi_u32 v2, v1, v2236; CHECK-NEXT: v_sub_i32_e32 v5, vcc, v0, v4237; CHECK-NEXT: v_sub_i32_e32 v6, vcc, v1, v2238; CHECK-NEXT: v_lshrrev_b32_e32 v5, 1, v5239; CHECK-NEXT: v_lshrrev_b32_e32 v6, 1, v6240; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4241; CHECK-NEXT: v_add_i32_e32 v2, vcc, v6, v2242; CHECK-NEXT: v_lshrrev_b32_e32 v4, 20, v4243; CHECK-NEXT: v_lshrrev_b32_e32 v2, 20, v2244; CHECK-NEXT: v_mul_lo_u32 v4, v4, v3245; CHECK-NEXT: v_mul_lo_u32 v2, v2, v3246; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v4247; CHECK-NEXT: v_sub_i32_e32 v1, vcc, v1, v2248; CHECK-NEXT: s_setpc_b64 s[30:31]249 %result = urem <2 x i32> %num, <i32 1235195, i32 1235195>250 ret <2 x i32> %result251}252 253define i32 @v_urem_i32_pow2_shl_denom(i32 %x, i32 %y) {254; CHECK-LABEL: v_urem_i32_pow2_shl_denom:255; CHECK: ; %bb.0:256; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)257; CHECK-NEXT: v_lshl_b32_e32 v1, 0x1000, v1258; CHECK-NEXT: v_cvt_f32_u32_e32 v2, v1259; CHECK-NEXT: v_sub_i32_e32 v3, vcc, 0, v1260; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2261; CHECK-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2262; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2263; CHECK-NEXT: v_mul_lo_u32 v3, v3, v2264; CHECK-NEXT: v_mul_hi_u32 v3, v2, v3265; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v3266; CHECK-NEXT: v_mul_hi_u32 v2, v0, v2267; CHECK-NEXT: v_mul_lo_u32 v2, v2, v1268; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v2269; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v0, v1270; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1271; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc272; CHECK-NEXT: v_sub_i32_e32 v2, vcc, v0, v1273; CHECK-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1274; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc275; CHECK-NEXT: s_setpc_b64 s[30:31]276 %shl.y = shl i32 4096, %y277 %r = urem i32 %x, %shl.y278 ret i32 %r279}280 281define <2 x i32> @v_urem_v2i32_pow2_shl_denom(<2 x i32> %x, <2 x i32> %y) {282; GISEL-LABEL: v_urem_v2i32_pow2_shl_denom:283; GISEL: ; %bb.0:284; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)285; GISEL-NEXT: v_lshl_b32_e32 v2, 0x1000, v2286; GISEL-NEXT: v_lshl_b32_e32 v3, 0x1000, v3287; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2288; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2289; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3290; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3291; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4292; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6293; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4294; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6295; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4296; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6297; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4298; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6299; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5300; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7301; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5302; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7303; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4304; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5305; GISEL-NEXT: v_mul_lo_u32 v4, v4, v2306; GISEL-NEXT: v_mul_lo_u32 v5, v5, v3307; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4308; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5309; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2310; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3311; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2312; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc313; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3314; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc315; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2316; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3317; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2318; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc319; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3320; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc321; GISEL-NEXT: s_setpc_b64 s[30:31]322;323; CGP-LABEL: v_urem_v2i32_pow2_shl_denom:324; CGP: ; %bb.0:325; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)326; CGP-NEXT: v_lshl_b32_e32 v2, 0x1000, v2327; CGP-NEXT: v_lshl_b32_e32 v3, 0x1000, v3328; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2329; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2330; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3331; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3332; CGP-NEXT: v_rcp_f32_e32 v4, v4333; CGP-NEXT: v_rcp_f32_e32 v6, v6334; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4335; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6336; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4337; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6338; CGP-NEXT: v_mul_lo_u32 v5, v5, v4339; CGP-NEXT: v_mul_lo_u32 v7, v7, v6340; CGP-NEXT: v_mul_hi_u32 v5, v4, v5341; CGP-NEXT: v_mul_hi_u32 v7, v6, v7342; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5343; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7344; CGP-NEXT: v_mul_hi_u32 v4, v0, v4345; CGP-NEXT: v_mul_hi_u32 v5, v1, v5346; CGP-NEXT: v_mul_lo_u32 v4, v4, v2347; CGP-NEXT: v_mul_lo_u32 v5, v5, v3348; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4349; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5350; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2351; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3352; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2353; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc354; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3355; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc356; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2357; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3358; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2359; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc360; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3361; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc362; CGP-NEXT: s_setpc_b64 s[30:31]363 %shl.y = shl <2 x i32> <i32 4096, i32 4096>, %y364 %r = urem <2 x i32> %x, %shl.y365 ret <2 x i32> %r366}367 368define i32 @v_urem_i32_24bit(i32 %num, i32 %den) {369; GISEL-LABEL: v_urem_i32_24bit:370; GISEL: ; %bb.0:371; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)372; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0373; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1374; GISEL-NEXT: v_cvt_f32_u32_e32 v2, v1375; GISEL-NEXT: v_sub_i32_e32 v3, vcc, 0, v1376; GISEL-NEXT: v_rcp_iflag_f32_e32 v2, v2377; GISEL-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2378; GISEL-NEXT: v_cvt_u32_f32_e32 v2, v2379; GISEL-NEXT: v_mul_lo_u32 v3, v3, v2380; GISEL-NEXT: v_mul_hi_u32 v3, v2, v3381; GISEL-NEXT: v_add_i32_e32 v2, vcc, v2, v3382; GISEL-NEXT: v_mul_hi_u32 v2, v0, v2383; GISEL-NEXT: v_mul_lo_u32 v2, v2, v1384; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v2385; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1386; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1387; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc388; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v0, v1389; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1390; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc391; GISEL-NEXT: s_setpc_b64 s[30:31]392;393; CGP-LABEL: v_urem_i32_24bit:394; CGP: ; %bb.0:395; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)396; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0397; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1398; CGP-NEXT: v_cvt_f32_u32_e32 v2, v0399; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1400; CGP-NEXT: v_rcp_f32_e32 v4, v3401; CGP-NEXT: v_mul_f32_e32 v4, v2, v4402; CGP-NEXT: v_trunc_f32_e32 v4, v4403; CGP-NEXT: v_fma_f32 v2, -v4, v3, v2404; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4405; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, v3406; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]407; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2408; CGP-NEXT: v_mul_lo_u32 v1, v2, v1409; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1410; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0411; CGP-NEXT: s_setpc_b64 s[30:31]412 %num.mask = and i32 %num, 16777215413 %den.mask = and i32 %den, 16777215414 %result = urem i32 %num.mask, %den.mask415 ret i32 %result416}417 418define <2 x i32> @v_urem_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) {419; GISEL-LABEL: v_urem_v2i32_24bit:420; GISEL: ; %bb.0:421; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)422; GISEL-NEXT: v_and_b32_e32 v0, 0xffffff, v0423; GISEL-NEXT: v_and_b32_e32 v1, 0xffffff, v1424; GISEL-NEXT: v_and_b32_e32 v2, 0xffffff, v2425; GISEL-NEXT: v_and_b32_e32 v3, 0xffffff, v3426; GISEL-NEXT: v_cvt_f32_u32_e32 v4, v2427; GISEL-NEXT: v_sub_i32_e32 v5, vcc, 0, v2428; GISEL-NEXT: v_cvt_f32_u32_e32 v6, v3429; GISEL-NEXT: v_sub_i32_e32 v7, vcc, 0, v3430; GISEL-NEXT: v_rcp_iflag_f32_e32 v4, v4431; GISEL-NEXT: v_rcp_iflag_f32_e32 v6, v6432; GISEL-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4433; GISEL-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6434; GISEL-NEXT: v_cvt_u32_f32_e32 v4, v4435; GISEL-NEXT: v_cvt_u32_f32_e32 v6, v6436; GISEL-NEXT: v_mul_lo_u32 v5, v5, v4437; GISEL-NEXT: v_mul_lo_u32 v7, v7, v6438; GISEL-NEXT: v_mul_hi_u32 v5, v4, v5439; GISEL-NEXT: v_mul_hi_u32 v7, v6, v7440; GISEL-NEXT: v_add_i32_e32 v4, vcc, v4, v5441; GISEL-NEXT: v_add_i32_e32 v5, vcc, v6, v7442; GISEL-NEXT: v_mul_hi_u32 v4, v0, v4443; GISEL-NEXT: v_mul_hi_u32 v5, v1, v5444; GISEL-NEXT: v_mul_lo_u32 v4, v4, v2445; GISEL-NEXT: v_mul_lo_u32 v5, v5, v3446; GISEL-NEXT: v_sub_i32_e32 v0, vcc, v0, v4447; GISEL-NEXT: v_sub_i32_e32 v1, vcc, v1, v5448; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2449; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3450; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2451; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc452; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3453; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc454; GISEL-NEXT: v_sub_i32_e32 v4, vcc, v0, v2455; GISEL-NEXT: v_sub_i32_e32 v5, vcc, v1, v3456; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2457; GISEL-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc458; GISEL-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3459; GISEL-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc460; GISEL-NEXT: s_setpc_b64 s[30:31]461;462; CGP-LABEL: v_urem_v2i32_24bit:463; CGP: ; %bb.0:464; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)465; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0466; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1467; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2468; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3469; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0470; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2471; CGP-NEXT: v_cvt_f32_u32_e32 v6, v1472; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3473; CGP-NEXT: v_rcp_f32_e32 v8, v5474; CGP-NEXT: v_rcp_f32_e32 v9, v7475; CGP-NEXT: v_mul_f32_e32 v8, v4, v8476; CGP-NEXT: v_mul_f32_e32 v9, v6, v9477; CGP-NEXT: v_trunc_f32_e32 v8, v8478; CGP-NEXT: v_trunc_f32_e32 v9, v9479; CGP-NEXT: v_fma_f32 v4, -v8, v5, v4480; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8481; CGP-NEXT: v_fma_f32 v6, -v9, v7, v6482; CGP-NEXT: v_cvt_u32_f32_e32 v9, v9483; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, v5484; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5]485; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v6|, v7486; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]487; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4488; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5489; CGP-NEXT: v_mul_lo_u32 v2, v4, v2490; CGP-NEXT: v_mul_lo_u32 v3, v5, v3491; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2492; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3493; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0494; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1495; CGP-NEXT: s_setpc_b64 s[30:31]496 %num.mask = and <2 x i32> %num, <i32 16777215, i32 16777215>497 %den.mask = and <2 x i32> %den, <i32 16777215, i32 16777215>498 %result = urem <2 x i32> %num.mask, %den.mask499 ret <2 x i32> %result500}501