3562 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s3; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s5; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s6; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=+real-true16 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-TRUE16 %s7; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr=-real-true16 -amdgpu-enable-delay-alu=0 -o - %s | FileCheck -check-prefixes=GFX10PLUS,GFX11,GFX11-FAKE16 %s8 9define i7 @v_usubsat_i7(i7 %lhs, i7 %rhs) {10; GFX6-LABEL: v_usubsat_i7:11; GFX6: ; %bb.0:12; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v014; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v115; GFX6-NEXT: v_min_u32_e32 v1, v0, v116; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v117; GFX6-NEXT: v_lshrrev_b32_e32 v0, 25, v018; GFX6-NEXT: s_setpc_b64 s[30:31]19;20; GFX8-LABEL: v_usubsat_i7:21; GFX8: ; %bb.0:22; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)23; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v024; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v125; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp26; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v027; GFX8-NEXT: s_setpc_b64 s[30:31]28;29; GFX9-LABEL: v_usubsat_i7:30; GFX9: ; %bb.0:31; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v033; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v134; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp35; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v036; GFX9-NEXT: s_setpc_b64 s[30:31]37;38; GFX10-LABEL: v_usubsat_i7:39; GFX10: ; %bb.0:40; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)41; GFX10-NEXT: v_lshlrev_b16 v0, 9, v042; GFX10-NEXT: v_lshlrev_b16 v1, 9, v143; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp44; GFX10-NEXT: v_lshrrev_b16 v0, 9, v045; GFX10-NEXT: s_setpc_b64 s[30:31]46;47; GFX11-TRUE16-LABEL: v_usubsat_i7:48; GFX11-TRUE16: ; %bb.0:49; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)50; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 9, v0.l51; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 9, v1.l52; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v0.h clamp53; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 9, v0.l54; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]55;56; GFX11-FAKE16-LABEL: v_usubsat_i7:57; GFX11-FAKE16: ; %bb.0:58; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)59; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 9, v060; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 9, v161; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, v0, v1 clamp62; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, 9, v063; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]64 %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)65 ret i7 %result66}67 68define amdgpu_ps i7 @s_usubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {69; GFX6-LABEL: s_usubsat_i7:70; GFX6: ; %bb.0:71; GFX6-NEXT: s_lshl_b32 s0, s0, 2572; GFX6-NEXT: s_lshl_b32 s1, s1, 2573; GFX6-NEXT: s_min_u32 s1, s0, s174; GFX6-NEXT: s_sub_i32 s0, s0, s175; GFX6-NEXT: s_lshr_b32 s0, s0, 2576; GFX6-NEXT: ; return to shader part epilog77;78; GFX8-LABEL: s_usubsat_i7:79; GFX8: ; %bb.0:80; GFX8-NEXT: s_lshl_b32 s1, s1, 981; GFX8-NEXT: s_lshl_b32 s0, s0, 982; GFX8-NEXT: v_mov_b32_e32 v0, s183; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp84; GFX8-NEXT: v_lshrrev_b16_e32 v0, 9, v085; GFX8-NEXT: v_readfirstlane_b32 s0, v086; GFX8-NEXT: ; return to shader part epilog87;88; GFX9-LABEL: s_usubsat_i7:89; GFX9: ; %bb.0:90; GFX9-NEXT: s_lshl_b32 s1, s1, 991; GFX9-NEXT: s_lshl_b32 s0, s0, 992; GFX9-NEXT: v_mov_b32_e32 v0, s193; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp94; GFX9-NEXT: v_lshrrev_b16_e32 v0, 9, v095; GFX9-NEXT: v_readfirstlane_b32 s0, v096; GFX9-NEXT: ; return to shader part epilog97;98; GFX10-LABEL: s_usubsat_i7:99; GFX10: ; %bb.0:100; GFX10-NEXT: s_lshl_b32 s0, s0, 9101; GFX10-NEXT: s_lshl_b32 s1, s1, 9102; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp103; GFX10-NEXT: v_lshrrev_b16 v0, 9, v0104; GFX10-NEXT: v_readfirstlane_b32 s0, v0105; GFX10-NEXT: ; return to shader part epilog106;107; GFX11-TRUE16-LABEL: s_usubsat_i7:108; GFX11-TRUE16: ; %bb.0:109; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 9110; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 9111; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp112; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 9, v0.l113; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0114; GFX11-TRUE16-NEXT: ; return to shader part epilog115;116; GFX11-FAKE16-LABEL: s_usubsat_i7:117; GFX11-FAKE16: ; %bb.0:118; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 9119; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 9120; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, s0, s1 clamp121; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, 9, v0122; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0123; GFX11-FAKE16-NEXT: ; return to shader part epilog124 %result = call i7 @llvm.usub.sat.i7(i7 %lhs, i7 %rhs)125 ret i7 %result126}127 128define i8 @v_usubsat_i8(i8 %lhs, i8 %rhs) {129; GFX6-LABEL: v_usubsat_i8:130; GFX6: ; %bb.0:131; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)132; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0133; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1134; GFX6-NEXT: v_min_u32_e32 v1, v0, v1135; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1136; GFX6-NEXT: v_lshrrev_b32_e32 v0, 24, v0137; GFX6-NEXT: s_setpc_b64 s[30:31]138;139; GFX8-LABEL: v_usubsat_i8:140; GFX8: ; %bb.0:141; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)142; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0143; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1144; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp145; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0146; GFX8-NEXT: s_setpc_b64 s[30:31]147;148; GFX9-LABEL: v_usubsat_i8:149; GFX9: ; %bb.0:150; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0152; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1153; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp154; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0155; GFX9-NEXT: s_setpc_b64 s[30:31]156;157; GFX10-LABEL: v_usubsat_i8:158; GFX10: ; %bb.0:159; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)160; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0161; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1162; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp163; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0164; GFX10-NEXT: s_setpc_b64 s[30:31]165;166; GFX11-TRUE16-LABEL: v_usubsat_i8:167; GFX11-TRUE16: ; %bb.0:168; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)169; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l170; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.h, 8, v1.l171; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v0.h clamp172; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l173; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]174;175; GFX11-FAKE16-LABEL: v_usubsat_i8:176; GFX11-FAKE16: ; %bb.0:177; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)178; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, 8, v0179; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1180; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, v0, v1 clamp181; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, 8, v0182; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]183 %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)184 ret i8 %result185}186 187define amdgpu_ps i8 @s_usubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {188; GFX6-LABEL: s_usubsat_i8:189; GFX6: ; %bb.0:190; GFX6-NEXT: s_lshl_b32 s0, s0, 24191; GFX6-NEXT: s_lshl_b32 s1, s1, 24192; GFX6-NEXT: s_min_u32 s1, s0, s1193; GFX6-NEXT: s_sub_i32 s0, s0, s1194; GFX6-NEXT: s_lshr_b32 s0, s0, 24195; GFX6-NEXT: ; return to shader part epilog196;197; GFX8-LABEL: s_usubsat_i8:198; GFX8: ; %bb.0:199; GFX8-NEXT: s_lshl_b32 s1, s1, 8200; GFX8-NEXT: s_lshl_b32 s0, s0, 8201; GFX8-NEXT: v_mov_b32_e32 v0, s1202; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp203; GFX8-NEXT: v_lshrrev_b16_e32 v0, 8, v0204; GFX8-NEXT: v_readfirstlane_b32 s0, v0205; GFX8-NEXT: ; return to shader part epilog206;207; GFX9-LABEL: s_usubsat_i8:208; GFX9: ; %bb.0:209; GFX9-NEXT: s_lshl_b32 s1, s1, 8210; GFX9-NEXT: s_lshl_b32 s0, s0, 8211; GFX9-NEXT: v_mov_b32_e32 v0, s1212; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp213; GFX9-NEXT: v_lshrrev_b16_e32 v0, 8, v0214; GFX9-NEXT: v_readfirstlane_b32 s0, v0215; GFX9-NEXT: ; return to shader part epilog216;217; GFX10-LABEL: s_usubsat_i8:218; GFX10: ; %bb.0:219; GFX10-NEXT: s_lshl_b32 s0, s0, 8220; GFX10-NEXT: s_lshl_b32 s1, s1, 8221; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp222; GFX10-NEXT: v_lshrrev_b16 v0, 8, v0223; GFX10-NEXT: v_readfirstlane_b32 s0, v0224; GFX10-NEXT: ; return to shader part epilog225;226; GFX11-TRUE16-LABEL: s_usubsat_i8:227; GFX11-TRUE16: ; %bb.0:228; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 8229; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8230; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp231; GFX11-TRUE16-NEXT: v_lshrrev_b16 v0.l, 8, v0.l232; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0233; GFX11-TRUE16-NEXT: ; return to shader part epilog234;235; GFX11-FAKE16-LABEL: s_usubsat_i8:236; GFX11-FAKE16: ; %bb.0:237; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 8238; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8239; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, s0, s1 clamp240; GFX11-FAKE16-NEXT: v_lshrrev_b16 v0, 8, v0241; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0242; GFX11-FAKE16-NEXT: ; return to shader part epilog243 %result = call i8 @llvm.usub.sat.i8(i8 %lhs, i8 %rhs)244 ret i8 %result245}246 247define i16 @v_usubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {248; GFX6-LABEL: v_usubsat_v2i8:249; GFX6: ; %bb.0:250; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)251; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0252; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1253; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0254; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1255; GFX6-NEXT: v_min_u32_e32 v1, v0, v1256; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1257; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2258; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3259; GFX6-NEXT: v_min_u32_e32 v2, v1, v2260; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2261; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1262; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 24263; GFX6-NEXT: s_setpc_b64 s[30:31]264;265; GFX8-LABEL: v_usubsat_v2i8:266; GFX8: ; %bb.0:267; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)268; GFX8-NEXT: v_mov_b32_e32 v2, 8269; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD270; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD271; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0272; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1273; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp274; GFX8-NEXT: v_sub_u16_e64 v1, v3, v2 clamp275; GFX8-NEXT: v_lshrrev_b16_e32 v1, 8, v1276; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1277; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD278; GFX8-NEXT: s_setpc_b64 s[30:31]279;280; GFX9-LABEL: v_usubsat_v2i8:281; GFX9: ; %bb.0:282; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)283; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0284; GFX9-NEXT: v_lshrrev_b32_e32 v3, 8, v1285; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0286; GFX9-NEXT: v_and_b32_e32 v1, 0xffff, v1287; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v0288; GFX9-NEXT: v_lshl_or_b32 v1, v3, 16, v1289; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]290; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]291; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp292; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]293; GFX9-NEXT: v_mov_b32_e32 v1, 0xff294; GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD295; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD296; GFX9-NEXT: s_setpc_b64 s[30:31]297;298; GFX10-LABEL: v_usubsat_v2i8:299; GFX10: ; %bb.0:300; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)301; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0302; GFX10-NEXT: v_lshrrev_b32_e32 v3, 8, v1303; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0304; GFX10-NEXT: v_and_b32_e32 v1, 0xffff, v1305; GFX10-NEXT: v_lshl_or_b32 v0, v2, 16, v0306; GFX10-NEXT: v_lshl_or_b32 v1, v3, 16, v1307; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]308; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]309; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp310; GFX10-NEXT: v_mov_b32_e32 v1, 0xff311; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]312; GFX10-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD313; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD314; GFX10-NEXT: s_setpc_b64 s[30:31]315;316; GFX11-TRUE16-LABEL: v_usubsat_v2i8:317; GFX11-TRUE16: ; %bb.0:318; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0320; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1321; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l322; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v3.l323; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]324; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]325; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp326; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]327; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h328; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l329; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]330;331; GFX11-FAKE16-LABEL: v_usubsat_v2i8:332; GFX11-FAKE16: ; %bb.0:333; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)334; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0335; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1336; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0337; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1338; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v2, 16, v0339; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v1340; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]341; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]342; GFX11-FAKE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp343; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]344; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0345; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0346; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1347; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1348; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1349; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]350 %lhs = bitcast i16 %lhs.arg to <2 x i8>351 %rhs = bitcast i16 %rhs.arg to <2 x i8>352 %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)353 %cast.result = bitcast <2 x i8> %result to i16354 ret i16 %cast.result355}356 357define amdgpu_ps i16 @s_usubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {358; GFX6-LABEL: s_usubsat_v2i8:359; GFX6: ; %bb.0:360; GFX6-NEXT: s_lshr_b32 s2, s0, 8361; GFX6-NEXT: s_lshr_b32 s3, s1, 8362; GFX6-NEXT: s_lshl_b32 s0, s0, 24363; GFX6-NEXT: s_lshl_b32 s1, s1, 24364; GFX6-NEXT: s_min_u32 s1, s0, s1365; GFX6-NEXT: s_sub_i32 s0, s0, s1366; GFX6-NEXT: s_lshl_b32 s1, s2, 24367; GFX6-NEXT: s_lshl_b32 s2, s3, 24368; GFX6-NEXT: s_min_u32 s2, s1, s2369; GFX6-NEXT: s_sub_i32 s1, s1, s2370; GFX6-NEXT: s_lshr_b32 s1, s1, 24371; GFX6-NEXT: v_mov_b32_e32 v0, s0372; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24373; GFX6-NEXT: v_readfirstlane_b32 s0, v0374; GFX6-NEXT: ; return to shader part epilog375;376; GFX8-LABEL: s_usubsat_v2i8:377; GFX8: ; %bb.0:378; GFX8-NEXT: s_lshr_b32 s3, s1, 8379; GFX8-NEXT: s_lshl_b32 s1, s1, 8380; GFX8-NEXT: s_lshr_b32 s2, s0, 8381; GFX8-NEXT: s_lshl_b32 s0, s0, 8382; GFX8-NEXT: v_mov_b32_e32 v0, s1383; GFX8-NEXT: s_lshl_b32 s1, s3, 8384; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp385; GFX8-NEXT: s_lshl_b32 s0, s2, 8386; GFX8-NEXT: v_mov_b32_e32 v1, s1387; GFX8-NEXT: v_sub_u16_e64 v1, s0, v1 clamp388; GFX8-NEXT: v_lshrrev_b16_e32 v1, 8, v1389; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1390; GFX8-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD391; GFX8-NEXT: v_readfirstlane_b32 s0, v0392; GFX8-NEXT: ; return to shader part epilog393;394; GFX9-LABEL: s_usubsat_v2i8:395; GFX9: ; %bb.0:396; GFX9-NEXT: s_lshr_b32 s2, s0, 8397; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2398; GFX9-NEXT: s_lshr_b32 s3, s1, 8399; GFX9-NEXT: s_lshr_b32 s2, s0, 16400; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3401; GFX9-NEXT: s_lshl_b32 s0, s0, 0x80008402; GFX9-NEXT: s_lshl_b32 s2, s2, 8403; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2404; GFX9-NEXT: s_lshr_b32 s2, s1, 16405; GFX9-NEXT: s_lshl_b32 s1, s1, 0x80008406; GFX9-NEXT: s_lshl_b32 s2, s2, 8407; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2408; GFX9-NEXT: v_mov_b32_e32 v0, s1409; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp410; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]411; GFX9-NEXT: v_mov_b32_e32 v1, 0xff412; GFX9-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD413; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD414; GFX9-NEXT: v_readfirstlane_b32 s0, v0415; GFX9-NEXT: ; return to shader part epilog416;417; GFX10-LABEL: s_usubsat_v2i8:418; GFX10: ; %bb.0:419; GFX10-NEXT: s_lshr_b32 s2, s0, 8420; GFX10-NEXT: s_lshr_b32 s3, s1, 8421; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2422; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3423; GFX10-NEXT: s_lshr_b32 s2, s0, 16424; GFX10-NEXT: s_lshr_b32 s3, s1, 16425; GFX10-NEXT: s_lshl_b32 s0, s0, 0x80008426; GFX10-NEXT: s_lshl_b32 s2, s2, 8427; GFX10-NEXT: s_lshl_b32 s1, s1, 0x80008428; GFX10-NEXT: s_lshl_b32 s3, s3, 8429; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2430; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3431; GFX10-NEXT: v_mov_b32_e32 v1, 0xff432; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp433; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]434; GFX10-NEXT: v_and_b32_sdwa v1, v0, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD435; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD436; GFX10-NEXT: v_readfirstlane_b32 s0, v0437; GFX10-NEXT: ; return to shader part epilog438;439; GFX11-TRUE16-LABEL: s_usubsat_v2i8:440; GFX11-TRUE16: ; %bb.0:441; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 8442; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 8443; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2444; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s3445; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16446; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s1, 16447; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 0x80008448; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 8449; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 0x80008450; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 8451; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2452; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s3453; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, s0, s1 clamp454; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v0 op_sel_hi:[0,1]455; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v1.h456; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l457; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0458; GFX11-TRUE16-NEXT: ; return to shader part epilog459;460; GFX11-FAKE16-LABEL: s_usubsat_v2i8:461; GFX11-FAKE16: ; %bb.0:462; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 8463; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s1, 8464; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2465; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s1, s1, s3466; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16467; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s1, 16468; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 0x80008469; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 8470; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 0x80008471; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 8472; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2473; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s1, s1, s3474; GFX11-FAKE16-NEXT: v_pk_sub_u16 v0, s0, s1 clamp475; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]476; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 16, v0477; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xff, v0478; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1479; GFX11-FAKE16-NEXT: v_lshlrev_b16 v1, 8, v1480; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v0, v1481; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0482; GFX11-FAKE16-NEXT: ; return to shader part epilog483 %lhs = bitcast i16 %lhs.arg to <2 x i8>484 %rhs = bitcast i16 %rhs.arg to <2 x i8>485 %result = call <2 x i8> @llvm.usub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)486 %cast.result = bitcast <2 x i8> %result to i16487 ret i16 %cast.result488}489 490define i32 @v_usubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {491; GFX6-LABEL: v_usubsat_v4i8:492; GFX6: ; %bb.0:493; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)494; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0495; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0496; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0497; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1498; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1499; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1500; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0501; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1502; GFX6-NEXT: v_min_u32_e32 v1, v0, v1503; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1504; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2505; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5506; GFX6-NEXT: v_min_u32_e32 v2, v1, v2507; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2508; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3509; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6510; GFX6-NEXT: v_min_u32_e32 v3, v2, v3511; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3512; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4513; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7514; GFX6-NEXT: v_min_u32_e32 v4, v3, v4515; GFX6-NEXT: v_lshrrev_b32_e32 v1, 24, v1516; GFX6-NEXT: v_lshrrev_b32_e32 v2, 24, v2517; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4518; GFX6-NEXT: v_lshrrev_b32_e32 v3, 24, v3519; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 24520; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v2521; GFX6-NEXT: v_or_b32_e32 v0, v0, v1522; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v3523; GFX6-NEXT: v_or_b32_e32 v0, v0, v1524; GFX6-NEXT: s_setpc_b64 s[30:31]525;526; GFX8-LABEL: v_usubsat_v4i8:527; GFX8: ; %bb.0:528; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)529; GFX8-NEXT: v_mov_b32_e32 v2, 8530; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD531; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0532; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0533; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD534; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1535; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1536; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0537; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1538; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp539; GFX8-NEXT: v_sub_u16_e64 v1, v3, v2 clamp540; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4541; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6542; GFX8-NEXT: v_sub_u16_e64 v2, v2, v3 clamp543; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5544; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7545; GFX8-NEXT: v_sub_u16_e64 v3, v3, v4 clamp546; GFX8-NEXT: v_mov_b32_e32 v4, 0xff547; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD548; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD549; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1550; GFX8-NEXT: v_or_b32_e32 v0, v0, v1551; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD552; GFX8-NEXT: v_or_b32_e32 v0, v0, v1553; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD554; GFX8-NEXT: v_or_b32_e32 v0, v0, v1555; GFX8-NEXT: s_setpc_b64 s[30:31]556;557; GFX9-LABEL: v_usubsat_v4i8:558; GFX9: ; %bb.0:559; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)560; GFX9-NEXT: v_lshrrev_b32_e32 v3, 24, v0561; GFX9-NEXT: v_lshrrev_b32_e32 v2, 8, v0562; GFX9-NEXT: v_lshrrev_b32_e32 v4, 8, v1563; GFX9-NEXT: v_and_b32_e32 v6, 0xffff, v0564; GFX9-NEXT: v_alignbit_b32 v0, v3, v0, 16565; GFX9-NEXT: v_and_b32_e32 v3, 0xffff, v1566; GFX9-NEXT: v_lshrrev_b32_e32 v5, 24, v1567; GFX9-NEXT: v_lshl_or_b32 v2, v2, 16, v6568; GFX9-NEXT: v_lshl_or_b32 v3, v4, 16, v3569; GFX9-NEXT: v_alignbit_b32 v1, v5, v1, 16570; GFX9-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]571; GFX9-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]572; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]573; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]574; GFX9-NEXT: v_pk_sub_u16 v2, v2, v3 clamp575; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp576; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]577; GFX9-NEXT: v_mov_b32_e32 v3, 8578; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]579; GFX9-NEXT: v_mov_b32_e32 v2, 0xff580; GFX9-NEXT: v_lshlrev_b32_sdwa v3, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2581; GFX9-NEXT: v_and_or_b32 v1, v1, v2, v3582; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v0583; GFX9-NEXT: v_mov_b32_e32 v3, 24584; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2585; GFX9-NEXT: v_lshlrev_b32_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2586; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0587; GFX9-NEXT: s_setpc_b64 s[30:31]588;589; GFX10-LABEL: v_usubsat_v4i8:590; GFX10: ; %bb.0:591; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)592; GFX10-NEXT: v_lshrrev_b32_e32 v2, 8, v0593; GFX10-NEXT: v_lshrrev_b32_e32 v3, 24, v0594; GFX10-NEXT: v_and_b32_e32 v4, 0xffff, v0595; GFX10-NEXT: v_lshrrev_b32_e32 v5, 8, v1596; GFX10-NEXT: v_and_b32_e32 v6, 0xffff, v1597; GFX10-NEXT: v_lshrrev_b32_e32 v7, 24, v1598; GFX10-NEXT: v_alignbit_b32 v0, v3, v0, 16599; GFX10-NEXT: v_lshl_or_b32 v2, v2, 16, v4600; GFX10-NEXT: v_mov_b32_e32 v4, 24601; GFX10-NEXT: v_lshl_or_b32 v3, v5, 16, v6602; GFX10-NEXT: v_alignbit_b32 v1, v7, v1, 16603; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]604; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]605; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]606; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]607; GFX10-NEXT: v_pk_sub_u16 v2, v2, v3 clamp608; GFX10-NEXT: v_pk_sub_u16 v0, v0, v1 clamp609; GFX10-NEXT: v_mov_b32_e32 v1, 8610; GFX10-NEXT: v_pk_lshrrev_b16 v2, 8, v2 op_sel_hi:[0,1]611; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]612; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2613; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v0614; GFX10-NEXT: v_lshlrev_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2615; GFX10-NEXT: v_and_or_b32 v1, 0xff, v2, v1616; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3617; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0618; GFX10-NEXT: s_setpc_b64 s[30:31]619;620; GFX11-TRUE16-LABEL: v_usubsat_v4i8:621; GFX11-TRUE16: ; %bb.0:622; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)623; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0624; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 8, v1625; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0626; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 24, v0627; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v1628; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1629; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l630; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v4.l631; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.h, v5.l632; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v7.l633; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]634; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]635; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v2, 8, v3 op_sel_hi:[0,1]636; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp637; GFX11-TRUE16-NEXT: v_pk_lshlrev_b16 v1, 8, v6 op_sel_hi:[0,1]638; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]639; GFX11-TRUE16-NEXT: v_pk_sub_u16 v1, v2, v1 clamp640; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h641; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]642; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2643; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h644; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1645; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2646; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3647; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1648; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v2649; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 24, v3650; GFX11-TRUE16-NEXT: v_or3_b32 v0, v0, v1, v2651; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]652;653; GFX11-FAKE16-LABEL: v_usubsat_v4i8:654; GFX11-FAKE16: ; %bb.0:655; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)656; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v2, 8, v0657; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v3, 8, v1658; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v0659; GFX11-FAKE16-NEXT: v_and_b32_e32 v5, 0xffff, v1660; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v6, 24, v0661; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v7, 24, v1662; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v2, 16, v4663; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v3, 16, v5664; GFX11-FAKE16-NEXT: v_alignbit_b32 v0, v6, v0, 16665; GFX11-FAKE16-NEXT: v_alignbit_b32 v1, v7, v1, 16666; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]667; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]668; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]669; GFX11-FAKE16-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]670; GFX11-FAKE16-NEXT: v_pk_sub_u16 v2, v2, v3 clamp671; GFX11-FAKE16-NEXT: v_pk_sub_u16 v0, v0, v1 clamp672; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v1, 8, v2 op_sel_hi:[0,1]673; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]674; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v1, 16, 8675; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v0676; GFX11-FAKE16-NEXT: v_bfe_u32 v0, v0, 16, 8677; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2678; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v3, 16, v3679; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 24, v0680; GFX11-FAKE16-NEXT: v_and_or_b32 v1, 0xff, v1, v2681; GFX11-FAKE16-NEXT: v_or3_b32 v0, v1, v3, v0682; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]683 %lhs = bitcast i32 %lhs.arg to <4 x i8>684 %rhs = bitcast i32 %rhs.arg to <4 x i8>685 %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)686 %cast.result = bitcast <4 x i8> %result to i32687 ret i32 %cast.result688}689 690define amdgpu_ps i32 @s_usubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {691; GFX6-LABEL: s_usubsat_v4i8:692; GFX6: ; %bb.0:693; GFX6-NEXT: s_lshr_b32 s2, s0, 8694; GFX6-NEXT: s_lshr_b32 s3, s0, 16695; GFX6-NEXT: s_lshr_b32 s4, s0, 24696; GFX6-NEXT: s_lshr_b32 s5, s1, 8697; GFX6-NEXT: s_lshr_b32 s6, s1, 16698; GFX6-NEXT: s_lshr_b32 s7, s1, 24699; GFX6-NEXT: s_lshl_b32 s0, s0, 24700; GFX6-NEXT: s_lshl_b32 s1, s1, 24701; GFX6-NEXT: s_min_u32 s1, s0, s1702; GFX6-NEXT: s_sub_i32 s0, s0, s1703; GFX6-NEXT: s_lshl_b32 s1, s2, 24704; GFX6-NEXT: s_lshl_b32 s2, s5, 24705; GFX6-NEXT: s_min_u32 s2, s1, s2706; GFX6-NEXT: s_sub_i32 s1, s1, s2707; GFX6-NEXT: s_lshl_b32 s2, s3, 24708; GFX6-NEXT: s_lshl_b32 s3, s6, 24709; GFX6-NEXT: s_min_u32 s3, s2, s3710; GFX6-NEXT: s_sub_i32 s2, s2, s3711; GFX6-NEXT: s_lshl_b32 s3, s4, 24712; GFX6-NEXT: s_lshl_b32 s4, s7, 24713; GFX6-NEXT: s_min_u32 s4, s3, s4714; GFX6-NEXT: s_lshr_b32 s1, s1, 24715; GFX6-NEXT: s_lshr_b32 s2, s2, 24716; GFX6-NEXT: s_sub_i32 s3, s3, s4717; GFX6-NEXT: v_mov_b32_e32 v0, s0718; GFX6-NEXT: s_lshr_b32 s3, s3, 24719; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 24720; GFX6-NEXT: s_lshl_b32 s0, s2, 16721; GFX6-NEXT: v_or_b32_e32 v0, s0, v0722; GFX6-NEXT: s_lshl_b32 s0, s3, 24723; GFX6-NEXT: v_or_b32_e32 v0, s0, v0724; GFX6-NEXT: v_readfirstlane_b32 s0, v0725; GFX6-NEXT: ; return to shader part epilog726;727; GFX8-LABEL: s_usubsat_v4i8:728; GFX8: ; %bb.0:729; GFX8-NEXT: s_lshr_b32 s5, s1, 8730; GFX8-NEXT: s_lshr_b32 s6, s1, 16731; GFX8-NEXT: s_lshr_b32 s7, s1, 24732; GFX8-NEXT: s_lshl_b32 s1, s1, 8733; GFX8-NEXT: s_lshr_b32 s2, s0, 8734; GFX8-NEXT: s_lshr_b32 s3, s0, 16735; GFX8-NEXT: s_lshr_b32 s4, s0, 24736; GFX8-NEXT: s_lshl_b32 s0, s0, 8737; GFX8-NEXT: v_mov_b32_e32 v0, s1738; GFX8-NEXT: s_lshl_b32 s1, s5, 8739; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp740; GFX8-NEXT: s_lshl_b32 s0, s2, 8741; GFX8-NEXT: v_mov_b32_e32 v1, s1742; GFX8-NEXT: v_sub_u16_e64 v1, s0, v1 clamp743; GFX8-NEXT: s_lshl_b32 s1, s6, 8744; GFX8-NEXT: v_mov_b32_e32 v4, 0xff745; GFX8-NEXT: s_lshl_b32 s0, s3, 8746; GFX8-NEXT: v_mov_b32_e32 v2, s1747; GFX8-NEXT: s_lshl_b32 s1, s7, 8748; GFX8-NEXT: v_and_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD749; GFX8-NEXT: v_sub_u16_e64 v2, s0, v2 clamp750; GFX8-NEXT: s_lshl_b32 s0, s4, 8751; GFX8-NEXT: v_mov_b32_e32 v3, s1752; GFX8-NEXT: v_and_b32_sdwa v0, v0, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD753; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1754; GFX8-NEXT: v_sub_u16_e64 v3, s0, v3 clamp755; GFX8-NEXT: v_or_b32_e32 v0, v0, v1756; GFX8-NEXT: v_and_b32_sdwa v1, v2, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD757; GFX8-NEXT: v_or_b32_e32 v0, v0, v1758; GFX8-NEXT: v_and_b32_sdwa v1, v3, v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD759; GFX8-NEXT: v_or_b32_e32 v0, v0, v1760; GFX8-NEXT: v_readfirstlane_b32 s0, v0761; GFX8-NEXT: ; return to shader part epilog762;763; GFX9-LABEL: s_usubsat_v4i8:764; GFX9: ; %bb.0:765; GFX9-NEXT: s_lshr_b32 s2, s0, 8766; GFX9-NEXT: s_lshr_b32 s3, s0, 16767; GFX9-NEXT: s_lshr_b32 s4, s0, 24768; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2769; GFX9-NEXT: s_pack_ll_b32_b16 s2, s3, s4770; GFX9-NEXT: s_lshr_b32 s4, s0, 16771; GFX9-NEXT: s_lshl_b32 s0, s0, 0x80008772; GFX9-NEXT: s_lshl_b32 s4, s4, 8773; GFX9-NEXT: s_lshr_b32 s5, s1, 8774; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s4775; GFX9-NEXT: s_lshr_b32 s4, s2, 16776; GFX9-NEXT: s_lshr_b32 s6, s1, 16777; GFX9-NEXT: s_lshr_b32 s7, s1, 24778; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s5779; GFX9-NEXT: s_lshl_b32 s2, s2, 0x80008780; GFX9-NEXT: s_lshl_b32 s4, s4, 8781; GFX9-NEXT: s_pack_ll_b32_b16 s2, s2, s4782; GFX9-NEXT: s_lshr_b32 s4, s1, 16783; GFX9-NEXT: s_pack_ll_b32_b16 s3, s6, s7784; GFX9-NEXT: s_lshl_b32 s1, s1, 0x80008785; GFX9-NEXT: s_lshl_b32 s4, s4, 8786; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s4787; GFX9-NEXT: s_lshr_b32 s4, s3, 16788; GFX9-NEXT: s_lshl_b32 s3, s3, 0x80008789; GFX9-NEXT: s_lshl_b32 s4, s4, 8790; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s4791; GFX9-NEXT: v_mov_b32_e32 v0, s1792; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp793; GFX9-NEXT: v_mov_b32_e32 v1, s3794; GFX9-NEXT: v_pk_sub_u16 v1, s2, v1 clamp795; GFX9-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]796; GFX9-NEXT: v_mov_b32_e32 v3, 8797; GFX9-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]798; GFX9-NEXT: v_mov_b32_e32 v2, 0xff799; GFX9-NEXT: v_lshlrev_b32_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2800; GFX9-NEXT: v_and_or_b32 v0, v0, v2, v3801; GFX9-NEXT: v_and_b32_e32 v2, 0xff, v1802; GFX9-NEXT: v_mov_b32_e32 v3, 24803; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2804; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2805; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1806; GFX9-NEXT: v_readfirstlane_b32 s0, v0807; GFX9-NEXT: ; return to shader part epilog808;809; GFX10-LABEL: s_usubsat_v4i8:810; GFX10: ; %bb.0:811; GFX10-NEXT: s_lshr_b32 s2, s0, 8812; GFX10-NEXT: s_lshr_b32 s3, s0, 16813; GFX10-NEXT: s_lshr_b32 s4, s0, 24814; GFX10-NEXT: s_lshr_b32 s5, s1, 8815; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2816; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4817; GFX10-NEXT: s_lshr_b32 s6, s1, 16818; GFX10-NEXT: s_lshr_b32 s7, s1, 24819; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5820; GFX10-NEXT: s_lshr_b32 s4, s0, 16821; GFX10-NEXT: s_lshr_b32 s5, s2, 16822; GFX10-NEXT: s_pack_ll_b32_b16 s3, s6, s7823; GFX10-NEXT: s_lshl_b32 s0, s0, 0x80008824; GFX10-NEXT: s_lshl_b32 s4, s4, 8825; GFX10-NEXT: s_lshl_b32 s2, s2, 0x80008826; GFX10-NEXT: s_lshl_b32 s5, s5, 8827; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4828; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s5829; GFX10-NEXT: s_lshr_b32 s4, s1, 16830; GFX10-NEXT: s_lshr_b32 s5, s3, 16831; GFX10-NEXT: s_lshl_b32 s1, s1, 0x80008832; GFX10-NEXT: s_lshl_b32 s4, s4, 8833; GFX10-NEXT: s_lshl_b32 s3, s3, 0x80008834; GFX10-NEXT: s_lshl_b32 s5, s5, 8835; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s4836; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s5837; GFX10-NEXT: v_pk_sub_u16 v0, s0, s1 clamp838; GFX10-NEXT: v_pk_sub_u16 v1, s2, s3 clamp839; GFX10-NEXT: v_mov_b32_e32 v2, 8840; GFX10-NEXT: v_mov_b32_e32 v4, 24841; GFX10-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]842; GFX10-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]843; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2844; GFX10-NEXT: v_and_b32_e32 v3, 0xff, v1845; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2846; GFX10-NEXT: v_and_or_b32 v0, 0xff, v0, v2847; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3848; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1849; GFX10-NEXT: v_readfirstlane_b32 s0, v0850; GFX10-NEXT: ; return to shader part epilog851;852; GFX11-TRUE16-LABEL: s_usubsat_v4i8:853; GFX11-TRUE16: ; %bb.0:854; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 8855; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s0, 24856; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s1, 8857; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 24858; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s0, s2859; GFX11-TRUE16-NEXT: s_pack_hl_b32_b16 s0, s0, s3860; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s1, s4861; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s2, 16862; GFX11-TRUE16-NEXT: s_pack_hl_b32_b16 s1, s1, s5863; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s3, 16864; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s2, 0x80008865; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 8866; GFX11-TRUE16-NEXT: s_lshl_b32 s3, s3, 0x80008867; GFX11-TRUE16-NEXT: s_lshl_b32 s5, s5, 8868; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s4869; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s3, s3, s5870; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16871; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s1, 16872; GFX11-TRUE16-NEXT: v_pk_sub_u16 v0, s2, s3 clamp873; GFX11-TRUE16-NEXT: s_lshl_b32 s0, s0, 0x80008874; GFX11-TRUE16-NEXT: s_lshl_b32 s4, s4, 8875; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 0x80008876; GFX11-TRUE16-NEXT: s_lshl_b32 s2, s5, 8877; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s4878; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s1, s1, s2879; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]880; GFX11-TRUE16-NEXT: v_pk_sub_u16 v1, s0, s1 clamp881; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.l, v0.h882; GFX11-TRUE16-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]883; GFX11-TRUE16-NEXT: v_and_b32_e32 v2, 0xff, v2884; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.h885; GFX11-TRUE16-NEXT: v_and_b32_e32 v1, 0xff, v1886; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2887; GFX11-TRUE16-NEXT: v_and_b32_e32 v3, 0xff, v3888; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v1, 16, v1889; GFX11-TRUE16-NEXT: v_and_or_b32 v0, 0xff, v0, v2890; GFX11-TRUE16-NEXT: v_lshlrev_b32_e32 v2, 24, v3891; GFX11-TRUE16-NEXT: v_or3_b32 v0, v0, v1, v2892; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0893; GFX11-TRUE16-NEXT: ; return to shader part epilog894;895; GFX11-FAKE16-LABEL: s_usubsat_v4i8:896; GFX11-FAKE16: ; %bb.0:897; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 8898; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s0, 24899; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s1, 8900; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s1, 24901; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s0, s2902; GFX11-FAKE16-NEXT: s_pack_hl_b32_b16 s0, s0, s3903; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s3, s1, s4904; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s2, 16905; GFX11-FAKE16-NEXT: s_pack_hl_b32_b16 s1, s1, s5906; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s3, 16907; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 0x80008908; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 8909; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 0x80008910; GFX11-FAKE16-NEXT: s_lshl_b32 s5, s5, 8911; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s2, s2, s4912; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s3, s3, s5913; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s0, 16914; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s1, 16915; GFX11-FAKE16-NEXT: v_pk_sub_u16 v0, s2, s3 clamp916; GFX11-FAKE16-NEXT: s_lshl_b32 s0, s0, 0x80008917; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 8918; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 0x80008919; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s5, 8920; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s0, s0, s4921; GFX11-FAKE16-NEXT: s_pack_ll_b32_b16 s1, s1, s2922; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v0, 8, v0 op_sel_hi:[0,1]923; GFX11-FAKE16-NEXT: v_pk_sub_u16 v1, s0, s1 clamp924; GFX11-FAKE16-NEXT: v_bfe_u32 v2, v0, 16, 8925; GFX11-FAKE16-NEXT: v_pk_lshrrev_b16 v1, 8, v1 op_sel_hi:[0,1]926; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 8, v2927; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xff, v1928; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v1, 16, 8929; GFX11-FAKE16-NEXT: v_and_or_b32 v0, 0xff, v0, v2930; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v2, 16, v3931; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v1, 24, v1932; GFX11-FAKE16-NEXT: v_or3_b32 v0, v0, v2, v1933; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0934; GFX11-FAKE16-NEXT: ; return to shader part epilog935 %lhs = bitcast i32 %lhs.arg to <4 x i8>936 %rhs = bitcast i32 %rhs.arg to <4 x i8>937 %result = call <4 x i8> @llvm.usub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)938 %cast.result = bitcast <4 x i8> %result to i32939 ret i32 %cast.result940}941 942define i24 @v_usubsat_i24(i24 %lhs, i24 %rhs) {943; GFX6-LABEL: v_usubsat_i24:944; GFX6: ; %bb.0:945; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)946; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0947; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1948; GFX6-NEXT: v_min_u32_e32 v1, v0, v1949; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1950; GFX6-NEXT: v_lshrrev_b32_e32 v0, 8, v0951; GFX6-NEXT: s_setpc_b64 s[30:31]952;953; GFX8-LABEL: v_usubsat_i24:954; GFX8: ; %bb.0:955; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)956; GFX8-NEXT: v_lshlrev_b32_e32 v0, 8, v0957; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1958; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp959; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v0960; GFX8-NEXT: s_setpc_b64 s[30:31]961;962; GFX9-LABEL: v_usubsat_i24:963; GFX9: ; %bb.0:964; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0966; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1967; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp968; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v0969; GFX9-NEXT: s_setpc_b64 s[30:31]970;971; GFX10PLUS-LABEL: v_usubsat_i24:972; GFX10PLUS: ; %bb.0:973; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)974; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v0, 8, v0975; GFX10PLUS-NEXT: v_lshlrev_b32_e32 v1, 8, v1976; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp977; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v0978; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]979 %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)980 ret i24 %result981}982 983define amdgpu_ps i24 @s_usubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {984; GFX6-LABEL: s_usubsat_i24:985; GFX6: ; %bb.0:986; GFX6-NEXT: s_lshl_b32 s0, s0, 8987; GFX6-NEXT: s_lshl_b32 s1, s1, 8988; GFX6-NEXT: s_min_u32 s1, s0, s1989; GFX6-NEXT: s_sub_i32 s0, s0, s1990; GFX6-NEXT: s_lshr_b32 s0, s0, 8991; GFX6-NEXT: ; return to shader part epilog992;993; GFX8-LABEL: s_usubsat_i24:994; GFX8: ; %bb.0:995; GFX8-NEXT: s_lshl_b32 s1, s1, 8996; GFX8-NEXT: s_lshl_b32 s0, s0, 8997; GFX8-NEXT: v_mov_b32_e32 v0, s1998; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp999; GFX8-NEXT: v_lshrrev_b32_e32 v0, 8, v01000; GFX8-NEXT: v_readfirstlane_b32 s0, v01001; GFX8-NEXT: ; return to shader part epilog1002;1003; GFX9-LABEL: s_usubsat_i24:1004; GFX9: ; %bb.0:1005; GFX9-NEXT: s_lshl_b32 s1, s1, 81006; GFX9-NEXT: s_lshl_b32 s0, s0, 81007; GFX9-NEXT: v_mov_b32_e32 v0, s11008; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1009; GFX9-NEXT: v_lshrrev_b32_e32 v0, 8, v01010; GFX9-NEXT: v_readfirstlane_b32 s0, v01011; GFX9-NEXT: ; return to shader part epilog1012;1013; GFX10PLUS-LABEL: s_usubsat_i24:1014; GFX10PLUS: ; %bb.0:1015; GFX10PLUS-NEXT: s_lshl_b32 s0, s0, 81016; GFX10PLUS-NEXT: s_lshl_b32 s1, s1, 81017; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp1018; GFX10PLUS-NEXT: v_lshrrev_b32_e32 v0, 8, v01019; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01020; GFX10PLUS-NEXT: ; return to shader part epilog1021 %result = call i24 @llvm.usub.sat.i24(i24 %lhs, i24 %rhs)1022 ret i24 %result1023}1024 1025define i32 @v_usubsat_i32(i32 %lhs, i32 %rhs) {1026; GFX6-LABEL: v_usubsat_i32:1027; GFX6: ; %bb.0:1028; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1029; GFX6-NEXT: v_min_u32_e32 v1, v0, v11030; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11031; GFX6-NEXT: s_setpc_b64 s[30:31]1032;1033; GFX8-LABEL: v_usubsat_i32:1034; GFX8: ; %bb.0:1035; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1036; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v1 clamp1037; GFX8-NEXT: s_setpc_b64 s[30:31]1038;1039; GFX9-LABEL: v_usubsat_i32:1040; GFX9: ; %bb.0:1041; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1042; GFX9-NEXT: v_sub_u32_e64 v0, v0, v1 clamp1043; GFX9-NEXT: s_setpc_b64 s[30:31]1044;1045; GFX10PLUS-LABEL: v_usubsat_i32:1046; GFX10PLUS: ; %bb.0:1047; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1048; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v1 clamp1049; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1050 %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)1051 ret i32 %result1052}1053 1054define amdgpu_ps i32 @s_usubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {1055; GFX6-LABEL: s_usubsat_i32:1056; GFX6: ; %bb.0:1057; GFX6-NEXT: s_min_u32 s1, s0, s11058; GFX6-NEXT: s_sub_i32 s0, s0, s11059; GFX6-NEXT: ; return to shader part epilog1060;1061; GFX8-LABEL: s_usubsat_i32:1062; GFX8: ; %bb.0:1063; GFX8-NEXT: v_mov_b32_e32 v0, s11064; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp1065; GFX8-NEXT: v_readfirstlane_b32 s0, v01066; GFX8-NEXT: ; return to shader part epilog1067;1068; GFX9-LABEL: s_usubsat_i32:1069; GFX9: ; %bb.0:1070; GFX9-NEXT: v_mov_b32_e32 v0, s11071; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1072; GFX9-NEXT: v_readfirstlane_b32 s0, v01073; GFX9-NEXT: ; return to shader part epilog1074;1075; GFX10PLUS-LABEL: s_usubsat_i32:1076; GFX10PLUS: ; %bb.0:1077; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s1 clamp1078; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01079; GFX10PLUS-NEXT: ; return to shader part epilog1080 %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)1081 ret i32 %result1082}1083 1084define amdgpu_ps float @usubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {1085; GFX6-LABEL: usubsat_i32_sv:1086; GFX6: ; %bb.0:1087; GFX6-NEXT: v_min_u32_e32 v0, s0, v01088; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v01089; GFX6-NEXT: ; return to shader part epilog1090;1091; GFX8-LABEL: usubsat_i32_sv:1092; GFX8: ; %bb.0:1093; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], s0, v0 clamp1094; GFX8-NEXT: ; return to shader part epilog1095;1096; GFX9-LABEL: usubsat_i32_sv:1097; GFX9: ; %bb.0:1098; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1099; GFX9-NEXT: ; return to shader part epilog1100;1101; GFX10PLUS-LABEL: usubsat_i32_sv:1102; GFX10PLUS: ; %bb.0:1103; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, v0 clamp1104; GFX10PLUS-NEXT: ; return to shader part epilog1105 %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)1106 %cast = bitcast i32 %result to float1107 ret float %cast1108}1109 1110define amdgpu_ps float @usubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {1111; GFX6-LABEL: usubsat_i32_vs:1112; GFX6: ; %bb.0:1113; GFX6-NEXT: v_min_u32_e32 v1, s0, v01114; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11115; GFX6-NEXT: ; return to shader part epilog1116;1117; GFX8-LABEL: usubsat_i32_vs:1118; GFX8: ; %bb.0:1119; GFX8-NEXT: v_sub_u32_e64 v0, s[0:1], v0, s0 clamp1120; GFX8-NEXT: ; return to shader part epilog1121;1122; GFX9-LABEL: usubsat_i32_vs:1123; GFX9: ; %bb.0:1124; GFX9-NEXT: v_sub_u32_e64 v0, v0, s0 clamp1125; GFX9-NEXT: ; return to shader part epilog1126;1127; GFX10PLUS-LABEL: usubsat_i32_vs:1128; GFX10PLUS: ; %bb.0:1129; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, s0 clamp1130; GFX10PLUS-NEXT: ; return to shader part epilog1131 %result = call i32 @llvm.usub.sat.i32(i32 %lhs, i32 %rhs)1132 %cast = bitcast i32 %result to float1133 ret float %cast1134}1135 1136define <2 x i32> @v_usubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {1137; GFX6-LABEL: v_usubsat_v2i32:1138; GFX6: ; %bb.0:1139; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1140; GFX6-NEXT: v_min_u32_e32 v2, v0, v21141; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v21142; GFX6-NEXT: v_min_u32_e32 v2, v1, v31143; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v21144; GFX6-NEXT: s_setpc_b64 s[30:31]1145;1146; GFX8-LABEL: v_usubsat_v2i32:1147; GFX8: ; %bb.0:1148; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1149; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v2 clamp1150; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v3 clamp1151; GFX8-NEXT: s_setpc_b64 s[30:31]1152;1153; GFX9-LABEL: v_usubsat_v2i32:1154; GFX9: ; %bb.0:1155; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1156; GFX9-NEXT: v_sub_u32_e64 v0, v0, v2 clamp1157; GFX9-NEXT: v_sub_u32_e64 v1, v1, v3 clamp1158; GFX9-NEXT: s_setpc_b64 s[30:31]1159;1160; GFX10PLUS-LABEL: v_usubsat_v2i32:1161; GFX10PLUS: ; %bb.0:1162; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1163; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v2 clamp1164; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v3 clamp1165; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1166 %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1167 ret <2 x i32> %result1168}1169 1170define amdgpu_ps <2 x i32> @s_usubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {1171; GFX6-LABEL: s_usubsat_v2i32:1172; GFX6: ; %bb.0:1173; GFX6-NEXT: s_min_u32 s2, s0, s21174; GFX6-NEXT: s_sub_i32 s0, s0, s21175; GFX6-NEXT: s_min_u32 s2, s1, s31176; GFX6-NEXT: s_sub_i32 s1, s1, s21177; GFX6-NEXT: ; return to shader part epilog1178;1179; GFX8-LABEL: s_usubsat_v2i32:1180; GFX8: ; %bb.0:1181; GFX8-NEXT: v_mov_b32_e32 v0, s21182; GFX8-NEXT: v_mov_b32_e32 v1, s31183; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], s0, v0 clamp1184; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp1185; GFX8-NEXT: v_readfirstlane_b32 s0, v01186; GFX8-NEXT: v_readfirstlane_b32 s1, v11187; GFX8-NEXT: ; return to shader part epilog1188;1189; GFX9-LABEL: s_usubsat_v2i32:1190; GFX9: ; %bb.0:1191; GFX9-NEXT: v_mov_b32_e32 v0, s21192; GFX9-NEXT: v_mov_b32_e32 v1, s31193; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1194; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp1195; GFX9-NEXT: v_readfirstlane_b32 s0, v01196; GFX9-NEXT: v_readfirstlane_b32 s1, v11197; GFX9-NEXT: ; return to shader part epilog1198;1199; GFX10PLUS-LABEL: s_usubsat_v2i32:1200; GFX10PLUS: ; %bb.0:1201; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s2 clamp1202; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s3 clamp1203; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01204; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11205; GFX10PLUS-NEXT: ; return to shader part epilog1206 %result = call <2 x i32> @llvm.usub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)1207 ret <2 x i32> %result1208}1209 1210define <3 x i32> @v_usubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {1211; GFX6-LABEL: v_usubsat_v3i32:1212; GFX6: ; %bb.0:1213; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1214; GFX6-NEXT: v_min_u32_e32 v3, v0, v31215; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v31216; GFX6-NEXT: v_min_u32_e32 v3, v1, v41217; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v31218; GFX6-NEXT: v_min_u32_e32 v3, v2, v51219; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v31220; GFX6-NEXT: s_setpc_b64 s[30:31]1221;1222; GFX8-LABEL: v_usubsat_v3i32:1223; GFX8: ; %bb.0:1224; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1225; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v3 clamp1226; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v4 clamp1227; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v5 clamp1228; GFX8-NEXT: s_setpc_b64 s[30:31]1229;1230; GFX9-LABEL: v_usubsat_v3i32:1231; GFX9: ; %bb.0:1232; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1233; GFX9-NEXT: v_sub_u32_e64 v0, v0, v3 clamp1234; GFX9-NEXT: v_sub_u32_e64 v1, v1, v4 clamp1235; GFX9-NEXT: v_sub_u32_e64 v2, v2, v5 clamp1236; GFX9-NEXT: s_setpc_b64 s[30:31]1237;1238; GFX10PLUS-LABEL: v_usubsat_v3i32:1239; GFX10PLUS: ; %bb.0:1240; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1241; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v3 clamp1242; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v4 clamp1243; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v5 clamp1244; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1245 %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1246 ret <3 x i32> %result1247}1248 1249define amdgpu_ps <3 x i32> @s_usubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {1250; GFX6-LABEL: s_usubsat_v3i32:1251; GFX6: ; %bb.0:1252; GFX6-NEXT: s_min_u32 s3, s0, s31253; GFX6-NEXT: s_sub_i32 s0, s0, s31254; GFX6-NEXT: s_min_u32 s3, s1, s41255; GFX6-NEXT: s_sub_i32 s1, s1, s31256; GFX6-NEXT: s_min_u32 s3, s2, s51257; GFX6-NEXT: s_sub_i32 s2, s2, s31258; GFX6-NEXT: ; return to shader part epilog1259;1260; GFX8-LABEL: s_usubsat_v3i32:1261; GFX8: ; %bb.0:1262; GFX8-NEXT: v_mov_b32_e32 v0, s31263; GFX8-NEXT: v_mov_b32_e32 v1, s41264; GFX8-NEXT: v_mov_b32_e32 v2, s51265; GFX8-NEXT: v_sub_u32_e64 v0, s[6:7], s0, v0 clamp1266; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp1267; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp1268; GFX8-NEXT: v_readfirstlane_b32 s0, v01269; GFX8-NEXT: v_readfirstlane_b32 s1, v11270; GFX8-NEXT: v_readfirstlane_b32 s2, v21271; GFX8-NEXT: ; return to shader part epilog1272;1273; GFX9-LABEL: s_usubsat_v3i32:1274; GFX9: ; %bb.0:1275; GFX9-NEXT: v_mov_b32_e32 v0, s31276; GFX9-NEXT: v_mov_b32_e32 v1, s41277; GFX9-NEXT: v_mov_b32_e32 v2, s51278; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1279; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp1280; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp1281; GFX9-NEXT: v_readfirstlane_b32 s0, v01282; GFX9-NEXT: v_readfirstlane_b32 s1, v11283; GFX9-NEXT: v_readfirstlane_b32 s2, v21284; GFX9-NEXT: ; return to shader part epilog1285;1286; GFX10PLUS-LABEL: s_usubsat_v3i32:1287; GFX10PLUS: ; %bb.0:1288; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s3 clamp1289; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s4 clamp1290; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s5 clamp1291; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01292; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11293; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21294; GFX10PLUS-NEXT: ; return to shader part epilog1295 %result = call <3 x i32> @llvm.usub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)1296 ret <3 x i32> %result1297}1298 1299define <4 x i32> @v_usubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {1300; GFX6-LABEL: v_usubsat_v4i32:1301; GFX6: ; %bb.0:1302; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1303; GFX6-NEXT: v_min_u32_e32 v4, v0, v41304; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v41305; GFX6-NEXT: v_min_u32_e32 v4, v1, v51306; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v41307; GFX6-NEXT: v_min_u32_e32 v4, v2, v61308; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v41309; GFX6-NEXT: v_min_u32_e32 v4, v3, v71310; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v41311; GFX6-NEXT: s_setpc_b64 s[30:31]1312;1313; GFX8-LABEL: v_usubsat_v4i32:1314; GFX8: ; %bb.0:1315; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1316; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v4 clamp1317; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v5 clamp1318; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v6 clamp1319; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v7 clamp1320; GFX8-NEXT: s_setpc_b64 s[30:31]1321;1322; GFX9-LABEL: v_usubsat_v4i32:1323; GFX9: ; %bb.0:1324; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1325; GFX9-NEXT: v_sub_u32_e64 v0, v0, v4 clamp1326; GFX9-NEXT: v_sub_u32_e64 v1, v1, v5 clamp1327; GFX9-NEXT: v_sub_u32_e64 v2, v2, v6 clamp1328; GFX9-NEXT: v_sub_u32_e64 v3, v3, v7 clamp1329; GFX9-NEXT: s_setpc_b64 s[30:31]1330;1331; GFX10PLUS-LABEL: v_usubsat_v4i32:1332; GFX10PLUS: ; %bb.0:1333; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1334; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v4 clamp1335; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v5 clamp1336; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v6 clamp1337; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, v3, v7 clamp1338; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1339 %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1340 ret <4 x i32> %result1341}1342 1343define amdgpu_ps <4 x i32> @s_usubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {1344; GFX6-LABEL: s_usubsat_v4i32:1345; GFX6: ; %bb.0:1346; GFX6-NEXT: s_min_u32 s4, s0, s41347; GFX6-NEXT: s_sub_i32 s0, s0, s41348; GFX6-NEXT: s_min_u32 s4, s1, s51349; GFX6-NEXT: s_sub_i32 s1, s1, s41350; GFX6-NEXT: s_min_u32 s4, s2, s61351; GFX6-NEXT: s_sub_i32 s2, s2, s41352; GFX6-NEXT: s_min_u32 s4, s3, s71353; GFX6-NEXT: s_sub_i32 s3, s3, s41354; GFX6-NEXT: ; return to shader part epilog1355;1356; GFX8-LABEL: s_usubsat_v4i32:1357; GFX8: ; %bb.0:1358; GFX8-NEXT: v_mov_b32_e32 v0, s41359; GFX8-NEXT: v_mov_b32_e32 v1, s51360; GFX8-NEXT: v_mov_b32_e32 v2, s61361; GFX8-NEXT: v_mov_b32_e32 v3, s71362; GFX8-NEXT: v_sub_u32_e64 v0, s[8:9], s0, v0 clamp1363; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp1364; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp1365; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp1366; GFX8-NEXT: v_readfirstlane_b32 s0, v01367; GFX8-NEXT: v_readfirstlane_b32 s1, v11368; GFX8-NEXT: v_readfirstlane_b32 s2, v21369; GFX8-NEXT: v_readfirstlane_b32 s3, v31370; GFX8-NEXT: ; return to shader part epilog1371;1372; GFX9-LABEL: s_usubsat_v4i32:1373; GFX9: ; %bb.0:1374; GFX9-NEXT: v_mov_b32_e32 v0, s41375; GFX9-NEXT: v_mov_b32_e32 v1, s51376; GFX9-NEXT: v_mov_b32_e32 v2, s61377; GFX9-NEXT: v_mov_b32_e32 v3, s71378; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1379; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp1380; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp1381; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp1382; GFX9-NEXT: v_readfirstlane_b32 s0, v01383; GFX9-NEXT: v_readfirstlane_b32 s1, v11384; GFX9-NEXT: v_readfirstlane_b32 s2, v21385; GFX9-NEXT: v_readfirstlane_b32 s3, v31386; GFX9-NEXT: ; return to shader part epilog1387;1388; GFX10PLUS-LABEL: s_usubsat_v4i32:1389; GFX10PLUS: ; %bb.0:1390; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s4 clamp1391; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s5 clamp1392; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s6 clamp1393; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s7 clamp1394; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01395; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11396; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21397; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v31398; GFX10PLUS-NEXT: ; return to shader part epilog1399 %result = call <4 x i32> @llvm.usub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)1400 ret <4 x i32> %result1401}1402 1403define <5 x i32> @v_usubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {1404; GFX6-LABEL: v_usubsat_v5i32:1405; GFX6: ; %bb.0:1406; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1407; GFX6-NEXT: v_min_u32_e32 v5, v0, v51408; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v51409; GFX6-NEXT: v_min_u32_e32 v5, v1, v61410; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v51411; GFX6-NEXT: v_min_u32_e32 v5, v2, v71412; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v51413; GFX6-NEXT: v_min_u32_e32 v5, v3, v81414; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v51415; GFX6-NEXT: v_min_u32_e32 v5, v4, v91416; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v51417; GFX6-NEXT: s_setpc_b64 s[30:31]1418;1419; GFX8-LABEL: v_usubsat_v5i32:1420; GFX8: ; %bb.0:1421; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1422; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v5 clamp1423; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v6 clamp1424; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v7 clamp1425; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v8 clamp1426; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v9 clamp1427; GFX8-NEXT: s_setpc_b64 s[30:31]1428;1429; GFX9-LABEL: v_usubsat_v5i32:1430; GFX9: ; %bb.0:1431; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1432; GFX9-NEXT: v_sub_u32_e64 v0, v0, v5 clamp1433; GFX9-NEXT: v_sub_u32_e64 v1, v1, v6 clamp1434; GFX9-NEXT: v_sub_u32_e64 v2, v2, v7 clamp1435; GFX9-NEXT: v_sub_u32_e64 v3, v3, v8 clamp1436; GFX9-NEXT: v_sub_u32_e64 v4, v4, v9 clamp1437; GFX9-NEXT: s_setpc_b64 s[30:31]1438;1439; GFX10PLUS-LABEL: v_usubsat_v5i32:1440; GFX10PLUS: ; %bb.0:1441; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1442; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, v0, v5 clamp1443; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, v1, v6 clamp1444; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, v2, v7 clamp1445; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, v3, v8 clamp1446; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, v4, v9 clamp1447; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]1448 %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1449 ret <5 x i32> %result1450}1451 1452define amdgpu_ps <5 x i32> @s_usubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {1453; GFX6-LABEL: s_usubsat_v5i32:1454; GFX6: ; %bb.0:1455; GFX6-NEXT: s_min_u32 s5, s0, s51456; GFX6-NEXT: s_sub_i32 s0, s0, s51457; GFX6-NEXT: s_min_u32 s5, s1, s61458; GFX6-NEXT: s_sub_i32 s1, s1, s51459; GFX6-NEXT: s_min_u32 s5, s2, s71460; GFX6-NEXT: s_sub_i32 s2, s2, s51461; GFX6-NEXT: s_min_u32 s5, s3, s81462; GFX6-NEXT: s_sub_i32 s3, s3, s51463; GFX6-NEXT: s_min_u32 s5, s4, s91464; GFX6-NEXT: s_sub_i32 s4, s4, s51465; GFX6-NEXT: ; return to shader part epilog1466;1467; GFX8-LABEL: s_usubsat_v5i32:1468; GFX8: ; %bb.0:1469; GFX8-NEXT: v_mov_b32_e32 v0, s51470; GFX8-NEXT: v_mov_b32_e32 v1, s61471; GFX8-NEXT: v_mov_b32_e32 v2, s71472; GFX8-NEXT: v_mov_b32_e32 v3, s81473; GFX8-NEXT: v_mov_b32_e32 v4, s91474; GFX8-NEXT: v_sub_u32_e64 v0, s[10:11], s0, v0 clamp1475; GFX8-NEXT: v_sub_u32_e64 v1, s[0:1], s1, v1 clamp1476; GFX8-NEXT: v_sub_u32_e64 v2, s[0:1], s2, v2 clamp1477; GFX8-NEXT: v_sub_u32_e64 v3, s[0:1], s3, v3 clamp1478; GFX8-NEXT: v_sub_u32_e64 v4, s[0:1], s4, v4 clamp1479; GFX8-NEXT: v_readfirstlane_b32 s0, v01480; GFX8-NEXT: v_readfirstlane_b32 s1, v11481; GFX8-NEXT: v_readfirstlane_b32 s2, v21482; GFX8-NEXT: v_readfirstlane_b32 s3, v31483; GFX8-NEXT: v_readfirstlane_b32 s4, v41484; GFX8-NEXT: ; return to shader part epilog1485;1486; GFX9-LABEL: s_usubsat_v5i32:1487; GFX9: ; %bb.0:1488; GFX9-NEXT: v_mov_b32_e32 v0, s51489; GFX9-NEXT: v_mov_b32_e32 v1, s61490; GFX9-NEXT: v_mov_b32_e32 v2, s71491; GFX9-NEXT: v_mov_b32_e32 v3, s81492; GFX9-NEXT: v_mov_b32_e32 v4, s91493; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1494; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp1495; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp1496; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp1497; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp1498; GFX9-NEXT: v_readfirstlane_b32 s0, v01499; GFX9-NEXT: v_readfirstlane_b32 s1, v11500; GFX9-NEXT: v_readfirstlane_b32 s2, v21501; GFX9-NEXT: v_readfirstlane_b32 s3, v31502; GFX9-NEXT: v_readfirstlane_b32 s4, v41503; GFX9-NEXT: ; return to shader part epilog1504;1505; GFX10PLUS-LABEL: s_usubsat_v5i32:1506; GFX10PLUS: ; %bb.0:1507; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s5 clamp1508; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s6 clamp1509; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s7 clamp1510; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s8 clamp1511; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s9 clamp1512; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01513; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11514; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21515; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v31516; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v41517; GFX10PLUS-NEXT: ; return to shader part epilog1518 %result = call <5 x i32> @llvm.usub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)1519 ret <5 x i32> %result1520}1521 1522define <16 x i32> @v_usubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {1523; GFX6-LABEL: v_usubsat_v16i32:1524; GFX6: ; %bb.0:1525; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1526; GFX6-NEXT: v_min_u32_e32 v16, v0, v161527; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v161528; GFX6-NEXT: v_min_u32_e32 v16, v1, v171529; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v161530; GFX6-NEXT: v_min_u32_e32 v16, v2, v181531; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v161532; GFX6-NEXT: v_min_u32_e32 v16, v3, v191533; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v161534; GFX6-NEXT: buffer_load_dword v16, off, s[0:3], s321535; GFX6-NEXT: v_min_u32_e32 v17, v4, v201536; GFX6-NEXT: v_min_u32_e32 v18, v5, v211537; GFX6-NEXT: v_min_u32_e32 v19, v6, v221538; GFX6-NEXT: v_min_u32_e32 v20, v7, v231539; GFX6-NEXT: v_min_u32_e32 v21, v8, v241540; GFX6-NEXT: v_min_u32_e32 v22, v9, v251541; GFX6-NEXT: v_min_u32_e32 v23, v10, v261542; GFX6-NEXT: v_min_u32_e32 v24, v11, v271543; GFX6-NEXT: v_min_u32_e32 v25, v12, v281544; GFX6-NEXT: v_min_u32_e32 v26, v13, v291545; GFX6-NEXT: v_min_u32_e32 v27, v14, v301546; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v171547; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v181548; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v191549; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v201550; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v211551; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v221552; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v231553; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v241554; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v251555; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v261556; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v271557; GFX6-NEXT: s_waitcnt vmcnt(0)1558; GFX6-NEXT: v_min_u32_e32 v16, v15, v161559; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v161560; GFX6-NEXT: s_setpc_b64 s[30:31]1561;1562; GFX8-LABEL: v_usubsat_v16i32:1563; GFX8: ; %bb.0:1564; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1565; GFX8-NEXT: v_sub_u32_e64 v0, s[4:5], v0, v16 clamp1566; GFX8-NEXT: buffer_load_dword v16, off, s[0:3], s321567; GFX8-NEXT: v_sub_u32_e64 v1, s[4:5], v1, v17 clamp1568; GFX8-NEXT: v_sub_u32_e64 v2, s[4:5], v2, v18 clamp1569; GFX8-NEXT: v_sub_u32_e64 v3, s[4:5], v3, v19 clamp1570; GFX8-NEXT: v_sub_u32_e64 v4, s[4:5], v4, v20 clamp1571; GFX8-NEXT: v_sub_u32_e64 v5, s[4:5], v5, v21 clamp1572; GFX8-NEXT: v_sub_u32_e64 v6, s[4:5], v6, v22 clamp1573; GFX8-NEXT: v_sub_u32_e64 v7, s[4:5], v7, v23 clamp1574; GFX8-NEXT: v_sub_u32_e64 v8, s[4:5], v8, v24 clamp1575; GFX8-NEXT: v_sub_u32_e64 v9, s[4:5], v9, v25 clamp1576; GFX8-NEXT: v_sub_u32_e64 v10, s[4:5], v10, v26 clamp1577; GFX8-NEXT: v_sub_u32_e64 v11, s[4:5], v11, v27 clamp1578; GFX8-NEXT: v_sub_u32_e64 v12, s[4:5], v12, v28 clamp1579; GFX8-NEXT: v_sub_u32_e64 v13, s[4:5], v13, v29 clamp1580; GFX8-NEXT: v_sub_u32_e64 v14, s[4:5], v14, v30 clamp1581; GFX8-NEXT: s_waitcnt vmcnt(0)1582; GFX8-NEXT: v_sub_u32_e64 v15, s[4:5], v15, v16 clamp1583; GFX8-NEXT: s_setpc_b64 s[30:31]1584;1585; GFX9-LABEL: v_usubsat_v16i32:1586; GFX9: ; %bb.0:1587; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1588; GFX9-NEXT: v_sub_u32_e64 v0, v0, v16 clamp1589; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s321590; GFX9-NEXT: v_sub_u32_e64 v1, v1, v17 clamp1591; GFX9-NEXT: v_sub_u32_e64 v2, v2, v18 clamp1592; GFX9-NEXT: v_sub_u32_e64 v3, v3, v19 clamp1593; GFX9-NEXT: v_sub_u32_e64 v4, v4, v20 clamp1594; GFX9-NEXT: v_sub_u32_e64 v5, v5, v21 clamp1595; GFX9-NEXT: v_sub_u32_e64 v6, v6, v22 clamp1596; GFX9-NEXT: v_sub_u32_e64 v7, v7, v23 clamp1597; GFX9-NEXT: v_sub_u32_e64 v8, v8, v24 clamp1598; GFX9-NEXT: v_sub_u32_e64 v9, v9, v25 clamp1599; GFX9-NEXT: v_sub_u32_e64 v10, v10, v26 clamp1600; GFX9-NEXT: v_sub_u32_e64 v11, v11, v27 clamp1601; GFX9-NEXT: v_sub_u32_e64 v12, v12, v28 clamp1602; GFX9-NEXT: v_sub_u32_e64 v13, v13, v29 clamp1603; GFX9-NEXT: v_sub_u32_e64 v14, v14, v30 clamp1604; GFX9-NEXT: s_waitcnt vmcnt(0)1605; GFX9-NEXT: v_sub_u32_e64 v15, v15, v16 clamp1606; GFX9-NEXT: s_setpc_b64 s[30:31]1607;1608; GFX10-LABEL: v_usubsat_v16i32:1609; GFX10: ; %bb.0:1610; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1611; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s321612; GFX10-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp1613; GFX10-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp1614; GFX10-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp1615; GFX10-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp1616; GFX10-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp1617; GFX10-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp1618; GFX10-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp1619; GFX10-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp1620; GFX10-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp1621; GFX10-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp1622; GFX10-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp1623; GFX10-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp1624; GFX10-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp1625; GFX10-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp1626; GFX10-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp1627; GFX10-NEXT: s_waitcnt vmcnt(0)1628; GFX10-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp1629; GFX10-NEXT: s_setpc_b64 s[30:31]1630;1631; GFX11-LABEL: v_usubsat_v16i32:1632; GFX11: ; %bb.0:1633; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1634; GFX11-NEXT: scratch_load_b32 v31, off, s321635; GFX11-NEXT: v_sub_nc_u32_e64 v0, v0, v16 clamp1636; GFX11-NEXT: v_sub_nc_u32_e64 v1, v1, v17 clamp1637; GFX11-NEXT: v_sub_nc_u32_e64 v2, v2, v18 clamp1638; GFX11-NEXT: v_sub_nc_u32_e64 v3, v3, v19 clamp1639; GFX11-NEXT: v_sub_nc_u32_e64 v4, v4, v20 clamp1640; GFX11-NEXT: v_sub_nc_u32_e64 v5, v5, v21 clamp1641; GFX11-NEXT: v_sub_nc_u32_e64 v6, v6, v22 clamp1642; GFX11-NEXT: v_sub_nc_u32_e64 v7, v7, v23 clamp1643; GFX11-NEXT: v_sub_nc_u32_e64 v8, v8, v24 clamp1644; GFX11-NEXT: v_sub_nc_u32_e64 v9, v9, v25 clamp1645; GFX11-NEXT: v_sub_nc_u32_e64 v10, v10, v26 clamp1646; GFX11-NEXT: v_sub_nc_u32_e64 v11, v11, v27 clamp1647; GFX11-NEXT: v_sub_nc_u32_e64 v12, v12, v28 clamp1648; GFX11-NEXT: v_sub_nc_u32_e64 v13, v13, v29 clamp1649; GFX11-NEXT: v_sub_nc_u32_e64 v14, v14, v30 clamp1650; GFX11-NEXT: s_waitcnt vmcnt(0)1651; GFX11-NEXT: v_sub_nc_u32_e64 v15, v15, v31 clamp1652; GFX11-NEXT: s_setpc_b64 s[30:31]1653 %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)1654 ret <16 x i32> %result1655}1656 1657define amdgpu_ps <16 x i32> @s_usubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {1658; GFX6-LABEL: s_usubsat_v16i32:1659; GFX6: ; %bb.0:1660; GFX6-NEXT: s_min_u32 s16, s0, s161661; GFX6-NEXT: s_sub_i32 s0, s0, s161662; GFX6-NEXT: s_min_u32 s16, s1, s171663; GFX6-NEXT: s_sub_i32 s1, s1, s161664; GFX6-NEXT: s_min_u32 s16, s2, s181665; GFX6-NEXT: s_sub_i32 s2, s2, s161666; GFX6-NEXT: s_min_u32 s16, s3, s191667; GFX6-NEXT: s_sub_i32 s3, s3, s161668; GFX6-NEXT: s_min_u32 s16, s4, s201669; GFX6-NEXT: s_sub_i32 s4, s4, s161670; GFX6-NEXT: s_min_u32 s16, s5, s211671; GFX6-NEXT: s_sub_i32 s5, s5, s161672; GFX6-NEXT: s_min_u32 s16, s6, s221673; GFX6-NEXT: s_sub_i32 s6, s6, s161674; GFX6-NEXT: s_min_u32 s16, s7, s231675; GFX6-NEXT: s_sub_i32 s7, s7, s161676; GFX6-NEXT: s_min_u32 s16, s8, s241677; GFX6-NEXT: s_sub_i32 s8, s8, s161678; GFX6-NEXT: s_min_u32 s16, s9, s251679; GFX6-NEXT: s_sub_i32 s9, s9, s161680; GFX6-NEXT: s_min_u32 s16, s10, s261681; GFX6-NEXT: s_sub_i32 s10, s10, s161682; GFX6-NEXT: s_min_u32 s16, s11, s271683; GFX6-NEXT: s_sub_i32 s11, s11, s161684; GFX6-NEXT: s_min_u32 s16, s12, s281685; GFX6-NEXT: s_sub_i32 s12, s12, s161686; GFX6-NEXT: s_min_u32 s16, s13, s291687; GFX6-NEXT: s_sub_i32 s13, s13, s161688; GFX6-NEXT: s_min_u32 s16, s14, s301689; GFX6-NEXT: s_sub_i32 s14, s14, s161690; GFX6-NEXT: s_min_u32 s16, s15, s311691; GFX6-NEXT: s_sub_i32 s15, s15, s161692; GFX6-NEXT: ; return to shader part epilog1693;1694; GFX8-LABEL: s_usubsat_v16i32:1695; GFX8: ; %bb.0:1696; GFX8-NEXT: v_mov_b32_e32 v0, s161697; GFX8-NEXT: v_mov_b32_e32 v1, s171698; GFX8-NEXT: v_mov_b32_e32 v2, s181699; GFX8-NEXT: v_mov_b32_e32 v3, s191700; GFX8-NEXT: v_mov_b32_e32 v4, s201701; GFX8-NEXT: v_mov_b32_e32 v5, s211702; GFX8-NEXT: v_mov_b32_e32 v6, s221703; GFX8-NEXT: v_mov_b32_e32 v7, s231704; GFX8-NEXT: v_mov_b32_e32 v8, s241705; GFX8-NEXT: v_mov_b32_e32 v9, s251706; GFX8-NEXT: v_mov_b32_e32 v10, s261707; GFX8-NEXT: v_mov_b32_e32 v11, s271708; GFX8-NEXT: v_mov_b32_e32 v12, s281709; GFX8-NEXT: v_mov_b32_e32 v13, s291710; GFX8-NEXT: v_mov_b32_e32 v14, s301711; GFX8-NEXT: v_mov_b32_e32 v15, s311712; GFX8-NEXT: v_sub_u32_e64 v0, s[32:33], s0, v0 clamp1713; GFX8-NEXT: v_sub_u32_e64 v1, s[16:17], s1, v1 clamp1714; GFX8-NEXT: v_sub_u32_e64 v2, s[16:17], s2, v2 clamp1715; GFX8-NEXT: v_sub_u32_e64 v3, s[2:3], s3, v3 clamp1716; GFX8-NEXT: v_sub_u32_e64 v4, s[2:3], s4, v4 clamp1717; GFX8-NEXT: v_sub_u32_e64 v5, s[2:3], s5, v5 clamp1718; GFX8-NEXT: v_sub_u32_e64 v6, s[2:3], s6, v6 clamp1719; GFX8-NEXT: v_sub_u32_e64 v7, s[2:3], s7, v7 clamp1720; GFX8-NEXT: v_sub_u32_e64 v8, s[2:3], s8, v8 clamp1721; GFX8-NEXT: v_sub_u32_e64 v9, s[2:3], s9, v9 clamp1722; GFX8-NEXT: v_sub_u32_e64 v10, s[2:3], s10, v10 clamp1723; GFX8-NEXT: v_sub_u32_e64 v11, s[2:3], s11, v11 clamp1724; GFX8-NEXT: v_sub_u32_e64 v12, s[2:3], s12, v12 clamp1725; GFX8-NEXT: v_sub_u32_e64 v13, s[2:3], s13, v13 clamp1726; GFX8-NEXT: v_sub_u32_e64 v14, s[2:3], s14, v14 clamp1727; GFX8-NEXT: v_sub_u32_e64 v15, s[2:3], s15, v15 clamp1728; GFX8-NEXT: v_readfirstlane_b32 s0, v01729; GFX8-NEXT: v_readfirstlane_b32 s1, v11730; GFX8-NEXT: v_readfirstlane_b32 s2, v21731; GFX8-NEXT: v_readfirstlane_b32 s3, v31732; GFX8-NEXT: v_readfirstlane_b32 s4, v41733; GFX8-NEXT: v_readfirstlane_b32 s5, v51734; GFX8-NEXT: v_readfirstlane_b32 s6, v61735; GFX8-NEXT: v_readfirstlane_b32 s7, v71736; GFX8-NEXT: v_readfirstlane_b32 s8, v81737; GFX8-NEXT: v_readfirstlane_b32 s9, v91738; GFX8-NEXT: v_readfirstlane_b32 s10, v101739; GFX8-NEXT: v_readfirstlane_b32 s11, v111740; GFX8-NEXT: v_readfirstlane_b32 s12, v121741; GFX8-NEXT: v_readfirstlane_b32 s13, v131742; GFX8-NEXT: v_readfirstlane_b32 s14, v141743; GFX8-NEXT: v_readfirstlane_b32 s15, v151744; GFX8-NEXT: ; return to shader part epilog1745;1746; GFX9-LABEL: s_usubsat_v16i32:1747; GFX9: ; %bb.0:1748; GFX9-NEXT: v_mov_b32_e32 v0, s161749; GFX9-NEXT: v_mov_b32_e32 v1, s171750; GFX9-NEXT: v_mov_b32_e32 v2, s181751; GFX9-NEXT: v_mov_b32_e32 v3, s191752; GFX9-NEXT: v_mov_b32_e32 v4, s201753; GFX9-NEXT: v_mov_b32_e32 v5, s211754; GFX9-NEXT: v_mov_b32_e32 v6, s221755; GFX9-NEXT: v_mov_b32_e32 v7, s231756; GFX9-NEXT: v_mov_b32_e32 v8, s241757; GFX9-NEXT: v_mov_b32_e32 v9, s251758; GFX9-NEXT: v_mov_b32_e32 v10, s261759; GFX9-NEXT: v_mov_b32_e32 v11, s271760; GFX9-NEXT: v_mov_b32_e32 v12, s281761; GFX9-NEXT: v_mov_b32_e32 v13, s291762; GFX9-NEXT: v_mov_b32_e32 v14, s301763; GFX9-NEXT: v_mov_b32_e32 v15, s311764; GFX9-NEXT: v_sub_u32_e64 v0, s0, v0 clamp1765; GFX9-NEXT: v_sub_u32_e64 v1, s1, v1 clamp1766; GFX9-NEXT: v_sub_u32_e64 v2, s2, v2 clamp1767; GFX9-NEXT: v_sub_u32_e64 v3, s3, v3 clamp1768; GFX9-NEXT: v_sub_u32_e64 v4, s4, v4 clamp1769; GFX9-NEXT: v_sub_u32_e64 v5, s5, v5 clamp1770; GFX9-NEXT: v_sub_u32_e64 v6, s6, v6 clamp1771; GFX9-NEXT: v_sub_u32_e64 v7, s7, v7 clamp1772; GFX9-NEXT: v_sub_u32_e64 v8, s8, v8 clamp1773; GFX9-NEXT: v_sub_u32_e64 v9, s9, v9 clamp1774; GFX9-NEXT: v_sub_u32_e64 v10, s10, v10 clamp1775; GFX9-NEXT: v_sub_u32_e64 v11, s11, v11 clamp1776; GFX9-NEXT: v_sub_u32_e64 v12, s12, v12 clamp1777; GFX9-NEXT: v_sub_u32_e64 v13, s13, v13 clamp1778; GFX9-NEXT: v_sub_u32_e64 v14, s14, v14 clamp1779; GFX9-NEXT: v_sub_u32_e64 v15, s15, v15 clamp1780; GFX9-NEXT: v_readfirstlane_b32 s0, v01781; GFX9-NEXT: v_readfirstlane_b32 s1, v11782; GFX9-NEXT: v_readfirstlane_b32 s2, v21783; GFX9-NEXT: v_readfirstlane_b32 s3, v31784; GFX9-NEXT: v_readfirstlane_b32 s4, v41785; GFX9-NEXT: v_readfirstlane_b32 s5, v51786; GFX9-NEXT: v_readfirstlane_b32 s6, v61787; GFX9-NEXT: v_readfirstlane_b32 s7, v71788; GFX9-NEXT: v_readfirstlane_b32 s8, v81789; GFX9-NEXT: v_readfirstlane_b32 s9, v91790; GFX9-NEXT: v_readfirstlane_b32 s10, v101791; GFX9-NEXT: v_readfirstlane_b32 s11, v111792; GFX9-NEXT: v_readfirstlane_b32 s12, v121793; GFX9-NEXT: v_readfirstlane_b32 s13, v131794; GFX9-NEXT: v_readfirstlane_b32 s14, v141795; GFX9-NEXT: v_readfirstlane_b32 s15, v151796; GFX9-NEXT: ; return to shader part epilog1797;1798; GFX10PLUS-LABEL: s_usubsat_v16i32:1799; GFX10PLUS: ; %bb.0:1800; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v0, s0, s16 clamp1801; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v1, s1, s17 clamp1802; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v2, s2, s18 clamp1803; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v3, s3, s19 clamp1804; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v4, s4, s20 clamp1805; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v5, s5, s21 clamp1806; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v6, s6, s22 clamp1807; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v7, s7, s23 clamp1808; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v8, s8, s24 clamp1809; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v9, s9, s25 clamp1810; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v10, s10, s26 clamp1811; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v11, s11, s27 clamp1812; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v12, s12, s28 clamp1813; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v13, s13, s29 clamp1814; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v14, s14, s30 clamp1815; GFX10PLUS-NEXT: v_sub_nc_u32_e64 v15, s15, s31 clamp1816; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v01817; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v11818; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v21819; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v31820; GFX10PLUS-NEXT: v_readfirstlane_b32 s4, v41821; GFX10PLUS-NEXT: v_readfirstlane_b32 s5, v51822; GFX10PLUS-NEXT: v_readfirstlane_b32 s6, v61823; GFX10PLUS-NEXT: v_readfirstlane_b32 s7, v71824; GFX10PLUS-NEXT: v_readfirstlane_b32 s8, v81825; GFX10PLUS-NEXT: v_readfirstlane_b32 s9, v91826; GFX10PLUS-NEXT: v_readfirstlane_b32 s10, v101827; GFX10PLUS-NEXT: v_readfirstlane_b32 s11, v111828; GFX10PLUS-NEXT: v_readfirstlane_b32 s12, v121829; GFX10PLUS-NEXT: v_readfirstlane_b32 s13, v131830; GFX10PLUS-NEXT: v_readfirstlane_b32 s14, v141831; GFX10PLUS-NEXT: v_readfirstlane_b32 s15, v151832; GFX10PLUS-NEXT: ; return to shader part epilog1833 %result = call <16 x i32> @llvm.usub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)1834 ret <16 x i32> %result1835}1836 1837define i16 @v_usubsat_i16(i16 %lhs, i16 %rhs) {1838; GFX6-LABEL: v_usubsat_i16:1839; GFX6: ; %bb.0:1840; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1841; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v01842; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v11843; GFX6-NEXT: v_min_u32_e32 v1, v0, v11844; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11845; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v01846; GFX6-NEXT: s_setpc_b64 s[30:31]1847;1848; GFX8-LABEL: v_usubsat_i16:1849; GFX8: ; %bb.0:1850; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1851; GFX8-NEXT: v_sub_u16_e64 v0, v0, v1 clamp1852; GFX8-NEXT: s_setpc_b64 s[30:31]1853;1854; GFX9-LABEL: v_usubsat_i16:1855; GFX9: ; %bb.0:1856; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1857; GFX9-NEXT: v_sub_u16_e64 v0, v0, v1 clamp1858; GFX9-NEXT: s_setpc_b64 s[30:31]1859;1860; GFX10-LABEL: v_usubsat_i16:1861; GFX10: ; %bb.0:1862; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1863; GFX10-NEXT: v_sub_nc_u16 v0, v0, v1 clamp1864; GFX10-NEXT: s_setpc_b64 s[30:31]1865;1866; GFX11-TRUE16-LABEL: v_usubsat_i16:1867; GFX11-TRUE16: ; %bb.0:1868; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1869; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, v1.l clamp1870; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1871;1872; GFX11-FAKE16-LABEL: v_usubsat_i16:1873; GFX11-FAKE16: ; %bb.0:1874; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1875; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, v0, v1 clamp1876; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1877 %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)1878 ret i16 %result1879}1880 1881define amdgpu_ps i16 @s_usubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {1882; GFX6-LABEL: s_usubsat_i16:1883; GFX6: ; %bb.0:1884; GFX6-NEXT: s_lshl_b32 s0, s0, 161885; GFX6-NEXT: s_lshl_b32 s1, s1, 161886; GFX6-NEXT: s_min_u32 s1, s0, s11887; GFX6-NEXT: s_sub_i32 s0, s0, s11888; GFX6-NEXT: s_lshr_b32 s0, s0, 161889; GFX6-NEXT: ; return to shader part epilog1890;1891; GFX8-LABEL: s_usubsat_i16:1892; GFX8: ; %bb.0:1893; GFX8-NEXT: v_mov_b32_e32 v0, s11894; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp1895; GFX8-NEXT: v_readfirstlane_b32 s0, v01896; GFX8-NEXT: ; return to shader part epilog1897;1898; GFX9-LABEL: s_usubsat_i16:1899; GFX9: ; %bb.0:1900; GFX9-NEXT: v_mov_b32_e32 v0, s11901; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp1902; GFX9-NEXT: v_readfirstlane_b32 s0, v01903; GFX9-NEXT: ; return to shader part epilog1904;1905; GFX10-LABEL: s_usubsat_i16:1906; GFX10: ; %bb.0:1907; GFX10-NEXT: v_sub_nc_u16 v0, s0, s1 clamp1908; GFX10-NEXT: v_readfirstlane_b32 s0, v01909; GFX10-NEXT: ; return to shader part epilog1910;1911; GFX11-TRUE16-LABEL: s_usubsat_i16:1912; GFX11-TRUE16: ; %bb.0:1913; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, s1 clamp1914; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v01915; GFX11-TRUE16-NEXT: ; return to shader part epilog1916;1917; GFX11-FAKE16-LABEL: s_usubsat_i16:1918; GFX11-FAKE16: ; %bb.0:1919; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, s0, s1 clamp1920; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v01921; GFX11-FAKE16-NEXT: ; return to shader part epilog1922 %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)1923 ret i16 %result1924}1925 1926define amdgpu_ps half @usubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {1927; GFX6-LABEL: usubsat_i16_sv:1928; GFX6: ; %bb.0:1929; GFX6-NEXT: s_lshl_b32 s0, s0, 161930; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v01931; GFX6-NEXT: v_min_u32_e32 v0, s0, v01932; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v01933; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v01934; GFX6-NEXT: ; return to shader part epilog1935;1936; GFX8-LABEL: usubsat_i16_sv:1937; GFX8: ; %bb.0:1938; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp1939; GFX8-NEXT: ; return to shader part epilog1940;1941; GFX9-LABEL: usubsat_i16_sv:1942; GFX9: ; %bb.0:1943; GFX9-NEXT: v_sub_u16_e64 v0, s0, v0 clamp1944; GFX9-NEXT: ; return to shader part epilog1945;1946; GFX10-LABEL: usubsat_i16_sv:1947; GFX10: ; %bb.0:1948; GFX10-NEXT: v_sub_nc_u16 v0, s0, v0 clamp1949; GFX10-NEXT: ; return to shader part epilog1950;1951; GFX11-TRUE16-LABEL: usubsat_i16_sv:1952; GFX11-TRUE16: ; %bb.0:1953; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, s0, v0.l clamp1954; GFX11-TRUE16-NEXT: ; return to shader part epilog1955;1956; GFX11-FAKE16-LABEL: usubsat_i16_sv:1957; GFX11-FAKE16: ; %bb.0:1958; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, s0, v0 clamp1959; GFX11-FAKE16-NEXT: ; return to shader part epilog1960 %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)1961 %cast = bitcast i16 %result to half1962 ret half %cast1963}1964 1965define amdgpu_ps half @usubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {1966; GFX6-LABEL: usubsat_i16_vs:1967; GFX6: ; %bb.0:1968; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v01969; GFX6-NEXT: s_lshl_b32 s0, s0, 161970; GFX6-NEXT: v_min_u32_e32 v1, s0, v01971; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v11972; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v01973; GFX6-NEXT: ; return to shader part epilog1974;1975; GFX8-LABEL: usubsat_i16_vs:1976; GFX8: ; %bb.0:1977; GFX8-NEXT: v_sub_u16_e64 v0, v0, s0 clamp1978; GFX8-NEXT: ; return to shader part epilog1979;1980; GFX9-LABEL: usubsat_i16_vs:1981; GFX9: ; %bb.0:1982; GFX9-NEXT: v_sub_u16_e64 v0, v0, s0 clamp1983; GFX9-NEXT: ; return to shader part epilog1984;1985; GFX10-LABEL: usubsat_i16_vs:1986; GFX10: ; %bb.0:1987; GFX10-NEXT: v_sub_nc_u16 v0, v0, s0 clamp1988; GFX10-NEXT: ; return to shader part epilog1989;1990; GFX11-TRUE16-LABEL: usubsat_i16_vs:1991; GFX11-TRUE16: ; %bb.0:1992; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.l, v0.l, s0 clamp1993; GFX11-TRUE16-NEXT: ; return to shader part epilog1994;1995; GFX11-FAKE16-LABEL: usubsat_i16_vs:1996; GFX11-FAKE16: ; %bb.0:1997; GFX11-FAKE16-NEXT: v_sub_nc_u16 v0, v0, s0 clamp1998; GFX11-FAKE16-NEXT: ; return to shader part epilog1999 %result = call i16 @llvm.usub.sat.i16(i16 %lhs, i16 %rhs)2000 %cast = bitcast i16 %result to half2001 ret half %cast2002}2003 2004define <2 x i16> @v_usubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {2005; GFX6-LABEL: v_usubsat_v2i16:2006; GFX6: ; %bb.0:2007; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2008; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02009; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22010; GFX6-NEXT: v_min_u32_e32 v2, v0, v22011; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22012; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12013; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v32014; GFX6-NEXT: v_min_u32_e32 v2, v1, v22015; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v22016; GFX6-NEXT: v_lshrrev_b32_e32 v0, 16, v02017; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12018; GFX6-NEXT: s_setpc_b64 s[30:31]2019;2020; GFX8-LABEL: v_usubsat_v2i16:2021; GFX8: ; %bb.0:2022; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2023; GFX8-NEXT: v_sub_u16_e64 v2, v0, v1 clamp2024; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12025; GFX8-NEXT: v_or_b32_e32 v0, v2, v02026; GFX8-NEXT: s_setpc_b64 s[30:31]2027;2028; GFX9-LABEL: v_usubsat_v2i16:2029; GFX9: ; %bb.0:2030; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2031; GFX9-NEXT: v_pk_sub_u16 v0, v0, v1 clamp2032; GFX9-NEXT: s_setpc_b64 s[30:31]2033;2034; GFX10PLUS-LABEL: v_usubsat_v2i16:2035; GFX10PLUS: ; %bb.0:2036; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2037; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v1 clamp2038; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2039 %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2040 ret <2 x i16> %result2041}2042 2043define amdgpu_ps i32 @s_usubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {2044; GFX6-LABEL: s_usubsat_v2i16:2045; GFX6: ; %bb.0:2046; GFX6-NEXT: s_lshl_b32 s0, s0, 162047; GFX6-NEXT: s_lshl_b32 s2, s2, 162048; GFX6-NEXT: s_min_u32 s2, s0, s22049; GFX6-NEXT: s_sub_i32 s0, s0, s22050; GFX6-NEXT: s_lshl_b32 s1, s1, 162051; GFX6-NEXT: s_lshl_b32 s2, s3, 162052; GFX6-NEXT: s_min_u32 s2, s1, s22053; GFX6-NEXT: s_sub_i32 s1, s1, s22054; GFX6-NEXT: s_lshr_b32 s1, s1, 162055; GFX6-NEXT: v_mov_b32_e32 v0, s02056; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 162057; GFX6-NEXT: v_readfirstlane_b32 s0, v02058; GFX6-NEXT: ; return to shader part epilog2059;2060; GFX8-LABEL: s_usubsat_v2i16:2061; GFX8: ; %bb.0:2062; GFX8-NEXT: s_lshr_b32 s2, s0, 162063; GFX8-NEXT: s_lshr_b32 s3, s1, 162064; GFX8-NEXT: v_mov_b32_e32 v0, s12065; GFX8-NEXT: v_mov_b32_e32 v1, s32066; GFX8-NEXT: v_mov_b32_e32 v2, s22067; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp2068; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2069; GFX8-NEXT: v_or_b32_e32 v0, v0, v12070; GFX8-NEXT: v_readfirstlane_b32 s0, v02071; GFX8-NEXT: ; return to shader part epilog2072;2073; GFX9-LABEL: s_usubsat_v2i16:2074; GFX9: ; %bb.0:2075; GFX9-NEXT: v_mov_b32_e32 v0, s12076; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2077; GFX9-NEXT: v_readfirstlane_b32 s0, v02078; GFX9-NEXT: ; return to shader part epilog2079;2080; GFX10PLUS-LABEL: s_usubsat_v2i16:2081; GFX10PLUS: ; %bb.0:2082; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s1 clamp2083; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02084; GFX10PLUS-NEXT: ; return to shader part epilog2085 %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2086 %cast = bitcast <2 x i16> %result to i322087 ret i32 %cast2088}2089 2090define amdgpu_ps float @usubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {2091; GFX6-LABEL: usubsat_v2i16_sv:2092; GFX6: ; %bb.0:2093; GFX6-NEXT: s_lshl_b32 s0, s0, 162094; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02095; GFX6-NEXT: v_min_u32_e32 v0, s0, v02096; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v02097; GFX6-NEXT: s_lshl_b32 s0, s1, 162098; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12099; GFX6-NEXT: v_min_u32_e32 v1, s0, v12100; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v12101; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12102; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 162103; GFX6-NEXT: ; return to shader part epilog2104;2105; GFX8-LABEL: usubsat_v2i16_sv:2106; GFX8: ; %bb.0:2107; GFX8-NEXT: s_lshr_b32 s1, s0, 162108; GFX8-NEXT: v_mov_b32_e32 v2, s12109; GFX8-NEXT: v_sub_u16_e64 v1, s0, v0 clamp2110; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_12111; GFX8-NEXT: v_or_b32_e32 v0, v1, v02112; GFX8-NEXT: ; return to shader part epilog2113;2114; GFX9-LABEL: usubsat_v2i16_sv:2115; GFX9: ; %bb.0:2116; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2117; GFX9-NEXT: ; return to shader part epilog2118;2119; GFX10PLUS-LABEL: usubsat_v2i16_sv:2120; GFX10PLUS: ; %bb.0:2121; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2122; GFX10PLUS-NEXT: ; return to shader part epilog2123 %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2124 %cast = bitcast <2 x i16> %result to float2125 ret float %cast2126}2127 2128define amdgpu_ps float @usubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {2129; GFX6-LABEL: usubsat_v2i16_vs:2130; GFX6: ; %bb.0:2131; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02132; GFX6-NEXT: s_lshl_b32 s0, s0, 162133; GFX6-NEXT: v_min_u32_e32 v2, s0, v02134; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12135; GFX6-NEXT: s_lshl_b32 s0, s1, 162136; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22137; GFX6-NEXT: v_min_u32_e32 v2, s0, v12138; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v22139; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12140; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 162141; GFX6-NEXT: ; return to shader part epilog2142;2143; GFX8-LABEL: usubsat_v2i16_vs:2144; GFX8: ; %bb.0:2145; GFX8-NEXT: s_lshr_b32 s1, s0, 162146; GFX8-NEXT: v_mov_b32_e32 v2, s12147; GFX8-NEXT: v_sub_u16_e64 v1, v0, s0 clamp2148; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2149; GFX8-NEXT: v_or_b32_e32 v0, v1, v02150; GFX8-NEXT: ; return to shader part epilog2151;2152; GFX9-LABEL: usubsat_v2i16_vs:2153; GFX9: ; %bb.0:2154; GFX9-NEXT: v_pk_sub_u16 v0, v0, s0 clamp2155; GFX9-NEXT: ; return to shader part epilog2156;2157; GFX10PLUS-LABEL: usubsat_v2i16_vs:2158; GFX10PLUS: ; %bb.0:2159; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, s0 clamp2160; GFX10PLUS-NEXT: ; return to shader part epilog2161 %result = call <2 x i16> @llvm.usub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)2162 %cast = bitcast <2 x i16> %result to float2163 ret float %cast2164}2165 2166; FIXME: v3i16 insert/extract2167; define <3 x i16> @v_usubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {2168; %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)2169; ret <3 x i16> %result2170; }2171 2172; define amdgpu_ps <3 x i16> @s_usubsat_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs) {2173; %result = call <3 x i16> @llvm.usub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)2174; ret <3 x i16> %result2175; }2176 2177define <2 x float> @v_usubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {2178; GFX6-LABEL: v_usubsat_v4i16:2179; GFX6: ; %bb.0:2180; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2181; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02182; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v42183; GFX6-NEXT: v_min_u32_e32 v4, v0, v42184; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v42185; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12186; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v52187; GFX6-NEXT: v_min_u32_e32 v4, v1, v42188; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v42189; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22190; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v62191; GFX6-NEXT: v_min_u32_e32 v4, v2, v42192; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v42193; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32194; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v72195; GFX6-NEXT: v_min_u32_e32 v4, v3, v42196; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v42197; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12198; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v32199; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 162200; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 162201; GFX6-NEXT: s_setpc_b64 s[30:31]2202;2203; GFX8-LABEL: v_usubsat_v4i16:2204; GFX8: ; %bb.0:2205; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2206; GFX8-NEXT: v_sub_u16_e64 v4, v0, v2 clamp2207; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v2 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12208; GFX8-NEXT: v_sub_u16_e64 v2, v1, v3 clamp2209; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12210; GFX8-NEXT: v_or_b32_e32 v0, v4, v02211; GFX8-NEXT: v_or_b32_e32 v1, v2, v12212; GFX8-NEXT: s_setpc_b64 s[30:31]2213;2214; GFX9-LABEL: v_usubsat_v4i16:2215; GFX9: ; %bb.0:2216; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2217; GFX9-NEXT: v_pk_sub_u16 v0, v0, v2 clamp2218; GFX9-NEXT: v_pk_sub_u16 v1, v1, v3 clamp2219; GFX9-NEXT: s_setpc_b64 s[30:31]2220;2221; GFX10PLUS-LABEL: v_usubsat_v4i16:2222; GFX10PLUS: ; %bb.0:2223; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2224; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v2 clamp2225; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v3 clamp2226; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2227 %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)2228 %cast = bitcast <4 x i16> %result to <2 x float>2229 ret <2 x float> %cast2230}2231 2232define amdgpu_ps <2 x i32> @s_usubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {2233; GFX6-LABEL: s_usubsat_v4i16:2234; GFX6: ; %bb.0:2235; GFX6-NEXT: s_lshl_b32 s0, s0, 162236; GFX6-NEXT: s_lshl_b32 s4, s4, 162237; GFX6-NEXT: s_min_u32 s4, s0, s42238; GFX6-NEXT: s_sub_i32 s0, s0, s42239; GFX6-NEXT: s_lshl_b32 s1, s1, 162240; GFX6-NEXT: s_lshl_b32 s4, s5, 162241; GFX6-NEXT: s_min_u32 s4, s1, s42242; GFX6-NEXT: s_sub_i32 s1, s1, s42243; GFX6-NEXT: s_lshl_b32 s2, s2, 162244; GFX6-NEXT: s_lshl_b32 s4, s6, 162245; GFX6-NEXT: s_min_u32 s4, s2, s42246; GFX6-NEXT: s_sub_i32 s2, s2, s42247; GFX6-NEXT: s_lshl_b32 s3, s3, 162248; GFX6-NEXT: s_lshl_b32 s4, s7, 162249; GFX6-NEXT: s_min_u32 s4, s3, s42250; GFX6-NEXT: s_sub_i32 s3, s3, s42251; GFX6-NEXT: s_lshr_b32 s1, s1, 162252; GFX6-NEXT: s_lshr_b32 s3, s3, 162253; GFX6-NEXT: v_mov_b32_e32 v0, s02254; GFX6-NEXT: v_mov_b32_e32 v1, s22255; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 162256; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 162257; GFX6-NEXT: v_readfirstlane_b32 s0, v02258; GFX6-NEXT: v_readfirstlane_b32 s1, v12259; GFX6-NEXT: ; return to shader part epilog2260;2261; GFX8-LABEL: s_usubsat_v4i16:2262; GFX8: ; %bb.0:2263; GFX8-NEXT: s_lshr_b32 s4, s0, 162264; GFX8-NEXT: s_lshr_b32 s6, s2, 162265; GFX8-NEXT: s_lshr_b32 s5, s1, 162266; GFX8-NEXT: s_lshr_b32 s7, s3, 162267; GFX8-NEXT: v_mov_b32_e32 v1, s62268; GFX8-NEXT: v_mov_b32_e32 v2, s42269; GFX8-NEXT: v_mov_b32_e32 v0, s22270; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2271; GFX8-NEXT: v_mov_b32_e32 v2, s32272; GFX8-NEXT: v_mov_b32_e32 v3, s72273; GFX8-NEXT: v_mov_b32_e32 v4, s52274; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp2275; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp2276; GFX8-NEXT: v_sub_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2277; GFX8-NEXT: v_or_b32_e32 v0, v0, v12278; GFX8-NEXT: v_or_b32_e32 v1, v2, v32279; GFX8-NEXT: v_readfirstlane_b32 s0, v02280; GFX8-NEXT: v_readfirstlane_b32 s1, v12281; GFX8-NEXT: ; return to shader part epilog2282;2283; GFX9-LABEL: s_usubsat_v4i16:2284; GFX9: ; %bb.0:2285; GFX9-NEXT: v_mov_b32_e32 v0, s22286; GFX9-NEXT: v_mov_b32_e32 v1, s32287; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2288; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp2289; GFX9-NEXT: v_readfirstlane_b32 s0, v02290; GFX9-NEXT: v_readfirstlane_b32 s1, v12291; GFX9-NEXT: ; return to shader part epilog2292;2293; GFX10PLUS-LABEL: s_usubsat_v4i16:2294; GFX10PLUS: ; %bb.0:2295; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s2 clamp2296; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s3 clamp2297; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02298; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v12299; GFX10PLUS-NEXT: ; return to shader part epilog2300 %result = call <4 x i16> @llvm.usub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)2301 %cast = bitcast <4 x i16> %result to <2 x i32>2302 ret <2 x i32> %cast2303}2304 2305; FIXME2306; define <5 x i16> @v_usubsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {2307; %result = call <5 x i16> @llvm.usub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)2308; ret <5 x i16> %result2309; }2310 2311; define amdgpu_ps <5 x i16> @s_usubsat_v5i16(<5 x i16> inreg %lhs, <5 x i16> inreg %rhs) {2312; %result = call <5 x i16> @llvm.usub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)2313; ret <5 x i16> %result2314; }2315 2316define <3 x float> @v_usubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {2317; GFX6-LABEL: v_usubsat_v6i16:2318; GFX6: ; %bb.0:2319; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2320; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02321; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v62322; GFX6-NEXT: v_min_u32_e32 v6, v0, v62323; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v62324; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12325; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v72326; GFX6-NEXT: v_min_u32_e32 v6, v1, v62327; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v62328; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22329; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v82330; GFX6-NEXT: v_min_u32_e32 v6, v2, v62331; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v62332; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32333; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v92334; GFX6-NEXT: v_min_u32_e32 v6, v3, v62335; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v62336; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v42337; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v102338; GFX6-NEXT: v_min_u32_e32 v6, v4, v62339; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v62340; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v52341; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v112342; GFX6-NEXT: v_min_u32_e32 v6, v5, v62343; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v62344; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12345; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v32346; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v52347; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 162348; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 162349; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 162350; GFX6-NEXT: s_setpc_b64 s[30:31]2351;2352; GFX8-LABEL: v_usubsat_v6i16:2353; GFX8: ; %bb.0:2354; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2355; GFX8-NEXT: v_sub_u16_e64 v6, v0, v3 clamp2356; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12357; GFX8-NEXT: v_sub_u16_e64 v3, v1, v4 clamp2358; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12359; GFX8-NEXT: v_sub_u16_e64 v4, v2, v5 clamp2360; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12361; GFX8-NEXT: v_or_b32_e32 v0, v6, v02362; GFX8-NEXT: v_or_b32_e32 v1, v3, v12363; GFX8-NEXT: v_or_b32_e32 v2, v4, v22364; GFX8-NEXT: s_setpc_b64 s[30:31]2365;2366; GFX9-LABEL: v_usubsat_v6i16:2367; GFX9: ; %bb.0:2368; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2369; GFX9-NEXT: v_pk_sub_u16 v0, v0, v3 clamp2370; GFX9-NEXT: v_pk_sub_u16 v1, v1, v4 clamp2371; GFX9-NEXT: v_pk_sub_u16 v2, v2, v5 clamp2372; GFX9-NEXT: s_setpc_b64 s[30:31]2373;2374; GFX10PLUS-LABEL: v_usubsat_v6i16:2375; GFX10PLUS: ; %bb.0:2376; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2377; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v3 clamp2378; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v4 clamp2379; GFX10PLUS-NEXT: v_pk_sub_u16 v2, v2, v5 clamp2380; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2381 %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)2382 %cast = bitcast <6 x i16> %result to <3 x float>2383 ret <3 x float> %cast2384}2385 2386define amdgpu_ps <3 x i32> @s_usubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {2387; GFX6-LABEL: s_usubsat_v6i16:2388; GFX6: ; %bb.0:2389; GFX6-NEXT: s_lshl_b32 s0, s0, 162390; GFX6-NEXT: s_lshl_b32 s6, s6, 162391; GFX6-NEXT: s_min_u32 s6, s0, s62392; GFX6-NEXT: s_sub_i32 s0, s0, s62393; GFX6-NEXT: s_lshl_b32 s1, s1, 162394; GFX6-NEXT: s_lshl_b32 s6, s7, 162395; GFX6-NEXT: s_min_u32 s6, s1, s62396; GFX6-NEXT: s_sub_i32 s1, s1, s62397; GFX6-NEXT: s_lshl_b32 s2, s2, 162398; GFX6-NEXT: s_lshl_b32 s6, s8, 162399; GFX6-NEXT: s_min_u32 s6, s2, s62400; GFX6-NEXT: s_sub_i32 s2, s2, s62401; GFX6-NEXT: s_lshl_b32 s3, s3, 162402; GFX6-NEXT: s_lshl_b32 s6, s9, 162403; GFX6-NEXT: s_min_u32 s6, s3, s62404; GFX6-NEXT: s_sub_i32 s3, s3, s62405; GFX6-NEXT: s_lshl_b32 s4, s4, 162406; GFX6-NEXT: s_lshl_b32 s6, s10, 162407; GFX6-NEXT: s_min_u32 s6, s4, s62408; GFX6-NEXT: s_sub_i32 s4, s4, s62409; GFX6-NEXT: s_lshl_b32 s5, s5, 162410; GFX6-NEXT: s_lshl_b32 s6, s11, 162411; GFX6-NEXT: s_min_u32 s6, s5, s62412; GFX6-NEXT: s_sub_i32 s5, s5, s62413; GFX6-NEXT: s_lshr_b32 s1, s1, 162414; GFX6-NEXT: s_lshr_b32 s3, s3, 162415; GFX6-NEXT: s_lshr_b32 s5, s5, 162416; GFX6-NEXT: v_mov_b32_e32 v0, s02417; GFX6-NEXT: v_mov_b32_e32 v1, s22418; GFX6-NEXT: v_mov_b32_e32 v2, s42419; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 162420; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 162421; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 162422; GFX6-NEXT: v_readfirstlane_b32 s0, v02423; GFX6-NEXT: v_readfirstlane_b32 s1, v12424; GFX6-NEXT: v_readfirstlane_b32 s2, v22425; GFX6-NEXT: ; return to shader part epilog2426;2427; GFX8-LABEL: s_usubsat_v6i16:2428; GFX8: ; %bb.0:2429; GFX8-NEXT: s_lshr_b32 s6, s0, 162430; GFX8-NEXT: s_lshr_b32 s7, s1, 162431; GFX8-NEXT: s_lshr_b32 s9, s3, 162432; GFX8-NEXT: s_lshr_b32 s10, s4, 162433; GFX8-NEXT: s_lshr_b32 s8, s2, 162434; GFX8-NEXT: s_lshr_b32 s11, s5, 162435; GFX8-NEXT: v_mov_b32_e32 v1, s92436; GFX8-NEXT: v_mov_b32_e32 v2, s62437; GFX8-NEXT: v_mov_b32_e32 v3, s102438; GFX8-NEXT: v_mov_b32_e32 v4, s72439; GFX8-NEXT: v_mov_b32_e32 v0, s32440; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2441; GFX8-NEXT: v_mov_b32_e32 v2, s42442; GFX8-NEXT: v_sub_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2443; GFX8-NEXT: v_mov_b32_e32 v4, s52444; GFX8-NEXT: v_mov_b32_e32 v5, s112445; GFX8-NEXT: v_mov_b32_e32 v6, s82446; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp2447; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp2448; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp2449; GFX8-NEXT: v_sub_u16_sdwa v5, v6, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2450; GFX8-NEXT: v_or_b32_e32 v0, v0, v12451; GFX8-NEXT: v_or_b32_e32 v1, v2, v32452; GFX8-NEXT: v_or_b32_e32 v2, v4, v52453; GFX8-NEXT: v_readfirstlane_b32 s0, v02454; GFX8-NEXT: v_readfirstlane_b32 s1, v12455; GFX8-NEXT: v_readfirstlane_b32 s2, v22456; GFX8-NEXT: ; return to shader part epilog2457;2458; GFX9-LABEL: s_usubsat_v6i16:2459; GFX9: ; %bb.0:2460; GFX9-NEXT: v_mov_b32_e32 v0, s32461; GFX9-NEXT: v_mov_b32_e32 v1, s42462; GFX9-NEXT: v_mov_b32_e32 v2, s52463; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2464; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp2465; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp2466; GFX9-NEXT: v_readfirstlane_b32 s0, v02467; GFX9-NEXT: v_readfirstlane_b32 s1, v12468; GFX9-NEXT: v_readfirstlane_b32 s2, v22469; GFX9-NEXT: ; return to shader part epilog2470;2471; GFX10PLUS-LABEL: s_usubsat_v6i16:2472; GFX10PLUS: ; %bb.0:2473; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s3 clamp2474; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s4 clamp2475; GFX10PLUS-NEXT: v_pk_sub_u16 v2, s2, s5 clamp2476; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02477; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v12478; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v22479; GFX10PLUS-NEXT: ; return to shader part epilog2480 %result = call <6 x i16> @llvm.usub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)2481 %cast = bitcast <6 x i16> %result to <3 x i32>2482 ret <3 x i32> %cast2483}2484 2485define <4 x float> @v_usubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {2486; GFX6-LABEL: v_usubsat_v8i16:2487; GFX6: ; %bb.0:2488; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2489; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v02490; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v82491; GFX6-NEXT: v_min_u32_e32 v8, v0, v82492; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v82493; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v12494; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v92495; GFX6-NEXT: v_min_u32_e32 v8, v1, v82496; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v82497; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v22498; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v102499; GFX6-NEXT: v_min_u32_e32 v8, v2, v82500; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v82501; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32502; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v112503; GFX6-NEXT: v_min_u32_e32 v8, v3, v82504; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v82505; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v42506; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v122507; GFX6-NEXT: v_min_u32_e32 v8, v4, v82508; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v82509; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v52510; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v132511; GFX6-NEXT: v_min_u32_e32 v8, v5, v82512; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v82513; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v62514; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v142515; GFX6-NEXT: v_min_u32_e32 v8, v6, v82516; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v82517; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v72518; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v152519; GFX6-NEXT: v_min_u32_e32 v8, v7, v82520; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v82521; GFX6-NEXT: v_lshrrev_b32_e32 v1, 16, v12522; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v32523; GFX6-NEXT: v_lshrrev_b32_e32 v5, 16, v52524; GFX6-NEXT: v_lshrrev_b32_e32 v7, 16, v72525; GFX6-NEXT: v_alignbit_b32 v0, v1, v0, 162526; GFX6-NEXT: v_alignbit_b32 v1, v3, v2, 162527; GFX6-NEXT: v_alignbit_b32 v2, v5, v4, 162528; GFX6-NEXT: v_alignbit_b32 v3, v7, v6, 162529; GFX6-NEXT: s_setpc_b64 s[30:31]2530;2531; GFX8-LABEL: v_usubsat_v8i16:2532; GFX8: ; %bb.0:2533; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2534; GFX8-NEXT: v_sub_u16_e64 v8, v0, v4 clamp2535; GFX8-NEXT: v_sub_u16_sdwa v0, v0, v4 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12536; GFX8-NEXT: v_sub_u16_e64 v4, v1, v5 clamp2537; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12538; GFX8-NEXT: v_sub_u16_e64 v5, v2, v6 clamp2539; GFX8-NEXT: v_sub_u16_sdwa v2, v2, v6 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12540; GFX8-NEXT: v_sub_u16_e64 v6, v3, v7 clamp2541; GFX8-NEXT: v_sub_u16_sdwa v3, v3, v7 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_12542; GFX8-NEXT: v_or_b32_e32 v0, v8, v02543; GFX8-NEXT: v_or_b32_e32 v1, v4, v12544; GFX8-NEXT: v_or_b32_e32 v2, v5, v22545; GFX8-NEXT: v_or_b32_e32 v3, v6, v32546; GFX8-NEXT: s_setpc_b64 s[30:31]2547;2548; GFX9-LABEL: v_usubsat_v8i16:2549; GFX9: ; %bb.0:2550; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2551; GFX9-NEXT: v_pk_sub_u16 v0, v0, v4 clamp2552; GFX9-NEXT: v_pk_sub_u16 v1, v1, v5 clamp2553; GFX9-NEXT: v_pk_sub_u16 v2, v2, v6 clamp2554; GFX9-NEXT: v_pk_sub_u16 v3, v3, v7 clamp2555; GFX9-NEXT: s_setpc_b64 s[30:31]2556;2557; GFX10PLUS-LABEL: v_usubsat_v8i16:2558; GFX10PLUS: ; %bb.0:2559; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2560; GFX10PLUS-NEXT: v_pk_sub_u16 v0, v0, v4 clamp2561; GFX10PLUS-NEXT: v_pk_sub_u16 v1, v1, v5 clamp2562; GFX10PLUS-NEXT: v_pk_sub_u16 v2, v2, v6 clamp2563; GFX10PLUS-NEXT: v_pk_sub_u16 v3, v3, v7 clamp2564; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2565 %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)2566 %cast = bitcast <8 x i16> %result to <4 x float>2567 ret <4 x float> %cast2568}2569 2570define amdgpu_ps <4 x i32> @s_usubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {2571; GFX6-LABEL: s_usubsat_v8i16:2572; GFX6: ; %bb.0:2573; GFX6-NEXT: s_lshl_b32 s0, s0, 162574; GFX6-NEXT: s_lshl_b32 s8, s8, 162575; GFX6-NEXT: s_min_u32 s8, s0, s82576; GFX6-NEXT: s_sub_i32 s0, s0, s82577; GFX6-NEXT: s_lshl_b32 s1, s1, 162578; GFX6-NEXT: s_lshl_b32 s8, s9, 162579; GFX6-NEXT: s_min_u32 s8, s1, s82580; GFX6-NEXT: s_sub_i32 s1, s1, s82581; GFX6-NEXT: s_lshl_b32 s2, s2, 162582; GFX6-NEXT: s_lshl_b32 s8, s10, 162583; GFX6-NEXT: s_min_u32 s8, s2, s82584; GFX6-NEXT: s_sub_i32 s2, s2, s82585; GFX6-NEXT: s_lshl_b32 s3, s3, 162586; GFX6-NEXT: s_lshl_b32 s8, s11, 162587; GFX6-NEXT: s_min_u32 s8, s3, s82588; GFX6-NEXT: s_sub_i32 s3, s3, s82589; GFX6-NEXT: s_lshl_b32 s4, s4, 162590; GFX6-NEXT: s_lshl_b32 s8, s12, 162591; GFX6-NEXT: s_min_u32 s8, s4, s82592; GFX6-NEXT: s_sub_i32 s4, s4, s82593; GFX6-NEXT: s_lshl_b32 s5, s5, 162594; GFX6-NEXT: s_lshl_b32 s8, s13, 162595; GFX6-NEXT: s_min_u32 s8, s5, s82596; GFX6-NEXT: s_sub_i32 s5, s5, s82597; GFX6-NEXT: s_lshl_b32 s6, s6, 162598; GFX6-NEXT: s_lshl_b32 s8, s14, 162599; GFX6-NEXT: s_min_u32 s8, s6, s82600; GFX6-NEXT: s_sub_i32 s6, s6, s82601; GFX6-NEXT: s_lshl_b32 s7, s7, 162602; GFX6-NEXT: s_lshl_b32 s8, s15, 162603; GFX6-NEXT: s_min_u32 s8, s7, s82604; GFX6-NEXT: s_sub_i32 s7, s7, s82605; GFX6-NEXT: s_lshr_b32 s1, s1, 162606; GFX6-NEXT: s_lshr_b32 s3, s3, 162607; GFX6-NEXT: s_lshr_b32 s5, s5, 162608; GFX6-NEXT: s_lshr_b32 s7, s7, 162609; GFX6-NEXT: v_mov_b32_e32 v0, s02610; GFX6-NEXT: v_mov_b32_e32 v1, s22611; GFX6-NEXT: v_mov_b32_e32 v2, s42612; GFX6-NEXT: v_mov_b32_e32 v3, s62613; GFX6-NEXT: v_alignbit_b32 v0, s1, v0, 162614; GFX6-NEXT: v_alignbit_b32 v1, s3, v1, 162615; GFX6-NEXT: v_alignbit_b32 v2, s5, v2, 162616; GFX6-NEXT: v_alignbit_b32 v3, s7, v3, 162617; GFX6-NEXT: v_readfirstlane_b32 s0, v02618; GFX6-NEXT: v_readfirstlane_b32 s1, v12619; GFX6-NEXT: v_readfirstlane_b32 s2, v22620; GFX6-NEXT: v_readfirstlane_b32 s3, v32621; GFX6-NEXT: ; return to shader part epilog2622;2623; GFX8-LABEL: s_usubsat_v8i16:2624; GFX8: ; %bb.0:2625; GFX8-NEXT: s_lshr_b32 s8, s0, 162626; GFX8-NEXT: s_lshr_b32 s9, s1, 162627; GFX8-NEXT: s_lshr_b32 s10, s2, 162628; GFX8-NEXT: s_lshr_b32 s12, s4, 162629; GFX8-NEXT: s_lshr_b32 s13, s5, 162630; GFX8-NEXT: s_lshr_b32 s14, s6, 162631; GFX8-NEXT: s_lshr_b32 s11, s3, 162632; GFX8-NEXT: s_lshr_b32 s15, s7, 162633; GFX8-NEXT: v_mov_b32_e32 v1, s122634; GFX8-NEXT: v_mov_b32_e32 v2, s82635; GFX8-NEXT: v_mov_b32_e32 v3, s132636; GFX8-NEXT: v_mov_b32_e32 v4, s92637; GFX8-NEXT: v_mov_b32_e32 v5, s142638; GFX8-NEXT: v_mov_b32_e32 v6, s102639; GFX8-NEXT: v_mov_b32_e32 v0, s42640; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2641; GFX8-NEXT: v_mov_b32_e32 v2, s52642; GFX8-NEXT: v_sub_u16_sdwa v3, v4, v3 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2643; GFX8-NEXT: v_mov_b32_e32 v4, s62644; GFX8-NEXT: v_sub_u16_sdwa v5, v6, v5 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2645; GFX8-NEXT: v_mov_b32_e32 v6, s72646; GFX8-NEXT: v_mov_b32_e32 v7, s152647; GFX8-NEXT: v_mov_b32_e32 v8, s112648; GFX8-NEXT: v_sub_u16_e64 v0, s0, v0 clamp2649; GFX8-NEXT: v_sub_u16_e64 v2, s1, v2 clamp2650; GFX8-NEXT: v_sub_u16_e64 v4, s2, v4 clamp2651; GFX8-NEXT: v_sub_u16_e64 v6, s3, v6 clamp2652; GFX8-NEXT: v_sub_u16_sdwa v7, v8, v7 clamp dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2653; GFX8-NEXT: v_or_b32_e32 v0, v0, v12654; GFX8-NEXT: v_or_b32_e32 v1, v2, v32655; GFX8-NEXT: v_or_b32_e32 v2, v4, v52656; GFX8-NEXT: v_or_b32_e32 v3, v6, v72657; GFX8-NEXT: v_readfirstlane_b32 s0, v02658; GFX8-NEXT: v_readfirstlane_b32 s1, v12659; GFX8-NEXT: v_readfirstlane_b32 s2, v22660; GFX8-NEXT: v_readfirstlane_b32 s3, v32661; GFX8-NEXT: ; return to shader part epilog2662;2663; GFX9-LABEL: s_usubsat_v8i16:2664; GFX9: ; %bb.0:2665; GFX9-NEXT: v_mov_b32_e32 v0, s42666; GFX9-NEXT: v_mov_b32_e32 v1, s52667; GFX9-NEXT: v_mov_b32_e32 v2, s62668; GFX9-NEXT: v_mov_b32_e32 v3, s72669; GFX9-NEXT: v_pk_sub_u16 v0, s0, v0 clamp2670; GFX9-NEXT: v_pk_sub_u16 v1, s1, v1 clamp2671; GFX9-NEXT: v_pk_sub_u16 v2, s2, v2 clamp2672; GFX9-NEXT: v_pk_sub_u16 v3, s3, v3 clamp2673; GFX9-NEXT: v_readfirstlane_b32 s0, v02674; GFX9-NEXT: v_readfirstlane_b32 s1, v12675; GFX9-NEXT: v_readfirstlane_b32 s2, v22676; GFX9-NEXT: v_readfirstlane_b32 s3, v32677; GFX9-NEXT: ; return to shader part epilog2678;2679; GFX10PLUS-LABEL: s_usubsat_v8i16:2680; GFX10PLUS: ; %bb.0:2681; GFX10PLUS-NEXT: v_pk_sub_u16 v0, s0, s4 clamp2682; GFX10PLUS-NEXT: v_pk_sub_u16 v1, s1, s5 clamp2683; GFX10PLUS-NEXT: v_pk_sub_u16 v2, s2, s6 clamp2684; GFX10PLUS-NEXT: v_pk_sub_u16 v3, s3, s7 clamp2685; GFX10PLUS-NEXT: v_readfirstlane_b32 s0, v02686; GFX10PLUS-NEXT: v_readfirstlane_b32 s1, v12687; GFX10PLUS-NEXT: v_readfirstlane_b32 s2, v22688; GFX10PLUS-NEXT: v_readfirstlane_b32 s3, v32689; GFX10PLUS-NEXT: ; return to shader part epilog2690 %result = call <8 x i16> @llvm.usub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)2691 %cast = bitcast <8 x i16> %result to <4 x i32>2692 ret <4 x i32> %cast2693}2694 2695define i48 @v_usubsat_i48(i48 %lhs, i48 %rhs) {2696; GFX6-LABEL: v_usubsat_i48:2697; GFX6: ; %bb.0:2698; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2699; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12700; GFX6-NEXT: v_and_b32_e32 v3, 0xffff, v32701; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22702; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2703; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v02704; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v12705; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02706; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32707; GFX6-NEXT: v_or_b32_e32 v0, v0, v32708; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v22709; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2710; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc2711; GFX6-NEXT: s_setpc_b64 s[30:31]2712;2713; GFX8-LABEL: v_usubsat_i48:2714; GFX8: ; %bb.0:2715; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2716; GFX8-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2717; GFX8-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]2718; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v22719; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2720; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2721; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2722; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2723; GFX8-NEXT: s_setpc_b64 s[30:31]2724;2725; GFX9-LABEL: v_usubsat_i48:2726; GFX9: ; %bb.0:2727; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2728; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2729; GFX9-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]2730; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v22731; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc2732; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2733; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2734; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2735; GFX9-NEXT: s_setpc_b64 s[30:31]2736;2737; GFX10PLUS-LABEL: v_usubsat_i48:2738; GFX10PLUS: ; %bb.0:2739; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2740; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2741; GFX10PLUS-NEXT: v_lshlrev_b64 v[2:3], 16, v[2:3]2742; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v22743; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo2744; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo2745; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo2746; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2747; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2748 %result = call i48 @llvm.usub.sat.i48(i48 %lhs, i48 %rhs)2749 ret i48 %result2750}2751 2752define amdgpu_ps i48 @s_usubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {2753; GFX6-LABEL: s_usubsat_i48:2754; GFX6: ; %bb.0:2755; GFX6-NEXT: s_sub_u32 s0, s0, s22756; GFX6-NEXT: s_cselect_b32 s2, 1, 02757; GFX6-NEXT: s_and_b32 s1, s1, 0xffff2758; GFX6-NEXT: s_and_b32 s3, s3, 0xffff2759; GFX6-NEXT: s_cmp_lg_u32 s2, 02760; GFX6-NEXT: s_subb_u32 s2, s1, s32761; GFX6-NEXT: s_and_b32 s1, s2, 0xffff2762; GFX6-NEXT: s_cmp_lg_u32 s2, s12763; GFX6-NEXT: s_cselect_b32 s2, 1, 02764; GFX6-NEXT: s_lshr_b32 s3, s0, 162765; GFX6-NEXT: s_and_b32 s0, s0, 0xffff2766; GFX6-NEXT: s_lshl_b32 s3, s3, 162767; GFX6-NEXT: s_or_b32 s0, s0, s32768; GFX6-NEXT: s_cmp_lg_u32 s2, 02769; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2770; GFX6-NEXT: ; return to shader part epilog2771;2772; GFX8-LABEL: s_usubsat_i48:2773; GFX8: ; %bb.0:2774; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 162775; GFX8-NEXT: s_lshl_b64 s[2:3], s[2:3], 162776; GFX8-NEXT: s_sub_u32 s0, s0, s22777; GFX8-NEXT: s_subb_u32 s1, s1, s32778; GFX8-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2779; GFX8-NEXT: s_lshr_b64 s[0:1], s[0:1], 162780; GFX8-NEXT: ; return to shader part epilog2781;2782; GFX9-LABEL: s_usubsat_i48:2783; GFX9: ; %bb.0:2784; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 162785; GFX9-NEXT: s_lshl_b64 s[2:3], s[2:3], 162786; GFX9-NEXT: s_sub_u32 s0, s0, s22787; GFX9-NEXT: s_subb_u32 s1, s1, s32788; GFX9-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2789; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 162790; GFX9-NEXT: ; return to shader part epilog2791;2792; GFX10PLUS-LABEL: s_usubsat_i48:2793; GFX10PLUS: ; %bb.0:2794; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 162795; GFX10PLUS-NEXT: s_lshl_b64 s[2:3], s[2:3], 162796; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s22797; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s32798; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2799; GFX10PLUS-NEXT: s_lshr_b64 s[0:1], s[0:1], 162800; GFX10PLUS-NEXT: ; return to shader part epilog2801 %result = call i48 @llvm.usub.sat.i48(i48 %lhs, i48 %rhs)2802 ret i48 %result2803}2804 2805define amdgpu_ps <2 x float> @usubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {2806; GFX6-LABEL: usubsat_i48_sv:2807; GFX6: ; %bb.0:2808; GFX6-NEXT: s_and_b32 s1, s1, 0xffff2809; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12810; GFX6-NEXT: v_mov_b32_e32 v2, s12811; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v02812; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc2813; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v02814; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v12815; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02816; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32817; GFX6-NEXT: v_or_b32_e32 v0, v0, v32818; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v22819; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2820; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc2821; GFX6-NEXT: ; return to shader part epilog2822;2823; GFX8-LABEL: usubsat_i48_sv:2824; GFX8: ; %bb.0:2825; GFX8-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2826; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 162827; GFX8-NEXT: v_mov_b32_e32 v2, s12828; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v02829; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc2830; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2831; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2832; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2833; GFX8-NEXT: ; return to shader part epilog2834;2835; GFX9-LABEL: usubsat_i48_sv:2836; GFX9: ; %bb.0:2837; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2838; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 162839; GFX9-NEXT: v_mov_b32_e32 v2, s12840; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v02841; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc2842; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2843; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2844; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2845; GFX9-NEXT: ; return to shader part epilog2846;2847; GFX10PLUS-LABEL: usubsat_i48_sv:2848; GFX10PLUS: ; %bb.0:2849; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2850; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 162851; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v02852; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo2853; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo2854; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo2855; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2856; GFX10PLUS-NEXT: ; return to shader part epilog2857 %result = call i48 @llvm.usub.sat.i48(i48 %lhs, i48 %rhs)2858 %ext.result = zext i48 %result to i642859 %cast = bitcast i64 %ext.result to <2 x float>2860 ret <2 x float> %cast2861}2862 2863define amdgpu_ps <2 x float> @usubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {2864; GFX6-LABEL: usubsat_i48_vs:2865; GFX6: ; %bb.0:2866; GFX6-NEXT: s_and_b32 s1, s1, 0xffff2867; GFX6-NEXT: v_and_b32_e32 v1, 0xffff, v12868; GFX6-NEXT: v_mov_b32_e32 v2, s12869; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v02870; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc2871; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v02872; GFX6-NEXT: v_and_b32_e32 v2, 0xffff, v12873; GFX6-NEXT: v_and_b32_e32 v0, 0xffff, v02874; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v32875; GFX6-NEXT: v_or_b32_e32 v0, v0, v32876; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, v1, v22877; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2878; GFX6-NEXT: v_cndmask_b32_e64 v1, v2, 0, vcc2879; GFX6-NEXT: ; return to shader part epilog2880;2881; GFX8-LABEL: usubsat_i48_vs:2882; GFX8: ; %bb.0:2883; GFX8-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2884; GFX8-NEXT: s_lshl_b64 s[0:1], s[0:1], 162885; GFX8-NEXT: v_mov_b32_e32 v2, s12886; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v02887; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc2888; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2889; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2890; GFX8-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2891; GFX8-NEXT: ; return to shader part epilog2892;2893; GFX9-LABEL: usubsat_i48_vs:2894; GFX9: ; %bb.0:2895; GFX9-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2896; GFX9-NEXT: s_lshl_b64 s[0:1], s[0:1], 162897; GFX9-NEXT: v_mov_b32_e32 v2, s12898; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v02899; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc2900; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2901; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2902; GFX9-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2903; GFX9-NEXT: ; return to shader part epilog2904;2905; GFX10PLUS-LABEL: usubsat_i48_vs:2906; GFX10PLUS: ; %bb.0:2907; GFX10PLUS-NEXT: v_lshlrev_b64 v[0:1], 16, v[0:1]2908; GFX10PLUS-NEXT: s_lshl_b64 s[0:1], s[0:1], 162909; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s02910; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo2911; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo2912; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo2913; GFX10PLUS-NEXT: v_lshrrev_b64 v[0:1], 16, v[0:1]2914; GFX10PLUS-NEXT: ; return to shader part epilog2915 %result = call i48 @llvm.usub.sat.i48(i48 %lhs, i48 %rhs)2916 %ext.result = zext i48 %result to i642917 %cast = bitcast i64 %ext.result to <2 x float>2918 ret <2 x float> %cast2919}2920 2921define i64 @v_usubsat_i64(i64 %lhs, i64 %rhs) {2922; GFX6-LABEL: v_usubsat_i64:2923; GFX6: ; %bb.0:2924; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2925; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v22926; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2927; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2928; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2929; GFX6-NEXT: s_setpc_b64 s[30:31]2930;2931; GFX8-LABEL: v_usubsat_i64:2932; GFX8: ; %bb.0:2933; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2934; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v22935; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v3, vcc2936; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2937; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2938; GFX8-NEXT: s_setpc_b64 s[30:31]2939;2940; GFX9-LABEL: v_usubsat_i64:2941; GFX9: ; %bb.0:2942; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2943; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v22944; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc2945; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc2946; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc2947; GFX9-NEXT: s_setpc_b64 s[30:31]2948;2949; GFX10PLUS-LABEL: v_usubsat_i64:2950; GFX10PLUS: ; %bb.0:2951; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2952; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v22953; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v3, vcc_lo2954; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo2955; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo2956; GFX10PLUS-NEXT: s_setpc_b64 s[30:31]2957 %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)2958 ret i64 %result2959}2960 2961define amdgpu_ps i64 @s_usubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {2962; GFX6-LABEL: s_usubsat_i64:2963; GFX6: ; %bb.0:2964; GFX6-NEXT: s_sub_u32 s0, s0, s22965; GFX6-NEXT: s_subb_u32 s1, s1, s32966; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2967; GFX6-NEXT: ; return to shader part epilog2968;2969; GFX8-LABEL: s_usubsat_i64:2970; GFX8: ; %bb.0:2971; GFX8-NEXT: s_sub_u32 s0, s0, s22972; GFX8-NEXT: s_subb_u32 s1, s1, s32973; GFX8-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2974; GFX8-NEXT: ; return to shader part epilog2975;2976; GFX9-LABEL: s_usubsat_i64:2977; GFX9: ; %bb.0:2978; GFX9-NEXT: s_sub_u32 s0, s0, s22979; GFX9-NEXT: s_subb_u32 s1, s1, s32980; GFX9-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2981; GFX9-NEXT: ; return to shader part epilog2982;2983; GFX10PLUS-LABEL: s_usubsat_i64:2984; GFX10PLUS: ; %bb.0:2985; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s22986; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s32987; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]2988; GFX10PLUS-NEXT: ; return to shader part epilog2989 %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)2990 ret i64 %result2991}2992 2993define amdgpu_ps <2 x float> @usubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {2994; GFX6-LABEL: usubsat_i64_sv:2995; GFX6: ; %bb.0:2996; GFX6-NEXT: v_mov_b32_e32 v2, s12997; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v02998; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc2999; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3000; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3001; GFX6-NEXT: ; return to shader part epilog3002;3003; GFX8-LABEL: usubsat_i64_sv:3004; GFX8: ; %bb.0:3005; GFX8-NEXT: v_mov_b32_e32 v2, s13006; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v03007; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v2, v1, vcc3008; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3009; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3010; GFX8-NEXT: ; return to shader part epilog3011;3012; GFX9-LABEL: usubsat_i64_sv:3013; GFX9: ; %bb.0:3014; GFX9-NEXT: v_mov_b32_e32 v2, s13015; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v03016; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v2, v1, vcc3017; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3018; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3019; GFX9-NEXT: ; return to shader part epilog3020;3021; GFX10PLUS-LABEL: usubsat_i64_sv:3022; GFX10PLUS: ; %bb.0:3023; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v03024; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3025; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3026; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3027; GFX10PLUS-NEXT: ; return to shader part epilog3028 %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)3029 %cast = bitcast i64 %result to <2 x float>3030 ret <2 x float> %cast3031}3032 3033define amdgpu_ps <2 x float> @usubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {3034; GFX6-LABEL: usubsat_i64_vs:3035; GFX6: ; %bb.0:3036; GFX6-NEXT: v_mov_b32_e32 v2, s13037; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v03038; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc3039; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3040; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3041; GFX6-NEXT: ; return to shader part epilog3042;3043; GFX8-LABEL: usubsat_i64_vs:3044; GFX8: ; %bb.0:3045; GFX8-NEXT: v_mov_b32_e32 v2, s13046; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v03047; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v2, vcc3048; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3049; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3050; GFX8-NEXT: ; return to shader part epilog3051;3052; GFX9-LABEL: usubsat_i64_vs:3053; GFX9: ; %bb.0:3054; GFX9-NEXT: v_mov_b32_e32 v2, s13055; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v03056; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v2, vcc3057; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3058; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3059; GFX9-NEXT: ; return to shader part epilog3060;3061; GFX10PLUS-LABEL: usubsat_i64_vs:3062; GFX10PLUS: ; %bb.0:3063; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s03064; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3065; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3066; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3067; GFX10PLUS-NEXT: ; return to shader part epilog3068 %result = call i64 @llvm.usub.sat.i64(i64 %lhs, i64 %rhs)3069 %cast = bitcast i64 %result to <2 x float>3070 ret <2 x float> %cast3071}3072 3073define <2 x i64> @v_usubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {3074; GFX6-LABEL: v_usubsat_v2i64:3075; GFX6: ; %bb.0:3076; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3077; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v43078; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc3079; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3080; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3081; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v63082; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc3083; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3084; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3085; GFX6-NEXT: s_setpc_b64 s[30:31]3086;3087; GFX8-LABEL: v_usubsat_v2i64:3088; GFX8: ; %bb.0:3089; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3090; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v43091; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v5, vcc3092; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3093; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3094; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v63095; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc3096; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3097; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3098; GFX8-NEXT: s_setpc_b64 s[30:31]3099;3100; GFX9-LABEL: v_usubsat_v2i64:3101; GFX9: ; %bb.0:3102; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3103; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v43104; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v5, vcc3105; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3106; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3107; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, v2, v63108; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v7, vcc3109; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3110; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3111; GFX9-NEXT: s_setpc_b64 s[30:31]3112;3113; GFX10-LABEL: v_usubsat_v2i64:3114; GFX10: ; %bb.0:3115; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3116; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v43117; GFX10-NEXT: v_sub_co_u32 v2, s4, v2, v63118; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo3119; GFX10-NEXT: v_sub_co_ci_u32_e64 v3, s4, v3, v7, s43120; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3121; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3122; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, s43123; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0, s43124; GFX10-NEXT: s_setpc_b64 s[30:31]3125;3126; GFX11-LABEL: v_usubsat_v2i64:3127; GFX11: ; %bb.0:3128; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3129; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v43130; GFX11-NEXT: v_sub_co_u32 v2, s0, v2, v63131; GFX11-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v5, vcc_lo3132; GFX11-NEXT: v_sub_co_ci_u32_e64 v3, s0, v3, v7, s03133; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3134; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3135; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, s03136; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, s03137; GFX11-NEXT: s_setpc_b64 s[30:31]3138 %result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)3139 ret <2 x i64> %result3140}3141 3142define amdgpu_ps <2 x i64> @s_usubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {3143; GFX6-LABEL: s_usubsat_v2i64:3144; GFX6: ; %bb.0:3145; GFX6-NEXT: s_sub_u32 s0, s0, s43146; GFX6-NEXT: s_subb_u32 s1, s1, s53147; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3148; GFX6-NEXT: s_sub_u32 s2, s2, s63149; GFX6-NEXT: s_subb_u32 s3, s3, s73150; GFX6-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3151; GFX6-NEXT: ; return to shader part epilog3152;3153; GFX8-LABEL: s_usubsat_v2i64:3154; GFX8: ; %bb.0:3155; GFX8-NEXT: s_sub_u32 s0, s0, s43156; GFX8-NEXT: s_subb_u32 s1, s1, s53157; GFX8-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3158; GFX8-NEXT: s_sub_u32 s2, s2, s63159; GFX8-NEXT: s_subb_u32 s3, s3, s73160; GFX8-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3161; GFX8-NEXT: ; return to shader part epilog3162;3163; GFX9-LABEL: s_usubsat_v2i64:3164; GFX9: ; %bb.0:3165; GFX9-NEXT: s_sub_u32 s0, s0, s43166; GFX9-NEXT: s_subb_u32 s1, s1, s53167; GFX9-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3168; GFX9-NEXT: s_sub_u32 s2, s2, s63169; GFX9-NEXT: s_subb_u32 s3, s3, s73170; GFX9-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3171; GFX9-NEXT: ; return to shader part epilog3172;3173; GFX10PLUS-LABEL: s_usubsat_v2i64:3174; GFX10PLUS: ; %bb.0:3175; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s43176; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s53177; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3178; GFX10PLUS-NEXT: s_sub_u32 s2, s2, s63179; GFX10PLUS-NEXT: s_subb_u32 s3, s3, s73180; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3181; GFX10PLUS-NEXT: ; return to shader part epilog3182 %result = call <2 x i64> @llvm.usub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)3183 ret <2 x i64> %result3184}3185 3186define amdgpu_ps i128 @s_usubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {3187; GFX6-LABEL: s_usubsat_i128:3188; GFX6: ; %bb.0:3189; GFX6-NEXT: s_sub_u32 s0, s0, s43190; GFX6-NEXT: s_subb_u32 s1, s1, s53191; GFX6-NEXT: s_subb_u32 s2, s2, s63192; GFX6-NEXT: s_subb_u32 s3, s3, s73193; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3194; GFX6-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3195; GFX6-NEXT: ; return to shader part epilog3196;3197; GFX8-LABEL: s_usubsat_i128:3198; GFX8: ; %bb.0:3199; GFX8-NEXT: s_sub_u32 s0, s0, s43200; GFX8-NEXT: s_subb_u32 s1, s1, s53201; GFX8-NEXT: s_subb_u32 s2, s2, s63202; GFX8-NEXT: s_subb_u32 s3, s3, s73203; GFX8-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3204; GFX8-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3205; GFX8-NEXT: ; return to shader part epilog3206;3207; GFX9-LABEL: s_usubsat_i128:3208; GFX9: ; %bb.0:3209; GFX9-NEXT: s_sub_u32 s0, s0, s43210; GFX9-NEXT: s_subb_u32 s1, s1, s53211; GFX9-NEXT: s_subb_u32 s2, s2, s63212; GFX9-NEXT: s_subb_u32 s3, s3, s73213; GFX9-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3214; GFX9-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3215; GFX9-NEXT: ; return to shader part epilog3216;3217; GFX10PLUS-LABEL: s_usubsat_i128:3218; GFX10PLUS: ; %bb.0:3219; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s43220; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s53221; GFX10PLUS-NEXT: s_subb_u32 s2, s2, s63222; GFX10PLUS-NEXT: s_subb_u32 s3, s3, s73223; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3224; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3225; GFX10PLUS-NEXT: ; return to shader part epilog3226 %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)3227 ret i128 %result3228}3229 3230define amdgpu_ps <4 x float> @usubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {3231; GFX6-LABEL: usubsat_i128_sv:3232; GFX6: ; %bb.0:3233; GFX6-NEXT: v_mov_b32_e32 v4, s13234; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v03235; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc3236; GFX6-NEXT: v_mov_b32_e32 v4, s23237; GFX6-NEXT: v_mov_b32_e32 v5, s33238; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc3239; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc3240; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3241; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3242; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3243; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3244; GFX6-NEXT: ; return to shader part epilog3245;3246; GFX8-LABEL: usubsat_i128_sv:3247; GFX8: ; %bb.0:3248; GFX8-NEXT: v_mov_b32_e32 v4, s13249; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v03250; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v4, v1, vcc3251; GFX8-NEXT: v_mov_b32_e32 v4, s23252; GFX8-NEXT: v_mov_b32_e32 v5, s33253; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v4, v2, vcc3254; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v5, v3, vcc3255; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3256; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3257; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3258; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3259; GFX8-NEXT: ; return to shader part epilog3260;3261; GFX9-LABEL: usubsat_i128_sv:3262; GFX9: ; %bb.0:3263; GFX9-NEXT: v_mov_b32_e32 v4, s13264; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, s0, v03265; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v4, v1, vcc3266; GFX9-NEXT: v_mov_b32_e32 v4, s23267; GFX9-NEXT: v_mov_b32_e32 v5, s33268; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v4, v2, vcc3269; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v5, v3, vcc3270; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3271; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3272; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3273; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3274; GFX9-NEXT: ; return to shader part epilog3275;3276; GFX10PLUS-LABEL: usubsat_i128_sv:3277; GFX10PLUS: ; %bb.0:3278; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, s0, v03279; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3280; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo3281; GFX10PLUS-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo3282; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3283; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3284; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo3285; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo3286; GFX10PLUS-NEXT: ; return to shader part epilog3287 %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)3288 %cast = bitcast i128 %result to <4 x float>3289 ret <4 x float> %cast3290}3291 3292define amdgpu_ps <4 x float> @usubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {3293; GFX6-LABEL: usubsat_i128_vs:3294; GFX6: ; %bb.0:3295; GFX6-NEXT: v_mov_b32_e32 v4, s13296; GFX6-NEXT: v_subrev_i32_e32 v0, vcc, s0, v03297; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc3298; GFX6-NEXT: v_mov_b32_e32 v4, s23299; GFX6-NEXT: v_mov_b32_e32 v5, s33300; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v2, v4, vcc3301; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc3302; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3303; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3304; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3305; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3306; GFX6-NEXT: ; return to shader part epilog3307;3308; GFX8-LABEL: usubsat_i128_vs:3309; GFX8: ; %bb.0:3310; GFX8-NEXT: v_mov_b32_e32 v4, s13311; GFX8-NEXT: v_subrev_u32_e32 v0, vcc, s0, v03312; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v4, vcc3313; GFX8-NEXT: v_mov_b32_e32 v4, s23314; GFX8-NEXT: v_mov_b32_e32 v5, s33315; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v4, vcc3316; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v5, vcc3317; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3318; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3319; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3320; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3321; GFX8-NEXT: ; return to shader part epilog3322;3323; GFX9-LABEL: usubsat_i128_vs:3324; GFX9: ; %bb.0:3325; GFX9-NEXT: v_mov_b32_e32 v4, s13326; GFX9-NEXT: v_subrev_co_u32_e32 v0, vcc, s0, v03327; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v4, vcc3328; GFX9-NEXT: v_mov_b32_e32 v4, s23329; GFX9-NEXT: v_mov_b32_e32 v5, s33330; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc3331; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v5, vcc3332; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3333; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3334; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3335; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3336; GFX9-NEXT: ; return to shader part epilog3337;3338; GFX10PLUS-LABEL: usubsat_i128_vs:3339; GFX10PLUS: ; %bb.0:3340; GFX10PLUS-NEXT: v_sub_co_u32 v0, vcc_lo, v0, s03341; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v1, vcc_lo, s1, v1, vcc_lo3342; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v2, vcc_lo, s2, v2, vcc_lo3343; GFX10PLUS-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s3, v3, vcc_lo3344; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3345; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3346; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo3347; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo3348; GFX10PLUS-NEXT: ; return to shader part epilog3349 %result = call i128 @llvm.usub.sat.i128(i128 %lhs, i128 %rhs)3350 %cast = bitcast i128 %result to <4 x float>3351 ret <4 x float> %cast3352}3353 3354define <2 x i128> @v_usubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {3355; GFX6-LABEL: v_usubsat_v2i128:3356; GFX6: ; %bb.0:3357; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3358; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v83359; GFX6-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc3360; GFX6-NEXT: v_subb_u32_e32 v2, vcc, v2, v10, vcc3361; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v11, vcc3362; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3363; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3364; GFX6-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3365; GFX6-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3366; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v123367; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v5, v13, vcc3368; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v14, vcc3369; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v15, vcc3370; GFX6-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc3371; GFX6-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc3372; GFX6-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc3373; GFX6-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc3374; GFX6-NEXT: s_setpc_b64 s[30:31]3375;3376; GFX8-LABEL: v_usubsat_v2i128:3377; GFX8: ; %bb.0:3378; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3379; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v83380; GFX8-NEXT: v_subb_u32_e32 v1, vcc, v1, v9, vcc3381; GFX8-NEXT: v_subb_u32_e32 v2, vcc, v2, v10, vcc3382; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v11, vcc3383; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3384; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3385; GFX8-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3386; GFX8-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3387; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v123388; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v5, v13, vcc3389; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v14, vcc3390; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v15, vcc3391; GFX8-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc3392; GFX8-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc3393; GFX8-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc3394; GFX8-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc3395; GFX8-NEXT: s_setpc_b64 s[30:31]3396;3397; GFX9-LABEL: v_usubsat_v2i128:3398; GFX9: ; %bb.0:3399; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3400; GFX9-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v83401; GFX9-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v9, vcc3402; GFX9-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v10, vcc3403; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v11, vcc3404; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc3405; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc3406; GFX9-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc3407; GFX9-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc3408; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v4, v123409; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v13, vcc3410; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v14, vcc3411; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v15, vcc3412; GFX9-NEXT: v_cndmask_b32_e64 v4, v4, 0, vcc3413; GFX9-NEXT: v_cndmask_b32_e64 v5, v5, 0, vcc3414; GFX9-NEXT: v_cndmask_b32_e64 v6, v6, 0, vcc3415; GFX9-NEXT: v_cndmask_b32_e64 v7, v7, 0, vcc3416; GFX9-NEXT: s_setpc_b64 s[30:31]3417;3418; GFX10-LABEL: v_usubsat_v2i128:3419; GFX10: ; %bb.0:3420; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3421; GFX10-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v83422; GFX10-NEXT: v_sub_co_u32 v4, s4, v4, v123423; GFX10-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo3424; GFX10-NEXT: v_sub_co_ci_u32_e64 v5, s4, v5, v13, s43425; GFX10-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo3426; GFX10-NEXT: v_sub_co_ci_u32_e64 v6, s4, v6, v14, s43427; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo3428; GFX10-NEXT: v_sub_co_ci_u32_e64 v7, s4, v7, v15, s43429; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3430; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3431; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo3432; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo3433; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, 0, s43434; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, 0, s43435; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, 0, s43436; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, 0, s43437; GFX10-NEXT: s_setpc_b64 s[30:31]3438;3439; GFX11-LABEL: v_usubsat_v2i128:3440; GFX11: ; %bb.0:3441; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3442; GFX11-NEXT: v_sub_co_u32 v0, vcc_lo, v0, v83443; GFX11-NEXT: v_sub_co_u32 v4, s0, v4, v123444; GFX11-NEXT: v_sub_co_ci_u32_e32 v1, vcc_lo, v1, v9, vcc_lo3445; GFX11-NEXT: v_sub_co_ci_u32_e64 v5, s0, v5, v13, s03446; GFX11-NEXT: v_sub_co_ci_u32_e32 v2, vcc_lo, v2, v10, vcc_lo3447; GFX11-NEXT: v_sub_co_ci_u32_e64 v6, s0, v6, v14, s03448; GFX11-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, v3, v11, vcc_lo3449; GFX11-NEXT: v_sub_co_ci_u32_e64 v7, s0, v7, v15, s03450; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, 0, vcc_lo3451; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, 0, vcc_lo3452; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, 0, vcc_lo3453; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, 0, vcc_lo3454; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, 0, s03455; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, 0, s03456; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, 0, s03457; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, 0, s03458; GFX11-NEXT: s_setpc_b64 s[30:31]3459 %result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)3460 ret <2 x i128> %result3461}3462 3463define amdgpu_ps <2 x i128> @s_usubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {3464; GFX6-LABEL: s_usubsat_v2i128:3465; GFX6: ; %bb.0:3466; GFX6-NEXT: s_sub_u32 s0, s0, s83467; GFX6-NEXT: s_subb_u32 s1, s1, s93468; GFX6-NEXT: s_subb_u32 s2, s2, s103469; GFX6-NEXT: s_subb_u32 s3, s3, s113470; GFX6-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3471; GFX6-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3472; GFX6-NEXT: s_sub_u32 s4, s4, s123473; GFX6-NEXT: s_subb_u32 s5, s5, s133474; GFX6-NEXT: s_subb_u32 s6, s6, s143475; GFX6-NEXT: s_subb_u32 s7, s7, s153476; GFX6-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]3477; GFX6-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]3478; GFX6-NEXT: ; return to shader part epilog3479;3480; GFX8-LABEL: s_usubsat_v2i128:3481; GFX8: ; %bb.0:3482; GFX8-NEXT: s_sub_u32 s0, s0, s83483; GFX8-NEXT: s_subb_u32 s1, s1, s93484; GFX8-NEXT: s_subb_u32 s2, s2, s103485; GFX8-NEXT: s_subb_u32 s3, s3, s113486; GFX8-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3487; GFX8-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3488; GFX8-NEXT: s_sub_u32 s4, s4, s123489; GFX8-NEXT: s_subb_u32 s5, s5, s133490; GFX8-NEXT: s_subb_u32 s6, s6, s143491; GFX8-NEXT: s_subb_u32 s7, s7, s153492; GFX8-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]3493; GFX8-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]3494; GFX8-NEXT: ; return to shader part epilog3495;3496; GFX9-LABEL: s_usubsat_v2i128:3497; GFX9: ; %bb.0:3498; GFX9-NEXT: s_sub_u32 s0, s0, s83499; GFX9-NEXT: s_subb_u32 s1, s1, s93500; GFX9-NEXT: s_subb_u32 s2, s2, s103501; GFX9-NEXT: s_subb_u32 s3, s3, s113502; GFX9-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3503; GFX9-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3504; GFX9-NEXT: s_sub_u32 s4, s4, s123505; GFX9-NEXT: s_subb_u32 s5, s5, s133506; GFX9-NEXT: s_subb_u32 s6, s6, s143507; GFX9-NEXT: s_subb_u32 s7, s7, s153508; GFX9-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]3509; GFX9-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]3510; GFX9-NEXT: ; return to shader part epilog3511;3512; GFX10PLUS-LABEL: s_usubsat_v2i128:3513; GFX10PLUS: ; %bb.0:3514; GFX10PLUS-NEXT: s_sub_u32 s0, s0, s83515; GFX10PLUS-NEXT: s_subb_u32 s1, s1, s93516; GFX10PLUS-NEXT: s_subb_u32 s2, s2, s103517; GFX10PLUS-NEXT: s_subb_u32 s3, s3, s113518; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], 0, s[0:1]3519; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], 0, s[2:3]3520; GFX10PLUS-NEXT: s_sub_u32 s4, s4, s123521; GFX10PLUS-NEXT: s_subb_u32 s5, s5, s133522; GFX10PLUS-NEXT: s_subb_u32 s6, s6, s143523; GFX10PLUS-NEXT: s_subb_u32 s7, s7, s153524; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], 0, s[4:5]3525; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], 0, s[6:7]3526; GFX10PLUS-NEXT: ; return to shader part epilog3527 %result = call <2 x i128> @llvm.usub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)3528 ret <2 x i128> %result3529}3530 3531declare i7 @llvm.usub.sat.i7(i7, i7) #03532declare i8 @llvm.usub.sat.i8(i8, i8) #03533declare <2 x i8> @llvm.usub.sat.v2i8(<2 x i8>, <2 x i8>) #03534declare <4 x i8> @llvm.usub.sat.v4i8(<4 x i8>, <4 x i8>) #03535 3536declare i16 @llvm.usub.sat.i16(i16, i16) #03537declare <2 x i16> @llvm.usub.sat.v2i16(<2 x i16>, <2 x i16>) #03538declare <3 x i16> @llvm.usub.sat.v3i16(<3 x i16>, <3 x i16>) #03539declare <4 x i16> @llvm.usub.sat.v4i16(<4 x i16>, <4 x i16>) #03540declare <5 x i16> @llvm.usub.sat.v5i16(<5 x i16>, <5 x i16>) #03541declare <6 x i16> @llvm.usub.sat.v6i16(<6 x i16>, <6 x i16>) #03542declare <8 x i16> @llvm.usub.sat.v8i16(<8 x i16>, <8 x i16>) #03543 3544declare i24 @llvm.usub.sat.i24(i24, i24) #03545 3546declare i32 @llvm.usub.sat.i32(i32, i32) #03547declare <2 x i32> @llvm.usub.sat.v2i32(<2 x i32>, <2 x i32>) #03548declare <3 x i32> @llvm.usub.sat.v3i32(<3 x i32>, <3 x i32>) #03549declare <4 x i32> @llvm.usub.sat.v4i32(<4 x i32>, <4 x i32>) #03550declare <5 x i32> @llvm.usub.sat.v5i32(<5 x i32>, <5 x i32>) #03551declare <16 x i32> @llvm.usub.sat.v16i32(<16 x i32>, <16 x i32>) #03552 3553declare i48 @llvm.usub.sat.i48(i48, i48) #03554 3555declare i64 @llvm.usub.sat.i64(i64, i64) #03556declare <2 x i64> @llvm.usub.sat.v2i64(<2 x i64>, <2 x i64>) #03557 3558declare i128 @llvm.usub.sat.i128(i128, i128) #03559declare <2 x i128> @llvm.usub.sat.v2i128(<2 x i128>, <2 x i128>) #03560 3561attributes #0 = { nounwind readnone speculatable willreturn }3562