387 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1200 -mattr=+wavefrontsize64 < %s | FileCheck %s --check-prefix=GFX123 4define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {5; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm:6; GFX12: ; %bb.0: ; %bb7; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[6:9], v[0:1], v[2:3], 1.08; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off9; GFX12-NEXT: s_endpgm10bb:11 %res = call <4 x float>@llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16.v4f16.v4f32(<4 x half> %A, <4 x half> %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)12 store <4 x float> %res, ptr addrspace(1) %out13 ret void14}15 16define amdgpu_ps void @test_wmma_f32_16x16x16_f16_imm_non_inlineable(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {17; GFX12-LABEL: test_wmma_f32_16x16x16_f16_imm_non_inlineable:18; GFX12: ; %bb.0: ; %bb19; GFX12-NEXT: s_mov_b32 s0, 0x4040000020; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)21; GFX12-NEXT: s_mov_b32 s3, s022; GFX12-NEXT: s_mov_b32 s1, s023; GFX12-NEXT: s_mov_b32 s2, s024; GFX12-NEXT: v_mov_b32_e32 v9, s325; GFX12-NEXT: v_mov_b32_e32 v8, s226; GFX12-NEXT: v_mov_b32_e32 v7, s127; GFX12-NEXT: v_mov_b32_e32 v6, s028; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)29; GFX12-NEXT: v_wmma_f32_16x16x16_f16 v[6:9], v[0:1], v[2:3], v[6:9]30; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off31; GFX12-NEXT: s_endpgm32bb:33 %res = call <4 x float>@llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16.v4f16.v4f32(<4 x half> %A, <4 x half> %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)34 store <4 x float> %res, ptr addrspace(1) %out35 ret void36}37 38define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {39; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm:40; GFX12: ; %bb.0: ; %bb41; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[6:9], v[0:1], v[2:3], 1.042; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off43; GFX12-NEXT: s_endpgm44bb:45 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16.v4i16.v4f32(<4 x i16> %A, <4 x i16> %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)46 store <4 x float> %res, ptr addrspace(1) %out47 ret void48}49 50define amdgpu_ps void @test_wmma_f32_16x16x16_bf16_imm_non_inlineable(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {51; GFX12-LABEL: test_wmma_f32_16x16x16_bf16_imm_non_inlineable:52; GFX12: ; %bb.0: ; %bb53; GFX12-NEXT: s_mov_b32 s0, 0x4040000054; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)55; GFX12-NEXT: s_mov_b32 s3, s056; GFX12-NEXT: s_mov_b32 s1, s057; GFX12-NEXT: s_mov_b32 s2, s058; GFX12-NEXT: v_mov_b32_e32 v9, s359; GFX12-NEXT: v_mov_b32_e32 v8, s260; GFX12-NEXT: v_mov_b32_e32 v7, s161; GFX12-NEXT: v_mov_b32_e32 v6, s062; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)63; GFX12-NEXT: v_wmma_f32_16x16x16_bf16 v[6:9], v[0:1], v[2:3], v[6:9]64; GFX12-NEXT: global_store_b128 v[4:5], v[6:9], off65; GFX12-NEXT: s_endpgm66bb:67 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16.v4i16.v4f32(<4 x i16> %A, <4 x i16> %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)68 store <4 x float> %res, ptr addrspace(1) %out69 ret void70}71 72define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {73; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm:74; GFX12: ; %bb.0: ; %bb75; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[6:7], v[0:1], v[2:3], 1.076; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off77; GFX12-NEXT: s_endpgm78bb:79 %res = call <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16.v4f16.v4f16(<4 x half> %A, <4 x half> %B, <4 x half> <half 1.0, half 1.0, half 1.0, half 1.0>, i1 0)80 store <4 x half> %res, ptr addrspace(1) %out81 ret void82}83 84define amdgpu_ps void @test_wmma_f16_16x16x16_f16_imm_non_inlineable(<4 x half> %A, <4 x half> %B, ptr addrspace(1) %out) {85; GFX12-LABEL: test_wmma_f16_16x16x16_f16_imm_non_inlineable:86; GFX12: ; %bb.0: ; %bb87; GFX12-NEXT: s_mov_b32 s0, 0x4200420088; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)89; GFX12-NEXT: s_mov_b32 s1, s090; GFX12-NEXT: v_mov_b32_e32 v7, s191; GFX12-NEXT: v_mov_b32_e32 v6, s092; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)93; GFX12-NEXT: v_wmma_f16_16x16x16_f16 v[6:7], v[0:1], v[2:3], v[6:7]94; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off95; GFX12-NEXT: s_endpgm96bb:97 %res = call <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16.v4f16.v4f16(<4 x half> %A, <4 x half> %B, <4 x half> <half 3.0, half 3.0, half 3.0, half 3.0>, i1 0)98 store <4 x half> %res, ptr addrspace(1) %out99 ret void100}101 102define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {103; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm:104; GFX12: ; %bb.0: ; %bb105; GFX12-NEXT: s_mov_b32 s0, 0x3f803f80106; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)107; GFX12-NEXT: s_mov_b32 s1, s0108; GFX12-NEXT: v_mov_b32_e32 v7, s1109; GFX12-NEXT: v_mov_b32_e32 v6, s0110; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)111; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]112; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off113; GFX12-NEXT: s_endpgm114bb:115 %res = call <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16.v4i16.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> <i16 16256, i16 16256, i16 16256, i16 16256>, i1 0)116 store <4 x i16> %res, ptr addrspace(1) %out117 ret void118}119 120define amdgpu_ps void @test_wmma_bf16_16x16x16_bf16_imm_non_inlineable(<4 x i16> %A, <4 x i16> %B, ptr addrspace(1) %out) {121; GFX12-LABEL: test_wmma_bf16_16x16x16_bf16_imm_non_inlineable:122; GFX12: ; %bb.0: ; %bb123; GFX12-NEXT: s_mov_b32 s0, 0x3fc03fc0124; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)125; GFX12-NEXT: s_mov_b32 s1, s0126; GFX12-NEXT: v_mov_b32_e32 v7, s1127; GFX12-NEXT: v_mov_b32_e32 v6, s0128; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)129; GFX12-NEXT: v_wmma_bf16_16x16x16_bf16 v[6:7], v[0:1], v[2:3], v[6:7]130; GFX12-NEXT: global_store_b64 v[4:5], v[6:7], off131; GFX12-NEXT: s_endpgm132bb:133 %res = call <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16.v4i16.v4i16(<4 x i16> %A, <4 x i16> %B, <4 x i16> <i16 16320, i16 16320, i16 16320, i16 16320>, i1 0)134 store <4 x i16> %res, ptr addrspace(1) %out135 ret void136}137 138define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {139; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm:140; GFX12: ; %bb.0: ; %bb141; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:7], v0, v1, 1142; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off143; GFX12-NEXT: s_endpgm144bb:145 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)146 store <4 x i32> %res, ptr addrspace(1) %out147 ret void148}149 150define amdgpu_ps void @test_wmma_i32_16x16x16_iu8_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {151; GFX12-LABEL: test_wmma_i32_16x16x16_iu8_imm_non_inlineable:152; GFX12: ; %bb.0: ; %bb153; GFX12-NEXT: s_movk_i32 s0, 0x80154; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)155; GFX12-NEXT: s_mov_b32 s3, s0156; GFX12-NEXT: s_mov_b32 s1, s0157; GFX12-NEXT: s_mov_b32 s2, s0158; GFX12-NEXT: v_mov_b32_e32 v7, s3159; GFX12-NEXT: v_mov_b32_e32 v6, s2160; GFX12-NEXT: v_mov_b32_e32 v5, s1161; GFX12-NEXT: v_mov_b32_e32 v4, s0162; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)163; GFX12-NEXT: v_wmma_i32_16x16x16_iu8 v[4:7], v0, v1, v[4:7]164; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off165; GFX12-NEXT: s_endpgm166bb:167 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)168 store <4 x i32> %res, ptr addrspace(1) %out169 ret void170}171 172define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm(i32 %A, i32 %B, ptr addrspace(1) %out) {173; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm:174; GFX12: ; %bb.0: ; %bb175; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v0, v1, 1176; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off177; GFX12-NEXT: s_endpgm178bb:179 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)180 store <4 x i32> %res, ptr addrspace(1) %out181 ret void182}183 184define amdgpu_ps void @test_wmma_i32_16x16x16_iu4_imm_non_inlineable(i32 %A, i32 %B, ptr addrspace(1) %out) {185; GFX12-LABEL: test_wmma_i32_16x16x16_iu4_imm_non_inlineable:186; GFX12: ; %bb.0: ; %bb187; GFX12-NEXT: s_movk_i32 s0, 0x80188; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)189; GFX12-NEXT: s_mov_b32 s3, s0190; GFX12-NEXT: s_mov_b32 s1, s0191; GFX12-NEXT: s_mov_b32 s2, s0192; GFX12-NEXT: v_mov_b32_e32 v7, s3193; GFX12-NEXT: v_mov_b32_e32 v6, s2194; GFX12-NEXT: v_mov_b32_e32 v5, s1195; GFX12-NEXT: v_mov_b32_e32 v4, s0196; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)197; GFX12-NEXT: v_wmma_i32_16x16x16_iu4 v[4:7], v0, v1, v[4:7]198; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off199; GFX12-NEXT: s_endpgm200bb:201 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)202 store <4 x i32> %res, ptr addrspace(1) %out203 ret void204}205 206define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {207; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm:208; GFX12: ; %bb.0: ; %bb209; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[4:7], v0, v1, 1.0210; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off211; GFX12-NEXT: s_endpgm212bb:213 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)214 store <4 x float> %res, ptr addrspace(1) %out215 ret void216}217 218define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {219; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_fp8_imm_non_inlineable:220; GFX12: ; %bb.0: ; %bb221; GFX12-NEXT: s_mov_b32 s0, 0x40400000222; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)223; GFX12-NEXT: s_mov_b32 s3, s0224; GFX12-NEXT: s_mov_b32 s1, s0225; GFX12-NEXT: s_mov_b32 s2, s0226; GFX12-NEXT: v_mov_b32_e32 v7, s3227; GFX12-NEXT: v_mov_b32_e32 v6, s2228; GFX12-NEXT: v_mov_b32_e32 v5, s1229; GFX12-NEXT: v_mov_b32_e32 v4, s0230; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)231; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_fp8 v[4:7], v0, v1, v[4:7]232; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off233; GFX12-NEXT: s_endpgm234bb:235 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)236 store <4 x float> %res, ptr addrspace(1) %out237 ret void238}239 240define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {241; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm:242; GFX12: ; %bb.0: ; %bb243; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[4:7], v0, v1, 1.0244; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off245; GFX12-NEXT: s_endpgm246bb:247 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)248 store <4 x float> %res, ptr addrspace(1) %out249 ret void250}251 252define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {253; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_fp8_imm_non_inlineable:254; GFX12: ; %bb.0: ; %bb255; GFX12-NEXT: s_mov_b32 s0, 0x40400000256; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)257; GFX12-NEXT: s_mov_b32 s3, s0258; GFX12-NEXT: s_mov_b32 s1, s0259; GFX12-NEXT: s_mov_b32 s2, s0260; GFX12-NEXT: v_mov_b32_e32 v7, s3261; GFX12-NEXT: v_mov_b32_e32 v6, s2262; GFX12-NEXT: v_mov_b32_e32 v5, s1263; GFX12-NEXT: v_mov_b32_e32 v4, s0264; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)265; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_fp8 v[4:7], v0, v1, v[4:7]266; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off267; GFX12-NEXT: s_endpgm268bb:269 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)270 store <4 x float> %res, ptr addrspace(1) %out271 ret void272}273 274define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {275; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm:276; GFX12: ; %bb.0: ; %bb277; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[4:7], v0, v1, 1.0278; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off279; GFX12-NEXT: s_endpgm280bb:281 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)282 store <4 x float> %res, ptr addrspace(1) %out283 ret void284}285 286define amdgpu_ps void @test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {287; GFX12-LABEL: test_wmma_f32_16x16x16_fp8_bf8_imm_non_inlineable:288; GFX12: ; %bb.0: ; %bb289; GFX12-NEXT: s_mov_b32 s0, 0x40400000290; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)291; GFX12-NEXT: s_mov_b32 s3, s0292; GFX12-NEXT: s_mov_b32 s1, s0293; GFX12-NEXT: s_mov_b32 s2, s0294; GFX12-NEXT: v_mov_b32_e32 v7, s3295; GFX12-NEXT: v_mov_b32_e32 v6, s2296; GFX12-NEXT: v_mov_b32_e32 v5, s1297; GFX12-NEXT: v_mov_b32_e32 v4, s0298; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)299; GFX12-NEXT: v_wmma_f32_16x16x16_fp8_bf8 v[4:7], v0, v1, v[4:7]300; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off301; GFX12-NEXT: s_endpgm302bb:303 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)304 store <4 x float> %res, ptr addrspace(1) %out305 ret void306}307 308define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {309; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm:310; GFX12: ; %bb.0: ; %bb311; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[4:7], v0, v1, 1.0312; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off313; GFX12-NEXT: s_endpgm314bb:315 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 1.0, float 1.0, float 1.0, float 1.0>)316 store <4 x float> %res, ptr addrspace(1) %out317 ret void318}319 320define amdgpu_ps void @test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable(i32 %A, i32 %B, <4 x float> %C, ptr addrspace(1) %out) {321; GFX12-LABEL: test_wmma_f32_16x16x16_bf8_bf8_imm_non_inlineable:322; GFX12: ; %bb.0: ; %bb323; GFX12-NEXT: s_mov_b32 s0, 0x40400000324; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)325; GFX12-NEXT: s_mov_b32 s3, s0326; GFX12-NEXT: s_mov_b32 s1, s0327; GFX12-NEXT: s_mov_b32 s2, s0328; GFX12-NEXT: v_mov_b32_e32 v7, s3329; GFX12-NEXT: v_mov_b32_e32 v6, s2330; GFX12-NEXT: v_mov_b32_e32 v5, s1331; GFX12-NEXT: v_mov_b32_e32 v4, s0332; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)333; GFX12-NEXT: v_wmma_f32_16x16x16_bf8_bf8 v[4:7], v0, v1, v[4:7]334; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off335; GFX12-NEXT: s_endpgm336bb:337 %res = call <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32.i32.v4f32(i32 %A, i32 %B, <4 x float> <float 3.0, float 3.0, float 3.0, float 3.0>)338 store <4 x float> %res, ptr addrspace(1) %out339 ret void340}341 342define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm(i32 %A, i32 %B, <4 x i32> %C, ptr addrspace(1) %out) {343; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm:344; GFX12: ; %bb.0: ; %bb345; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:7], v0, v1, 1346; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off347; GFX12-NEXT: s_endpgm348bb:349 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 1, i32 1, i32 1, i32 1>, i1 0)350 store <4 x i32> %res, ptr addrspace(1) %out351 ret void352}353 354define amdgpu_ps void @test_wmma_i32_16x16x32_iu4_imm_non_inlineable(i32 %A, i32 %B, <4 x i32> %C, ptr addrspace(1) %out) {355; GFX12-LABEL: test_wmma_i32_16x16x32_iu4_imm_non_inlineable:356; GFX12: ; %bb.0: ; %bb357; GFX12-NEXT: s_movk_i32 s0, 0x80358; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)359; GFX12-NEXT: s_mov_b32 s3, s0360; GFX12-NEXT: s_mov_b32 s1, s0361; GFX12-NEXT: s_mov_b32 s2, s0362; GFX12-NEXT: v_mov_b32_e32 v7, s3363; GFX12-NEXT: v_mov_b32_e32 v6, s2364; GFX12-NEXT: v_mov_b32_e32 v5, s1365; GFX12-NEXT: v_mov_b32_e32 v4, s0366; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)367; GFX12-NEXT: v_wmma_i32_16x16x32_iu4 v[4:7], v0, v1, v[4:7]368; GFX12-NEXT: global_store_b128 v[2:3], v[4:7], off369; GFX12-NEXT: s_endpgm370bb:371 %res = call <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32.i32.v4i32(i1 0, i32 %A, i1 0, i32 %B, <4 x i32> <i32 128, i32 128, i32 128, i32 128>, i1 0)372 store <4 x i32> %res, ptr addrspace(1) %out373 ret void374}375 376declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.f16.v4f32.v4f16.v4f16.v4f32(<4 x half>, <4 x half>, <4 x float>)377declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf16.v4f32.v4i16.v4i16.v4f32(<4 x i16>, <4 x i16>, <4 x float>)378declare <4 x half> @llvm.amdgcn.wmma.f16.16x16x16.f16.v4f16.v4f16.v4f16.v4f16(<4 x half>, <4 x half>, <4 x half>, i1 immarg)379declare <4 x i16> @llvm.amdgcn.wmma.bf16.16x16x16.bf16.v4i16.v4i16.v4i16.v4i16(<4 x i16>, <4 x i16>, <4 x i16>, i1 immarg)380declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu8.v4i32.i32.i32.v4i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)381declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x16.iu4.v4i32.i32.i32.v4i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)382declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.fp8.v4f32.i32.i32.v4f32(i32, i32, <4 x float>)383declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.fp8.bf8.v4f32.i32.i32.v4f32(i32, i32, <4 x float>)384declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.fp8.v4f32.i32.i32.v4f32(i32, i32, <4 x float>)385declare <4 x float> @llvm.amdgcn.wmma.f32.16x16x16.bf8.bf8.v4f32.i32.i32.v4f32(i32, i32, <4 x float>)386declare <4 x i32> @llvm.amdgcn.wmma.i32.16x16x32.iu4.v4i32.i32.i32.v4i32(i1 immarg, i32, i1 immarg, i32, <4 x i32>, i1 immarg)387