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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck -check-prefixes=GCN,GFX7 %s3; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck -check-prefixes=GCN,GFX8 %s4; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX900 %s5; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx906 < %s | FileCheck -check-prefixes=GCN,GFX906 %s6; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s7; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10 %s8 9define amdgpu_ps i32 @scalar_xnor_i32_one_use(i32 inreg %a, i32 inreg %b) {10; GCN-LABEL: scalar_xnor_i32_one_use:11; GCN: ; %bb.0: ; %entry12; GCN-NEXT: s_xnor_b32 s0, s0, s113; GCN-NEXT: ; return to shader part epilog14;15; GFX10-LABEL: scalar_xnor_i32_one_use:16; GFX10: ; %bb.0: ; %entry17; GFX10-NEXT: s_xnor_b32 s0, s0, s118; GFX10-NEXT: ; return to shader part epilog19entry:20 %xor = xor i32 %a, %b21 %r0.val = xor i32 %xor, -122 ret i32 %r0.val23}24 25; FIXME: fails to match26define amdgpu_ps i32 @scalar_xnor_v2i16_one_use(<2 x i16> inreg %a, <2 x i16> inreg %b) {27; GFX7-LABEL: scalar_xnor_v2i16_one_use:28; GFX7: ; %bb.0: ; %entry29; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]30; GFX7-NEXT: s_lshl_b32 s1, s1, 1631; GFX7-NEXT: s_and_b32 s0, s0, 0xffff32; GFX7-NEXT: s_or_b32 s0, s1, s033; GFX7-NEXT: s_xor_b32 s0, s0, -134; GFX7-NEXT: ; return to shader part epilog35;36; GFX8-LABEL: scalar_xnor_v2i16_one_use:37; GFX8: ; %bb.0: ; %entry38; GFX8-NEXT: s_xor_b32 s0, s0, s139; GFX8-NEXT: s_xor_b32 s0, s0, -140; GFX8-NEXT: ; return to shader part epilog41;42; GFX900-LABEL: scalar_xnor_v2i16_one_use:43; GFX900: ; %bb.0: ; %entry44; GFX900-NEXT: s_xor_b32 s0, s0, s145; GFX900-NEXT: s_xor_b32 s0, s0, -146; GFX900-NEXT: ; return to shader part epilog47;48; GFX906-LABEL: scalar_xnor_v2i16_one_use:49; GFX906: ; %bb.0: ; %entry50; GFX906-NEXT: s_xor_b32 s0, s0, s151; GFX906-NEXT: s_xor_b32 s0, s0, -152; GFX906-NEXT: ; return to shader part epilog53;54; GFX10-LABEL: scalar_xnor_v2i16_one_use:55; GFX10: ; %bb.0: ; %entry56; GFX10-NEXT: s_xor_b32 s0, s0, s157; GFX10-NEXT: s_xor_b32 s0, s0, -158; GFX10-NEXT: ; return to shader part epilog59entry:60 %xor = xor <2 x i16> %a, %b61 %r0.val = xor <2 x i16> %xor, <i16 -1, i16 -1>62 %cast = bitcast <2 x i16> %r0.val to i3263 ret i32 %cast64}65 66define amdgpu_ps <2 x i32> @scalar_xnor_i32_mul_use(i32 inreg %a, i32 inreg %b) {67; GCN-LABEL: scalar_xnor_i32_mul_use:68; GCN: ; %bb.0: ; %entry69; GCN-NEXT: s_xor_b32 s1, s0, s170; GCN-NEXT: s_not_b32 s2, s171; GCN-NEXT: s_add_i32 s1, s1, s072; GCN-NEXT: s_mov_b32 s0, s273; GCN-NEXT: ; return to shader part epilog74;75; GFX10-LABEL: scalar_xnor_i32_mul_use:76; GFX10: ; %bb.0: ; %entry77; GFX10-NEXT: s_xor_b32 s1, s0, s178; GFX10-NEXT: s_not_b32 s2, s179; GFX10-NEXT: s_add_i32 s1, s1, s080; GFX10-NEXT: s_mov_b32 s0, s281; GFX10-NEXT: ; return to shader part epilog82entry:83 %xor = xor i32 %a, %b84 %r0.val = xor i32 %xor, -185 %r1.val = add i32 %xor, %a86 %ins0 = insertelement <2 x i32> poison, i32 %r0.val, i32 087 %ins1 = insertelement <2 x i32> %ins0, i32 %r1.val, i32 188 ret <2 x i32> %ins189}90 91define amdgpu_ps i64 @scalar_xnor_i64_one_use(i64 inreg %a, i64 inreg %b) {92; GCN-LABEL: scalar_xnor_i64_one_use:93; GCN: ; %bb.0:94; GCN-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3]95; GCN-NEXT: ; return to shader part epilog96;97; GFX10-LABEL: scalar_xnor_i64_one_use:98; GFX10: ; %bb.0:99; GFX10-NEXT: s_xnor_b64 s[0:1], s[0:1], s[2:3]100; GFX10-NEXT: ; return to shader part epilog101 %xor = xor i64 %a, %b102 %r0.val = xor i64 %xor, -1103 ret i64 %r0.val104}105 106; FIXME: fails to match107define amdgpu_ps i64 @scalar_xnor_v4i16_one_use(<4 x i16> inreg %a, <4 x i16> inreg %b) {108; GFX7-LABEL: scalar_xnor_v4i16_one_use:109; GFX7: ; %bb.0:110; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]111; GFX7-NEXT: s_xor_b64 s[2:3], s[2:3], s[6:7]112; GFX7-NEXT: s_lshl_b32 s1, s1, 16113; GFX7-NEXT: s_and_b32 s0, s0, 0xffff114; GFX7-NEXT: s_or_b32 s0, s1, s0115; GFX7-NEXT: s_lshl_b32 s1, s3, 16116; GFX7-NEXT: s_and_b32 s2, s2, 0xffff117; GFX7-NEXT: s_or_b32 s1, s1, s2118; GFX7-NEXT: s_xor_b64 s[0:1], s[0:1], -1119; GFX7-NEXT: ; return to shader part epilog120;121; GFX8-LABEL: scalar_xnor_v4i16_one_use:122; GFX8: ; %bb.0:123; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]124; GFX8-NEXT: s_xor_b64 s[0:1], s[0:1], -1125; GFX8-NEXT: ; return to shader part epilog126;127; GFX900-LABEL: scalar_xnor_v4i16_one_use:128; GFX900: ; %bb.0:129; GFX900-NEXT: s_mov_b32 s4, -1130; GFX900-NEXT: s_mov_b32 s5, s4131; GFX900-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]132; GFX900-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]133; GFX900-NEXT: ; return to shader part epilog134;135; GFX906-LABEL: scalar_xnor_v4i16_one_use:136; GFX906: ; %bb.0:137; GFX906-NEXT: s_mov_b32 s4, -1138; GFX906-NEXT: s_mov_b32 s5, s4139; GFX906-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]140; GFX906-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]141; GFX906-NEXT: ; return to shader part epilog142;143; GFX10-LABEL: scalar_xnor_v4i16_one_use:144; GFX10: ; %bb.0:145; GFX10-NEXT: s_mov_b32 s4, -1146; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]147; GFX10-NEXT: s_mov_b32 s5, s4148; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[4:5]149; GFX10-NEXT: ; return to shader part epilog150 %xor = xor <4 x i16> %a, %b151 %ret = xor <4 x i16> %xor, <i16 -1, i16 -1, i16 -1, i16 -1>152 %cast = bitcast <4 x i16> %ret to i64153 ret i64 %cast154}155 156define amdgpu_ps <2 x i64> @scalar_xnor_i64_mul_use(i64 inreg %a, i64 inreg %b) {157; GCN-LABEL: scalar_xnor_i64_mul_use:158; GCN: ; %bb.0:159; GCN-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3]160; GCN-NEXT: s_not_b64 s[4:5], s[2:3]161; GCN-NEXT: s_add_u32 s2, s2, s0162; GCN-NEXT: s_addc_u32 s3, s3, s1163; GCN-NEXT: s_mov_b32 s0, s4164; GCN-NEXT: s_mov_b32 s1, s5165; GCN-NEXT: ; return to shader part epilog166;167; GFX10-LABEL: scalar_xnor_i64_mul_use:168; GFX10: ; %bb.0:169; GFX10-NEXT: s_xor_b64 s[2:3], s[0:1], s[2:3]170; GFX10-NEXT: s_not_b64 s[4:5], s[2:3]171; GFX10-NEXT: s_add_u32 s2, s2, s0172; GFX10-NEXT: s_addc_u32 s3, s3, s1173; GFX10-NEXT: s_mov_b32 s0, s4174; GFX10-NEXT: s_mov_b32 s1, s5175; GFX10-NEXT: ; return to shader part epilog176 %xor = xor i64 %a, %b177 %r0.val = xor i64 %xor, -1178 %r1.val = add i64 %xor, %a179 %ins0 = insertelement <2 x i64> poison, i64 %r0.val, i32 0180 %ins1 = insertelement <2 x i64> %ins0, i64 %r1.val, i32 1181 ret <2 x i64> %ins1182}183 184define i32 @vector_xnor_i32_one_use(i32 %a, i32 %b) {185; GFX7-LABEL: vector_xnor_i32_one_use:186; GFX7: ; %bb.0: ; %entry187; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)188; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1189; GFX7-NEXT: v_not_b32_e32 v0, v0190; GFX7-NEXT: s_setpc_b64 s[30:31]191;192; GFX8-LABEL: vector_xnor_i32_one_use:193; GFX8: ; %bb.0: ; %entry194; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)195; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1196; GFX8-NEXT: v_not_b32_e32 v0, v0197; GFX8-NEXT: s_setpc_b64 s[30:31]198;199; GFX900-LABEL: vector_xnor_i32_one_use:200; GFX900: ; %bb.0: ; %entry201; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; GFX900-NEXT: v_xor_b32_e32 v0, v0, v1203; GFX900-NEXT: v_not_b32_e32 v0, v0204; GFX900-NEXT: s_setpc_b64 s[30:31]205;206; GFX906-LABEL: vector_xnor_i32_one_use:207; GFX906: ; %bb.0: ; %entry208; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX906-NEXT: v_xnor_b32_e32 v0, v0, v1210; GFX906-NEXT: s_setpc_b64 s[30:31]211;212; GFX10-LABEL: vector_xnor_i32_one_use:213; GFX10: ; %bb.0: ; %entry214; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)215; GFX10-NEXT: v_xnor_b32_e32 v0, v0, v1216; GFX10-NEXT: s_setpc_b64 s[30:31]217entry:218 %xor = xor i32 %a, %b219 %r = xor i32 %xor, -1220 ret i32 %r221}222 223define i64 @vector_xnor_i64_one_use(i64 %a, i64 %b) {224; GFX7-LABEL: vector_xnor_i64_one_use:225; GFX7: ; %bb.0: ; %entry226; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)227; GFX7-NEXT: v_xor_b32_e32 v0, v0, v2228; GFX7-NEXT: v_xor_b32_e32 v1, v1, v3229; GFX7-NEXT: v_not_b32_e32 v0, v0230; GFX7-NEXT: v_not_b32_e32 v1, v1231; GFX7-NEXT: s_setpc_b64 s[30:31]232;233; GFX8-LABEL: vector_xnor_i64_one_use:234; GFX8: ; %bb.0: ; %entry235; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)236; GFX8-NEXT: v_xor_b32_e32 v0, v0, v2237; GFX8-NEXT: v_xor_b32_e32 v1, v1, v3238; GFX8-NEXT: v_not_b32_e32 v0, v0239; GFX8-NEXT: v_not_b32_e32 v1, v1240; GFX8-NEXT: s_setpc_b64 s[30:31]241;242; GFX900-LABEL: vector_xnor_i64_one_use:243; GFX900: ; %bb.0: ; %entry244; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)245; GFX900-NEXT: v_xor_b32_e32 v0, v0, v2246; GFX900-NEXT: v_xor_b32_e32 v1, v1, v3247; GFX900-NEXT: v_not_b32_e32 v0, v0248; GFX900-NEXT: v_not_b32_e32 v1, v1249; GFX900-NEXT: s_setpc_b64 s[30:31]250;251; GFX906-LABEL: vector_xnor_i64_one_use:252; GFX906: ; %bb.0: ; %entry253; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)254; GFX906-NEXT: v_xnor_b32_e32 v0, v0, v2255; GFX906-NEXT: v_xnor_b32_e32 v1, v1, v3256; GFX906-NEXT: s_setpc_b64 s[30:31]257;258; GFX10-LABEL: vector_xnor_i64_one_use:259; GFX10: ; %bb.0: ; %entry260; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)261; GFX10-NEXT: v_xnor_b32_e32 v0, v0, v2262; GFX10-NEXT: v_xnor_b32_e32 v1, v1, v3263; GFX10-NEXT: s_setpc_b64 s[30:31]264entry:265 %xor = xor i64 %a, %b266 %r = xor i64 %xor, -1267 ret i64 %r268}269 270define amdgpu_ps float @xnor_s_v_i32_one_use(i32 inreg %s, i32 %v) {271; GFX7-LABEL: xnor_s_v_i32_one_use:272; GFX7: ; %bb.0:273; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0274; GFX7-NEXT: v_not_b32_e32 v0, v0275; GFX7-NEXT: ; return to shader part epilog276;277; GFX8-LABEL: xnor_s_v_i32_one_use:278; GFX8: ; %bb.0:279; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0280; GFX8-NEXT: v_not_b32_e32 v0, v0281; GFX8-NEXT: ; return to shader part epilog282;283; GFX900-LABEL: xnor_s_v_i32_one_use:284; GFX900: ; %bb.0:285; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0286; GFX900-NEXT: v_not_b32_e32 v0, v0287; GFX900-NEXT: ; return to shader part epilog288;289; GFX906-LABEL: xnor_s_v_i32_one_use:290; GFX906: ; %bb.0:291; GFX906-NEXT: v_xnor_b32_e32 v0, s0, v0292; GFX906-NEXT: ; return to shader part epilog293;294; GFX10-LABEL: xnor_s_v_i32_one_use:295; GFX10: ; %bb.0:296; GFX10-NEXT: v_xnor_b32_e32 v0, s0, v0297; GFX10-NEXT: ; return to shader part epilog298 %xor = xor i32 %s, %v299 %d = xor i32 %xor, -1300 %cast = bitcast i32 %d to float301 ret float %cast302}303 304define amdgpu_ps float @xnor_v_s_i32_one_use(i32 inreg %s, i32 %v) {305; GFX7-LABEL: xnor_v_s_i32_one_use:306; GFX7: ; %bb.0:307; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0308; GFX7-NEXT: v_not_b32_e32 v0, v0309; GFX7-NEXT: ; return to shader part epilog310;311; GFX8-LABEL: xnor_v_s_i32_one_use:312; GFX8: ; %bb.0:313; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0314; GFX8-NEXT: v_not_b32_e32 v0, v0315; GFX8-NEXT: ; return to shader part epilog316;317; GFX900-LABEL: xnor_v_s_i32_one_use:318; GFX900: ; %bb.0:319; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0320; GFX900-NEXT: v_not_b32_e32 v0, v0321; GFX900-NEXT: ; return to shader part epilog322;323; GFX906-LABEL: xnor_v_s_i32_one_use:324; GFX906: ; %bb.0:325; GFX906-NEXT: v_xnor_b32_e64 v0, v0, s0326; GFX906-NEXT: ; return to shader part epilog327;328; GFX10-LABEL: xnor_v_s_i32_one_use:329; GFX10: ; %bb.0:330; GFX10-NEXT: v_xnor_b32_e64 v0, v0, s0331; GFX10-NEXT: ; return to shader part epilog332 %xor = xor i32 %v, %s333 %d = xor i32 %xor, -1334 %cast = bitcast i32 %d to float335 ret float %cast336}337 338define amdgpu_ps <2 x float> @xnor_i64_s_v_one_use(i64 inreg %a, i64 %b64) {339; GFX7-LABEL: xnor_i64_s_v_one_use:340; GFX7: ; %bb.0: ; %entry341; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29342; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0343; GFX7-NEXT: v_xor_b32_e32 v1, s1, v1344; GFX7-NEXT: v_not_b32_e32 v0, v0345; GFX7-NEXT: v_not_b32_e32 v1, v1346; GFX7-NEXT: ; return to shader part epilog347;348; GFX8-LABEL: xnor_i64_s_v_one_use:349; GFX8: ; %bb.0: ; %entry350; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]351; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0352; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1353; GFX8-NEXT: v_not_b32_e32 v0, v0354; GFX8-NEXT: v_not_b32_e32 v1, v1355; GFX8-NEXT: ; return to shader part epilog356;357; GFX900-LABEL: xnor_i64_s_v_one_use:358; GFX900: ; %bb.0: ; %entry359; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]360; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0361; GFX900-NEXT: v_xor_b32_e32 v1, s1, v1362; GFX900-NEXT: v_not_b32_e32 v0, v0363; GFX900-NEXT: v_not_b32_e32 v1, v1364; GFX900-NEXT: ; return to shader part epilog365;366; GFX906-LABEL: xnor_i64_s_v_one_use:367; GFX906: ; %bb.0: ; %entry368; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]369; GFX906-NEXT: v_xnor_b32_e32 v0, s0, v0370; GFX906-NEXT: v_xnor_b32_e32 v1, s1, v1371; GFX906-NEXT: ; return to shader part epilog372;373; GFX10-LABEL: xnor_i64_s_v_one_use:374; GFX10: ; %bb.0: ; %entry375; GFX10-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]376; GFX10-NEXT: v_xnor_b32_e32 v0, s0, v0377; GFX10-NEXT: v_xnor_b32_e32 v1, s1, v1378; GFX10-NEXT: ; return to shader part epilog379entry:380 %b = shl i64 %b64, 29381 %xor = xor i64 %a, %b382 %r0.val = xor i64 %xor, -1383 %cast = bitcast i64 %r0.val to <2 x float>384 ret <2 x float> %cast385}386 387define amdgpu_ps <2 x float> @xnor_i64_v_s_one_use(i64 inreg %a, i64 %b64) {388; GFX7-LABEL: xnor_i64_v_s_one_use:389; GFX7: ; %bb.0:390; GFX7-NEXT: v_lshl_b64 v[0:1], v[0:1], 29391; GFX7-NEXT: v_xor_b32_e32 v0, s0, v0392; GFX7-NEXT: v_xor_b32_e32 v1, s1, v1393; GFX7-NEXT: v_not_b32_e32 v0, v0394; GFX7-NEXT: v_not_b32_e32 v1, v1395; GFX7-NEXT: ; return to shader part epilog396;397; GFX8-LABEL: xnor_i64_v_s_one_use:398; GFX8: ; %bb.0:399; GFX8-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]400; GFX8-NEXT: v_xor_b32_e32 v0, s0, v0401; GFX8-NEXT: v_xor_b32_e32 v1, s1, v1402; GFX8-NEXT: v_not_b32_e32 v0, v0403; GFX8-NEXT: v_not_b32_e32 v1, v1404; GFX8-NEXT: ; return to shader part epilog405;406; GFX900-LABEL: xnor_i64_v_s_one_use:407; GFX900: ; %bb.0:408; GFX900-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]409; GFX900-NEXT: v_xor_b32_e32 v0, s0, v0410; GFX900-NEXT: v_xor_b32_e32 v1, s1, v1411; GFX900-NEXT: v_not_b32_e32 v0, v0412; GFX900-NEXT: v_not_b32_e32 v1, v1413; GFX900-NEXT: ; return to shader part epilog414;415; GFX906-LABEL: xnor_i64_v_s_one_use:416; GFX906: ; %bb.0:417; GFX906-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]418; GFX906-NEXT: v_xnor_b32_e64 v0, v0, s0419; GFX906-NEXT: v_xnor_b32_e64 v1, v1, s1420; GFX906-NEXT: ; return to shader part epilog421;422; GFX10-LABEL: xnor_i64_v_s_one_use:423; GFX10: ; %bb.0:424; GFX10-NEXT: v_lshlrev_b64 v[0:1], 29, v[0:1]425; GFX10-NEXT: v_xnor_b32_e64 v0, v0, s0426; GFX10-NEXT: v_xnor_b32_e64 v1, v1, s1427; GFX10-NEXT: ; return to shader part epilog428 %b = shl i64 %b64, 29429 %xor = xor i64 %b, %a430 %r0.val = xor i64 %xor, -1431 %cast = bitcast i64 %r0.val to <2 x float>432 ret <2 x float> %cast433}434 435define i32 @vector_xor_na_b_i32_one_use(i32 %a, i32 %b) {436; GFX7-LABEL: vector_xor_na_b_i32_one_use:437; GFX7: ; %bb.0: ; %entry438; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)439; GFX7-NEXT: v_not_b32_e32 v0, v0440; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1441; GFX7-NEXT: s_setpc_b64 s[30:31]442;443; GFX8-LABEL: vector_xor_na_b_i32_one_use:444; GFX8: ; %bb.0: ; %entry445; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)446; GFX8-NEXT: v_not_b32_e32 v0, v0447; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1448; GFX8-NEXT: s_setpc_b64 s[30:31]449;450; GFX900-LABEL: vector_xor_na_b_i32_one_use:451; GFX900: ; %bb.0: ; %entry452; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)453; GFX900-NEXT: v_not_b32_e32 v0, v0454; GFX900-NEXT: v_xor_b32_e32 v0, v0, v1455; GFX900-NEXT: s_setpc_b64 s[30:31]456;457; GFX906-LABEL: vector_xor_na_b_i32_one_use:458; GFX906: ; %bb.0: ; %entry459; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)460; GFX906-NEXT: v_xnor_b32_e32 v0, v0, v1461; GFX906-NEXT: s_setpc_b64 s[30:31]462;463; GFX10-LABEL: vector_xor_na_b_i32_one_use:464; GFX10: ; %bb.0: ; %entry465; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)466; GFX10-NEXT: v_xnor_b32_e32 v0, v0, v1467; GFX10-NEXT: s_setpc_b64 s[30:31]468entry:469 %na = xor i32 %a, -1470 %r = xor i32 %na, %b471 ret i32 %r472}473 474define i32 @vector_xor_a_nb_i32_one_use(i32 %a, i32 %b) {475; GFX7-LABEL: vector_xor_a_nb_i32_one_use:476; GFX7: ; %bb.0: ; %entry477; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)478; GFX7-NEXT: v_not_b32_e32 v1, v1479; GFX7-NEXT: v_xor_b32_e32 v0, v0, v1480; GFX7-NEXT: s_setpc_b64 s[30:31]481;482; GFX8-LABEL: vector_xor_a_nb_i32_one_use:483; GFX8: ; %bb.0: ; %entry484; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)485; GFX8-NEXT: v_not_b32_e32 v1, v1486; GFX8-NEXT: v_xor_b32_e32 v0, v0, v1487; GFX8-NEXT: s_setpc_b64 s[30:31]488;489; GFX900-LABEL: vector_xor_a_nb_i32_one_use:490; GFX900: ; %bb.0: ; %entry491; GFX900-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)492; GFX900-NEXT: v_not_b32_e32 v1, v1493; GFX900-NEXT: v_xor_b32_e32 v0, v0, v1494; GFX900-NEXT: s_setpc_b64 s[30:31]495;496; GFX906-LABEL: vector_xor_a_nb_i32_one_use:497; GFX906: ; %bb.0: ; %entry498; GFX906-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)499; GFX906-NEXT: v_xnor_b32_e32 v0, v1, v0500; GFX906-NEXT: s_setpc_b64 s[30:31]501;502; GFX10-LABEL: vector_xor_a_nb_i32_one_use:503; GFX10: ; %bb.0: ; %entry504; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)505; GFX10-NEXT: v_xnor_b32_e32 v0, v1, v0506; GFX10-NEXT: s_setpc_b64 s[30:31]507entry:508 %nb = xor i32 %b, -1509 %r = xor i32 %a, %nb510 ret i32 %r511}512 513define amdgpu_ps <2 x i32> @scalar_xor_a_nb_i64_one_use(i64 inreg %a, i64 inreg %b) {514; GCN-LABEL: scalar_xor_a_nb_i64_one_use:515; GCN: ; %bb.0: ; %entry516; GCN-NEXT: s_not_b64 s[2:3], s[2:3]517; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]518; GCN-NEXT: ; return to shader part epilog519;520; GFX10-LABEL: scalar_xor_a_nb_i64_one_use:521; GFX10: ; %bb.0: ; %entry522; GFX10-NEXT: s_not_b64 s[2:3], s[2:3]523; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]524; GFX10-NEXT: ; return to shader part epilog525entry:526 %nb = xor i64 %b, -1527 %r0.val = xor i64 %a, %nb528 %cast = bitcast i64 %r0.val to <2 x i32>529 ret <2 x i32> %cast530}531 532define amdgpu_ps <2 x i32> @scalar_xor_na_b_i64_one_use(i64 inreg %a, i64 inreg %b) {533; GCN-LABEL: scalar_xor_na_b_i64_one_use:534; GCN: ; %bb.0: ; %entry535; GCN-NEXT: s_not_b64 s[0:1], s[0:1]536; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]537; GCN-NEXT: ; return to shader part epilog538;539; GFX10-LABEL: scalar_xor_na_b_i64_one_use:540; GFX10: ; %bb.0: ; %entry541; GFX10-NEXT: s_not_b64 s[0:1], s[0:1]542; GFX10-NEXT: s_xor_b64 s[0:1], s[0:1], s[2:3]543; GFX10-NEXT: ; return to shader part epilog544entry:545 %na = xor i64 %a, -1546 %r0.val = xor i64 %na, %b547 %cast = bitcast i64 %r0.val to <2 x i32>548 ret <2 x i32> %cast549}550