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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor -S %s -o - | FileCheck %s3 4@g1 = protected addrspace(1) externally_initialized global i32 0, align 45@g2 = protected addrspace(1) externally_initialized global i32 0, align 46 7define internal void @volatile_load_store_as_0(ptr %p) {8; CHECK-LABEL: define internal void @volatile_load_store_as_0(9; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0:[0-9]+]] {10; CHECK-NEXT: [[VAL_0:%.*]] = load i32, ptr addrspace(1) @g1, align 411; CHECK-NEXT: [[VAL_1:%.*]] = load volatile i32, ptr [[P]], align 412; CHECK-NEXT: store i32 [[VAL_1]], ptr addrspace(1) @g1, align 413; CHECK-NEXT: store volatile i32 [[VAL_0]], ptr [[P]], align 414; CHECK-NEXT: ret void15;16 %val.0 = load i32, ptr addrspace(1) @g1, align 417 %val.1 = load volatile i32, ptr %p, align 418 store i32 %val.1, ptr addrspace(1) @g1, align 419 store volatile i32 %val.0, ptr %p, align 420 ret void21}22 23define void @call_volatile_load_store_as_0(ptr %p1, ptr %p2) {24; CHECK-LABEL: define void @call_volatile_load_store_as_0(25; CHECK-SAME: ptr [[P1:%.*]], ptr [[P2:%.*]]) #[[ATTR0]] {26; CHECK-NEXT: call void @volatile_load_store_as_0(ptr [[P1]])27; CHECK-NEXT: call void @volatile_load_store_as_0(ptr [[P2]])28; CHECK-NEXT: ret void29;30 call void @volatile_load_store_as_0(ptr %p1)31 call void @volatile_load_store_as_0(ptr %p2)32 ret void33}34 35define internal void @volatile_load_store_as_1(ptr %p) {36; CHECK-LABEL: define internal void @volatile_load_store_as_1(37; CHECK-SAME: ptr [[P:%.*]]) #[[ATTR0]] {38; CHECK-NEXT: [[VAL_0:%.*]] = load i32, ptr addrspace(1) @g1, align 439; CHECK-NEXT: [[VAL_1:%.*]] = load volatile i32, ptr [[P]], align 440; CHECK-NEXT: store i32 [[VAL_1]], ptr addrspace(1) @g1, align 441; CHECK-NEXT: store volatile i32 [[VAL_0]], ptr [[P]], align 442; CHECK-NEXT: ret void43;44 %val.0 = load i32, ptr addrspace(1) @g1, align 445 %val.1 = load volatile i32, ptr %p, align 446 store i32 %val.1, ptr addrspace(1) @g1, align 447 store volatile i32 %val.0, ptr %p, align 448 ret void49}50 51define void @call_volatile_load_store_as_1(ptr addrspace(1) %p1, ptr addrspace(1) %p2) {52; CHECK-LABEL: define void @call_volatile_load_store_as_1(53; CHECK-SAME: ptr addrspace(1) [[P1:%.*]], ptr addrspace(1) [[P2:%.*]]) #[[ATTR0]] {54; CHECK-NEXT: [[P1_CAST:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr55; CHECK-NEXT: [[P2_CAST:%.*]] = addrspacecast ptr addrspace(1) [[P2]] to ptr56; CHECK-NEXT: call void @volatile_load_store_as_1(ptr [[P1_CAST]])57; CHECK-NEXT: call void @volatile_load_store_as_1(ptr [[P2_CAST]])58; CHECK-NEXT: ret void59;60 %p1.cast = addrspacecast ptr addrspace(1) %p1 to ptr61 %p2.cast = addrspacecast ptr addrspace(1) %p2 to ptr62 call void @volatile_load_store_as_1(ptr %p1.cast)63 call void @volatile_load_store_as_1(ptr %p2.cast)64 ret void65}66 67define internal void @volatile_load_store_as_4(ptr %p) {68 %val.0 = load i32, ptr addrspace(1) @g1, align 469 %val.1 = load volatile i32, ptr %p, align 470 store i32 %val.1, ptr addrspace(1) @g1, align 471 store volatile i32 %val.0, ptr %p, align 472 ret void73}74 75define void @call_volatile_load_store_as_4(ptr addrspace(4) %p1, ptr addrspace(4) %p2) {76; CHECK-LABEL: define void @call_volatile_load_store_as_4(77; CHECK-SAME: ptr addrspace(4) [[P1:%.*]], ptr addrspace(4) [[P2:%.*]]) #[[ATTR0]] {78; CHECK-NEXT: [[P1_CAST:%.*]] = addrspacecast ptr addrspace(4) [[P1]] to ptr79; CHECK-NEXT: [[P2_CAST:%.*]] = addrspacecast ptr addrspace(4) [[P2]] to ptr80; CHECK-NEXT: call void @volatile_load_store_as_1(ptr [[P1_CAST]])81; CHECK-NEXT: call void @volatile_load_store_as_1(ptr [[P2_CAST]])82; CHECK-NEXT: ret void83;84 %p1.cast = addrspacecast ptr addrspace(4) %p1 to ptr85 %p2.cast = addrspacecast ptr addrspace(4) %p2 to ptr86 call void @volatile_load_store_as_1(ptr %p1.cast)87 call void @volatile_load_store_as_1(ptr %p2.cast)88 ret void89}90 91define internal void @can_infer_cmpxchg(ptr %word) {92; CHECK-LABEL: define internal void @can_infer_cmpxchg(93; CHECK-SAME: ptr [[WORD:%.*]]) #[[ATTR0]] {94; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)95; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr addrspace(1) [[TMP1]], i32 0, i32 4 monotonic monotonic, align 496; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)97; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr addrspace(1) [[TMP2]], i32 0, i32 5 acq_rel monotonic, align 498; CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)99; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr addrspace(1) [[TMP3]], i32 0, i32 6 acquire monotonic, align 4100; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)101; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr addrspace(1) [[TMP4]], i32 0, i32 7 release monotonic, align 4102; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)103; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr addrspace(1) [[TMP5]], i32 0, i32 8 seq_cst monotonic, align 4104; CHECK-NEXT: [[TMP6:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)105; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr addrspace(1) [[TMP6]], i32 0, i32 9 seq_cst monotonic, align 4106; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[WORD]], i32 0, i32 10 seq_cst monotonic, align 4107; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[WORD]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4108; CHECK-NEXT: ret void109;110 %cmpxchg.0 = cmpxchg ptr %word, i32 0, i32 4 monotonic monotonic, align 4111 %cmpxchg.1 = cmpxchg ptr %word, i32 0, i32 5 acq_rel monotonic, align 4112 %cmpxchg.2 = cmpxchg ptr %word, i32 0, i32 6 acquire monotonic, align 4113 %cmpxchg.3 = cmpxchg ptr %word, i32 0, i32 7 release monotonic, align 4114 %cmpxchg.4 = cmpxchg ptr %word, i32 0, i32 8 seq_cst monotonic, align 4115 %cmpxchg.5 = cmpxchg weak ptr %word, i32 0, i32 9 seq_cst monotonic, align 4116 %cmpxchg.6 = cmpxchg volatile ptr %word, i32 0, i32 10 seq_cst monotonic, align 4117 %cmpxchg.7 = cmpxchg weak volatile ptr %word, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4118 ret void119}120 121define internal void @can_not_infer_cmpxchg(ptr %word) {122; CHECK-LABEL: define internal void @can_not_infer_cmpxchg(123; CHECK-SAME: ptr [[WORD:%.*]]) #[[ATTR0]] {124; CHECK-NEXT: [[CMPXCHG_0:%.*]] = cmpxchg ptr [[WORD]], i32 0, i32 4 monotonic monotonic, align 4125; CHECK-NEXT: [[CMPXCHG_1:%.*]] = cmpxchg ptr [[WORD]], i32 0, i32 5 acq_rel monotonic, align 4126; CHECK-NEXT: [[CMPXCHG_2:%.*]] = cmpxchg ptr [[WORD]], i32 0, i32 6 acquire monotonic, align 4127; CHECK-NEXT: [[CMPXCHG_3:%.*]] = cmpxchg ptr [[WORD]], i32 0, i32 7 release monotonic, align 4128; CHECK-NEXT: [[CMPXCHG_4:%.*]] = cmpxchg ptr [[WORD]], i32 0, i32 8 seq_cst monotonic, align 4129; CHECK-NEXT: [[CMPXCHG_5:%.*]] = cmpxchg weak ptr [[WORD]], i32 0, i32 9 seq_cst monotonic, align 4130; CHECK-NEXT: [[CMPXCHG_6:%.*]] = cmpxchg volatile ptr [[WORD]], i32 0, i32 10 seq_cst monotonic, align 4131; CHECK-NEXT: [[CMPXCHG_7:%.*]] = cmpxchg weak volatile ptr [[WORD]], i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4132; CHECK-NEXT: ret void133;134 %cmpxchg.0 = cmpxchg ptr %word, i32 0, i32 4 monotonic monotonic, align 4135 %cmpxchg.1 = cmpxchg ptr %word, i32 0, i32 5 acq_rel monotonic, align 4136 %cmpxchg.2 = cmpxchg ptr %word, i32 0, i32 6 acquire monotonic, align 4137 %cmpxchg.3 = cmpxchg ptr %word, i32 0, i32 7 release monotonic, align 4138 %cmpxchg.4 = cmpxchg ptr %word, i32 0, i32 8 seq_cst monotonic, align 4139 %cmpxchg.5 = cmpxchg weak ptr %word, i32 0, i32 9 seq_cst monotonic, align 4140 %cmpxchg.6 = cmpxchg volatile ptr %word, i32 0, i32 10 seq_cst monotonic, align 4141 %cmpxchg.7 = cmpxchg weak volatile ptr %word, i32 0, i32 11 syncscope("singlethread") seq_cst monotonic, align 4142 ret void143}144 145define internal void @can_infer_atomicrmw(ptr %word) {146; CHECK-LABEL: define internal void @can_infer_atomicrmw(147; CHECK-SAME: ptr [[WORD:%.*]]) #[[ATTR0]] {148; CHECK-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)149; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr addrspace(1) [[TMP1]], i32 12 monotonic, align 4150; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)151; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr addrspace(1) [[TMP2]], i32 13 monotonic, align 4152; CHECK-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)153; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr addrspace(1) [[TMP3]], i32 14 monotonic, align 4154; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)155; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr addrspace(1) [[TMP4]], i32 15 monotonic, align 4156; CHECK-NEXT: [[TMP5:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)157; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr addrspace(1) [[TMP5]], i32 16 monotonic, align 4158; CHECK-NEXT: [[TMP6:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)159; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr addrspace(1) [[TMP6]], i32 17 monotonic, align 4160; CHECK-NEXT: [[TMP7:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)161; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr addrspace(1) [[TMP7]], i32 18 monotonic, align 4162; CHECK-NEXT: [[TMP8:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)163; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr addrspace(1) [[TMP8]], i32 19 monotonic, align 4164; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[WORD]], i32 20 monotonic, align 4165; CHECK-NEXT: [[TMP10:%.*]] = addrspacecast ptr [[WORD]] to ptr addrspace(1)166; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr addrspace(1) [[TMP10]], i32 21 syncscope("singlethread") monotonic, align 4167; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[WORD]], i32 22 syncscope("singlethread") monotonic, align 4168; CHECK-NEXT: ret void169;170 %atomicrmw.xchg = atomicrmw xchg ptr %word, i32 12 monotonic, align 4171 %atomicrmw.add = atomicrmw add ptr %word, i32 13 monotonic, align 4172 %atomicrmw.sub = atomicrmw sub ptr %word, i32 14 monotonic, align 4173 %atomicrmw.and = atomicrmw and ptr %word, i32 15 monotonic, align 4174 %atomicrmw.nand = atomicrmw nand ptr %word, i32 16 monotonic, align 4175 %atomicrmw.or = atomicrmw or ptr %word, i32 17 monotonic, align 4176 %atomicrmw.xor = atomicrmw xor ptr %word, i32 18 monotonic, align 4177 %atomicrmw.max = atomicrmw max ptr %word, i32 19 monotonic, align 4178 %atomicrmw.min = atomicrmw volatile min ptr %word, i32 20 monotonic, align 4179 %atomicrmw.umax = atomicrmw umax ptr %word, i32 21 syncscope("singlethread") monotonic, align 4180 %atomicrmw.umin = atomicrmw volatile umin ptr %word, i32 22 syncscope("singlethread") monotonic, align 4181 ret void182}183 184define internal void @can_not_infer_atomicrmw(ptr %word) {185; CHECK-LABEL: define internal void @can_not_infer_atomicrmw(186; CHECK-SAME: ptr [[WORD:%.*]]) #[[ATTR0]] {187; CHECK-NEXT: [[ATOMICRMW_XCHG:%.*]] = atomicrmw xchg ptr [[WORD]], i32 12 monotonic, align 4188; CHECK-NEXT: [[ATOMICRMW_ADD:%.*]] = atomicrmw add ptr [[WORD]], i32 13 monotonic, align 4189; CHECK-NEXT: [[ATOMICRMW_SUB:%.*]] = atomicrmw sub ptr [[WORD]], i32 14 monotonic, align 4190; CHECK-NEXT: [[ATOMICRMW_AND:%.*]] = atomicrmw and ptr [[WORD]], i32 15 monotonic, align 4191; CHECK-NEXT: [[ATOMICRMW_NAND:%.*]] = atomicrmw nand ptr [[WORD]], i32 16 monotonic, align 4192; CHECK-NEXT: [[ATOMICRMW_OR:%.*]] = atomicrmw or ptr [[WORD]], i32 17 monotonic, align 4193; CHECK-NEXT: [[ATOMICRMW_XOR:%.*]] = atomicrmw xor ptr [[WORD]], i32 18 monotonic, align 4194; CHECK-NEXT: [[ATOMICRMW_MAX:%.*]] = atomicrmw max ptr [[WORD]], i32 19 monotonic, align 4195; CHECK-NEXT: [[ATOMICRMW_MIN:%.*]] = atomicrmw volatile min ptr [[WORD]], i32 20 monotonic, align 4196; CHECK-NEXT: [[ATOMICRMW_UMAX:%.*]] = atomicrmw umax ptr [[WORD]], i32 21 syncscope("singlethread") monotonic, align 4197; CHECK-NEXT: [[ATOMICRMW_UMIN:%.*]] = atomicrmw volatile umin ptr [[WORD]], i32 22 syncscope("singlethread") monotonic, align 4198; CHECK-NEXT: ret void199;200 %atomicrmw.xchg = atomicrmw xchg ptr %word, i32 12 monotonic, align 4201 %atomicrmw.add = atomicrmw add ptr %word, i32 13 monotonic, align 4202 %atomicrmw.sub = atomicrmw sub ptr %word, i32 14 monotonic, align 4203 %atomicrmw.and = atomicrmw and ptr %word, i32 15 monotonic, align 4204 %atomicrmw.nand = atomicrmw nand ptr %word, i32 16 monotonic, align 4205 %atomicrmw.or = atomicrmw or ptr %word, i32 17 monotonic, align 4206 %atomicrmw.xor = atomicrmw xor ptr %word, i32 18 monotonic, align 4207 %atomicrmw.max = atomicrmw max ptr %word, i32 19 monotonic, align 4208 %atomicrmw.min = atomicrmw volatile min ptr %word, i32 20 monotonic, align 4209 %atomicrmw.umax = atomicrmw umax ptr %word, i32 21 syncscope("singlethread") monotonic, align 4210 %atomicrmw.umin = atomicrmw volatile umin ptr %word, i32 22 syncscope("singlethread") monotonic, align 4211 ret void212}213 214define void @foo(ptr addrspace(3) %val) {215; CHECK-LABEL: define void @foo(216; CHECK-SAME: ptr addrspace(3) [[VAL:%.*]]) #[[ATTR1:[0-9]+]] {217; CHECK-NEXT: [[VAL_CAST:%.*]] = addrspacecast ptr addrspace(3) [[VAL]] to ptr218; CHECK-NEXT: call void @can_infer_cmpxchg(ptr addrspacecast (ptr addrspace(1) @g1 to ptr))219; CHECK-NEXT: call void @can_infer_cmpxchg(ptr addrspacecast (ptr addrspace(1) @g2 to ptr))220; CHECK-NEXT: call void @can_not_infer_cmpxchg(ptr addrspacecast (ptr addrspace(1) @g1 to ptr))221; CHECK-NEXT: call void @can_not_infer_cmpxchg(ptr addrspacecast (ptr addrspace(1) @g2 to ptr))222; CHECK-NEXT: call void @can_not_infer_cmpxchg(ptr [[VAL_CAST]])223; CHECK-NEXT: call void @can_infer_atomicrmw(ptr addrspacecast (ptr addrspace(1) @g1 to ptr))224; CHECK-NEXT: call void @can_infer_atomicrmw(ptr addrspacecast (ptr addrspace(1) @g2 to ptr))225; CHECK-NEXT: call void @can_not_infer_atomicrmw(ptr addrspacecast (ptr addrspace(1) @g1 to ptr))226; CHECK-NEXT: call void @can_not_infer_atomicrmw(ptr addrspacecast (ptr addrspace(1) @g2 to ptr))227; CHECK-NEXT: call void @can_not_infer_atomicrmw(ptr [[VAL_CAST]])228; CHECK-NEXT: ret void229;230 %g1.cast = addrspacecast ptr addrspace(1) @g1 to ptr231 %g2.cast = addrspacecast ptr addrspace(1) @g2 to ptr232 %val.cast = addrspacecast ptr addrspace(3) %val to ptr233 call void @can_infer_cmpxchg(ptr %g1.cast)234 call void @can_infer_cmpxchg(ptr %g2.cast)235 call void @can_not_infer_cmpxchg(ptr %g1.cast)236 call void @can_not_infer_cmpxchg(ptr %g2.cast)237 call void @can_not_infer_cmpxchg(ptr %val.cast)238 call void @can_infer_atomicrmw(ptr %g1.cast)239 call void @can_infer_atomicrmw(ptr %g2.cast)240 call void @can_not_infer_atomicrmw(ptr %g1.cast)241 call void @can_not_infer_atomicrmw(ptr %g2.cast)242 call void @can_not_infer_atomicrmw(ptr %val.cast)243 ret void244}245 246define void @kernel_argument_promotion_pattern_intra_procedure(ptr %p, i32 %val) {247; CHECK-LABEL: define void @kernel_argument_promotion_pattern_intra_procedure(248; CHECK-SAME: ptr [[P:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] {249; CHECK-NEXT: store i32 [[VAL]], ptr [[P]], align 4250; CHECK-NEXT: ret void251;252 %p.cast.0 = addrspacecast ptr %p to ptr addrspace(1)253 %p.cast.1 = addrspacecast ptr addrspace(1) %p.cast.0 to ptr254 store i32 %val, ptr %p.cast.1255 ret void256}257 258define internal void @use_argument_after_promotion(ptr %p, i32 %val) {259; CHECK-LABEL: define internal void @use_argument_after_promotion(260; CHECK-SAME: ptr [[P:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] {261; CHECK-NEXT: store i32 [[VAL]], ptr [[P]], align 4262; CHECK-NEXT: ret void263;264 store i32 %val, ptr %p265 ret void266}267 268define void @kernel_argument_promotion_pattern_inter_procedure(ptr %p, i32 %val) {269; CHECK-LABEL: define void @kernel_argument_promotion_pattern_inter_procedure(270; CHECK-SAME: ptr [[P:%.*]], i32 [[VAL:%.*]]) #[[ATTR0]] {271; CHECK-NEXT: call void @use_argument_after_promotion(ptr [[P]], i32 [[VAL]])272; CHECK-NEXT: ret void273;274 %p.cast.0 = addrspacecast ptr %p to ptr addrspace(1)275 %p.cast.1 = addrspacecast ptr addrspace(1) %p.cast.0 to ptr276 call void @use_argument_after_promotion(ptr %p.cast.1, i32 %val)277 ret void278}279 280define amdgpu_kernel void @kernel_argument_with_known_as(ptr addrspace(1) %p1, ptr addrspace(3) %p3, i32 %val) {281; CHECK-LABEL: define amdgpu_kernel void @kernel_argument_with_known_as(282; CHECK-SAME: ptr addrspace(1) [[P1:%.*]], ptr addrspace(3) [[P3:%.*]], i32 [[VAL:%.*]]) #[[ATTR1]] {283; CHECK-NEXT: [[P1_CAST:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr284; CHECK-NEXT: [[P3_CAST:%.*]] = addrspacecast ptr addrspace(3) [[P3]] to ptr285; CHECK-NEXT: [[B:%.*]] = icmp eq i32 [[VAL]], 0286; CHECK-NEXT: [[P:%.*]] = select i1 [[B]], ptr [[P1_CAST]], ptr [[P3_CAST]]287; CHECK-NEXT: [[ATOMIC_ADD:%.*]] = atomicrmw add ptr [[P]], i32 1 syncscope("agent") seq_cst, align 4, !noalias.addrspace [[META0:![0-9]+]], !amdgpu.no.fine.grained.memory [[META1:![0-9]+]], !amdgpu.no.remote.memory [[META1]]288; CHECK-NEXT: ret void289;290 %p1.cast = addrspacecast ptr addrspace(1) %p1 to ptr291 %p3.cast = addrspacecast ptr addrspace(3) %p3 to ptr292 %b = icmp eq i32 %val, 0293 %p = select i1 %b, ptr %p1.cast, ptr %p3.cast294 %atomic.add = atomicrmw add ptr %p, i32 1 syncscope("agent") seq_cst, align 4, !noalias.addrspace !0, !amdgpu.no.fine.grained.memory !1, !amdgpu.no.remote.memory !1295 ret void296}297 298!0 = !{i32 5, i32 6}299!1 = !{}300;.301; CHECK: [[META0]] = !{i32 5, i32 6}302; CHECK: [[META1]] = !{}303;.304