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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck -check-prefixes=GFX9 %s3; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=R600 %s4 5define amdgpu_kernel void @abs_v1(ptr addrspace(1) %out, i32 %arg) {6; GFX9-LABEL: abs_v1:7; GFX9: ; %bb.0:8; GFX9-NEXT: s_load_dword s2, s[4:5], 0x89; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x010; GFX9-NEXT: v_mov_b32_e32 v0, 011; GFX9-NEXT: s_waitcnt lgkmcnt(0)12; GFX9-NEXT: s_abs_i32 s2, s213; GFX9-NEXT: v_mov_b32_e32 v1, s214; GFX9-NEXT: global_store_dword v0, v1, s[0:1]15; GFX9-NEXT: s_endpgm16;17; R600-LABEL: abs_v1:18; R600: ; %bb.0:19; R600-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]20; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 121; R600-NEXT: CF_END22; R600-NEXT: PAD23; R600-NEXT: ALU clause starting at 4:24; R600-NEXT: MOV * T0.W, KC0[2].Z,25; R600-NEXT: SUB_INT * T1.W, 0.0, PV.W,26; R600-NEXT: MAX_INT T0.X, T0.W, PV.W,27; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,28; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)29 %res = call i32 @llvm.abs.i32(i32 %arg, i1 false)30 store i32 %res, ptr addrspace(1) %out, align 431 ret void32}33 34define amdgpu_kernel void @abs_v2(ptr addrspace(1) %out, i32 %arg) {35; GFX9-LABEL: abs_v2:36; GFX9: ; %bb.0:37; GFX9-NEXT: s_load_dword s2, s[4:5], 0x838; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x039; GFX9-NEXT: v_mov_b32_e32 v0, 040; GFX9-NEXT: s_waitcnt lgkmcnt(0)41; GFX9-NEXT: s_abs_i32 s2, s242; GFX9-NEXT: v_mov_b32_e32 v1, s243; GFX9-NEXT: global_store_dword v0, v1, s[0:1]44; GFX9-NEXT: s_endpgm45;46; R600-LABEL: abs_v2:47; R600: ; %bb.0:48; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]49; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 150; R600-NEXT: CF_END51; R600-NEXT: PAD52; R600-NEXT: ALU clause starting at 4:53; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[2].Z,54; R600-NEXT: MAX_INT T0.X, KC0[2].Z, PV.W,55; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,56; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)57 %neg = sub i32 0, %arg58 %cond = icmp sgt i32 %arg, %neg59 %res = select i1 %cond, i32 %arg, i32 %neg60 store i32 %res, ptr addrspace(1) %out, align 461 ret void62}63 64define amdgpu_kernel void @abs_v3(ptr addrspace(1) %out, i32 %arg) {65; GFX9-LABEL: abs_v3:66; GFX9: ; %bb.0:67; GFX9-NEXT: s_load_dword s2, s[4:5], 0x868; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x069; GFX9-NEXT: v_mov_b32_e32 v0, 070; GFX9-NEXT: s_waitcnt lgkmcnt(0)71; GFX9-NEXT: s_abs_i32 s2, s272; GFX9-NEXT: v_mov_b32_e32 v1, s273; GFX9-NEXT: global_store_dword v0, v1, s[0:1]74; GFX9-NEXT: s_endpgm75;76; R600-LABEL: abs_v3:77; R600: ; %bb.0:78; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]79; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 180; R600-NEXT: CF_END81; R600-NEXT: PAD82; R600-NEXT: ALU clause starting at 4:83; R600-NEXT: SUB_INT * T0.W, 0.0, KC0[2].Z,84; R600-NEXT: MAX_INT T0.X, PV.W, KC0[2].Z,85; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,86; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)87 %neg = sub i32 0, %arg88 %cond = icmp sgt i32 %neg, %arg89 %res = select i1 %cond, i32 %neg, i32 %arg90 store i32 %res, ptr addrspace(1) %out, align 491 ret void92}93