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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s3 4 5define amdgpu_gs float @absdiff_valu_input_regression() {6; CHECK-LABEL: absdiff_valu_input_regression:7; CHECK: ; %bb.0: ; %bb8; CHECK-NEXT: s_mov_b32 s0, 09; CHECK-NEXT: .LBB0_1: ; %bb110; CHECK-NEXT: ; =>This Inner Loop Header: Depth=111; CHECK-NEXT: s_mov_b32 s1, s012; CHECK-NEXT: s_or_b32 s0, s0, 113; CHECK-NEXT: s_cmp_gt_i32 s1, 014; CHECK-NEXT: s_cbranch_scc1 .LBB0_115; CHECK-NEXT: ; %bb.2: ; %bb1116; CHECK-NEXT: v_med3_i32 v0, s1, 0, 117; CHECK-NEXT: v_sub_u32_e32 v0, 0, v018; CHECK-NEXT: v_sub_u32_e32 v1, 0, v019; CHECK-NEXT: v_max_i32_e32 v0, v0, v120; CHECK-NEXT: ; return to shader part epilog21bb:22 br label %bb123 24bb1: ; preds = %bb1, %bb25 %i = phi i32 [ 0, %bb ], [ %i9, %bb1 ]26 %i2 = phi i32 [ 0, %bb ], [ %i5, %bb1 ]27 %i3 = or i32 %i2, 128 %i4 = or i32 %i3, 029 %i5 = call i32 @llvm.smax.i32(i32 %i, i32 0)30 %i6 = call i32 @llvm.umin.i32(i32 %i5, i32 1)31 %i7 = sub i32 0, %i632 %i8 = call i32 @llvm.abs.i32(i32 %i7, i1 false)33 %i9 = or i32 %i, 134 %i10 = icmp sgt i32 %i, 035 br i1 %i10, label %bb1, label %bb1136 37bb11: ; preds = %bb138 %i12 = bitcast i32 %i8 to float39 ret float %i1240}41 42define amdgpu_ps i16 @absdiff_i16_false(i16 inreg %arg0, i16 inreg %arg1) {43; CHECK-LABEL: absdiff_i16_false:44; CHECK: ; %bb.0:45; CHECK-NEXT: s_sub_i32 s0, s0, s146; CHECK-NEXT: s_sext_i32_i16 s1, s047; CHECK-NEXT: s_sub_i32 s0, 0, s048; CHECK-NEXT: s_sext_i32_i16 s0, s049; CHECK-NEXT: s_max_i32 s0, s1, s050; CHECK-NEXT: ; return to shader part epilog51 %diff = sub i16 %arg0, %arg152 %res = call i16 @llvm.abs.i16(i16 %diff, i1 false) ; INT_MIN input returns INT_MIN53 ret i16 %res54}55 56define amdgpu_ps i16 @absdiff_i16_true(i16 inreg %arg0, i16 inreg %arg1) {57; CHECK-LABEL: absdiff_i16_true:58; CHECK: ; %bb.0:59; CHECK-NEXT: s_sub_i32 s0, s0, s160; CHECK-NEXT: s_sext_i32_i16 s1, s061; CHECK-NEXT: s_sub_i32 s0, 0, s062; CHECK-NEXT: s_sext_i32_i16 s0, s063; CHECK-NEXT: s_max_i32 s0, s1, s064; CHECK-NEXT: ; return to shader part epilog65 %diff = sub i16 %arg0, %arg166 %res = call i16 @llvm.abs.i16(i16 %diff, i1 true) ; INT_MIN input returns poison67 ret i16 %res68}69 70define amdgpu_ps i32 @absdiff_i32_false(i32 inreg %arg0, i32 inreg %arg1) {71; CHECK-LABEL: absdiff_i32_false:72; CHECK: ; %bb.0:73; CHECK-NEXT: s_absdiff_i32 s0, s0, s174; CHECK-NEXT: ; return to shader part epilog75 %diff = sub i32 %arg0, %arg176 %res = call i32 @llvm.abs.i32(i32 %diff, i1 false) ; INT_MIN input returns INT_MIN77 ret i32 %res78}79 80define amdgpu_ps i32 @absdiff_i32_true(i32 inreg %arg0, i32 inreg %arg1) {81; CHECK-LABEL: absdiff_i32_true:82; CHECK: ; %bb.0:83; CHECK-NEXT: s_absdiff_i32 s0, s0, s184; CHECK-NEXT: ; return to shader part epilog85 %diff = sub i32 %arg0, %arg186 %res = call i32 @llvm.abs.i32(i32 %diff, i1 true) ; INT_MIN input returns poison87 ret i32 %res88}89 90; Multiple uses of %diff. No benefit for using s_absdiff_i32.91define amdgpu_ps i32 @absdiff_i32_false_multi_use(i32 inreg %arg0, i32 inreg %arg1) {92; CHECK-LABEL: absdiff_i32_false_multi_use:93; CHECK: ; %bb.0:94; CHECK-NEXT: s_sub_i32 s1, s0, s195; CHECK-NEXT: s_abs_i32 s0, s196; CHECK-NEXT: ;;#ASMSTART97; CHECK-NEXT: ; use s198; CHECK-NEXT: ;;#ASMEND99; CHECK-NEXT: ; return to shader part epilog100 %diff = sub i32 %arg0, %arg1101 %res = call i32 @llvm.abs.i32(i32 %diff, i1 false) ; INT_MIN input returns INT_MIN102 call void asm "; use $0", "s"(i32 %diff)103 ret i32 %res104}105 106define <2 x i32> @absdiff_2xi32_false(<2 x i32> %arg0, <2 x i32> %arg1) {107; CHECK-LABEL: absdiff_2xi32_false:108; CHECK: ; %bb.0:109; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)110; CHECK-NEXT: v_sub_u32_e32 v0, v0, v2111; CHECK-NEXT: v_sub_u32_e32 v1, v1, v3112; CHECK-NEXT: v_sub_u32_e32 v2, 0, v0113; CHECK-NEXT: v_max_i32_e32 v0, v2, v0114; CHECK-NEXT: v_sub_u32_e32 v2, 0, v1115; CHECK-NEXT: v_max_i32_e32 v1, v2, v1116; CHECK-NEXT: s_setpc_b64 s[30:31]117 %diff = sub <2 x i32> %arg0, %arg1118 %res = call <2 x i32> @llvm.abs.v2i32(<2 x i32> %diff, i1 false) ; INT_MIN input returns INT_MIN119 ret <2 x i32> %res120}121 122define <4 x i32> @absdiff_4xi32_false(<4 x i32> %arg0, <4 x i32> %arg1) {123; CHECK-LABEL: absdiff_4xi32_false:124; CHECK: ; %bb.0:125; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; CHECK-NEXT: v_sub_u32_e32 v0, v0, v4127; CHECK-NEXT: v_sub_u32_e32 v1, v1, v5128; CHECK-NEXT: v_sub_u32_e32 v4, 0, v0129; CHECK-NEXT: v_sub_u32_e32 v2, v2, v6130; CHECK-NEXT: v_max_i32_e32 v0, v4, v0131; CHECK-NEXT: v_sub_u32_e32 v4, 0, v1132; CHECK-NEXT: v_sub_u32_e32 v3, v3, v7133; CHECK-NEXT: v_max_i32_e32 v1, v4, v1134; CHECK-NEXT: v_sub_u32_e32 v4, 0, v2135; CHECK-NEXT: v_max_i32_e32 v2, v4, v2136; CHECK-NEXT: v_sub_u32_e32 v4, 0, v3137; CHECK-NEXT: v_max_i32_e32 v3, v4, v3138; CHECK-NEXT: s_setpc_b64 s[30:31]139 %diff = sub <4 x i32> %arg0, %arg1140 %res = call <4 x i32> @llvm.abs.v4i32(<4 x i32> %diff, i1 false) ; INT_MIN input returns INT_MIN141 ret <4 x i32> %res142}143