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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GISEL %s4 5define amdgpu_ps float @add_max_u32_vvv(i32 %a, i32 %b, i32 %c) {6; GCN-LABEL: add_max_u32_vvv:7; GCN: ; %bb.0:8; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 19; GCN-NEXT: v_add_max_u32 v0, v0, v1, v210; GCN-NEXT: ; return to shader part epilog11 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)12 %max = call i32 @llvm.umax.i32(i32 %add, i32 %c)13 %ret = bitcast i32 %max to float14 ret float %ret15}16 17define amdgpu_ps float @add_max_u32_svv(i32 inreg %a, i32 %b, i32 %c) {18; GCN-LABEL: add_max_u32_svv:19; GCN: ; %bb.0:20; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 121; GCN-NEXT: v_add_max_u32 v0, s0, v0, v122; GCN-NEXT: ; return to shader part epilog23 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)24 %max = call i32 @llvm.umax.i32(i32 %add, i32 %c)25 %ret = bitcast i32 %max to float26 ret float %ret27}28 29define amdgpu_ps float @add_max_u32_ssv(i32 inreg %a, i32 inreg %b, i32 %c) {30; GCN-LABEL: add_max_u32_ssv:31; GCN: ; %bb.0:32; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 133; GCN-NEXT: v_add_max_u32 v0, s0, s1, v034; GCN-NEXT: ; return to shader part epilog35 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)36 %max = call i32 @llvm.umax.i32(i32 %add, i32 %c)37 %ret = bitcast i32 %max to float38 ret float %ret39}40 41define amdgpu_ps float @add_max_u32_sss(i32 inreg %a, i32 inreg %b, i32 inreg %c) {42; SDAG-LABEL: add_max_u32_sss:43; SDAG: ; %bb.0:44; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 145; SDAG-NEXT: v_add_nc_u32_e64 v0, s0, s1 clamp46; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)47; SDAG-NEXT: v_max_u32_e32 v0, s2, v048; SDAG-NEXT: ; return to shader part epilog49;50; GISEL-LABEL: add_max_u32_sss:51; GISEL: ; %bb.0:52; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 153; GISEL-NEXT: v_mov_b32_e32 v0, s254; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)55; GISEL-NEXT: v_add_max_u32 v0, s0, s1, v056; GISEL-NEXT: ; return to shader part epilog57 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)58 %max = call i32 @llvm.umax.i32(i32 %add, i32 %c)59 %ret = bitcast i32 %max to float60 ret float %ret61}62 63define amdgpu_ps float @add_max_u32_vsi(i32 %a, i32 inreg %b) {64; GCN-LABEL: add_max_u32_vsi:65; GCN: ; %bb.0:66; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 167; GCN-NEXT: v_add_max_u32 v0, v0, s0, 468; GCN-NEXT: ; return to shader part epilog69 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)70 %max = call i32 @llvm.umax.i32(i32 %add, i32 4)71 %ret = bitcast i32 %max to float72 ret float %ret73}74 75define amdgpu_ps float @add_max_u32_svl(i32 inreg %a, i32 %b) {76; GCN-LABEL: add_max_u32_svl:77; GCN: ; %bb.0:78; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 179; GCN-NEXT: v_add_max_u32 v0, s0, v0, 0x6480; GCN-NEXT: ; return to shader part epilog81 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)82 %max = call i32 @llvm.umax.i32(i32 %add, i32 100)83 %ret = bitcast i32 %max to float84 ret float %ret85}86 87define amdgpu_ps float @add_max_u32_slv(i32 inreg %a, i32 %b, i32 %c) {88; GCN-LABEL: add_max_u32_slv:89; GCN: ; %bb.0:90; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 191; GCN-NEXT: v_add_max_u32 v0, s0, v0, v192; GCN-NEXT: ; return to shader part epilog93 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)94 %max = call i32 @llvm.umax.i32(i32 %add, i32 %c)95 %ret = bitcast i32 %max to float96 ret float %ret97}98 99define amdgpu_ps float @add_max_i32_vvv(i32 %a, i32 %b, i32 %c) {100; GCN-LABEL: add_max_i32_vvv:101; GCN: ; %bb.0:102; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1103; GCN-NEXT: v_add_max_i32 v0, v0, v1, v2104; GCN-NEXT: ; return to shader part epilog105 %add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b)106 %max = call i32 @llvm.smax.i32(i32 %add, i32 %c)107 %ret = bitcast i32 %max to float108 ret float %ret109}110 111define amdgpu_ps float @add_min_u32_vvv(i32 %a, i32 %b, i32 %c) {112; GCN-LABEL: add_min_u32_vvv:113; GCN: ; %bb.0:114; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1115; GCN-NEXT: v_add_min_u32 v0, v0, v1, v2116; GCN-NEXT: ; return to shader part epilog117 %add = call i32 @llvm.uadd.sat.i32(i32 %a, i32 %b)118 %max = call i32 @llvm.umin.i32(i32 %add, i32 %c)119 %ret = bitcast i32 %max to float120 ret float %ret121}122 123define amdgpu_ps float @add_min_i32_vvv(i32 %a, i32 %b, i32 %c) {124; GCN-LABEL: add_min_i32_vvv:125; GCN: ; %bb.0:126; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1127; GCN-NEXT: v_add_min_i32 v0, v0, v1, v2128; GCN-NEXT: ; return to shader part epilog129 %add = call i32 @llvm.sadd.sat.i32(i32 %a, i32 %b)130 %max = call i32 @llvm.smin.i32(i32 %add, i32 %c)131 %ret = bitcast i32 %max to float132 ret float %ret133}134 135define amdgpu_ps float @add_max_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {136; GCN-LABEL: add_max_v2u16_vvv:137; GCN: ; %bb.0:138; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1139; GCN-NEXT: v_pk_add_max_u16 v0, v0, v1, v2140; GCN-NEXT: ; return to shader part epilog141 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)142 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)143 %ret = bitcast <2 x i16> %max to float144 ret float %ret145}146 147define amdgpu_ps float @add_max_v2u16_svv(<2 x i16> inreg %a, <2 x i16> %b, <2 x i16> %c) {148; GCN-LABEL: add_max_v2u16_svv:149; GCN: ; %bb.0:150; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1151; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, v1152; GCN-NEXT: ; return to shader part epilog153 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)154 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)155 %ret = bitcast <2 x i16> %max to float156 ret float %ret157}158 159define amdgpu_ps float @add_max_v2u16_ssv(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> %c) {160; GCN-LABEL: add_max_v2u16_ssv:161; GCN: ; %bb.0:162; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1163; GCN-NEXT: v_pk_add_max_u16 v0, s0, s1, v0164; GCN-NEXT: ; return to shader part epilog165 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)166 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)167 %ret = bitcast <2 x i16> %max to float168 ret float %ret169}170 171define amdgpu_ps float @add_max_v2u16_sss(<2 x i16> inreg %a, <2 x i16> inreg %b, <2 x i16> inreg %c) {172; SDAG-LABEL: add_max_v2u16_sss:173; SDAG: ; %bb.0:174; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1175; SDAG-NEXT: v_pk_add_u16 v0, s0, s1 clamp176; SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)177; SDAG-NEXT: v_pk_max_u16 v0, v0, s2178; SDAG-NEXT: ; return to shader part epilog179;180; GISEL-LABEL: add_max_v2u16_sss:181; GISEL: ; %bb.0:182; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1183; GISEL-NEXT: v_mov_b32_e32 v0, s2184; GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)185; GISEL-NEXT: v_pk_add_max_u16 v0, s0, s1, v0186; GISEL-NEXT: ; return to shader part epilog187 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)188 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %c)189 %ret = bitcast <2 x i16> %max to float190 ret float %ret191}192 193define amdgpu_ps float @add_max_v2u16_vsi(<2 x i16> %a, <2 x i16> inreg %b) {194; GCN-LABEL: add_max_v2u16_vsi:195; GCN: ; %bb.0:196; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1197; GCN-NEXT: v_pk_add_max_u16 v0, v0, s0, 4198; GCN-NEXT: ; return to shader part epilog199 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)200 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 4, i16 0>)201 %ret = bitcast <2 x i16> %max to float202 ret float %ret203}204 205define amdgpu_ps float @add_max_v2u16_svl(<2 x i16> inreg %a, <2 x i16> %b) {206; GCN-LABEL: add_max_v2u16_svl:207; GCN: ; %bb.0:208; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1209; GCN-NEXT: v_pk_add_max_u16 v0, s0, v0, 0x650064210; GCN-NEXT: ; return to shader part epilog211 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)212 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> <i16 100, i16 101>)213 %ret = bitcast <2 x i16> %max to float214 ret float %ret215}216 217define amdgpu_ps float @add_max_v2u16_slv(<2 x i16> inreg %a, <2 x i16> %b) {218; GCN-LABEL: add_max_v2u16_slv:219; GCN: ; %bb.0:220; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1221; GCN-NEXT: v_pk_add_max_u16 v0, 0x640064, s0, v0222; GCN-NEXT: ; return to shader part epilog223 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> <i16 100, i16 100>)224 %max = call <2 x i16> @llvm.umax.v216(<2 x i16> %add, <2 x i16> %b)225 %ret = bitcast <2 x i16> %max to float226 ret float %ret227}228 229define amdgpu_ps float @add_max_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {230; GCN-LABEL: add_max_v2s16_vvv:231; GCN: ; %bb.0:232; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1233; GCN-NEXT: v_pk_add_max_i16 v0, v0, v1, v2234; GCN-NEXT: ; return to shader part epilog235 %add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b)236 %max = call <2 x i16> @llvm.smax.v216(<2 x i16> %add, <2 x i16> %c)237 %ret = bitcast <2 x i16> %max to float238 ret float %ret239}240 241define amdgpu_ps float @add_min_v2u16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {242; GCN-LABEL: add_min_v2u16_vvv:243; GCN: ; %bb.0:244; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1245; GCN-NEXT: v_pk_add_min_u16 v0, v0, v1, v2246; GCN-NEXT: ; return to shader part epilog247 %add = call <2 x i16> @llvm.uadd.sat.i32(<2 x i16> %a, <2 x i16> %b)248 %max = call <2 x i16> @llvm.umin.v216(<2 x i16> %add, <2 x i16> %c)249 %ret = bitcast <2 x i16> %max to float250 ret float %ret251}252 253define amdgpu_ps float @add_min_v2s16_vvv(<2 x i16> %a, <2 x i16> %b, <2 x i16> %c) {254; GCN-LABEL: add_min_v2s16_vvv:255; GCN: ; %bb.0:256; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1257; GCN-NEXT: v_pk_add_min_i16 v0, v0, v1, v2258; GCN-NEXT: ; return to shader part epilog259 %add = call <2 x i16> @llvm.sadd.sat.i32(<2 x i16> %a, <2 x i16> %b)260 %max = call <2 x i16> @llvm.smin.v216(<2 x i16> %add, <2 x i16> %c)261 %ret = bitcast <2 x i16> %max to float262 ret float %ret263}264 265declare <2 x i16> @llvm.smin.v216(<2 x i16>, <2 x i16>)266declare <2 x i16> @llvm.smax.v216(<2 x i16>, <2 x i16>)267declare <2 x i16> @llvm.umin.v216(<2 x i16>, <2 x i16>)268declare <2 x i16> @llvm.umax.v216(<2 x i16>, <2 x i16>)269declare i32 @llvm.smin.i32(i32, i32)270declare i32 @llvm.smax.i32(i32, i32)271declare i32 @llvm.umin.i32(i32, i32)272declare i32 @llvm.umax.i32(i32, i32)273