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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_ADD3_U329; ===================================================================================10 11define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: add3:13; VI: ; %bb.0:14; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v115; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v216; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: add3:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_add3_u32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: add3:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_add3_u32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = add i32 %a, %b28 %result = add i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33; V_MAD_U32_U24 is given higher priority.34define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) {35; VI-LABEL: mad_no_add3:36; VI: ; %bb.0:37; VI-NEXT: v_mad_u32_u24 v0, v0, v1, v438; VI-NEXT: v_mad_u32_u24 v0, v2, v3, v039; VI-NEXT: ; return to shader part epilog40;41; GFX9-LABEL: mad_no_add3:42; GFX9: ; %bb.0:43; GFX9-NEXT: v_mad_u32_u24 v0, v0, v1, v444; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v045; GFX9-NEXT: ; return to shader part epilog46;47; GFX10-LABEL: mad_no_add3:48; GFX10: ; %bb.0:49; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v450; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v051; GFX10-NEXT: ; return to shader part epilog52 %a0 = shl i32 %a, 853 %a1 = lshr i32 %a0, 854 %b0 = shl i32 %b, 855 %b1 = lshr i32 %b0, 856 %mul1 = mul i32 %a1, %b157 58 %c0 = shl i32 %c, 859 %c1 = lshr i32 %c0, 860 %d0 = shl i32 %d, 861 %d1 = lshr i32 %d0, 862 %mul2 = mul i32 %c1, %d163 64 %add0 = add i32 %e, %mul165 %add1 = add i32 %mul2, %add066 67 %bc = bitcast i32 %add1 to float68 ret float %bc69}70 71; ThreeOp instruction variant not used due to Constant Bus Limitations72; TODO: with reassociation it is possible to replace a v_add_u32_e32 with a s_add_i3273define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) {74; VI-LABEL: add3_vgpr_b:75; VI: ; %bb.0:76; VI-NEXT: s_add_i32 s3, s3, s277; VI-NEXT: v_add_u32_e32 v0, vcc, s3, v078; VI-NEXT: ; return to shader part epilog79;80; GFX9-LABEL: add3_vgpr_b:81; GFX9: ; %bb.0:82; GFX9-NEXT: s_add_i32 s3, s3, s283; GFX9-NEXT: v_add_u32_e32 v0, s3, v084; GFX9-NEXT: ; return to shader part epilog85;86; GFX10-LABEL: add3_vgpr_b:87; GFX10: ; %bb.0:88; GFX10-NEXT: v_add3_u32 v0, s3, s2, v089; GFX10-NEXT: ; return to shader part epilog90 %x = add i32 %a, %b91 %result = add i32 %x, %c92 %bc = bitcast i32 %result to float93 ret float %bc94}95 96define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) {97; VI-LABEL: add3_vgpr_all2:98; VI: ; %bb.0:99; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v2100; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1101; VI-NEXT: ; return to shader part epilog102;103; GFX9-LABEL: add3_vgpr_all2:104; GFX9: ; %bb.0:105; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0106; GFX9-NEXT: ; return to shader part epilog107;108; GFX10-LABEL: add3_vgpr_all2:109; GFX10: ; %bb.0:110; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0111; GFX10-NEXT: ; return to shader part epilog112 %x = add i32 %b, %c113 %result = add i32 %a, %x114 %bc = bitcast i32 %result to float115 ret float %bc116}117 118define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {119; VI-LABEL: add3_vgpr_bc:120; VI: ; %bb.0:121; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0122; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1123; VI-NEXT: ; return to shader part epilog124;125; GFX9-LABEL: add3_vgpr_bc:126; GFX9: ; %bb.0:127; GFX9-NEXT: v_add3_u32 v0, s2, v0, v1128; GFX9-NEXT: ; return to shader part epilog129;130; GFX10-LABEL: add3_vgpr_bc:131; GFX10: ; %bb.0:132; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1133; GFX10-NEXT: ; return to shader part epilog134 %x = add i32 %a, %b135 %result = add i32 %x, %c136 %bc = bitcast i32 %result to float137 ret float %bc138}139 140define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) {141; VI-LABEL: add3_vgpr_const:142; VI: ; %bb.0:143; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1144; VI-NEXT: v_add_u32_e32 v0, vcc, 16, v0145; VI-NEXT: ; return to shader part epilog146;147; GFX9-LABEL: add3_vgpr_const:148; GFX9: ; %bb.0:149; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16150; GFX9-NEXT: ; return to shader part epilog151;152; GFX10-LABEL: add3_vgpr_const:153; GFX10: ; %bb.0:154; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16155; GFX10-NEXT: ; return to shader part epilog156 %x = add i32 %a, %b157 %result = add i32 %x, 16158 %bc = bitcast i32 %result to float159 ret float %bc160}161 162define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x) {163; VI-LABEL: add3_multiuse_outer:164; VI: ; %bb.0:165; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1166; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2167; VI-NEXT: v_mul_lo_u32 v1, v0, v3168; VI-NEXT: ; return to shader part epilog169;170; GFX9-LABEL: add3_multiuse_outer:171; GFX9: ; %bb.0:172; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2173; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3174; GFX9-NEXT: ; return to shader part epilog175;176; GFX10-LABEL: add3_multiuse_outer:177; GFX10: ; %bb.0:178; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2179; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3180; GFX10-NEXT: ; return to shader part epilog181 %inner = add i32 %a, %b182 %outer = add i32 %inner, %c183 %x1 = mul i32 %outer, %x184 %r1 = insertelement <2 x i32> poison, i32 %outer, i32 0185 %r0 = insertelement <2 x i32> %r1, i32 %x1, i32 1186 %bc = bitcast <2 x i32> %r0 to <2 x float>187 ret <2 x float> %bc188}189 190define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) {191; VI-LABEL: add3_multiuse_inner:192; VI: ; %bb.0:193; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1194; VI-NEXT: v_add_u32_e32 v1, vcc, v0, v2195; VI-NEXT: ; return to shader part epilog196;197; GFX9-LABEL: add3_multiuse_inner:198; GFX9: ; %bb.0:199; GFX9-NEXT: v_add_u32_e32 v0, v0, v1200; GFX9-NEXT: v_add_u32_e32 v1, v0, v2201; GFX9-NEXT: ; return to shader part epilog202;203; GFX10-LABEL: add3_multiuse_inner:204; GFX10: ; %bb.0:205; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1206; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2207; GFX10-NEXT: ; return to shader part epilog208 %inner = add i32 %a, %b209 %outer = add i32 %inner, %c210 %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0211 %r0 = insertelement <2 x i32> %r1, i32 %outer, i32 1212 %bc = bitcast <2 x i32> %r0 to <2 x float>213 ret <2 x float> %bc214}215 216; A case where uniform values end up in VGPRs -- we could use v_add3_u32 here,217; but we don't.218define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float inreg %c) {219; VI-LABEL: add3_uniform_vgpr:220; VI: ; %bb.0:221; VI-NEXT: v_add_f32_e64 v0, s2, 1.0222; VI-NEXT: v_add_f32_e64 v1, s3, 2.0223; VI-NEXT: v_mov_b32_e32 v2, 0x40400000224; VI-NEXT: v_add_f32_e32 v2, s4, v2225; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v1226; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v2227; VI-NEXT: ; return to shader part epilog228;229; GFX9-LABEL: add3_uniform_vgpr:230; GFX9: ; %bb.0:231; GFX9-NEXT: v_add_f32_e64 v0, s2, 1.0232; GFX9-NEXT: v_add_f32_e64 v1, s3, 2.0233; GFX9-NEXT: v_mov_b32_e32 v2, 0x40400000234; GFX9-NEXT: v_add_f32_e32 v2, s4, v2235; GFX9-NEXT: v_add_u32_e32 v0, v0, v1236; GFX9-NEXT: v_add_u32_e32 v0, v0, v2237; GFX9-NEXT: ; return to shader part epilog238;239; GFX10-LABEL: add3_uniform_vgpr:240; GFX10: ; %bb.0:241; GFX10-NEXT: v_add_f32_e64 v0, s2, 1.0242; GFX10-NEXT: v_add_f32_e64 v1, s3, 2.0243; GFX10-NEXT: v_add_f32_e64 v2, 0x40400000, s4244; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1245; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2246; GFX10-NEXT: ; return to shader part epilog247 %a1 = fadd float %a, 1.0248 %b2 = fadd float %b, 2.0249 %c3 = fadd float %c, 3.0250 %bc.a = bitcast float %a1 to i32251 %bc.b = bitcast float %b2 to i32252 %bc.c = bitcast float %c3 to i32253 %x = add i32 %bc.a, %bc.b254 %result = add i32 %x, %bc.c255 %bc = bitcast i32 %result to float256 ret float %bc257}258