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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI %s3 4define amdgpu_kernel void @test_i64_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {5; SI-LABEL: test_i64_vreg:6; SI: ; %bb.0:7; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x98; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd9; SI-NEXT: s_mov_b32 s11, 0xf00010; SI-NEXT: s_mov_b32 s14, 011; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v012; SI-NEXT: v_mov_b32_e32 v1, 013; SI-NEXT: s_mov_b32 s15, s1114; SI-NEXT: s_mov_b64 s[6:7], s[14:15]15; SI-NEXT: s_waitcnt lgkmcnt(0)16; SI-NEXT: s_mov_b64 s[12:13], s[2:3]17; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[12:15], 0 addr6418; SI-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr6419; SI-NEXT: s_mov_b32 s10, -120; SI-NEXT: s_mov_b32 s8, s021; SI-NEXT: s_mov_b32 s9, s122; SI-NEXT: s_waitcnt vmcnt(0)23; SI-NEXT: v_add_i32_e32 v0, vcc, v2, v024; SI-NEXT: v_addc_u32_e32 v1, vcc, v3, v1, vcc25; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 026; SI-NEXT: s_endpgm27 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone28 %a_ptr = getelementptr i64, ptr addrspace(1) %inA, i32 %tid29 %b_ptr = getelementptr i64, ptr addrspace(1) %inB, i32 %tid30 %a = load i64, ptr addrspace(1) %a_ptr31 %b = load i64, ptr addrspace(1) %b_ptr32 %result = add i64 %a, %b33 store i64 %result, ptr addrspace(1) %out34 ret void35}36 37; Check that the SGPR add operand is correctly moved to a VGPR.38define amdgpu_kernel void @sgpr_operand(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, ptr addrspace(1) noalias %in_bar, i64 %a) {39; SI-LABEL: sgpr_operand:40; SI: ; %bb.0:41; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x942; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xf43; SI-NEXT: s_waitcnt lgkmcnt(0)44; SI-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x045; SI-NEXT: s_mov_b32 s3, 0xf00046; SI-NEXT: s_waitcnt lgkmcnt(0)47; SI-NEXT: s_add_u32 s4, s6, s448; SI-NEXT: s_addc_u32 s5, s7, s549; SI-NEXT: s_mov_b32 s2, -150; SI-NEXT: v_mov_b32_e32 v0, s451; SI-NEXT: v_mov_b32_e32 v1, s552; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 053; SI-NEXT: s_endpgm54 %foo = load i64, ptr addrspace(1) %in, align 855 %result = add i64 %foo, %a56 store i64 %result, ptr addrspace(1) %out57 ret void58}59 60; Swap the arguments. Check that the SGPR -> VGPR copy works with the61; SGPR as other operand.62define amdgpu_kernel void @sgpr_operand_reversed(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in, i64 %a) {63; SI-LABEL: sgpr_operand_reversed:64; SI: ; %bb.0:65; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x966; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd67; SI-NEXT: s_waitcnt lgkmcnt(0)68; SI-NEXT: s_load_dwordx2 s[6:7], s[2:3], 0x069; SI-NEXT: s_mov_b32 s3, 0xf00070; SI-NEXT: s_waitcnt lgkmcnt(0)71; SI-NEXT: s_add_u32 s4, s4, s672; SI-NEXT: s_addc_u32 s5, s5, s773; SI-NEXT: s_mov_b32 s2, -174; SI-NEXT: v_mov_b32_e32 v0, s475; SI-NEXT: v_mov_b32_e32 v1, s576; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 077; SI-NEXT: s_endpgm78 %foo = load i64, ptr addrspace(1) %in, align 879 %result = add i64 %a, %foo80 store i64 %result, ptr addrspace(1) %out81 ret void82}83 84define amdgpu_kernel void @test_v2i64_sreg(ptr addrspace(1) noalias %out, <2 x i64> %a, <2 x i64> %b) {85; SI-LABEL: test_v2i64_sreg:86; SI: ; %bb.0:87; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd88; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x989; SI-NEXT: s_mov_b32 s3, 0xf00090; SI-NEXT: s_waitcnt lgkmcnt(0)91; SI-NEXT: s_add_u32 s4, s10, s1492; SI-NEXT: s_addc_u32 s5, s11, s1593; SI-NEXT: s_add_u32 s6, s8, s1294; SI-NEXT: s_addc_u32 s7, s9, s1395; SI-NEXT: s_mov_b32 s2, -196; SI-NEXT: v_mov_b32_e32 v2, s497; SI-NEXT: v_mov_b32_e32 v3, s598; SI-NEXT: v_mov_b32_e32 v0, s699; SI-NEXT: v_mov_b32_e32 v1, s7100; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0101; SI-NEXT: s_endpgm102 %result = add <2 x i64> %a, %b103 store <2 x i64> %result, ptr addrspace(1) %out104 ret void105}106 107define amdgpu_kernel void @test_v2i64_vreg(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {108; SI-LABEL: test_v2i64_vreg:109; SI: ; %bb.0:110; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9111; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd112; SI-NEXT: s_mov_b32 s11, 0xf000113; SI-NEXT: s_mov_b32 s14, 0114; SI-NEXT: v_lshlrev_b32_e32 v4, 4, v0115; SI-NEXT: v_mov_b32_e32 v5, 0116; SI-NEXT: s_mov_b32 s15, s11117; SI-NEXT: s_mov_b64 s[6:7], s[14:15]118; SI-NEXT: s_waitcnt lgkmcnt(0)119; SI-NEXT: s_mov_b64 s[12:13], s[2:3]120; SI-NEXT: buffer_load_dwordx4 v[0:3], v[4:5], s[12:15], 0 addr64121; SI-NEXT: buffer_load_dwordx4 v[4:7], v[4:5], s[4:7], 0 addr64122; SI-NEXT: s_mov_b32 s10, -1123; SI-NEXT: s_mov_b32 s8, s0124; SI-NEXT: s_mov_b32 s9, s1125; SI-NEXT: s_waitcnt vmcnt(0)126; SI-NEXT: v_add_i32_e32 v2, vcc, v2, v6127; SI-NEXT: v_addc_u32_e32 v3, vcc, v3, v7, vcc128; SI-NEXT: v_add_i32_e32 v0, vcc, v0, v4129; SI-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc130; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0131; SI-NEXT: s_endpgm132 %tid = call i32 @llvm.amdgcn.workitem.id.x() readnone133 %a_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inA, i32 %tid134 %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inB, i32 %tid135 %a = load <2 x i64>, ptr addrspace(1) %a_ptr136 %b = load <2 x i64>, ptr addrspace(1) %b_ptr137 %result = add <2 x i64> %a, %b138 store <2 x i64> %result, ptr addrspace(1) %out139 ret void140}141 142define amdgpu_kernel void @trunc_i64_add_to_i32(ptr addrspace(1) %out, i32, i64 %a, i32, i64 %b) {143; SI-LABEL: trunc_i64_add_to_i32:144; SI: ; %bb.0:145; SI-NEXT: s_load_dword s2, s[4:5], 0xd146; SI-NEXT: s_load_dword s6, s[4:5], 0x11147; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9148; SI-NEXT: s_mov_b32 s3, 0xf000149; SI-NEXT: s_waitcnt lgkmcnt(0)150; SI-NEXT: s_add_i32 s4, s6, s2151; SI-NEXT: s_mov_b32 s2, -1152; SI-NEXT: v_mov_b32_e32 v0, s4153; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0154; SI-NEXT: s_endpgm155 %add = add i64 %b, %a156 %trunc = trunc i64 %add to i32157 store i32 %trunc, ptr addrspace(1) %out, align 8158 ret void159}160