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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_ADD_LSHL_U329; ===================================================================================10 11define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: add_shl:13; VI: ; %bb.0:14; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v115; VI-NEXT: v_lshlrev_b32_e32 v0, v2, v016; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: add_shl:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: add_shl:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = add i32 %a, %b28 %result = shl i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) {34; VI-LABEL: add_shl_vgpr_c:35; VI: ; %bb.0:36; VI-NEXT: s_add_i32 s2, s2, s337; VI-NEXT: v_lshlrev_b32_e64 v0, v0, s238; VI-NEXT: ; return to shader part epilog39;40; GFX9-LABEL: add_shl_vgpr_c:41; GFX9: ; %bb.0:42; GFX9-NEXT: s_add_i32 s2, s2, s343; GFX9-NEXT: v_lshlrev_b32_e64 v0, v0, s244; GFX9-NEXT: ; return to shader part epilog45;46; GFX10-LABEL: add_shl_vgpr_c:47; GFX10: ; %bb.0:48; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v049; GFX10-NEXT: ; return to shader part epilog50 %x = add i32 %a, %b51 %result = shl i32 %x, %c52 %bc = bitcast i32 %result to float53 ret float %bc54}55 56define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) {57; VI-LABEL: add_shl_vgpr_ac:58; VI: ; %bb.0:59; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v060; VI-NEXT: v_lshlrev_b32_e32 v0, v1, v061; VI-NEXT: ; return to shader part epilog62;63; GFX9-LABEL: add_shl_vgpr_ac:64; GFX9: ; %bb.0:65; GFX9-NEXT: v_add_lshl_u32 v0, v0, s2, v166; GFX9-NEXT: ; return to shader part epilog67;68; GFX10-LABEL: add_shl_vgpr_ac:69; GFX10: ; %bb.0:70; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v171; GFX10-NEXT: ; return to shader part epilog72 %x = add i32 %a, %b73 %result = shl i32 %x, %c74 %bc = bitcast i32 %result to float75 ret float %bc76}77 78define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) {79; VI-LABEL: add_shl_vgpr_const:80; VI: ; %bb.0:81; VI-NEXT: v_add_u32_e32 v0, vcc, v0, v182; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v083; VI-NEXT: ; return to shader part epilog84;85; GFX9-LABEL: add_shl_vgpr_const:86; GFX9: ; %bb.0:87; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 988; GFX9-NEXT: ; return to shader part epilog89;90; GFX10-LABEL: add_shl_vgpr_const:91; GFX10: ; %bb.0:92; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 993; GFX10-NEXT: ; return to shader part epilog94 %x = add i32 %a, %b95 %result = shl i32 %x, 996 %bc = bitcast i32 %result to float97 ret float %bc98}99 100define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) {101; VI-LABEL: add_shl_vgpr_const_inline_const:102; VI: ; %bb.0:103; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0104; VI-NEXT: v_add_u32_e32 v0, vcc, 0x7e800, v0105; VI-NEXT: ; return to shader part epilog106;107; GFX9-LABEL: add_shl_vgpr_const_inline_const:108; GFX9: ; %bb.0:109; GFX9-NEXT: v_mov_b32_e32 v1, 0x7e800110; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1111; GFX9-NEXT: ; return to shader part epilog112;113; GFX10-LABEL: add_shl_vgpr_const_inline_const:114; GFX10: ; %bb.0:115; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800116; GFX10-NEXT: ; return to shader part epilog117 %x = add i32 %a, 1012118 %result = shl i32 %x, 9119 %bc = bitcast i32 %result to float120 ret float %bc121}122 123; TODO: Non-optimal code generation because SelectionDAG combines124; (shl (add x, CONST), y) ---> (add (shl x, y), CONST').125;126define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) {127; VI-LABEL: add_shl_vgpr_inline_const_x2:128; VI: ; %bb.0:129; VI-NEXT: v_lshlrev_b32_e32 v0, 9, v0130; VI-NEXT: v_add_u32_e32 v0, vcc, 0x600, v0131; VI-NEXT: ; return to shader part epilog132;133; GFX9-LABEL: add_shl_vgpr_inline_const_x2:134; GFX9: ; %bb.0:135; GFX9-NEXT: v_mov_b32_e32 v1, 0x600136; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1137; GFX9-NEXT: ; return to shader part epilog138;139; GFX10-LABEL: add_shl_vgpr_inline_const_x2:140; GFX10: ; %bb.0:141; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600142; GFX10-NEXT: ; return to shader part epilog143 %x = add i32 %a, 3144 %result = shl i32 %x, 9145 %bc = bitcast i32 %result to float146 ret float %bc147}148