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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX11 %s3# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX12 %s4# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=finalize-isel -o - %s | FileCheck -check-prefix=GFX11 %s5# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -passes=finalize-isel -o - %s | FileCheck -check-prefix=GFX12 %s6 7---8name: reg_ops9tracksRegLiveness: true10body: |11 bb.0:12 ; GFX11-LABEL: name: reg_ops13 ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF14 ; GFX11-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF15 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub016 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub117 ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub018 ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub119 ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY2]], implicit-def $scc20 ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], [[COPY3]], implicit-def $scc, implicit $scc21 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub122 ;23 ; GFX12-LABEL: name: reg_ops24 ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF25 ; GFX12-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF26 ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], [[DEF1]]27 %0:sreg_64 = IMPLICIT_DEF28 %1:sreg_64 = IMPLICIT_DEF29 %2:sreg_64 = S_ADD_U64_PSEUDO %0, %1, implicit-def $scc30...31 32---33name: lhs_imm34tracksRegLiveness: true35body: |36 bb.0:37 ; GFX11-LABEL: name: lhs_imm38 ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF39 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub040 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub141 ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 6565, [[COPY]], implicit-def $scc42 ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 0, [[COPY1]], implicit-def $scc, implicit $scc43 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub144 ;45 ; GFX12-LABEL: name: lhs_imm46 ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF47 ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 6565, [[DEF]]48 %0:sreg_64 = IMPLICIT_DEF49 %1:sreg_64 = S_ADD_U64_PSEUDO 6565, %0, implicit-def $scc50...51 52---53name: rhs_imm54tracksRegLiveness: true55body: |56 bb.0:57 ; GFX11-LABEL: name: rhs_imm58 ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF59 ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub060 ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub161 ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 6565, implicit-def $scc62 ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], 0, implicit-def $scc, implicit $scc63 ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub164 ;65 ; GFX12-LABEL: name: rhs_imm66 ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF67 ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], 656568 %0:sreg_64 = IMPLICIT_DEF69 %1:sreg_64 = S_ADD_U64_PSEUDO %0, 6565, implicit-def $scc70...71