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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GCN,GFX1250 %s4 5define amdgpu_ps <2 x float> @test_add_u64_vv(i64 %a, i64 %b) {6; GFX12-LABEL: test_add_u64_vv:7; GFX12: ; %bb.0:8; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v29; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)10; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo11; GFX12-NEXT: ; return to shader part epilog12;13; GFX1250-LABEL: test_add_u64_vv:14; GFX1250: ; %bb.0:15; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 116; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], v[0:1], v[2:3]17; GFX1250-NEXT: ; return to shader part epilog18 %add = add i64 %a, %b19 %ret = bitcast i64 %add to <2 x float>20 ret <2 x float> %ret21}22 23define amdgpu_ps <2 x float> @test_add_u64_vs(i64 %a, i64 inreg %b) {24; GFX12-LABEL: test_add_u64_vs:25; GFX12: ; %bb.0:26; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, s027; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)28; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo29; GFX12-NEXT: ; return to shader part epilog30;31; GFX1250-LABEL: test_add_u64_vs:32; GFX1250: ; %bb.0:33; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 134; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]35; GFX1250-NEXT: ; return to shader part epilog36 %add = add i64 %a, %b37 %ret = bitcast i64 %add to <2 x float>38 ret <2 x float> %ret39}40 41define amdgpu_ps <2 x float> @test_add_u64_sv(i64 inreg %a, i64 %b) {42; GFX12-LABEL: test_add_u64_sv:43; GFX12: ; %bb.0:44; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, s0, v045; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)46; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc_lo47; GFX12-NEXT: ; return to shader part epilog48;49; GFX1250-LABEL: test_add_u64_sv:50; GFX1250: ; %bb.0:51; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 152; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1]53; GFX1250-NEXT: ; return to shader part epilog54 %add = add i64 %a, %b55 %ret = bitcast i64 %add to <2 x float>56 ret <2 x float> %ret57}58 59define amdgpu_ps <2 x float> @test_add_u64_ss(i64 inreg %a, i64 inreg %b) {60; GFX12-LABEL: test_add_u64_ss:61; GFX12: ; %bb.0:62; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]63; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)64; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s165; GFX12-NEXT: ; return to shader part epilog66;67; GFX1250-LABEL: test_add_u64_ss:68; GFX1250: ; %bb.0:69; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 170; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3]71; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)72; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s173; GFX1250-NEXT: ; return to shader part epilog74 %add = add i64 %a, %b75 %ret = bitcast i64 %add to <2 x float>76 ret <2 x float> %ret77}78 79define amdgpu_ps <2 x float> @test_add_u64_v_inline_lit(i64 %a) {80; GFX12-LABEL: test_add_u64_v_inline_lit:81; GFX12: ; %bb.0:82; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, 583; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)84; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo85; GFX12-NEXT: ; return to shader part epilog86;87; GFX1250-LABEL: test_add_u64_v_inline_lit:88; GFX1250: ; %bb.0:89; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 190; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 5, v[0:1]91; GFX1250-NEXT: ; return to shader part epilog92 %add = add i64 %a, 593 %ret = bitcast i64 %add to <2 x float>94 ret <2 x float> %ret95}96 97define amdgpu_ps <2 x float> @test_add_u64_v_small_imm(i64 %a) {98; GFX12-LABEL: test_add_u64_v_small_imm:99; GFX12: ; %bb.0:100; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x1f4, v0101; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)102; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo103; GFX12-NEXT: ; return to shader part epilog104;105; GFX1250-LABEL: test_add_u64_v_small_imm:106; GFX1250: ; %bb.0:107; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1108; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 0x1f4, v[0:1]109; GFX1250-NEXT: ; return to shader part epilog110 %add = add i64 %a, 500111 %ret = bitcast i64 %add to <2 x float>112 ret <2 x float> %ret113}114 115define amdgpu_ps <2 x float> @test_add_u64_v_64bit_imm(i64 %a) {116; GFX12-LABEL: test_add_u64_v_64bit_imm:117; GFX12: ; %bb.0:118; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, 0x3b9ac9ff, v0119; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)120; GFX12-NEXT: v_add_co_ci_u32_e64 v1, null, 1, v1, vcc_lo121; GFX12-NEXT: ; return to shader part epilog122;123; GFX1250-LABEL: test_add_u64_v_64bit_imm:124; GFX1250: ; %bb.0:125; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1126; GFX1250-NEXT: v_add_nc_u64_e32 v[0:1], 0x13b9ac9ff, v[0:1]127; GFX1250-NEXT: ; return to shader part epilog128 %add = add i64 %a, 5294967295129 %ret = bitcast i64 %add to <2 x float>130 ret <2 x float> %ret131}132 133define amdgpu_ps <2 x float> @test_add_u64_s_small_imm(i64 inreg %a) {134; GFX12-LABEL: test_add_u64_s_small_imm:135; GFX12: ; %bb.0:136; GFX12-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4137; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)138; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1139; GFX12-NEXT: ; return to shader part epilog140;141; GFX1250-LABEL: test_add_u64_s_small_imm:142; GFX1250: ; %bb.0:143; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1144; GFX1250-NEXT: s_add_nc_u64 s[0:1], s[0:1], 0x1f4145; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)146; GFX1250-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1147; GFX1250-NEXT: ; return to shader part epilog148 %add = add i64 %a, 500149 %ret = bitcast i64 %add to <2 x float>150 ret <2 x float> %ret151}152;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:153; GCN: {{.*}}154