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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-SDAG %s3; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250,GFX1250-GISEL %s4 5; Test code sequences for addrspacecast with globally addressable scratch.6 7target triple = "amdgcn-amd-amdhsa"8 9define amdgpu_kernel void @use_private_to_flat_addrspacecast(ptr addrspace(5) %ptr) {10; GFX1250-SDAG-LABEL: use_private_to_flat_addrspacecast:11; GFX1250-SDAG: ; %bb.0:12; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 113; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2414; GFX1250-SDAG-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 015; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x016; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)17; GFX1250-SDAG-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_lshlrev_b32 v1, 20, v018; GFX1250-SDAG-NEXT: s_cmp_lg_u32 s0, -119; GFX1250-SDAG-NEXT: s_cselect_b32 vcc_lo, -1, 020; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], src_flat_scratch_base_lo, v[0:1]21; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_2)22; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0, v123; GFX1250-SDAG-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo24; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS25; GFX1250-SDAG-NEXT: s_wait_storecnt 0x026; GFX1250-SDAG-NEXT: s_endpgm27;28; GFX1250-GISEL-LABEL: use_private_to_flat_addrspacecast:29; GFX1250-GISEL: ; %bb.0:30; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 131; GFX1250-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2432; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], src_flat_scratch_base_lo33; GFX1250-GISEL-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 034; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x035; GFX1250-GISEL-NEXT: s_cmp_lg_u32 s0, -136; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)37; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, s0, v038; GFX1250-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v239; GFX1250-GISEL-NEXT: s_cselect_b32 s1, 1, 040; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)41; GFX1250-GISEL-NEXT: s_and_b32 s1, 1, s142; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v2, v1, vcc_lo43; GFX1250-GISEL-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s144; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)45; GFX1250-GISEL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_cndmask_b32 v1, 0, v146; GFX1250-GISEL-NEXT: v_cndmask_b32_e32 v0, 0, v0, vcc_lo47; GFX1250-GISEL-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS48; GFX1250-GISEL-NEXT: s_wait_storecnt 0x049; GFX1250-GISEL-NEXT: s_endpgm50 %stof = addrspacecast ptr addrspace(5) %ptr to ptr51 store volatile i32 0, ptr %stof52 ret void53}54 55define amdgpu_kernel void @use_private_to_flat_addrspacecast_nonnull(ptr addrspace(5) %ptr) {56; GFX1250-SDAG-LABEL: use_private_to_flat_addrspacecast_nonnull:57; GFX1250-SDAG: ; %bb.0:58; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 159; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x2460; GFX1250-SDAG-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 061; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)62; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 20, v063; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x064; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, s065; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], src_flat_scratch_base_lo, v[0:1]66; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS67; GFX1250-SDAG-NEXT: s_wait_storecnt 0x068; GFX1250-SDAG-NEXT: s_endpgm69;70; GFX1250-GISEL-LABEL: use_private_to_flat_addrspacecast_nonnull:71; GFX1250-GISEL: ; %bb.0:72; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 173; GFX1250-GISEL-NEXT: s_load_b32 s0, s[4:5], 0x2474; GFX1250-GISEL-NEXT: v_mbcnt_lo_u32_b32 v2, -1, 075; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], src_flat_scratch_base_lo76; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)77; GFX1250-GISEL-NEXT: v_lshlrev_b32_e32 v2, 20, v278; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x079; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, s0, v080; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1)81; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v2, v1, vcc_lo82; GFX1250-GISEL-NEXT: v_mov_b32_e32 v2, 083; GFX1250-GISEL-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS84; GFX1250-GISEL-NEXT: s_wait_storecnt 0x085; GFX1250-GISEL-NEXT: s_endpgm86 %stof = call ptr @llvm.amdgcn.addrspacecast.nonnull.p0.p5(ptr addrspace(5) %ptr)87 store volatile i32 0, ptr %stof88 ret void89}90 91define amdgpu_kernel void @use_flat_to_private_addrspacecast(ptr %ptr) {92; GFX1250-LABEL: use_flat_to_private_addrspacecast:93; GFX1250: ; %bb.0:94; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 195; GFX1250-NEXT: s_load_b64 s[0:1], s[4:5], 0x2496; GFX1250-NEXT: v_mov_b32_e32 v0, 097; GFX1250-NEXT: s_wait_kmcnt 0x098; GFX1250-NEXT: s_sub_co_i32 s2, s0, src_flat_scratch_base_lo99; GFX1250-NEXT: s_cmp_lg_u64 s[0:1], 0100; GFX1250-NEXT: s_cselect_b32 s0, s2, -1101; GFX1250-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS102; GFX1250-NEXT: s_wait_storecnt 0x0103; GFX1250-NEXT: s_endpgm104 %ftos = addrspacecast ptr %ptr to ptr addrspace(5)105 store volatile i32 0, ptr addrspace(5) %ftos106 ret void107}108 109define amdgpu_kernel void @use_flat_to_private_addrspacecast_nonnull(ptr %ptr) {110; GFX1250-SDAG-LABEL: use_flat_to_private_addrspacecast_nonnull:111; GFX1250-SDAG: ; %bb.0:112; GFX1250-SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1113; GFX1250-SDAG-NEXT: s_load_b32 s0, s[4:5], 0x24114; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0115; GFX1250-SDAG-NEXT: s_wait_kmcnt 0x0116; GFX1250-SDAG-NEXT: s_sub_co_i32 s0, s0, src_flat_scratch_base_lo117; GFX1250-SDAG-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS118; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0119; GFX1250-SDAG-NEXT: s_endpgm120;121; GFX1250-GISEL-LABEL: use_flat_to_private_addrspacecast_nonnull:122; GFX1250-GISEL: ; %bb.0:123; GFX1250-GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1124; GFX1250-GISEL-NEXT: s_load_b64 s[0:1], s[4:5], 0x24125; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0126; GFX1250-GISEL-NEXT: s_wait_kmcnt 0x0127; GFX1250-GISEL-NEXT: s_sub_co_i32 s0, s0, src_flat_scratch_base_lo128; GFX1250-GISEL-NEXT: scratch_store_b32 off, v0, s0 scope:SCOPE_SYS129; GFX1250-GISEL-NEXT: s_wait_storecnt 0x0130; GFX1250-GISEL-NEXT: s_endpgm131 %ftos = call ptr addrspace(5) @llvm.amdgcn.addrspacecast.nonnull.p5.p0(ptr %ptr)132 store volatile i32 0, ptr addrspace(5) %ftos133 ret void134}135