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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s3 4define amdgpu_kernel void @alignbit_shr_pat(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {5; GCN-LABEL: alignbit_shr_pat:6; GCN: ; %bb.0: ; %bb7; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x98; GCN-NEXT: s_load_dword s8, s[4:5], 0xd9; GCN-NEXT: s_mov_b32 s7, 0xf00010; GCN-NEXT: s_mov_b32 s6, -111; GCN-NEXT: s_waitcnt lgkmcnt(0)12; GCN-NEXT: s_mov_b32 s4, s013; GCN-NEXT: s_mov_b32 s5, s114; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 015; GCN-NEXT: s_mov_b32 s4, s216; GCN-NEXT: s_mov_b32 s5, s317; GCN-NEXT: s_and_b32 s0, s8, 3118; GCN-NEXT: s_waitcnt vmcnt(0)19; GCN-NEXT: v_lshr_b64 v[0:1], v[0:1], s020; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 021; GCN-NEXT: s_endpgm22bb:23 %tmp = load i64, ptr addrspace(1) %arg, align 824 %tmp3 = and i32 %arg2, 3125 %tmp4 = zext i32 %tmp3 to i6426 %tmp5 = lshr i64 %tmp, %tmp427 %tmp6 = trunc i64 %tmp5 to i3228 store i32 %tmp6, ptr addrspace(1) %arg1, align 429 ret void30}31 32define amdgpu_kernel void @alignbit_shr_pat_v(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {33; GCN-LABEL: alignbit_shr_pat_v:34; GCN: ; %bb.0: ; %bb35; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x936; GCN-NEXT: s_mov_b32 s7, 0xf00037; GCN-NEXT: s_mov_b32 s6, 038; GCN-NEXT: v_lshlrev_b32_e32 v1, 3, v039; GCN-NEXT: v_mov_b32_e32 v2, 040; GCN-NEXT: s_waitcnt lgkmcnt(0)41; GCN-NEXT: s_mov_b64 s[4:5], s[0:1]42; GCN-NEXT: buffer_load_dwordx2 v[3:4], v[1:2], s[4:7], 0 addr6443; GCN-NEXT: v_lshlrev_b32_e32 v1, 2, v044; GCN-NEXT: s_mov_b64 s[4:5], s[2:3]45; GCN-NEXT: buffer_load_dword v0, v[1:2], s[4:7], 0 addr6446; GCN-NEXT: s_waitcnt vmcnt(0)47; GCN-NEXT: v_alignbit_b32 v0, v4, v3, v048; GCN-NEXT: buffer_store_dword v0, v[1:2], s[4:7], 0 addr6449; GCN-NEXT: s_endpgm50bb:51 %tid = tail call i32 @llvm.amdgcn.workitem.id.x()52 %gep1 = getelementptr inbounds i64, ptr addrspace(1) %arg, i32 %tid53 %tmp = load i64, ptr addrspace(1) %gep1, align 854 %gep2 = getelementptr inbounds i32, ptr addrspace(1) %arg1, i32 %tid55 %amt = load i32, ptr addrspace(1) %gep2, align 456 %tmp3 = and i32 %amt, 3157 %tmp4 = zext i32 %tmp3 to i6458 %tmp5 = lshr i64 %tmp, %tmp459 %tmp6 = trunc i64 %tmp5 to i3260 store i32 %tmp6, ptr addrspace(1) %gep2, align 461 ret void62}63 64define amdgpu_kernel void @alignbit_shr_pat_wrong_and30(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {65; GCN-LABEL: alignbit_shr_pat_wrong_and30:66; GCN: ; %bb.0: ; %bb67; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x968; GCN-NEXT: s_load_dword s8, s[4:5], 0xd69; GCN-NEXT: s_mov_b32 s7, 0xf00070; GCN-NEXT: s_mov_b32 s6, -171; GCN-NEXT: s_waitcnt lgkmcnt(0)72; GCN-NEXT: s_mov_b32 s4, s073; GCN-NEXT: s_mov_b32 s5, s174; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 075; GCN-NEXT: s_mov_b32 s4, s276; GCN-NEXT: s_mov_b32 s5, s377; GCN-NEXT: s_and_b32 s0, s8, 3078; GCN-NEXT: s_waitcnt vmcnt(0)79; GCN-NEXT: v_lshr_b64 v[0:1], v[0:1], s080; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 081; GCN-NEXT: s_endpgm82bb:83 %tmp = load i64, ptr addrspace(1) %arg, align 884 %tmp3 = and i32 %arg2, 3085 %tmp4 = zext i32 %tmp3 to i6486 %tmp5 = lshr i64 %tmp, %tmp487 %tmp6 = trunc i64 %tmp5 to i3288 store i32 %tmp6, ptr addrspace(1) %arg1, align 489 ret void90}91 92define amdgpu_kernel void @alignbit_shr_pat_wrong_and63(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, i32 %arg2) {93; GCN-LABEL: alignbit_shr_pat_wrong_and63:94; GCN: ; %bb.0: ; %bb95; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x996; GCN-NEXT: s_load_dword s8, s[4:5], 0xd97; GCN-NEXT: s_mov_b32 s7, 0xf00098; GCN-NEXT: s_mov_b32 s6, -199; GCN-NEXT: s_waitcnt lgkmcnt(0)100; GCN-NEXT: s_mov_b32 s4, s0101; GCN-NEXT: s_mov_b32 s5, s1102; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0103; GCN-NEXT: s_mov_b32 s4, s2104; GCN-NEXT: s_mov_b32 s5, s3105; GCN-NEXT: s_waitcnt vmcnt(0)106; GCN-NEXT: v_lshr_b64 v[0:1], v[0:1], s8107; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0108; GCN-NEXT: s_endpgm109bb:110 %tmp = load i64, ptr addrspace(1) %arg, align 8111 %tmp3 = and i32 %arg2, 63112 %tmp4 = zext i32 %tmp3 to i64113 %tmp5 = lshr i64 %tmp, %tmp4114 %tmp6 = trunc i64 %tmp5 to i32115 store i32 %tmp6, ptr addrspace(1) %arg1, align 4116 ret void117}118 119define amdgpu_kernel void @alignbit_shr_pat_const30(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {120; GCN-LABEL: alignbit_shr_pat_const30:121; GCN: ; %bb.0: ; %bb122; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9123; GCN-NEXT: s_mov_b32 s7, 0xf000124; GCN-NEXT: s_mov_b32 s6, -1125; GCN-NEXT: s_waitcnt lgkmcnt(0)126; GCN-NEXT: s_mov_b32 s4, s0127; GCN-NEXT: s_mov_b32 s5, s1128; GCN-NEXT: buffer_load_dwordx2 v[0:1], off, s[4:7], 0129; GCN-NEXT: s_mov_b32 s4, s2130; GCN-NEXT: s_mov_b32 s5, s3131; GCN-NEXT: s_waitcnt vmcnt(0)132; GCN-NEXT: v_lshr_b64 v[0:1], v[0:1], 30133; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0134; GCN-NEXT: s_endpgm135bb:136 %tmp = load i64, ptr addrspace(1) %arg, align 8137 %tmp5 = lshr i64 %tmp, 30138 %tmp6 = trunc i64 %tmp5 to i32139 store i32 %tmp6, ptr addrspace(1) %arg1, align 4140 ret void141}142 143define amdgpu_kernel void @alignbit_shr_pat_wrong_const33(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {144; GCN-LABEL: alignbit_shr_pat_wrong_const33:145; GCN: ; %bb.0: ; %bb146; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9147; GCN-NEXT: s_mov_b32 s7, 0xf000148; GCN-NEXT: s_mov_b32 s6, -1149; GCN-NEXT: s_waitcnt lgkmcnt(0)150; GCN-NEXT: s_mov_b32 s4, s2151; GCN-NEXT: s_mov_b32 s5, s3152; GCN-NEXT: s_mov_b32 s2, s6153; GCN-NEXT: s_mov_b32 s3, s7154; GCN-NEXT: buffer_load_dword v0, off, s[0:3], 0 offset:4155; GCN-NEXT: s_waitcnt vmcnt(0)156; GCN-NEXT: v_lshrrev_b32_e32 v0, 1, v0157; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0158; GCN-NEXT: s_endpgm159bb:160 %tmp = load i64, ptr addrspace(1) %arg, align 8161 %tmp5 = lshr i64 %tmp, 33162 %tmp6 = trunc i64 %tmp5 to i32163 store i32 %tmp6, ptr addrspace(1) %arg1, align 4164 ret void165}166 167declare i32 @llvm.amdgcn.workitem.id.x() #0168 169attributes #0 = { nounwind readnone speculatable }170