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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <5 x float> @bitcast_v5i32_to_v5f32(<5 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v5i32_to_v5f32:11; SI:       ; %bb.0:12; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v514; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT:  ; %bb.1: ; %cmp.true18; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v419; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v320; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v221; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v122; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v023; SI-NEXT:  ; %bb.2: ; %end24; SI-NEXT:    s_or_b64 exec, exec, s[4:5]25; SI-NEXT:    s_setpc_b64 s[30:31]26;27; VI-LABEL: bitcast_v5i32_to_v5f32:28; VI:       ; %bb.0:29; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)30; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v531; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc32; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]33; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]34; VI-NEXT:  ; %bb.1: ; %cmp.true35; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v436; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v337; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v238; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v139; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v040; VI-NEXT:  ; %bb.2: ; %end41; VI-NEXT:    s_or_b64 exec, exec, s[4:5]42; VI-NEXT:    s_setpc_b64 s[30:31]43;44; GFX9-LABEL: bitcast_v5i32_to_v5f32:45; GFX9:       ; %bb.0:46; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)47; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v548; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc49; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]50; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]51; GFX9-NEXT:  ; %bb.1: ; %cmp.true52; GFX9-NEXT:    v_add_u32_e32 v4, 3, v453; GFX9-NEXT:    v_add_u32_e32 v3, 3, v354; GFX9-NEXT:    v_add_u32_e32 v2, 3, v255; GFX9-NEXT:    v_add_u32_e32 v1, 3, v156; GFX9-NEXT:    v_add_u32_e32 v0, 3, v057; GFX9-NEXT:  ; %bb.2: ; %end58; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]59; GFX9-NEXT:    s_setpc_b64 s[30:31]60;61; GFX11-LABEL: bitcast_v5i32_to_v5f32:62; GFX11:       ; %bb.0:63; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)64; GFX11-NEXT:    s_mov_b32 s0, exec_lo65; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v566; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s067; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)68; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s069; GFX11-NEXT:  ; %bb.1: ; %cmp.true70; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v471; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v372; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v273; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v174; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v075; GFX11-NEXT:  ; %bb.2: ; %end76; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s077; GFX11-NEXT:    s_setpc_b64 s[30:31]78  %cmp = icmp eq i32 %b, 079  br i1 %cmp, label %cmp.true, label %cmp.false80 81cmp.true:82  %a1 = add <5 x i32> %a, splat (i32 3)83  %a2 = bitcast <5 x i32> %a1 to <5 x float>84  br label %end85 86cmp.false:87  %a3 = bitcast <5 x i32> %a to <5 x float>88  br label %end89 90end:91  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]92  ret <5 x float> %phi93}94 95define inreg <5 x float> @bitcast_v5i32_to_v5f32_scalar(<5 x i32> inreg %a, i32 inreg %b) {96; SI-LABEL: bitcast_v5i32_to_v5f32_scalar:97; SI:       ; %bb.0:98; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)99; SI-NEXT:    s_cmp_lg_u32 s21, 0100; SI-NEXT:    s_cbranch_scc0 .LBB1_4101; SI-NEXT:  ; %bb.1: ; %cmp.false102; SI-NEXT:    s_cbranch_execnz .LBB1_3103; SI-NEXT:  .LBB1_2: ; %cmp.true104; SI-NEXT:    s_add_i32 s20, s20, 3105; SI-NEXT:    s_add_i32 s19, s19, 3106; SI-NEXT:    s_add_i32 s18, s18, 3107; SI-NEXT:    s_add_i32 s17, s17, 3108; SI-NEXT:    s_add_i32 s16, s16, 3109; SI-NEXT:  .LBB1_3: ; %end110; SI-NEXT:    v_mov_b32_e32 v0, s16111; SI-NEXT:    v_mov_b32_e32 v1, s17112; SI-NEXT:    v_mov_b32_e32 v2, s18113; SI-NEXT:    v_mov_b32_e32 v3, s19114; SI-NEXT:    v_mov_b32_e32 v4, s20115; SI-NEXT:    s_setpc_b64 s[30:31]116; SI-NEXT:  .LBB1_4:117; SI-NEXT:    s_branch .LBB1_2118;119; VI-LABEL: bitcast_v5i32_to_v5f32_scalar:120; VI:       ; %bb.0:121; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)122; VI-NEXT:    s_cmp_lg_u32 s21, 0123; VI-NEXT:    s_cbranch_scc0 .LBB1_4124; VI-NEXT:  ; %bb.1: ; %cmp.false125; VI-NEXT:    s_cbranch_execnz .LBB1_3126; VI-NEXT:  .LBB1_2: ; %cmp.true127; VI-NEXT:    s_add_i32 s20, s20, 3128; VI-NEXT:    s_add_i32 s19, s19, 3129; VI-NEXT:    s_add_i32 s18, s18, 3130; VI-NEXT:    s_add_i32 s17, s17, 3131; VI-NEXT:    s_add_i32 s16, s16, 3132; VI-NEXT:  .LBB1_3: ; %end133; VI-NEXT:    v_mov_b32_e32 v0, s16134; VI-NEXT:    v_mov_b32_e32 v1, s17135; VI-NEXT:    v_mov_b32_e32 v2, s18136; VI-NEXT:    v_mov_b32_e32 v3, s19137; VI-NEXT:    v_mov_b32_e32 v4, s20138; VI-NEXT:    s_setpc_b64 s[30:31]139; VI-NEXT:  .LBB1_4:140; VI-NEXT:    s_branch .LBB1_2141;142; GFX9-LABEL: bitcast_v5i32_to_v5f32_scalar:143; GFX9:       ; %bb.0:144; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; GFX9-NEXT:    s_cmp_lg_u32 s21, 0146; GFX9-NEXT:    s_cbranch_scc0 .LBB1_4147; GFX9-NEXT:  ; %bb.1: ; %cmp.false148; GFX9-NEXT:    s_cbranch_execnz .LBB1_3149; GFX9-NEXT:  .LBB1_2: ; %cmp.true150; GFX9-NEXT:    s_add_i32 s20, s20, 3151; GFX9-NEXT:    s_add_i32 s19, s19, 3152; GFX9-NEXT:    s_add_i32 s18, s18, 3153; GFX9-NEXT:    s_add_i32 s17, s17, 3154; GFX9-NEXT:    s_add_i32 s16, s16, 3155; GFX9-NEXT:  .LBB1_3: ; %end156; GFX9-NEXT:    v_mov_b32_e32 v0, s16157; GFX9-NEXT:    v_mov_b32_e32 v1, s17158; GFX9-NEXT:    v_mov_b32_e32 v2, s18159; GFX9-NEXT:    v_mov_b32_e32 v3, s19160; GFX9-NEXT:    v_mov_b32_e32 v4, s20161; GFX9-NEXT:    s_setpc_b64 s[30:31]162; GFX9-NEXT:  .LBB1_4:163; GFX9-NEXT:    s_branch .LBB1_2164;165; GFX11-LABEL: bitcast_v5i32_to_v5f32_scalar:166; GFX11:       ; %bb.0:167; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)168; GFX11-NEXT:    s_cmp_lg_u32 s17, 0169; GFX11-NEXT:    s_mov_b32 s4, 0170; GFX11-NEXT:    s_cbranch_scc0 .LBB1_4171; GFX11-NEXT:  ; %bb.1: ; %Flow172; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s4173; GFX11-NEXT:    s_cbranch_vccnz .LBB1_3174; GFX11-NEXT:  .LBB1_2: ; %cmp.true175; GFX11-NEXT:    s_add_i32 s16, s16, 3176; GFX11-NEXT:    s_add_i32 s3, s3, 3177; GFX11-NEXT:    s_add_i32 s2, s2, 3178; GFX11-NEXT:    s_add_i32 s1, s1, 3179; GFX11-NEXT:    s_add_i32 s0, s0, 3180; GFX11-NEXT:  .LBB1_3: ; %end181; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)182; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1183; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3184; GFX11-NEXT:    v_mov_b32_e32 v4, s16185; GFX11-NEXT:    s_setpc_b64 s[30:31]186; GFX11-NEXT:  .LBB1_4:187; GFX11-NEXT:    s_branch .LBB1_2188  %cmp = icmp eq i32 %b, 0189  br i1 %cmp, label %cmp.true, label %cmp.false190 191cmp.true:192  %a1 = add <5 x i32> %a, splat (i32 3)193  %a2 = bitcast <5 x i32> %a1 to <5 x float>194  br label %end195 196cmp.false:197  %a3 = bitcast <5 x i32> %a to <5 x float>198  br label %end199 200end:201  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]202  ret <5 x float> %phi203}204 205define <5 x i32> @bitcast_v5f32_to_v5i32(<5 x float> %a, i32 %b) {206; SI-LABEL: bitcast_v5f32_to_v5i32:207; SI:       ; %bb.0:208; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5210; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc211; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]212; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]213; SI-NEXT:  ; %bb.1: ; %cmp.true214; SI-NEXT:    v_add_f32_e32 v4, 1.0, v4215; SI-NEXT:    v_add_f32_e32 v3, 1.0, v3216; SI-NEXT:    v_add_f32_e32 v2, 1.0, v2217; SI-NEXT:    v_add_f32_e32 v1, 1.0, v1218; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0219; SI-NEXT:  ; %bb.2: ; %end220; SI-NEXT:    s_or_b64 exec, exec, s[4:5]221; SI-NEXT:    s_setpc_b64 s[30:31]222;223; VI-LABEL: bitcast_v5f32_to_v5i32:224; VI:       ; %bb.0:225; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)226; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5227; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc228; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]229; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]230; VI-NEXT:  ; %bb.1: ; %cmp.true231; VI-NEXT:    v_add_f32_e32 v4, 1.0, v4232; VI-NEXT:    v_add_f32_e32 v3, 1.0, v3233; VI-NEXT:    v_add_f32_e32 v2, 1.0, v2234; VI-NEXT:    v_add_f32_e32 v1, 1.0, v1235; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0236; VI-NEXT:  ; %bb.2: ; %end237; VI-NEXT:    s_or_b64 exec, exec, s[4:5]238; VI-NEXT:    s_setpc_b64 s[30:31]239;240; GFX9-LABEL: bitcast_v5f32_to_v5i32:241; GFX9:       ; %bb.0:242; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)243; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5244; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc245; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]246; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]247; GFX9-NEXT:  ; %bb.1: ; %cmp.true248; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v4249; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v3250; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v2251; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1252; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0253; GFX9-NEXT:  ; %bb.2: ; %end254; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]255; GFX9-NEXT:    s_setpc_b64 s[30:31]256;257; GFX11-LABEL: bitcast_v5f32_to_v5i32:258; GFX11:       ; %bb.0:259; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)260; GFX11-NEXT:    s_mov_b32 s0, exec_lo261; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v5262; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0263; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)264; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0265; GFX11-NEXT:  ; %bb.1: ; %cmp.true266; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3267; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1268; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0269; GFX11-NEXT:  ; %bb.2: ; %end270; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0271; GFX11-NEXT:    s_setpc_b64 s[30:31]272  %cmp = icmp eq i32 %b, 0273  br i1 %cmp, label %cmp.true, label %cmp.false274 275cmp.true:276  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)277  %a2 = bitcast <5 x float> %a1 to <5 x i32>278  br label %end279 280cmp.false:281  %a3 = bitcast <5 x float> %a to <5 x i32>282  br label %end283 284end:285  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]286  ret <5 x i32> %phi287}288 289define inreg <5 x i32> @bitcast_v5f32_to_v5i32_scalar(<5 x float> inreg %a, i32 inreg %b) {290; SI-LABEL: bitcast_v5f32_to_v5i32_scalar:291; SI:       ; %bb.0:292; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)293; SI-NEXT:    s_cmp_lg_u32 s21, 0294; SI-NEXT:    s_cbranch_scc0 .LBB3_3295; SI-NEXT:  ; %bb.1: ; %cmp.false296; SI-NEXT:    s_cbranch_execnz .LBB3_4297; SI-NEXT:  .LBB3_2: ; %cmp.true298; SI-NEXT:    v_add_f32_e64 v4, s20, 1.0299; SI-NEXT:    v_add_f32_e64 v3, s19, 1.0300; SI-NEXT:    v_add_f32_e64 v2, s18, 1.0301; SI-NEXT:    v_add_f32_e64 v1, s17, 1.0302; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0303; SI-NEXT:    s_setpc_b64 s[30:31]304; SI-NEXT:  .LBB3_3:305; SI-NEXT:    s_branch .LBB3_2306; SI-NEXT:  .LBB3_4:307; SI-NEXT:    v_mov_b32_e32 v0, s16308; SI-NEXT:    v_mov_b32_e32 v1, s17309; SI-NEXT:    v_mov_b32_e32 v2, s18310; SI-NEXT:    v_mov_b32_e32 v3, s19311; SI-NEXT:    v_mov_b32_e32 v4, s20312; SI-NEXT:    s_setpc_b64 s[30:31]313;314; VI-LABEL: bitcast_v5f32_to_v5i32_scalar:315; VI:       ; %bb.0:316; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)317; VI-NEXT:    s_cmp_lg_u32 s21, 0318; VI-NEXT:    s_cbranch_scc0 .LBB3_3319; VI-NEXT:  ; %bb.1: ; %cmp.false320; VI-NEXT:    s_cbranch_execnz .LBB3_4321; VI-NEXT:  .LBB3_2: ; %cmp.true322; VI-NEXT:    v_add_f32_e64 v4, s20, 1.0323; VI-NEXT:    v_add_f32_e64 v3, s19, 1.0324; VI-NEXT:    v_add_f32_e64 v2, s18, 1.0325; VI-NEXT:    v_add_f32_e64 v1, s17, 1.0326; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0327; VI-NEXT:    s_setpc_b64 s[30:31]328; VI-NEXT:  .LBB3_3:329; VI-NEXT:    s_branch .LBB3_2330; VI-NEXT:  .LBB3_4:331; VI-NEXT:    v_mov_b32_e32 v0, s16332; VI-NEXT:    v_mov_b32_e32 v1, s17333; VI-NEXT:    v_mov_b32_e32 v2, s18334; VI-NEXT:    v_mov_b32_e32 v3, s19335; VI-NEXT:    v_mov_b32_e32 v4, s20336; VI-NEXT:    s_setpc_b64 s[30:31]337;338; GFX9-LABEL: bitcast_v5f32_to_v5i32_scalar:339; GFX9:       ; %bb.0:340; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; GFX9-NEXT:    s_cmp_lg_u32 s21, 0342; GFX9-NEXT:    s_cbranch_scc0 .LBB3_3343; GFX9-NEXT:  ; %bb.1: ; %cmp.false344; GFX9-NEXT:    s_cbranch_execnz .LBB3_4345; GFX9-NEXT:  .LBB3_2: ; %cmp.true346; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.0347; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.0348; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.0349; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.0350; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0351; GFX9-NEXT:    s_setpc_b64 s[30:31]352; GFX9-NEXT:  .LBB3_3:353; GFX9-NEXT:    s_branch .LBB3_2354; GFX9-NEXT:  .LBB3_4:355; GFX9-NEXT:    v_mov_b32_e32 v0, s16356; GFX9-NEXT:    v_mov_b32_e32 v1, s17357; GFX9-NEXT:    v_mov_b32_e32 v2, s18358; GFX9-NEXT:    v_mov_b32_e32 v3, s19359; GFX9-NEXT:    v_mov_b32_e32 v4, s20360; GFX9-NEXT:    s_setpc_b64 s[30:31]361;362; GFX11-LABEL: bitcast_v5f32_to_v5i32_scalar:363; GFX11:       ; %bb.0:364; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)365; GFX11-NEXT:    s_mov_b32 s4, s16366; GFX11-NEXT:    s_cmp_lg_u32 s17, 0367; GFX11-NEXT:    s_mov_b32 s5, 0368; GFX11-NEXT:    s_cbranch_scc0 .LBB3_3369; GFX11-NEXT:  ; %bb.1: ; %Flow370; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s5371; GFX11-NEXT:    s_cbranch_vccnz .LBB3_4372; GFX11-NEXT:  .LBB3_2: ; %cmp.true373; GFX11-NEXT:    v_add_f32_e64 v4, s4, 1.0374; GFX11-NEXT:    v_add_f32_e64 v3, s3, 1.0375; GFX11-NEXT:    v_add_f32_e64 v2, s2, 1.0376; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.0377; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.0378; GFX11-NEXT:    s_setpc_b64 s[30:31]379; GFX11-NEXT:  .LBB3_3:380; GFX11-NEXT:    s_branch .LBB3_2381; GFX11-NEXT:  .LBB3_4:382; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1383; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3384; GFX11-NEXT:    v_mov_b32_e32 v4, s4385; GFX11-NEXT:    s_setpc_b64 s[30:31]386  %cmp = icmp eq i32 %b, 0387  br i1 %cmp, label %cmp.true, label %cmp.false388 389cmp.true:390  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)391  %a2 = bitcast <5 x float> %a1 to <5 x i32>392  br label %end393 394cmp.false:395  %a3 = bitcast <5 x float> %a to <5 x i32>396  br label %end397 398end:399  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]400  ret <5 x i32> %phi401}402 403define <10 x i16> @bitcast_v5i32_to_v10i16(<5 x i32> %a, i32 %b) {404; SI-LABEL: bitcast_v5i32_to_v10i16:405; SI:       ; %bb.0:406; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)407; SI-NEXT:    v_mov_b32_e32 v8, v4408; SI-NEXT:    v_mov_b32_e32 v6, v3409; SI-NEXT:    v_mov_b32_e32 v4, v2410; SI-NEXT:    v_mov_b32_e32 v2, v1411; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5412; SI-NEXT:    ; implicit-def: $vgpr1413; SI-NEXT:    ; implicit-def: $vgpr3414; SI-NEXT:    ; implicit-def: $vgpr5415; SI-NEXT:    ; implicit-def: $vgpr7416; SI-NEXT:    ; implicit-def: $vgpr9417; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc418; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]419; SI-NEXT:    s_cbranch_execnz .LBB4_3420; SI-NEXT:  ; %bb.1: ; %Flow421; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]422; SI-NEXT:    s_cbranch_execnz .LBB4_4423; SI-NEXT:  .LBB4_2: ; %end424; SI-NEXT:    s_or_b64 exec, exec, s[4:5]425; SI-NEXT:    s_setpc_b64 s[30:31]426; SI-NEXT:  .LBB4_3: ; %cmp.false427; SI-NEXT:    v_alignbit_b32 v9, v0, v8, 16428; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 16429; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16430; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v6431; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2432; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]433; SI-NEXT:    s_cbranch_execz .LBB4_2434; SI-NEXT:  .LBB4_4: ; %cmp.true435; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v8436; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v2437; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0438; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v6439; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v4440; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 16441; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 16442; SI-NEXT:    v_alignbit_b32 v9, v0, v8, 16443; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v6444; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v2445; SI-NEXT:    s_or_b64 exec, exec, s[4:5]446; SI-NEXT:    s_setpc_b64 s[30:31]447;448; VI-LABEL: bitcast_v5i32_to_v10i16:449; VI:       ; %bb.0:450; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)451; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5452; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc453; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]454; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]455; VI-NEXT:  ; %bb.1: ; %cmp.true456; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v4457; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v3458; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v2459; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v1460; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0461; VI-NEXT:  ; %bb.2: ; %end462; VI-NEXT:    s_or_b64 exec, exec, s[4:5]463; VI-NEXT:    s_setpc_b64 s[30:31]464;465; GFX9-LABEL: bitcast_v5i32_to_v10i16:466; GFX9:       ; %bb.0:467; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)468; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5469; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc470; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]471; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]472; GFX9-NEXT:  ; %bb.1: ; %cmp.true473; GFX9-NEXT:    v_add_u32_e32 v4, 3, v4474; GFX9-NEXT:    v_add_u32_e32 v3, 3, v3475; GFX9-NEXT:    v_add_u32_e32 v2, 3, v2476; GFX9-NEXT:    v_add_u32_e32 v1, 3, v1477; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0478; GFX9-NEXT:  ; %bb.2: ; %end479; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]480; GFX9-NEXT:    s_setpc_b64 s[30:31]481;482; GFX11-LABEL: bitcast_v5i32_to_v10i16:483; GFX11:       ; %bb.0:484; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)485; GFX11-NEXT:    s_mov_b32 s0, exec_lo486; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v5487; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0488; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)489; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0490; GFX11-NEXT:  ; %bb.1: ; %cmp.true491; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v4492; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v3493; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v2494; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v1495; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0496; GFX11-NEXT:  ; %bb.2: ; %end497; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0498; GFX11-NEXT:    s_setpc_b64 s[30:31]499  %cmp = icmp eq i32 %b, 0500  br i1 %cmp, label %cmp.true, label %cmp.false501 502cmp.true:503  %a1 = add <5 x i32> %a, splat (i32 3)504  %a2 = bitcast <5 x i32> %a1 to <10 x i16>505  br label %end506 507cmp.false:508  %a3 = bitcast <5 x i32> %a to <10 x i16>509  br label %end510 511end:512  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]513  ret <10 x i16> %phi514}515 516define inreg <10 x i16> @bitcast_v5i32_to_v10i16_scalar(<5 x i32> inreg %a, i32 inreg %b) {517; SI-LABEL: bitcast_v5i32_to_v10i16_scalar:518; SI:       ; %bb.0:519; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)520; SI-NEXT:    s_cmp_lg_u32 s21, 0521; SI-NEXT:    s_cbranch_scc0 .LBB5_4522; SI-NEXT:  ; %bb.1: ; %cmp.false523; SI-NEXT:    s_lshr_b32 s12, s19, 16524; SI-NEXT:    s_lshr_b32 s13, s17, 16525; SI-NEXT:    s_lshr_b64 s[6:7], s[20:21], 16526; SI-NEXT:    s_lshr_b64 s[4:5], s[18:19], 16527; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 16528; SI-NEXT:    s_cbranch_execnz .LBB5_3529; SI-NEXT:  .LBB5_2: ; %cmp.true530; SI-NEXT:    s_add_i32 s20, s20, 3531; SI-NEXT:    s_add_i32 s17, s17, 3532; SI-NEXT:    s_add_i32 s16, s16, 3533; SI-NEXT:    s_add_i32 s19, s19, 3534; SI-NEXT:    s_add_i32 s18, s18, 3535; SI-NEXT:    s_lshr_b64 s[4:5], s[18:19], 16536; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 16537; SI-NEXT:    s_lshr_b32 s12, s19, 16538; SI-NEXT:    s_lshr_b32 s13, s17, 16539; SI-NEXT:    s_lshr_b64 s[6:7], s[20:21], 16540; SI-NEXT:  .LBB5_3: ; %end541; SI-NEXT:    v_mov_b32_e32 v0, s16542; SI-NEXT:    v_mov_b32_e32 v1, s8543; SI-NEXT:    v_mov_b32_e32 v2, s17544; SI-NEXT:    v_mov_b32_e32 v3, s13545; SI-NEXT:    v_mov_b32_e32 v4, s18546; SI-NEXT:    v_mov_b32_e32 v5, s4547; SI-NEXT:    v_mov_b32_e32 v6, s19548; SI-NEXT:    v_mov_b32_e32 v7, s12549; SI-NEXT:    v_mov_b32_e32 v8, s20550; SI-NEXT:    v_mov_b32_e32 v9, s6551; SI-NEXT:    s_setpc_b64 s[30:31]552; SI-NEXT:  .LBB5_4:553; SI-NEXT:    ; implicit-def: $sgpr8554; SI-NEXT:    ; implicit-def: $sgpr13555; SI-NEXT:    ; implicit-def: $sgpr4556; SI-NEXT:    ; implicit-def: $sgpr12557; SI-NEXT:    ; implicit-def: $sgpr6558; SI-NEXT:    s_branch .LBB5_2559;560; VI-LABEL: bitcast_v5i32_to_v10i16_scalar:561; VI:       ; %bb.0:562; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)563; VI-NEXT:    s_cmp_lg_u32 s21, 0564; VI-NEXT:    s_cbranch_scc0 .LBB5_4565; VI-NEXT:  ; %bb.1: ; %cmp.false566; VI-NEXT:    s_cbranch_execnz .LBB5_3567; VI-NEXT:  .LBB5_2: ; %cmp.true568; VI-NEXT:    s_add_i32 s20, s20, 3569; VI-NEXT:    s_add_i32 s19, s19, 3570; VI-NEXT:    s_add_i32 s18, s18, 3571; VI-NEXT:    s_add_i32 s17, s17, 3572; VI-NEXT:    s_add_i32 s16, s16, 3573; VI-NEXT:  .LBB5_3: ; %end574; VI-NEXT:    v_mov_b32_e32 v0, s16575; VI-NEXT:    v_mov_b32_e32 v1, s17576; VI-NEXT:    v_mov_b32_e32 v2, s18577; VI-NEXT:    v_mov_b32_e32 v3, s19578; VI-NEXT:    v_mov_b32_e32 v4, s20579; VI-NEXT:    s_setpc_b64 s[30:31]580; VI-NEXT:  .LBB5_4:581; VI-NEXT:    s_branch .LBB5_2582;583; GFX9-LABEL: bitcast_v5i32_to_v10i16_scalar:584; GFX9:       ; %bb.0:585; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)586; GFX9-NEXT:    s_cmp_lg_u32 s21, 0587; GFX9-NEXT:    s_cbranch_scc0 .LBB5_4588; GFX9-NEXT:  ; %bb.1: ; %cmp.false589; GFX9-NEXT:    s_cbranch_execnz .LBB5_3590; GFX9-NEXT:  .LBB5_2: ; %cmp.true591; GFX9-NEXT:    s_add_i32 s20, s20, 3592; GFX9-NEXT:    s_add_i32 s19, s19, 3593; GFX9-NEXT:    s_add_i32 s18, s18, 3594; GFX9-NEXT:    s_add_i32 s17, s17, 3595; GFX9-NEXT:    s_add_i32 s16, s16, 3596; GFX9-NEXT:  .LBB5_3: ; %end597; GFX9-NEXT:    v_mov_b32_e32 v0, s16598; GFX9-NEXT:    v_mov_b32_e32 v1, s17599; GFX9-NEXT:    v_mov_b32_e32 v2, s18600; GFX9-NEXT:    v_mov_b32_e32 v3, s19601; GFX9-NEXT:    v_mov_b32_e32 v4, s20602; GFX9-NEXT:    s_setpc_b64 s[30:31]603; GFX9-NEXT:  .LBB5_4:604; GFX9-NEXT:    s_branch .LBB5_2605;606; GFX11-LABEL: bitcast_v5i32_to_v10i16_scalar:607; GFX11:       ; %bb.0:608; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)609; GFX11-NEXT:    s_cmp_lg_u32 s17, 0610; GFX11-NEXT:    s_mov_b32 s4, 0611; GFX11-NEXT:    s_cbranch_scc0 .LBB5_4612; GFX11-NEXT:  ; %bb.1: ; %Flow613; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s4614; GFX11-NEXT:    s_cbranch_vccnz .LBB5_3615; GFX11-NEXT:  .LBB5_2: ; %cmp.true616; GFX11-NEXT:    s_add_i32 s16, s16, 3617; GFX11-NEXT:    s_add_i32 s3, s3, 3618; GFX11-NEXT:    s_add_i32 s2, s2, 3619; GFX11-NEXT:    s_add_i32 s1, s1, 3620; GFX11-NEXT:    s_add_i32 s0, s0, 3621; GFX11-NEXT:  .LBB5_3: ; %end622; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)623; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1624; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3625; GFX11-NEXT:    v_mov_b32_e32 v4, s16626; GFX11-NEXT:    s_setpc_b64 s[30:31]627; GFX11-NEXT:  .LBB5_4:628; GFX11-NEXT:    s_branch .LBB5_2629  %cmp = icmp eq i32 %b, 0630  br i1 %cmp, label %cmp.true, label %cmp.false631 632cmp.true:633  %a1 = add <5 x i32> %a, splat (i32 3)634  %a2 = bitcast <5 x i32> %a1 to <10 x i16>635  br label %end636 637cmp.false:638  %a3 = bitcast <5 x i32> %a to <10 x i16>639  br label %end640 641end:642  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]643  ret <10 x i16> %phi644}645 646define <5 x i32> @bitcast_v10i16_to_v5i32(<10 x i16> %a, i32 %b) {647; SI-LABEL: bitcast_v10i16_to_v5i32:648; SI:       ; %bb.0:649; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)650; SI-NEXT:    v_mov_b32_e32 v13, v4651; SI-NEXT:    v_mov_b32_e32 v12, v2652; SI-NEXT:    v_mov_b32_e32 v11, v0653; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v10654; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v1655; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v3656; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v5657; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v7658; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v9659; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4660; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc661; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]662; SI-NEXT:    s_cbranch_execnz .LBB6_3663; SI-NEXT:  ; %bb.1: ; %Flow664; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]665; SI-NEXT:    s_cbranch_execnz .LBB6_4666; SI-NEXT:  .LBB6_2: ; %end667; SI-NEXT:    s_or_b64 exec, exec, s[4:5]668; SI-NEXT:    s_setpc_b64 s[30:31]669; SI-NEXT:  .LBB6_3: ; %cmp.false670; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v11671; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v12672; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v13673; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v6674; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v8675; SI-NEXT:    v_or_b32_e32 v0, v0, v15676; SI-NEXT:    v_or_b32_e32 v1, v1, v14677; SI-NEXT:    v_or_b32_e32 v2, v2, v10678; SI-NEXT:    v_or_b32_e32 v3, v3, v7679; SI-NEXT:    v_or_b32_e32 v4, v4, v5680; SI-NEXT:    ; implicit-def: $vgpr11681; SI-NEXT:    ; implicit-def: $vgpr12682; SI-NEXT:    ; implicit-def: $vgpr13683; SI-NEXT:    ; implicit-def: $vgpr6684; SI-NEXT:    ; implicit-def: $vgpr8685; SI-NEXT:    ; implicit-def: $vgpr15686; SI-NEXT:    ; implicit-def: $vgpr14687; SI-NEXT:    ; implicit-def: $vgpr10688; SI-NEXT:    ; implicit-def: $vgpr7689; SI-NEXT:    ; implicit-def: $vgpr5690; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]691; SI-NEXT:    s_cbranch_execz .LBB6_2692; SI-NEXT:  .LBB6_4: ; %cmp.true693; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v11694; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v12695; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v13696; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v6697; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v8698; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0699; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v1700; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v2701; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v3702; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v4703; SI-NEXT:    v_or_b32_e32 v0, v15, v0704; SI-NEXT:    s_mov_b32 s6, 0x30000705; SI-NEXT:    v_or_b32_e32 v1, v14, v1706; SI-NEXT:    v_or_b32_e32 v2, v10, v2707; SI-NEXT:    v_or_b32_e32 v3, v7, v3708; SI-NEXT:    v_or_b32_e32 v4, v5, v4709; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0710; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v1711; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v2712; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v3713; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v4714; SI-NEXT:    s_or_b64 exec, exec, s[4:5]715; SI-NEXT:    s_setpc_b64 s[30:31]716;717; VI-LABEL: bitcast_v10i16_to_v5i32:718; VI:       ; %bb.0:719; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)720; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5721; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc722; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]723; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]724; VI-NEXT:    s_cbranch_execz .LBB6_2725; VI-NEXT:  ; %bb.1: ; %cmp.true726; VI-NEXT:    v_mov_b32_e32 v6, 3727; VI-NEXT:    v_add_u16_e32 v5, 3, v4728; VI-NEXT:    v_add_u16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD729; VI-NEXT:    v_or_b32_e32 v4, v5, v4730; VI-NEXT:    v_add_u16_e32 v5, 3, v3731; VI-NEXT:    v_add_u16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD732; VI-NEXT:    v_or_b32_e32 v3, v5, v3733; VI-NEXT:    v_add_u16_e32 v5, 3, v2734; VI-NEXT:    v_add_u16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD735; VI-NEXT:    v_or_b32_e32 v2, v5, v2736; VI-NEXT:    v_add_u16_e32 v5, 3, v1737; VI-NEXT:    v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD738; VI-NEXT:    v_or_b32_e32 v1, v5, v1739; VI-NEXT:    v_add_u16_e32 v5, 3, v0740; VI-NEXT:    v_add_u16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD741; VI-NEXT:    v_or_b32_e32 v0, v5, v0742; VI-NEXT:  .LBB6_2: ; %end743; VI-NEXT:    s_or_b64 exec, exec, s[4:5]744; VI-NEXT:    s_setpc_b64 s[30:31]745;746; GFX9-LABEL: bitcast_v10i16_to_v5i32:747; GFX9:       ; %bb.0:748; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)749; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5750; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc751; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]752; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]753; GFX9-NEXT:  ; %bb.1: ; %cmp.true754; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]755; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]756; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]757; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]758; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]759; GFX9-NEXT:  ; %bb.2: ; %end760; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]761; GFX9-NEXT:    s_setpc_b64 s[30:31]762;763; GFX11-LABEL: bitcast_v10i16_to_v5i32:764; GFX11:       ; %bb.0:765; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)766; GFX11-NEXT:    s_mov_b32 s0, exec_lo767; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v5768; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0769; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)770; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0771; GFX11-NEXT:  ; %bb.1: ; %cmp.true772; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]773; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]774; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]775; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]776; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]777; GFX11-NEXT:  ; %bb.2: ; %end778; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0779; GFX11-NEXT:    s_setpc_b64 s[30:31]780  %cmp = icmp eq i32 %b, 0781  br i1 %cmp, label %cmp.true, label %cmp.false782 783cmp.true:784  %a1 = add <10 x i16> %a, splat (i16 3)785  %a2 = bitcast <10 x i16> %a1 to <5 x i32>786  br label %end787 788cmp.false:789  %a3 = bitcast <10 x i16> %a to <5 x i32>790  br label %end791 792end:793  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]794  ret <5 x i32> %phi795}796 797define inreg <5 x i32> @bitcast_v10i16_to_v5i32_scalar(<10 x i16> inreg %a, i32 inreg %b) {798; SI-LABEL: bitcast_v10i16_to_v5i32_scalar:799; SI:       ; %bb.0:800; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)801; SI-NEXT:    s_cmp_lg_u32 s26, 0802; SI-NEXT:    s_cbranch_scc0 .LBB7_4803; SI-NEXT:  ; %bb.1: ; %cmp.false804; SI-NEXT:    s_and_b32 s4, s16, 0xffff805; SI-NEXT:    s_lshl_b32 s5, s17, 16806; SI-NEXT:    s_or_b32 s4, s4, s5807; SI-NEXT:    s_and_b32 s5, s18, 0xffff808; SI-NEXT:    s_lshl_b32 s6, s19, 16809; SI-NEXT:    s_or_b32 s5, s5, s6810; SI-NEXT:    s_and_b32 s6, s20, 0xffff811; SI-NEXT:    s_lshl_b32 s7, s21, 16812; SI-NEXT:    s_or_b32 s6, s6, s7813; SI-NEXT:    s_and_b32 s7, s22, 0xffff814; SI-NEXT:    s_lshl_b32 s8, s23, 16815; SI-NEXT:    s_or_b32 s7, s7, s8816; SI-NEXT:    s_and_b32 s8, s24, 0xffff817; SI-NEXT:    s_lshl_b32 s9, s25, 16818; SI-NEXT:    s_or_b32 s8, s8, s9819; SI-NEXT:    s_cbranch_execnz .LBB7_3820; SI-NEXT:  .LBB7_2: ; %cmp.true821; SI-NEXT:    s_add_i32 s16, s16, 3822; SI-NEXT:    s_and_b32 s4, s16, 0xffff823; SI-NEXT:    s_lshl_b32 s5, s17, 16824; SI-NEXT:    s_add_i32 s18, s18, 3825; SI-NEXT:    s_or_b32 s4, s5, s4826; SI-NEXT:    s_and_b32 s5, s18, 0xffff827; SI-NEXT:    s_lshl_b32 s6, s19, 16828; SI-NEXT:    s_add_i32 s20, s20, 3829; SI-NEXT:    s_or_b32 s5, s6, s5830; SI-NEXT:    s_and_b32 s6, s20, 0xffff831; SI-NEXT:    s_lshl_b32 s7, s21, 16832; SI-NEXT:    s_add_i32 s22, s22, 3833; SI-NEXT:    s_or_b32 s6, s7, s6834; SI-NEXT:    s_and_b32 s7, s22, 0xffff835; SI-NEXT:    s_lshl_b32 s8, s23, 16836; SI-NEXT:    s_add_i32 s24, s24, 3837; SI-NEXT:    s_or_b32 s7, s8, s7838; SI-NEXT:    s_and_b32 s8, s24, 0xffff839; SI-NEXT:    s_lshl_b32 s9, s25, 16840; SI-NEXT:    s_or_b32 s8, s9, s8841; SI-NEXT:    s_add_i32 s4, s4, 0x30000842; SI-NEXT:    s_add_i32 s5, s5, 0x30000843; SI-NEXT:    s_add_i32 s6, s6, 0x30000844; SI-NEXT:    s_add_i32 s7, s7, 0x30000845; SI-NEXT:    s_add_i32 s8, s8, 0x30000846; SI-NEXT:  .LBB7_3: ; %end847; SI-NEXT:    v_mov_b32_e32 v0, s4848; SI-NEXT:    v_mov_b32_e32 v1, s5849; SI-NEXT:    v_mov_b32_e32 v2, s6850; SI-NEXT:    v_mov_b32_e32 v3, s7851; SI-NEXT:    v_mov_b32_e32 v4, s8852; SI-NEXT:    s_setpc_b64 s[30:31]853; SI-NEXT:  .LBB7_4:854; SI-NEXT:    ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8855; SI-NEXT:    s_branch .LBB7_2856;857; VI-LABEL: bitcast_v10i16_to_v5i32_scalar:858; VI:       ; %bb.0:859; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)860; VI-NEXT:    s_cmp_lg_u32 s21, 0861; VI-NEXT:    s_cbranch_scc0 .LBB7_4862; VI-NEXT:  ; %bb.1: ; %cmp.false863; VI-NEXT:    s_cbranch_execnz .LBB7_3864; VI-NEXT:  .LBB7_2: ; %cmp.true865; VI-NEXT:    s_add_i32 s5, s20, 3866; VI-NEXT:    s_and_b32 s4, s20, 0xffff0000867; VI-NEXT:    s_and_b32 s5, s5, 0xffff868; VI-NEXT:    s_or_b32 s4, s4, s5869; VI-NEXT:    s_add_i32 s5, s19, 3870; VI-NEXT:    s_add_i32 s20, s4, 0x30000871; VI-NEXT:    s_and_b32 s4, s19, 0xffff0000872; VI-NEXT:    s_and_b32 s5, s5, 0xffff873; VI-NEXT:    s_or_b32 s4, s4, s5874; VI-NEXT:    s_add_i32 s5, s18, 3875; VI-NEXT:    s_add_i32 s19, s4, 0x30000876; VI-NEXT:    s_and_b32 s4, s18, 0xffff0000877; VI-NEXT:    s_and_b32 s5, s5, 0xffff878; VI-NEXT:    s_or_b32 s4, s4, s5879; VI-NEXT:    s_add_i32 s5, s17, 3880; VI-NEXT:    s_add_i32 s18, s4, 0x30000881; VI-NEXT:    s_and_b32 s4, s17, 0xffff0000882; VI-NEXT:    s_and_b32 s5, s5, 0xffff883; VI-NEXT:    s_or_b32 s4, s4, s5884; VI-NEXT:    s_add_i32 s5, s16, 3885; VI-NEXT:    s_add_i32 s17, s4, 0x30000886; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000887; VI-NEXT:    s_and_b32 s5, s5, 0xffff888; VI-NEXT:    s_or_b32 s4, s4, s5889; VI-NEXT:    s_add_i32 s16, s4, 0x30000890; VI-NEXT:  .LBB7_3: ; %end891; VI-NEXT:    v_mov_b32_e32 v0, s16892; VI-NEXT:    v_mov_b32_e32 v1, s17893; VI-NEXT:    v_mov_b32_e32 v2, s18894; VI-NEXT:    v_mov_b32_e32 v3, s19895; VI-NEXT:    v_mov_b32_e32 v4, s20896; VI-NEXT:    s_setpc_b64 s[30:31]897; VI-NEXT:  .LBB7_4:898; VI-NEXT:    s_branch .LBB7_2899;900; GFX9-LABEL: bitcast_v10i16_to_v5i32_scalar:901; GFX9:       ; %bb.0:902; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)903; GFX9-NEXT:    s_cmp_lg_u32 s21, 0904; GFX9-NEXT:    s_cbranch_scc0 .LBB7_3905; GFX9-NEXT:  ; %bb.1: ; %cmp.false906; GFX9-NEXT:    s_cbranch_execnz .LBB7_4907; GFX9-NEXT:  .LBB7_2: ; %cmp.true908; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]909; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]910; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]911; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]912; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]913; GFX9-NEXT:    s_setpc_b64 s[30:31]914; GFX9-NEXT:  .LBB7_3:915; GFX9-NEXT:    s_branch .LBB7_2916; GFX9-NEXT:  .LBB7_4:917; GFX9-NEXT:    v_mov_b32_e32 v0, s16918; GFX9-NEXT:    v_mov_b32_e32 v1, s17919; GFX9-NEXT:    v_mov_b32_e32 v2, s18920; GFX9-NEXT:    v_mov_b32_e32 v3, s19921; GFX9-NEXT:    v_mov_b32_e32 v4, s20922; GFX9-NEXT:    s_setpc_b64 s[30:31]923;924; GFX11-LABEL: bitcast_v10i16_to_v5i32_scalar:925; GFX11:       ; %bb.0:926; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)927; GFX11-NEXT:    s_mov_b32 s4, s16928; GFX11-NEXT:    s_cmp_lg_u32 s17, 0929; GFX11-NEXT:    s_mov_b32 s5, 0930; GFX11-NEXT:    s_cbranch_scc0 .LBB7_3931; GFX11-NEXT:  ; %bb.1: ; %Flow932; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s5933; GFX11-NEXT:    s_cbranch_vccnz .LBB7_4934; GFX11-NEXT:  .LBB7_2: ; %cmp.true935; GFX11-NEXT:    v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]936; GFX11-NEXT:    v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]937; GFX11-NEXT:    v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]938; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]939; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]940; GFX11-NEXT:    s_setpc_b64 s[30:31]941; GFX11-NEXT:  .LBB7_3:942; GFX11-NEXT:    s_branch .LBB7_2943; GFX11-NEXT:  .LBB7_4:944; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1945; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3946; GFX11-NEXT:    v_mov_b32_e32 v4, s4947; GFX11-NEXT:    s_setpc_b64 s[30:31]948  %cmp = icmp eq i32 %b, 0949  br i1 %cmp, label %cmp.true, label %cmp.false950 951cmp.true:952  %a1 = add <10 x i16> %a, splat (i16 3)953  %a2 = bitcast <10 x i16> %a1 to <5 x i32>954  br label %end955 956cmp.false:957  %a3 = bitcast <10 x i16> %a to <5 x i32>958  br label %end959 960end:961  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]962  ret <5 x i32> %phi963}964 965define <10 x half> @bitcast_v5i32_to_v10f16(<5 x i32> %a, i32 %b) {966; SI-LABEL: bitcast_v5i32_to_v10f16:967; SI:       ; %bb.0:968; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)969; SI-NEXT:    v_mov_b32_e32 v14, v4970; SI-NEXT:    v_mov_b32_e32 v13, v3971; SI-NEXT:    v_mov_b32_e32 v12, v2972; SI-NEXT:    v_mov_b32_e32 v11, v1973; SI-NEXT:    v_mov_b32_e32 v10, v0974; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v5975; SI-NEXT:    ; implicit-def: $vgpr0976; SI-NEXT:    ; implicit-def: $vgpr1977; SI-NEXT:    ; implicit-def: $vgpr2978; SI-NEXT:    ; implicit-def: $vgpr3979; SI-NEXT:    ; implicit-def: $vgpr4980; SI-NEXT:    ; implicit-def: $vgpr5981; SI-NEXT:    ; implicit-def: $vgpr6982; SI-NEXT:    ; implicit-def: $vgpr7983; SI-NEXT:    ; implicit-def: $vgpr8984; SI-NEXT:    ; implicit-def: $vgpr9985; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc986; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]987; SI-NEXT:    s_cbranch_execnz .LBB8_3988; SI-NEXT:  ; %bb.1: ; %Flow989; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]990; SI-NEXT:    s_cbranch_execnz .LBB8_4991; SI-NEXT:  .LBB8_2: ; %end992; SI-NEXT:    s_or_b64 exec, exec, s[4:5]993; SI-NEXT:    s_setpc_b64 s[30:31]994; SI-NEXT:  .LBB8_3: ; %cmp.false995; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v14996; SI-NEXT:    v_cvt_f32_f16_e32 v9, v0997; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v13998; SI-NEXT:    v_cvt_f32_f16_e32 v7, v0999; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v121000; SI-NEXT:    v_cvt_f32_f16_e32 v5, v01001; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v111002; SI-NEXT:    v_cvt_f32_f16_e32 v3, v01003; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v101004; SI-NEXT:    v_cvt_f32_f16_e32 v1, v01005; SI-NEXT:    v_cvt_f32_f16_e32 v8, v141006; SI-NEXT:    v_cvt_f32_f16_e32 v6, v131007; SI-NEXT:    v_cvt_f32_f16_e32 v4, v121008; SI-NEXT:    v_cvt_f32_f16_e32 v2, v111009; SI-NEXT:    v_cvt_f32_f16_e32 v0, v101010; SI-NEXT:    ; implicit-def: $vgpr101011; SI-NEXT:    ; implicit-def: $vgpr111012; SI-NEXT:    ; implicit-def: $vgpr121013; SI-NEXT:    ; implicit-def: $vgpr131014; SI-NEXT:    ; implicit-def: $vgpr141015; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1016; SI-NEXT:    s_cbranch_execz .LBB8_21017; SI-NEXT:  .LBB8_4: ; %cmp.true1018; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v101019; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v111020; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v121021; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v131022; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v141023; SI-NEXT:    v_cvt_f32_f16_e32 v8, v91024; SI-NEXT:    v_cvt_f32_f16_e32 v6, v71025; SI-NEXT:    v_cvt_f32_f16_e32 v4, v51026; SI-NEXT:    v_cvt_f32_f16_e32 v2, v31027; SI-NEXT:    v_cvt_f32_f16_e32 v0, v11028; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v91029; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v71030; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v51031; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v31032; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11033; SI-NEXT:    v_cvt_f32_f16_e32 v9, v91034; SI-NEXT:    v_cvt_f32_f16_e32 v7, v71035; SI-NEXT:    v_cvt_f32_f16_e32 v5, v51036; SI-NEXT:    v_cvt_f32_f16_e32 v3, v31037; SI-NEXT:    v_cvt_f32_f16_e32 v1, v11038; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1039; SI-NEXT:    s_setpc_b64 s[30:31]1040;1041; VI-LABEL: bitcast_v5i32_to_v10f16:1042; VI:       ; %bb.0:1043; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1044; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51045; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1046; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1047; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1048; VI-NEXT:  ; %bb.1: ; %cmp.true1049; VI-NEXT:    v_add_u32_e32 v4, vcc, 3, v41050; VI-NEXT:    v_add_u32_e32 v3, vcc, 3, v31051; VI-NEXT:    v_add_u32_e32 v2, vcc, 3, v21052; VI-NEXT:    v_add_u32_e32 v1, vcc, 3, v11053; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01054; VI-NEXT:  ; %bb.2: ; %end1055; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1056; VI-NEXT:    s_setpc_b64 s[30:31]1057;1058; GFX9-LABEL: bitcast_v5i32_to_v10f16:1059; GFX9:       ; %bb.0:1060; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1061; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51062; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1063; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1064; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1065; GFX9-NEXT:  ; %bb.1: ; %cmp.true1066; GFX9-NEXT:    v_add_u32_e32 v4, 3, v41067; GFX9-NEXT:    v_add_u32_e32 v3, 3, v31068; GFX9-NEXT:    v_add_u32_e32 v2, 3, v21069; GFX9-NEXT:    v_add_u32_e32 v1, 3, v11070; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01071; GFX9-NEXT:  ; %bb.2: ; %end1072; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1073; GFX9-NEXT:    s_setpc_b64 s[30:31]1074;1075; GFX11-LABEL: bitcast_v5i32_to_v10f16:1076; GFX11:       ; %bb.0:1077; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1078; GFX11-NEXT:    s_mov_b32 s0, exec_lo1079; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v51080; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01081; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1082; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01083; GFX11-NEXT:  ; %bb.1: ; %cmp.true1084; GFX11-NEXT:    v_add_nc_u32_e32 v4, 3, v41085; GFX11-NEXT:    v_add_nc_u32_e32 v3, 3, v31086; GFX11-NEXT:    v_add_nc_u32_e32 v2, 3, v21087; GFX11-NEXT:    v_add_nc_u32_e32 v1, 3, v11088; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v01089; GFX11-NEXT:  ; %bb.2: ; %end1090; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01091; GFX11-NEXT:    s_setpc_b64 s[30:31]1092  %cmp = icmp eq i32 %b, 01093  br i1 %cmp, label %cmp.true, label %cmp.false1094 1095cmp.true:1096  %a1 = add <5 x i32> %a, splat (i32 3)1097  %a2 = bitcast <5 x i32> %a1 to <10 x half>1098  br label %end1099 1100cmp.false:1101  %a3 = bitcast <5 x i32> %a to <10 x half>1102  br label %end1103 1104end:1105  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1106  ret <10 x half> %phi1107}1108 1109define inreg <10 x half> @bitcast_v5i32_to_v10f16_scalar(<5 x i32> inreg %a, i32 inreg %b) {1110; SI-LABEL: bitcast_v5i32_to_v10f16_scalar:1111; SI:       ; %bb.0:1112; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1113; SI-NEXT:    s_cmp_lg_u32 s21, 01114; SI-NEXT:    s_cbranch_scc0 .LBB9_41115; SI-NEXT:  ; %bb.1: ; %cmp.false1116; SI-NEXT:    s_lshr_b32 s4, s20, 161117; SI-NEXT:    v_cvt_f32_f16_e32 v9, s41118; SI-NEXT:    s_lshr_b32 s4, s19, 161119; SI-NEXT:    v_cvt_f32_f16_e32 v7, s41120; SI-NEXT:    s_lshr_b32 s4, s18, 161121; SI-NEXT:    v_cvt_f32_f16_e32 v5, s41122; SI-NEXT:    s_lshr_b32 s4, s17, 161123; SI-NEXT:    v_cvt_f32_f16_e32 v3, s41124; SI-NEXT:    s_lshr_b32 s4, s16, 161125; SI-NEXT:    v_cvt_f32_f16_e32 v1, s41126; SI-NEXT:    v_cvt_f32_f16_e32 v8, s201127; SI-NEXT:    v_cvt_f32_f16_e32 v6, s191128; SI-NEXT:    v_cvt_f32_f16_e32 v4, s181129; SI-NEXT:    v_cvt_f32_f16_e32 v2, s171130; SI-NEXT:    v_cvt_f32_f16_e32 v0, s161131; SI-NEXT:    s_cbranch_execnz .LBB9_31132; SI-NEXT:  .LBB9_2: ; %cmp.true1133; SI-NEXT:    s_add_i32 s20, s20, 31134; SI-NEXT:    s_add_i32 s19, s19, 31135; SI-NEXT:    s_lshr_b32 s4, s20, 161136; SI-NEXT:    s_add_i32 s18, s18, 31137; SI-NEXT:    v_cvt_f32_f16_e32 v9, s41138; SI-NEXT:    s_lshr_b32 s4, s19, 161139; SI-NEXT:    s_add_i32 s17, s17, 31140; SI-NEXT:    v_cvt_f32_f16_e32 v7, s41141; SI-NEXT:    s_lshr_b32 s4, s18, 161142; SI-NEXT:    s_add_i32 s16, s16, 31143; SI-NEXT:    v_cvt_f32_f16_e32 v5, s41144; SI-NEXT:    s_lshr_b32 s4, s17, 161145; SI-NEXT:    v_cvt_f32_f16_e32 v3, s41146; SI-NEXT:    s_lshr_b32 s4, s16, 161147; SI-NEXT:    v_cvt_f32_f16_e32 v8, s201148; SI-NEXT:    v_cvt_f32_f16_e32 v6, s191149; SI-NEXT:    v_cvt_f32_f16_e32 v4, s181150; SI-NEXT:    v_cvt_f32_f16_e32 v2, s171151; SI-NEXT:    v_cvt_f32_f16_e32 v0, s161152; SI-NEXT:    v_cvt_f32_f16_e32 v1, s41153; SI-NEXT:  .LBB9_3: ; %end1154; SI-NEXT:    s_setpc_b64 s[30:31]1155; SI-NEXT:  .LBB9_4:1156; SI-NEXT:    ; implicit-def: $vgpr01157; SI-NEXT:    ; implicit-def: $vgpr11158; SI-NEXT:    ; implicit-def: $vgpr21159; SI-NEXT:    ; implicit-def: $vgpr31160; SI-NEXT:    ; implicit-def: $vgpr41161; SI-NEXT:    ; implicit-def: $vgpr51162; SI-NEXT:    ; implicit-def: $vgpr61163; SI-NEXT:    ; implicit-def: $vgpr71164; SI-NEXT:    ; implicit-def: $vgpr81165; SI-NEXT:    ; implicit-def: $vgpr91166; SI-NEXT:    s_branch .LBB9_21167;1168; VI-LABEL: bitcast_v5i32_to_v10f16_scalar:1169; VI:       ; %bb.0:1170; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1171; VI-NEXT:    s_cmp_lg_u32 s21, 01172; VI-NEXT:    s_cbranch_scc0 .LBB9_41173; VI-NEXT:  ; %bb.1: ; %cmp.false1174; VI-NEXT:    s_cbranch_execnz .LBB9_31175; VI-NEXT:  .LBB9_2: ; %cmp.true1176; VI-NEXT:    s_add_i32 s20, s20, 31177; VI-NEXT:    s_add_i32 s19, s19, 31178; VI-NEXT:    s_add_i32 s18, s18, 31179; VI-NEXT:    s_add_i32 s17, s17, 31180; VI-NEXT:    s_add_i32 s16, s16, 31181; VI-NEXT:  .LBB9_3: ; %end1182; VI-NEXT:    v_mov_b32_e32 v0, s161183; VI-NEXT:    v_mov_b32_e32 v1, s171184; VI-NEXT:    v_mov_b32_e32 v2, s181185; VI-NEXT:    v_mov_b32_e32 v3, s191186; VI-NEXT:    v_mov_b32_e32 v4, s201187; VI-NEXT:    s_setpc_b64 s[30:31]1188; VI-NEXT:  .LBB9_4:1189; VI-NEXT:    s_branch .LBB9_21190;1191; GFX9-LABEL: bitcast_v5i32_to_v10f16_scalar:1192; GFX9:       ; %bb.0:1193; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1194; GFX9-NEXT:    s_cmp_lg_u32 s21, 01195; GFX9-NEXT:    s_cbranch_scc0 .LBB9_41196; GFX9-NEXT:  ; %bb.1: ; %cmp.false1197; GFX9-NEXT:    s_cbranch_execnz .LBB9_31198; GFX9-NEXT:  .LBB9_2: ; %cmp.true1199; GFX9-NEXT:    s_add_i32 s20, s20, 31200; GFX9-NEXT:    s_add_i32 s19, s19, 31201; GFX9-NEXT:    s_add_i32 s18, s18, 31202; GFX9-NEXT:    s_add_i32 s17, s17, 31203; GFX9-NEXT:    s_add_i32 s16, s16, 31204; GFX9-NEXT:  .LBB9_3: ; %end1205; GFX9-NEXT:    v_mov_b32_e32 v0, s161206; GFX9-NEXT:    v_mov_b32_e32 v1, s171207; GFX9-NEXT:    v_mov_b32_e32 v2, s181208; GFX9-NEXT:    v_mov_b32_e32 v3, s191209; GFX9-NEXT:    v_mov_b32_e32 v4, s201210; GFX9-NEXT:    s_setpc_b64 s[30:31]1211; GFX9-NEXT:  .LBB9_4:1212; GFX9-NEXT:    s_branch .LBB9_21213;1214; GFX11-LABEL: bitcast_v5i32_to_v10f16_scalar:1215; GFX11:       ; %bb.0:1216; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1217; GFX11-NEXT:    s_cmp_lg_u32 s17, 01218; GFX11-NEXT:    s_mov_b32 s4, 01219; GFX11-NEXT:    s_cbranch_scc0 .LBB9_41220; GFX11-NEXT:  ; %bb.1: ; %Flow1221; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s41222; GFX11-NEXT:    s_cbranch_vccnz .LBB9_31223; GFX11-NEXT:  .LBB9_2: ; %cmp.true1224; GFX11-NEXT:    s_add_i32 s16, s16, 31225; GFX11-NEXT:    s_add_i32 s3, s3, 31226; GFX11-NEXT:    s_add_i32 s2, s2, 31227; GFX11-NEXT:    s_add_i32 s1, s1, 31228; GFX11-NEXT:    s_add_i32 s0, s0, 31229; GFX11-NEXT:  .LBB9_3: ; %end1230; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1231; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11232; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31233; GFX11-NEXT:    v_mov_b32_e32 v4, s161234; GFX11-NEXT:    s_setpc_b64 s[30:31]1235; GFX11-NEXT:  .LBB9_4:1236; GFX11-NEXT:    s_branch .LBB9_21237  %cmp = icmp eq i32 %b, 01238  br i1 %cmp, label %cmp.true, label %cmp.false1239 1240cmp.true:1241  %a1 = add <5 x i32> %a, splat (i32 3)1242  %a2 = bitcast <5 x i32> %a1 to <10 x half>1243  br label %end1244 1245cmp.false:1246  %a3 = bitcast <5 x i32> %a to <10 x half>1247  br label %end1248 1249end:1250  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1251  ret <10 x half> %phi1252}1253 1254define <5 x i32> @bitcast_v10f16_to_v5i32(<10 x half> %a, i32 %b) {1255; SI-LABEL: bitcast_v10f16_to_v5i32:1256; SI:       ; %bb.0:1257; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1258; SI-NEXT:    v_cvt_f16_f32_e32 v17, v11259; SI-NEXT:    v_cvt_f16_f32_e32 v16, v01260; SI-NEXT:    v_cvt_f16_f32_e32 v15, v31261; SI-NEXT:    v_cvt_f16_f32_e32 v14, v21262; SI-NEXT:    v_cvt_f16_f32_e32 v13, v51263; SI-NEXT:    v_cvt_f16_f32_e32 v12, v41264; SI-NEXT:    v_cvt_f16_f32_e32 v11, v71265; SI-NEXT:    v_cvt_f16_f32_e32 v7, v61266; SI-NEXT:    v_cvt_f16_f32_e32 v6, v91267; SI-NEXT:    v_cvt_f16_f32_e32 v5, v81268; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v101269; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr41270; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1271; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1272; SI-NEXT:    s_cbranch_execnz .LBB10_31273; SI-NEXT:  ; %bb.1: ; %Flow1274; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1275; SI-NEXT:    s_cbranch_execnz .LBB10_41276; SI-NEXT:  .LBB10_2: ; %end1277; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1278; SI-NEXT:    s_setpc_b64 s[30:31]1279; SI-NEXT:  .LBB10_3: ; %cmp.false1280; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v171281; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v151282; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v131283; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v111284; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v61285; SI-NEXT:    v_or_b32_e32 v0, v16, v01286; SI-NEXT:    v_or_b32_e32 v1, v14, v11287; SI-NEXT:    v_or_b32_e32 v2, v12, v21288; SI-NEXT:    v_or_b32_e32 v3, v7, v31289; SI-NEXT:    v_or_b32_e32 v4, v5, v41290; SI-NEXT:    ; implicit-def: $vgpr171291; SI-NEXT:    ; implicit-def: $vgpr161292; SI-NEXT:    ; implicit-def: $vgpr151293; SI-NEXT:    ; implicit-def: $vgpr141294; SI-NEXT:    ; implicit-def: $vgpr131295; SI-NEXT:    ; implicit-def: $vgpr121296; SI-NEXT:    ; implicit-def: $vgpr111297; SI-NEXT:    ; implicit-def: $vgpr71298; SI-NEXT:    ; implicit-def: $vgpr61299; SI-NEXT:    ; implicit-def: $vgpr51300; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1301; SI-NEXT:    s_cbranch_execz .LBB10_21302; SI-NEXT:  .LBB10_4: ; %cmp.true1303; SI-NEXT:    v_cvt_f32_f16_e32 v0, v171304; SI-NEXT:    v_cvt_f32_f16_e32 v1, v161305; SI-NEXT:    v_cvt_f32_f16_e32 v2, v151306; SI-NEXT:    v_cvt_f32_f16_e32 v3, v141307; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v01308; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v11309; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01310; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21311; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11312; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21313; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01314; SI-NEXT:    v_cvt_f32_f16_e32 v4, v121315; SI-NEXT:    v_or_b32_e32 v0, v1, v01316; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v21317; SI-NEXT:    v_cvt_f32_f16_e32 v2, v131318; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31319; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31320; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v41321; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21322; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21323; SI-NEXT:    v_cvt_f16_f32_e32 v4, v41324; SI-NEXT:    v_or_b32_e32 v1, v3, v11325; SI-NEXT:    v_cvt_f32_f16_e32 v3, v111326; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v21327; SI-NEXT:    v_or_b32_e32 v2, v4, v21328; SI-NEXT:    v_cvt_f32_f16_e32 v4, v71329; SI-NEXT:    v_cvt_f32_f16_e32 v6, v61330; SI-NEXT:    v_cvt_f32_f16_e32 v5, v51331; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31332; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31333; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v41334; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v61335; SI-NEXT:    v_cvt_f16_f32_e32 v4, v41336; SI-NEXT:    v_cvt_f16_f32_e32 v6, v61337; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v51338; SI-NEXT:    v_cvt_f16_f32_e32 v5, v51339; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31340; SI-NEXT:    v_or_b32_e32 v3, v4, v31341; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v61342; SI-NEXT:    v_or_b32_e32 v4, v5, v41343; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1344; SI-NEXT:    s_setpc_b64 s[30:31]1345;1346; VI-LABEL: bitcast_v10f16_to_v5i32:1347; VI:       ; %bb.0:1348; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1349; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51350; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1351; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1352; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1353; VI-NEXT:    s_cbranch_execz .LBB10_21354; VI-NEXT:  ; %bb.1: ; %cmp.true1355; VI-NEXT:    v_mov_b32_e32 v5, 0x2001356; VI-NEXT:    v_add_f16_sdwa v6, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1357; VI-NEXT:    v_add_f16_e32 v4, 0x200, v41358; VI-NEXT:    v_or_b32_e32 v4, v4, v61359; VI-NEXT:    v_add_f16_sdwa v6, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1360; VI-NEXT:    v_add_f16_e32 v3, 0x200, v31361; VI-NEXT:    v_or_b32_e32 v3, v3, v61362; VI-NEXT:    v_add_f16_sdwa v6, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1363; VI-NEXT:    v_add_f16_e32 v2, 0x200, v21364; VI-NEXT:    v_or_b32_e32 v2, v2, v61365; VI-NEXT:    v_add_f16_sdwa v6, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1366; VI-NEXT:    v_add_f16_e32 v1, 0x200, v11367; VI-NEXT:    v_add_f16_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1368; VI-NEXT:    v_add_f16_e32 v0, 0x200, v01369; VI-NEXT:    v_or_b32_e32 v1, v1, v61370; VI-NEXT:    v_or_b32_e32 v0, v0, v51371; VI-NEXT:  .LBB10_2: ; %end1372; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1373; VI-NEXT:    s_setpc_b64 s[30:31]1374;1375; GFX9-LABEL: bitcast_v10f16_to_v5i32:1376; GFX9:       ; %bb.0:1377; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1378; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51379; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1380; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1381; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1382; GFX9-NEXT:  ; %bb.1: ; %cmp.true1383; GFX9-NEXT:    s_movk_i32 s6, 0x2001384; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]1385; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]1386; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]1387; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]1388; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]1389; GFX9-NEXT:  ; %bb.2: ; %end1390; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1391; GFX9-NEXT:    s_setpc_b64 s[30:31]1392;1393; GFX11-LABEL: bitcast_v10f16_to_v5i32:1394; GFX11:       ; %bb.0:1395; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1396; GFX11-NEXT:    s_mov_b32 s0, exec_lo1397; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v51398; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01399; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1400; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01401; GFX11-NEXT:  ; %bb.1: ; %cmp.true1402; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]1403; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]1404; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]1405; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]1406; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]1407; GFX11-NEXT:  ; %bb.2: ; %end1408; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01409; GFX11-NEXT:    s_setpc_b64 s[30:31]1410  %cmp = icmp eq i32 %b, 01411  br i1 %cmp, label %cmp.true, label %cmp.false1412 1413cmp.true:1414  %a1 = fadd <10 x half> %a, splat (half 0xH0200)1415  %a2 = bitcast <10 x half> %a1 to <5 x i32>1416  br label %end1417 1418cmp.false:1419  %a3 = bitcast <10 x half> %a to <5 x i32>1420  br label %end1421 1422end:1423  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1424  ret <5 x i32> %phi1425}1426 1427define inreg <5 x i32> @bitcast_v10f16_to_v5i32_scalar(<10 x half> inreg %a, i32 inreg %b) {1428; SI-LABEL: bitcast_v10f16_to_v5i32_scalar:1429; SI:       ; %bb.0:1430; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1431; SI-NEXT:    v_cvt_f16_f32_e32 v14, s171432; SI-NEXT:    v_cvt_f16_f32_e32 v13, s161433; SI-NEXT:    v_cvt_f16_f32_e32 v12, s191434; SI-NEXT:    v_cvt_f16_f32_e32 v11, s181435; SI-NEXT:    v_cvt_f16_f32_e32 v10, s211436; SI-NEXT:    v_cvt_f16_f32_e32 v9, s201437; SI-NEXT:    v_cvt_f16_f32_e32 v8, s231438; SI-NEXT:    v_cvt_f16_f32_e32 v7, s221439; SI-NEXT:    v_cvt_f16_f32_e32 v6, s251440; SI-NEXT:    v_cvt_f16_f32_e32 v5, s241441; SI-NEXT:    s_cmp_lg_u32 s26, 01442; SI-NEXT:    s_cbranch_scc0 .LBB11_41443; SI-NEXT:  ; %bb.1: ; %cmp.false1444; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v141445; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v121446; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v101447; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v81448; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v61449; SI-NEXT:    v_or_b32_e32 v0, v13, v01450; SI-NEXT:    v_or_b32_e32 v1, v11, v11451; SI-NEXT:    v_or_b32_e32 v2, v9, v21452; SI-NEXT:    v_or_b32_e32 v3, v7, v31453; SI-NEXT:    v_or_b32_e32 v4, v5, v41454; SI-NEXT:    s_cbranch_execnz .LBB11_31455; SI-NEXT:  .LBB11_2: ; %cmp.true1456; SI-NEXT:    v_cvt_f32_f16_e32 v0, v141457; SI-NEXT:    v_cvt_f32_f16_e32 v1, v131458; SI-NEXT:    v_cvt_f32_f16_e32 v2, v121459; SI-NEXT:    v_cvt_f32_f16_e32 v3, v111460; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v01461; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v11462; SI-NEXT:    v_cvt_f16_f32_e32 v0, v01463; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21464; SI-NEXT:    v_cvt_f16_f32_e32 v1, v11465; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21466; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01467; SI-NEXT:    v_cvt_f32_f16_e32 v4, v91468; SI-NEXT:    v_or_b32_e32 v0, v1, v01469; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v21470; SI-NEXT:    v_cvt_f32_f16_e32 v2, v101471; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31472; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31473; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v41474; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v21475; SI-NEXT:    v_cvt_f16_f32_e32 v2, v21476; SI-NEXT:    v_cvt_f16_f32_e32 v4, v41477; SI-NEXT:    v_or_b32_e32 v1, v3, v11478; SI-NEXT:    v_cvt_f32_f16_e32 v3, v81479; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v21480; SI-NEXT:    v_or_b32_e32 v2, v4, v21481; SI-NEXT:    v_cvt_f32_f16_e32 v4, v71482; SI-NEXT:    v_cvt_f32_f16_e32 v6, v61483; SI-NEXT:    v_cvt_f32_f16_e32 v5, v51484; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v31485; SI-NEXT:    v_cvt_f16_f32_e32 v3, v31486; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v41487; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v61488; SI-NEXT:    v_cvt_f16_f32_e32 v4, v41489; SI-NEXT:    v_cvt_f16_f32_e32 v6, v61490; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v51491; SI-NEXT:    v_cvt_f16_f32_e32 v5, v51492; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v31493; SI-NEXT:    v_or_b32_e32 v3, v4, v31494; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v61495; SI-NEXT:    v_or_b32_e32 v4, v5, v41496; SI-NEXT:  .LBB11_3: ; %end1497; SI-NEXT:    s_setpc_b64 s[30:31]1498; SI-NEXT:  .LBB11_4:1499; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr41500; SI-NEXT:    s_branch .LBB11_21501;1502; VI-LABEL: bitcast_v10f16_to_v5i32_scalar:1503; VI:       ; %bb.0:1504; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1505; VI-NEXT:    s_cmp_lg_u32 s21, 01506; VI-NEXT:    s_cbranch_scc0 .LBB11_31507; VI-NEXT:  ; %bb.1: ; %cmp.false1508; VI-NEXT:    s_cbranch_execnz .LBB11_41509; VI-NEXT:  .LBB11_2: ; %cmp.true1510; VI-NEXT:    s_lshr_b32 s4, s20, 161511; VI-NEXT:    v_mov_b32_e32 v0, 0x2001512; VI-NEXT:    v_mov_b32_e32 v1, s41513; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1514; VI-NEXT:    v_add_f16_e32 v2, s20, v01515; VI-NEXT:    s_lshr_b32 s4, s19, 161516; VI-NEXT:    v_or_b32_e32 v4, v2, v11517; VI-NEXT:    v_mov_b32_e32 v1, s41518; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1519; VI-NEXT:    v_add_f16_e32 v2, s19, v01520; VI-NEXT:    s_lshr_b32 s4, s18, 161521; VI-NEXT:    v_or_b32_e32 v3, v2, v11522; VI-NEXT:    v_mov_b32_e32 v1, s41523; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1524; VI-NEXT:    v_add_f16_e32 v2, s18, v01525; VI-NEXT:    s_lshr_b32 s4, s17, 161526; VI-NEXT:    v_or_b32_e32 v2, v2, v11527; VI-NEXT:    v_mov_b32_e32 v1, s41528; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1529; VI-NEXT:    v_add_f16_e32 v5, s17, v01530; VI-NEXT:    s_lshr_b32 s4, s16, 161531; VI-NEXT:    v_or_b32_e32 v1, v5, v11532; VI-NEXT:    v_mov_b32_e32 v5, s41533; VI-NEXT:    v_add_f16_sdwa v5, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1534; VI-NEXT:    v_add_f16_e32 v0, s16, v01535; VI-NEXT:    v_or_b32_e32 v0, v0, v51536; VI-NEXT:    s_setpc_b64 s[30:31]1537; VI-NEXT:  .LBB11_3:1538; VI-NEXT:    s_branch .LBB11_21539; VI-NEXT:  .LBB11_4:1540; VI-NEXT:    v_mov_b32_e32 v0, s161541; VI-NEXT:    v_mov_b32_e32 v1, s171542; VI-NEXT:    v_mov_b32_e32 v2, s181543; VI-NEXT:    v_mov_b32_e32 v3, s191544; VI-NEXT:    v_mov_b32_e32 v4, s201545; VI-NEXT:    s_setpc_b64 s[30:31]1546;1547; GFX9-LABEL: bitcast_v10f16_to_v5i32_scalar:1548; GFX9:       ; %bb.0:1549; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1550; GFX9-NEXT:    s_cmp_lg_u32 s21, 01551; GFX9-NEXT:    s_cbranch_scc0 .LBB11_31552; GFX9-NEXT:  ; %bb.1: ; %cmp.false1553; GFX9-NEXT:    s_cbranch_execnz .LBB11_41554; GFX9-NEXT:  .LBB11_2: ; %cmp.true1555; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2001556; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]1557; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]1558; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]1559; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]1560; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]1561; GFX9-NEXT:    s_setpc_b64 s[30:31]1562; GFX9-NEXT:  .LBB11_3:1563; GFX9-NEXT:    s_branch .LBB11_21564; GFX9-NEXT:  .LBB11_4:1565; GFX9-NEXT:    v_mov_b32_e32 v0, s161566; GFX9-NEXT:    v_mov_b32_e32 v1, s171567; GFX9-NEXT:    v_mov_b32_e32 v2, s181568; GFX9-NEXT:    v_mov_b32_e32 v3, s191569; GFX9-NEXT:    v_mov_b32_e32 v4, s201570; GFX9-NEXT:    s_setpc_b64 s[30:31]1571;1572; GFX11-LABEL: bitcast_v10f16_to_v5i32_scalar:1573; GFX11:       ; %bb.0:1574; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1575; GFX11-NEXT:    s_mov_b32 s4, s161576; GFX11-NEXT:    s_cmp_lg_u32 s17, 01577; GFX11-NEXT:    s_mov_b32 s5, 01578; GFX11-NEXT:    s_cbranch_scc0 .LBB11_31579; GFX11-NEXT:  ; %bb.1: ; %Flow1580; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s51581; GFX11-NEXT:    s_cbranch_vccnz .LBB11_41582; GFX11-NEXT:  .LBB11_2: ; %cmp.true1583; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]1584; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]1585; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]1586; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]1587; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]1588; GFX11-NEXT:    s_setpc_b64 s[30:31]1589; GFX11-NEXT:  .LBB11_3:1590; GFX11-NEXT:    s_branch .LBB11_21591; GFX11-NEXT:  .LBB11_4:1592; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11593; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31594; GFX11-NEXT:    v_mov_b32_e32 v4, s41595; GFX11-NEXT:    s_setpc_b64 s[30:31]1596  %cmp = icmp eq i32 %b, 01597  br i1 %cmp, label %cmp.true, label %cmp.false1598 1599cmp.true:1600  %a1 = fadd <10 x half> %a, splat (half 0xH0200)1601  %a2 = bitcast <10 x half> %a1 to <5 x i32>1602  br label %end1603 1604cmp.false:1605  %a3 = bitcast <10 x half> %a to <5 x i32>1606  br label %end1607 1608end:1609  %phi = phi <5 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1610  ret <5 x i32> %phi1611}1612 1613define <10 x i16> @bitcast_v5f32_to_v10i16(<5 x float> %a, i32 %b) {1614; SI-LABEL: bitcast_v5f32_to_v10i16:1615; SI:       ; %bb.0:1616; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1617; SI-NEXT:    v_mov_b32_e32 v8, v41618; SI-NEXT:    v_mov_b32_e32 v6, v31619; SI-NEXT:    v_mov_b32_e32 v4, v21620; SI-NEXT:    v_mov_b32_e32 v2, v11621; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51622; SI-NEXT:    ; implicit-def: $vgpr11623; SI-NEXT:    ; implicit-def: $vgpr31624; SI-NEXT:    ; implicit-def: $vgpr51625; SI-NEXT:    ; implicit-def: $vgpr71626; SI-NEXT:    ; implicit-def: $vgpr91627; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1628; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1629; SI-NEXT:    s_cbranch_execnz .LBB12_31630; SI-NEXT:  ; %bb.1: ; %Flow1631; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1632; SI-NEXT:    s_cbranch_execnz .LBB12_41633; SI-NEXT:  .LBB12_2: ; %end1634; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1635; SI-NEXT:    s_setpc_b64 s[30:31]1636; SI-NEXT:  .LBB12_3: ; %cmp.false1637; SI-NEXT:    v_alignbit_b32 v9, v0, v8, 161638; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 161639; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 161640; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v61641; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v21642; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1643; SI-NEXT:    s_cbranch_execz .LBB12_21644; SI-NEXT:  .LBB12_4: ; %cmp.true1645; SI-NEXT:    v_add_f32_e32 v8, 1.0, v81646; SI-NEXT:    v_add_f32_e32 v2, 1.0, v21647; SI-NEXT:    v_add_f32_e32 v0, 1.0, v01648; SI-NEXT:    v_add_f32_e32 v6, 1.0, v61649; SI-NEXT:    v_add_f32_e32 v4, 1.0, v41650; SI-NEXT:    v_alignbit_b32 v5, v6, v4, 161651; SI-NEXT:    v_alignbit_b32 v1, v2, v0, 161652; SI-NEXT:    v_alignbit_b32 v9, v0, v8, 161653; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v61654; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v21655; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1656; SI-NEXT:    s_setpc_b64 s[30:31]1657;1658; VI-LABEL: bitcast_v5f32_to_v10i16:1659; VI:       ; %bb.0:1660; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1661; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51662; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1663; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1664; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1665; VI-NEXT:  ; %bb.1: ; %cmp.true1666; VI-NEXT:    v_add_f32_e32 v4, 1.0, v41667; VI-NEXT:    v_add_f32_e32 v3, 1.0, v31668; VI-NEXT:    v_add_f32_e32 v2, 1.0, v21669; VI-NEXT:    v_add_f32_e32 v1, 1.0, v11670; VI-NEXT:    v_add_f32_e32 v0, 1.0, v01671; VI-NEXT:  ; %bb.2: ; %end1672; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1673; VI-NEXT:    s_setpc_b64 s[30:31]1674;1675; GFX9-LABEL: bitcast_v5f32_to_v10i16:1676; GFX9:       ; %bb.0:1677; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1678; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51679; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1680; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1681; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1682; GFX9-NEXT:  ; %bb.1: ; %cmp.true1683; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v41684; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v31685; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v21686; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v11687; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v01688; GFX9-NEXT:  ; %bb.2: ; %end1689; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1690; GFX9-NEXT:    s_setpc_b64 s[30:31]1691;1692; GFX11-LABEL: bitcast_v5f32_to_v10i16:1693; GFX11:       ; %bb.0:1694; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1695; GFX11-NEXT:    s_mov_b32 s0, exec_lo1696; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v51697; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01698; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1699; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01700; GFX11-NEXT:  ; %bb.1: ; %cmp.true1701; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v31702; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v11703; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v01704; GFX11-NEXT:  ; %bb.2: ; %end1705; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01706; GFX11-NEXT:    s_setpc_b64 s[30:31]1707  %cmp = icmp eq i32 %b, 01708  br i1 %cmp, label %cmp.true, label %cmp.false1709 1710cmp.true:1711  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)1712  %a2 = bitcast <5 x float> %a1 to <10 x i16>1713  br label %end1714 1715cmp.false:1716  %a3 = bitcast <5 x float> %a to <10 x i16>1717  br label %end1718 1719end:1720  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1721  ret <10 x i16> %phi1722}1723 1724define inreg <10 x i16> @bitcast_v5f32_to_v10i16_scalar(<5 x float> inreg %a, i32 inreg %b) {1725; SI-LABEL: bitcast_v5f32_to_v10i16_scalar:1726; SI:       ; %bb.0:1727; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1728; SI-NEXT:    s_cmp_lg_u32 s21, 01729; SI-NEXT:    s_cbranch_scc0 .LBB13_31730; SI-NEXT:  ; %bb.1: ; %cmp.false1731; SI-NEXT:    s_lshr_b32 s13, s19, 161732; SI-NEXT:    s_lshr_b32 s12, s17, 161733; SI-NEXT:    s_lshr_b64 s[6:7], s[20:21], 161734; SI-NEXT:    s_lshr_b64 s[4:5], s[18:19], 161735; SI-NEXT:    s_lshr_b64 s[8:9], s[16:17], 161736; SI-NEXT:    s_cbranch_execnz .LBB13_41737; SI-NEXT:  .LBB13_2: ; %cmp.true1738; SI-NEXT:    v_add_f32_e64 v8, s20, 1.01739; SI-NEXT:    v_add_f32_e64 v14, s17, 1.01740; SI-NEXT:    v_add_f32_e64 v13, s16, 1.01741; SI-NEXT:    v_add_f32_e64 v12, s19, 1.01742; SI-NEXT:    v_add_f32_e64 v11, s18, 1.01743; SI-NEXT:    v_lshr_b64 v[5:6], v[11:12], 161744; SI-NEXT:    v_lshr_b64 v[1:2], v[13:14], 161745; SI-NEXT:    v_lshr_b64 v[9:10], v[8:9], 161746; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v121747; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v141748; SI-NEXT:    s_branch .LBB13_51749; SI-NEXT:  .LBB13_3:1750; SI-NEXT:    ; implicit-def: $sgpr81751; SI-NEXT:    ; implicit-def: $sgpr121752; SI-NEXT:    ; implicit-def: $sgpr41753; SI-NEXT:    ; implicit-def: $sgpr131754; SI-NEXT:    ; implicit-def: $sgpr61755; SI-NEXT:    s_branch .LBB13_21756; SI-NEXT:  .LBB13_4:1757; SI-NEXT:    v_mov_b32_e32 v13, s161758; SI-NEXT:    v_mov_b32_e32 v14, s171759; SI-NEXT:    v_mov_b32_e32 v11, s181760; SI-NEXT:    v_mov_b32_e32 v12, s191761; SI-NEXT:    v_mov_b32_e32 v8, s201762; SI-NEXT:    v_mov_b32_e32 v3, s121763; SI-NEXT:    v_mov_b32_e32 v7, s131764; SI-NEXT:    v_mov_b32_e32 v9, s61765; SI-NEXT:    v_mov_b32_e32 v1, s81766; SI-NEXT:    v_mov_b32_e32 v5, s41767; SI-NEXT:  .LBB13_5: ; %end1768; SI-NEXT:    v_mov_b32_e32 v0, v131769; SI-NEXT:    v_mov_b32_e32 v2, v141770; SI-NEXT:    v_mov_b32_e32 v4, v111771; SI-NEXT:    v_mov_b32_e32 v6, v121772; SI-NEXT:    s_setpc_b64 s[30:31]1773;1774; VI-LABEL: bitcast_v5f32_to_v10i16_scalar:1775; VI:       ; %bb.0:1776; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1777; VI-NEXT:    s_cmp_lg_u32 s21, 01778; VI-NEXT:    s_cbranch_scc0 .LBB13_31779; VI-NEXT:  ; %bb.1: ; %cmp.false1780; VI-NEXT:    s_cbranch_execnz .LBB13_41781; VI-NEXT:  .LBB13_2: ; %cmp.true1782; VI-NEXT:    v_add_f32_e64 v4, s20, 1.01783; VI-NEXT:    v_add_f32_e64 v3, s19, 1.01784; VI-NEXT:    v_add_f32_e64 v2, s18, 1.01785; VI-NEXT:    v_add_f32_e64 v1, s17, 1.01786; VI-NEXT:    v_add_f32_e64 v0, s16, 1.01787; VI-NEXT:    s_setpc_b64 s[30:31]1788; VI-NEXT:  .LBB13_3:1789; VI-NEXT:    s_branch .LBB13_21790; VI-NEXT:  .LBB13_4:1791; VI-NEXT:    v_mov_b32_e32 v0, s161792; VI-NEXT:    v_mov_b32_e32 v1, s171793; VI-NEXT:    v_mov_b32_e32 v2, s181794; VI-NEXT:    v_mov_b32_e32 v3, s191795; VI-NEXT:    v_mov_b32_e32 v4, s201796; VI-NEXT:    v_mov_b32_e32 v5, s211797; VI-NEXT:    v_mov_b32_e32 v6, s221798; VI-NEXT:    v_mov_b32_e32 v7, s231799; VI-NEXT:    s_setpc_b64 s[30:31]1800;1801; GFX9-LABEL: bitcast_v5f32_to_v10i16_scalar:1802; GFX9:       ; %bb.0:1803; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1804; GFX9-NEXT:    s_cmp_lg_u32 s21, 01805; GFX9-NEXT:    s_cbranch_scc0 .LBB13_31806; GFX9-NEXT:  ; %bb.1: ; %cmp.false1807; GFX9-NEXT:    s_cbranch_execnz .LBB13_41808; GFX9-NEXT:  .LBB13_2: ; %cmp.true1809; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.01810; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.01811; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.01812; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.01813; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.01814; GFX9-NEXT:    s_setpc_b64 s[30:31]1815; GFX9-NEXT:  .LBB13_3:1816; GFX9-NEXT:    s_branch .LBB13_21817; GFX9-NEXT:  .LBB13_4:1818; GFX9-NEXT:    v_mov_b32_e32 v0, s161819; GFX9-NEXT:    v_mov_b32_e32 v1, s171820; GFX9-NEXT:    v_mov_b32_e32 v2, s181821; GFX9-NEXT:    v_mov_b32_e32 v3, s191822; GFX9-NEXT:    v_mov_b32_e32 v4, s201823; GFX9-NEXT:    v_mov_b32_e32 v5, s211824; GFX9-NEXT:    v_mov_b32_e32 v6, s221825; GFX9-NEXT:    v_mov_b32_e32 v7, s231826; GFX9-NEXT:    s_setpc_b64 s[30:31]1827;1828; GFX11-LABEL: bitcast_v5f32_to_v10i16_scalar:1829; GFX11:       ; %bb.0:1830; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1831; GFX11-NEXT:    s_mov_b32 s4, s161832; GFX11-NEXT:    s_cmp_lg_u32 s17, 01833; GFX11-NEXT:    s_mov_b32 s8, 01834; GFX11-NEXT:    s_cbranch_scc0 .LBB13_31835; GFX11-NEXT:  ; %bb.1: ; %Flow1836; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s81837; GFX11-NEXT:    s_cbranch_vccnz .LBB13_41838; GFX11-NEXT:  .LBB13_2: ; %cmp.true1839; GFX11-NEXT:    v_add_f32_e64 v4, s4, 1.01840; GFX11-NEXT:    v_add_f32_e64 v3, s3, 1.01841; GFX11-NEXT:    v_add_f32_e64 v2, s2, 1.01842; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.01843; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.01844; GFX11-NEXT:    s_setpc_b64 s[30:31]1845; GFX11-NEXT:  .LBB13_3:1846; GFX11-NEXT:    s_branch .LBB13_21847; GFX11-NEXT:  .LBB13_4:1848; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11849; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31850; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s51851; GFX11-NEXT:    v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s71852; GFX11-NEXT:    s_setpc_b64 s[30:31]1853  %cmp = icmp eq i32 %b, 01854  br i1 %cmp, label %cmp.true, label %cmp.false1855 1856cmp.true:1857  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)1858  %a2 = bitcast <5 x float> %a1 to <10 x i16>1859  br label %end1860 1861cmp.false:1862  %a3 = bitcast <5 x float> %a to <10 x i16>1863  br label %end1864 1865end:1866  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1867  ret <10 x i16> %phi1868}1869 1870define <5 x float> @bitcast_v10i16_to_v5f32(<10 x i16> %a, i32 %b) {1871; SI-LABEL: bitcast_v10i16_to_v5f32:1872; SI:       ; %bb.0:1873; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1874; SI-NEXT:    v_mov_b32_e32 v13, v41875; SI-NEXT:    v_mov_b32_e32 v12, v21876; SI-NEXT:    v_mov_b32_e32 v11, v01877; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v101878; SI-NEXT:    v_lshlrev_b32_e32 v15, 16, v11879; SI-NEXT:    v_lshlrev_b32_e32 v14, 16, v31880; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v51881; SI-NEXT:    v_lshlrev_b32_e32 v7, 16, v71882; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v91883; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr41884; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1885; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1886; SI-NEXT:    s_cbranch_execnz .LBB14_31887; SI-NEXT:  ; %bb.1: ; %Flow1888; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1889; SI-NEXT:    s_cbranch_execnz .LBB14_41890; SI-NEXT:  .LBB14_2: ; %end1891; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1892; SI-NEXT:    s_setpc_b64 s[30:31]1893; SI-NEXT:  .LBB14_3: ; %cmp.false1894; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v111895; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v121896; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v131897; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v61898; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v81899; SI-NEXT:    v_or_b32_e32 v0, v0, v151900; SI-NEXT:    v_or_b32_e32 v1, v1, v141901; SI-NEXT:    v_or_b32_e32 v2, v2, v101902; SI-NEXT:    v_or_b32_e32 v3, v3, v71903; SI-NEXT:    v_or_b32_e32 v4, v4, v51904; SI-NEXT:    ; implicit-def: $vgpr111905; SI-NEXT:    ; implicit-def: $vgpr121906; SI-NEXT:    ; implicit-def: $vgpr131907; SI-NEXT:    ; implicit-def: $vgpr61908; SI-NEXT:    ; implicit-def: $vgpr81909; SI-NEXT:    ; implicit-def: $vgpr151910; SI-NEXT:    ; implicit-def: $vgpr141911; SI-NEXT:    ; implicit-def: $vgpr101912; SI-NEXT:    ; implicit-def: $vgpr71913; SI-NEXT:    ; implicit-def: $vgpr51914; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1915; SI-NEXT:    s_cbranch_execz .LBB14_21916; SI-NEXT:  .LBB14_4: ; %cmp.true1917; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v111918; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v121919; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v131920; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v61921; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v81922; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v01923; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v11924; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v21925; SI-NEXT:    v_and_b32_e32 v3, 0xffff, v31926; SI-NEXT:    v_and_b32_e32 v4, 0xffff, v41927; SI-NEXT:    v_or_b32_e32 v0, v15, v01928; SI-NEXT:    s_mov_b32 s6, 0x300001929; SI-NEXT:    v_or_b32_e32 v1, v14, v11930; SI-NEXT:    v_or_b32_e32 v2, v10, v21931; SI-NEXT:    v_or_b32_e32 v3, v7, v31932; SI-NEXT:    v_or_b32_e32 v4, v5, v41933; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v01934; SI-NEXT:    v_add_i32_e32 v1, vcc, s6, v11935; SI-NEXT:    v_add_i32_e32 v2, vcc, 0x30000, v21936; SI-NEXT:    v_add_i32_e32 v3, vcc, 0x30000, v31937; SI-NEXT:    v_add_i32_e32 v4, vcc, 0x30000, v41938; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1939; SI-NEXT:    s_setpc_b64 s[30:31]1940;1941; VI-LABEL: bitcast_v10i16_to_v5f32:1942; VI:       ; %bb.0:1943; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1944; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51945; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1946; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1947; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1948; VI-NEXT:    s_cbranch_execz .LBB14_21949; VI-NEXT:  ; %bb.1: ; %cmp.true1950; VI-NEXT:    v_mov_b32_e32 v6, 31951; VI-NEXT:    v_add_u16_e32 v5, 3, v41952; VI-NEXT:    v_add_u16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1953; VI-NEXT:    v_or_b32_e32 v4, v5, v41954; VI-NEXT:    v_add_u16_e32 v5, 3, v31955; VI-NEXT:    v_add_u16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1956; VI-NEXT:    v_or_b32_e32 v3, v5, v31957; VI-NEXT:    v_add_u16_e32 v5, 3, v21958; VI-NEXT:    v_add_u16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1959; VI-NEXT:    v_or_b32_e32 v2, v5, v21960; VI-NEXT:    v_add_u16_e32 v5, 3, v11961; VI-NEXT:    v_add_u16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1962; VI-NEXT:    v_or_b32_e32 v1, v5, v11963; VI-NEXT:    v_add_u16_e32 v5, 3, v01964; VI-NEXT:    v_add_u16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1965; VI-NEXT:    v_or_b32_e32 v0, v5, v01966; VI-NEXT:  .LBB14_2: ; %end1967; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1968; VI-NEXT:    s_setpc_b64 s[30:31]1969;1970; GFX9-LABEL: bitcast_v10i16_to_v5f32:1971; GFX9:       ; %bb.0:1972; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1973; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v51974; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1975; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1976; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1977; GFX9-NEXT:  ; %bb.1: ; %cmp.true1978; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1979; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1980; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1981; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1982; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1983; GFX9-NEXT:  ; %bb.2: ; %end1984; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1985; GFX9-NEXT:    s_setpc_b64 s[30:31]1986;1987; GFX11-LABEL: bitcast_v10i16_to_v5f32:1988; GFX11:       ; %bb.0:1989; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1990; GFX11-NEXT:    s_mov_b32 s0, exec_lo1991; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v51992; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01993; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1994; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01995; GFX11-NEXT:  ; %bb.1: ; %cmp.true1996; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1997; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1998; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1999; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2000; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2001; GFX11-NEXT:  ; %bb.2: ; %end2002; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02003; GFX11-NEXT:    s_setpc_b64 s[30:31]2004  %cmp = icmp eq i32 %b, 02005  br i1 %cmp, label %cmp.true, label %cmp.false2006 2007cmp.true:2008  %a1 = add <10 x i16> %a, splat (i16 3)2009  %a2 = bitcast <10 x i16> %a1 to <5 x float>2010  br label %end2011 2012cmp.false:2013  %a3 = bitcast <10 x i16> %a to <5 x float>2014  br label %end2015 2016end:2017  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2018  ret <5 x float> %phi2019}2020 2021define inreg <5 x float> @bitcast_v10i16_to_v5f32_scalar(<10 x i16> inreg %a, i32 inreg %b) {2022; SI-LABEL: bitcast_v10i16_to_v5f32_scalar:2023; SI:       ; %bb.0:2024; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2025; SI-NEXT:    s_cmp_lg_u32 s26, 02026; SI-NEXT:    s_cbranch_scc0 .LBB15_42027; SI-NEXT:  ; %bb.1: ; %cmp.false2028; SI-NEXT:    s_and_b32 s4, s16, 0xffff2029; SI-NEXT:    s_lshl_b32 s5, s17, 162030; SI-NEXT:    s_or_b32 s4, s4, s52031; SI-NEXT:    s_and_b32 s5, s18, 0xffff2032; SI-NEXT:    s_lshl_b32 s6, s19, 162033; SI-NEXT:    s_or_b32 s5, s5, s62034; SI-NEXT:    s_and_b32 s6, s20, 0xffff2035; SI-NEXT:    s_lshl_b32 s7, s21, 162036; SI-NEXT:    s_or_b32 s6, s6, s72037; SI-NEXT:    s_and_b32 s7, s22, 0xffff2038; SI-NEXT:    s_lshl_b32 s8, s23, 162039; SI-NEXT:    s_or_b32 s7, s7, s82040; SI-NEXT:    s_and_b32 s8, s24, 0xffff2041; SI-NEXT:    s_lshl_b32 s9, s25, 162042; SI-NEXT:    s_or_b32 s8, s8, s92043; SI-NEXT:    s_cbranch_execnz .LBB15_32044; SI-NEXT:  .LBB15_2: ; %cmp.true2045; SI-NEXT:    s_add_i32 s16, s16, 32046; SI-NEXT:    s_and_b32 s4, s16, 0xffff2047; SI-NEXT:    s_lshl_b32 s5, s17, 162048; SI-NEXT:    s_add_i32 s18, s18, 32049; SI-NEXT:    s_or_b32 s4, s5, s42050; SI-NEXT:    s_and_b32 s5, s18, 0xffff2051; SI-NEXT:    s_lshl_b32 s6, s19, 162052; SI-NEXT:    s_add_i32 s20, s20, 32053; SI-NEXT:    s_or_b32 s5, s6, s52054; SI-NEXT:    s_and_b32 s6, s20, 0xffff2055; SI-NEXT:    s_lshl_b32 s7, s21, 162056; SI-NEXT:    s_add_i32 s22, s22, 32057; SI-NEXT:    s_or_b32 s6, s7, s62058; SI-NEXT:    s_and_b32 s7, s22, 0xffff2059; SI-NEXT:    s_lshl_b32 s8, s23, 162060; SI-NEXT:    s_add_i32 s24, s24, 32061; SI-NEXT:    s_or_b32 s7, s8, s72062; SI-NEXT:    s_and_b32 s8, s24, 0xffff2063; SI-NEXT:    s_lshl_b32 s9, s25, 162064; SI-NEXT:    s_or_b32 s8, s9, s82065; SI-NEXT:    s_add_i32 s4, s4, 0x300002066; SI-NEXT:    s_add_i32 s5, s5, 0x300002067; SI-NEXT:    s_add_i32 s6, s6, 0x300002068; SI-NEXT:    s_add_i32 s7, s7, 0x300002069; SI-NEXT:    s_add_i32 s8, s8, 0x300002070; SI-NEXT:  .LBB15_3: ; %end2071; SI-NEXT:    v_mov_b32_e32 v0, s42072; SI-NEXT:    v_mov_b32_e32 v1, s52073; SI-NEXT:    v_mov_b32_e32 v2, s62074; SI-NEXT:    v_mov_b32_e32 v3, s72075; SI-NEXT:    v_mov_b32_e32 v4, s82076; SI-NEXT:    s_setpc_b64 s[30:31]2077; SI-NEXT:  .LBB15_4:2078; SI-NEXT:    ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr82079; SI-NEXT:    s_branch .LBB15_22080;2081; VI-LABEL: bitcast_v10i16_to_v5f32_scalar:2082; VI:       ; %bb.0:2083; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2084; VI-NEXT:    s_cmp_lg_u32 s21, 02085; VI-NEXT:    s_cbranch_scc0 .LBB15_42086; VI-NEXT:  ; %bb.1: ; %cmp.false2087; VI-NEXT:    s_cbranch_execnz .LBB15_32088; VI-NEXT:  .LBB15_2: ; %cmp.true2089; VI-NEXT:    s_add_i32 s5, s20, 32090; VI-NEXT:    s_and_b32 s4, s20, 0xffff00002091; VI-NEXT:    s_and_b32 s5, s5, 0xffff2092; VI-NEXT:    s_or_b32 s4, s4, s52093; VI-NEXT:    s_add_i32 s5, s19, 32094; VI-NEXT:    s_add_i32 s20, s4, 0x300002095; VI-NEXT:    s_and_b32 s4, s19, 0xffff00002096; VI-NEXT:    s_and_b32 s5, s5, 0xffff2097; VI-NEXT:    s_or_b32 s4, s4, s52098; VI-NEXT:    s_add_i32 s5, s18, 32099; VI-NEXT:    s_add_i32 s19, s4, 0x300002100; VI-NEXT:    s_and_b32 s4, s18, 0xffff00002101; VI-NEXT:    s_and_b32 s5, s5, 0xffff2102; VI-NEXT:    s_or_b32 s4, s4, s52103; VI-NEXT:    s_add_i32 s5, s17, 32104; VI-NEXT:    s_add_i32 s18, s4, 0x300002105; VI-NEXT:    s_and_b32 s4, s17, 0xffff00002106; VI-NEXT:    s_and_b32 s5, s5, 0xffff2107; VI-NEXT:    s_or_b32 s4, s4, s52108; VI-NEXT:    s_add_i32 s5, s16, 32109; VI-NEXT:    s_add_i32 s17, s4, 0x300002110; VI-NEXT:    s_and_b32 s4, s16, 0xffff00002111; VI-NEXT:    s_and_b32 s5, s5, 0xffff2112; VI-NEXT:    s_or_b32 s4, s4, s52113; VI-NEXT:    s_add_i32 s16, s4, 0x300002114; VI-NEXT:  .LBB15_3: ; %end2115; VI-NEXT:    v_mov_b32_e32 v0, s162116; VI-NEXT:    v_mov_b32_e32 v1, s172117; VI-NEXT:    v_mov_b32_e32 v2, s182118; VI-NEXT:    v_mov_b32_e32 v3, s192119; VI-NEXT:    v_mov_b32_e32 v4, s202120; VI-NEXT:    s_setpc_b64 s[30:31]2121; VI-NEXT:  .LBB15_4:2122; VI-NEXT:    s_branch .LBB15_22123;2124; GFX9-LABEL: bitcast_v10i16_to_v5f32_scalar:2125; GFX9:       ; %bb.0:2126; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2127; GFX9-NEXT:    s_cmp_lg_u32 s21, 02128; GFX9-NEXT:    s_cbranch_scc0 .LBB15_32129; GFX9-NEXT:  ; %bb.1: ; %cmp.false2130; GFX9-NEXT:    s_cbranch_execnz .LBB15_42131; GFX9-NEXT:  .LBB15_2: ; %cmp.true2132; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]2133; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]2134; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]2135; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]2136; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]2137; GFX9-NEXT:    s_setpc_b64 s[30:31]2138; GFX9-NEXT:  .LBB15_3:2139; GFX9-NEXT:    s_branch .LBB15_22140; GFX9-NEXT:  .LBB15_4:2141; GFX9-NEXT:    v_mov_b32_e32 v0, s162142; GFX9-NEXT:    v_mov_b32_e32 v1, s172143; GFX9-NEXT:    v_mov_b32_e32 v2, s182144; GFX9-NEXT:    v_mov_b32_e32 v3, s192145; GFX9-NEXT:    v_mov_b32_e32 v4, s202146; GFX9-NEXT:    s_setpc_b64 s[30:31]2147;2148; GFX11-LABEL: bitcast_v10i16_to_v5f32_scalar:2149; GFX11:       ; %bb.0:2150; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2151; GFX11-NEXT:    s_mov_b32 s4, s162152; GFX11-NEXT:    s_cmp_lg_u32 s17, 02153; GFX11-NEXT:    s_mov_b32 s5, 02154; GFX11-NEXT:    s_cbranch_scc0 .LBB15_32155; GFX11-NEXT:  ; %bb.1: ; %Flow2156; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s52157; GFX11-NEXT:    s_cbranch_vccnz .LBB15_42158; GFX11-NEXT:  .LBB15_2: ; %cmp.true2159; GFX11-NEXT:    v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]2160; GFX11-NEXT:    v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]2161; GFX11-NEXT:    v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]2162; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]2163; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]2164; GFX11-NEXT:    s_setpc_b64 s[30:31]2165; GFX11-NEXT:  .LBB15_3:2166; GFX11-NEXT:    s_branch .LBB15_22167; GFX11-NEXT:  .LBB15_4:2168; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12169; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32170; GFX11-NEXT:    v_mov_b32_e32 v4, s42171; GFX11-NEXT:    s_setpc_b64 s[30:31]2172  %cmp = icmp eq i32 %b, 02173  br i1 %cmp, label %cmp.true, label %cmp.false2174 2175cmp.true:2176  %a1 = add <10 x i16> %a, splat (i16 3)2177  %a2 = bitcast <10 x i16> %a1 to <5 x float>2178  br label %end2179 2180cmp.false:2181  %a3 = bitcast <10 x i16> %a to <5 x float>2182  br label %end2183 2184end:2185  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2186  ret <5 x float> %phi2187}2188 2189define <10 x half> @bitcast_v5f32_to_v10f16(<5 x float> %a, i32 %b) {2190; SI-LABEL: bitcast_v5f32_to_v10f16:2191; SI:       ; %bb.0:2192; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2193; SI-NEXT:    v_mov_b32_e32 v14, v42194; SI-NEXT:    v_mov_b32_e32 v13, v32195; SI-NEXT:    v_mov_b32_e32 v12, v22196; SI-NEXT:    v_mov_b32_e32 v11, v12197; SI-NEXT:    v_mov_b32_e32 v10, v02198; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52199; SI-NEXT:    ; implicit-def: $vgpr02200; SI-NEXT:    ; implicit-def: $vgpr12201; SI-NEXT:    ; implicit-def: $vgpr22202; SI-NEXT:    ; implicit-def: $vgpr32203; SI-NEXT:    ; implicit-def: $vgpr42204; SI-NEXT:    ; implicit-def: $vgpr52205; SI-NEXT:    ; implicit-def: $vgpr62206; SI-NEXT:    ; implicit-def: $vgpr72207; SI-NEXT:    ; implicit-def: $vgpr82208; SI-NEXT:    ; implicit-def: $vgpr92209; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2210; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2211; SI-NEXT:    s_cbranch_execnz .LBB16_32212; SI-NEXT:  ; %bb.1: ; %Flow2213; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2214; SI-NEXT:    s_cbranch_execnz .LBB16_42215; SI-NEXT:  .LBB16_2: ; %end2216; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2217; SI-NEXT:    s_setpc_b64 s[30:31]2218; SI-NEXT:  .LBB16_3: ; %cmp.false2219; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v142220; SI-NEXT:    v_cvt_f32_f16_e32 v9, v02221; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v132222; SI-NEXT:    v_cvt_f32_f16_e32 v7, v02223; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v122224; SI-NEXT:    v_cvt_f32_f16_e32 v5, v02225; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v112226; SI-NEXT:    v_cvt_f32_f16_e32 v3, v02227; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v102228; SI-NEXT:    v_cvt_f32_f16_e32 v1, v02229; SI-NEXT:    v_cvt_f32_f16_e32 v8, v142230; SI-NEXT:    v_cvt_f32_f16_e32 v6, v132231; SI-NEXT:    v_cvt_f32_f16_e32 v4, v122232; SI-NEXT:    v_cvt_f32_f16_e32 v2, v112233; SI-NEXT:    v_cvt_f32_f16_e32 v0, v102234; SI-NEXT:    ; implicit-def: $vgpr102235; SI-NEXT:    ; implicit-def: $vgpr112236; SI-NEXT:    ; implicit-def: $vgpr122237; SI-NEXT:    ; implicit-def: $vgpr132238; SI-NEXT:    ; implicit-def: $vgpr142239; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2240; SI-NEXT:    s_cbranch_execz .LBB16_22241; SI-NEXT:  .LBB16_4: ; %cmp.true2242; SI-NEXT:    v_add_f32_e32 v1, 1.0, v102243; SI-NEXT:    v_add_f32_e32 v3, 1.0, v112244; SI-NEXT:    v_add_f32_e32 v5, 1.0, v122245; SI-NEXT:    v_add_f32_e32 v7, 1.0, v132246; SI-NEXT:    v_add_f32_e32 v9, 1.0, v142247; SI-NEXT:    v_cvt_f32_f16_e32 v8, v92248; SI-NEXT:    v_cvt_f32_f16_e32 v6, v72249; SI-NEXT:    v_cvt_f32_f16_e32 v4, v52250; SI-NEXT:    v_cvt_f32_f16_e32 v2, v32251; SI-NEXT:    v_cvt_f32_f16_e32 v0, v12252; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v92253; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v72254; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v52255; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v32256; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12257; SI-NEXT:    v_cvt_f32_f16_e32 v9, v92258; SI-NEXT:    v_cvt_f32_f16_e32 v7, v72259; SI-NEXT:    v_cvt_f32_f16_e32 v5, v52260; SI-NEXT:    v_cvt_f32_f16_e32 v3, v32261; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12262; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2263; SI-NEXT:    s_setpc_b64 s[30:31]2264;2265; VI-LABEL: bitcast_v5f32_to_v10f16:2266; VI:       ; %bb.0:2267; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2268; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52269; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2270; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2271; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2272; VI-NEXT:  ; %bb.1: ; %cmp.true2273; VI-NEXT:    v_add_f32_e32 v4, 1.0, v42274; VI-NEXT:    v_add_f32_e32 v3, 1.0, v32275; VI-NEXT:    v_add_f32_e32 v2, 1.0, v22276; VI-NEXT:    v_add_f32_e32 v1, 1.0, v12277; VI-NEXT:    v_add_f32_e32 v0, 1.0, v02278; VI-NEXT:  ; %bb.2: ; %end2279; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2280; VI-NEXT:    s_setpc_b64 s[30:31]2281;2282; GFX9-LABEL: bitcast_v5f32_to_v10f16:2283; GFX9:       ; %bb.0:2284; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2285; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52286; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2287; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2288; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2289; GFX9-NEXT:  ; %bb.1: ; %cmp.true2290; GFX9-NEXT:    v_add_f32_e32 v4, 1.0, v42291; GFX9-NEXT:    v_add_f32_e32 v3, 1.0, v32292; GFX9-NEXT:    v_add_f32_e32 v2, 1.0, v22293; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v12294; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v02295; GFX9-NEXT:  ; %bb.2: ; %end2296; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2297; GFX9-NEXT:    s_setpc_b64 s[30:31]2298;2299; GFX11-LABEL: bitcast_v5f32_to_v10f16:2300; GFX11:       ; %bb.0:2301; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2302; GFX11-NEXT:    s_mov_b32 s0, exec_lo2303; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v52304; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02305; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2306; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02307; GFX11-NEXT:  ; %bb.1: ; %cmp.true2308; GFX11-NEXT:    v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v32309; GFX11-NEXT:    v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v12310; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v02311; GFX11-NEXT:  ; %bb.2: ; %end2312; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02313; GFX11-NEXT:    s_setpc_b64 s[30:31]2314  %cmp = icmp eq i32 %b, 02315  br i1 %cmp, label %cmp.true, label %cmp.false2316 2317cmp.true:2318  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)2319  %a2 = bitcast <5 x float> %a1 to <10 x half>2320  br label %end2321 2322cmp.false:2323  %a3 = bitcast <5 x float> %a to <10 x half>2324  br label %end2325 2326end:2327  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2328  ret <10 x half> %phi2329}2330 2331define inreg <10 x half> @bitcast_v5f32_to_v10f16_scalar(<5 x float> inreg %a, i32 inreg %b) {2332; SI-LABEL: bitcast_v5f32_to_v10f16_scalar:2333; SI:       ; %bb.0:2334; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2335; SI-NEXT:    s_cmp_lg_u32 s21, 02336; SI-NEXT:    s_cbranch_scc0 .LBB17_42337; SI-NEXT:  ; %bb.1: ; %cmp.false2338; SI-NEXT:    s_lshr_b32 s4, s20, 162339; SI-NEXT:    v_cvt_f32_f16_e32 v9, s42340; SI-NEXT:    s_lshr_b32 s4, s19, 162341; SI-NEXT:    v_cvt_f32_f16_e32 v7, s42342; SI-NEXT:    s_lshr_b32 s4, s18, 162343; SI-NEXT:    v_cvt_f32_f16_e32 v5, s42344; SI-NEXT:    s_lshr_b32 s4, s17, 162345; SI-NEXT:    v_cvt_f32_f16_e32 v3, s42346; SI-NEXT:    s_lshr_b32 s4, s16, 162347; SI-NEXT:    v_cvt_f32_f16_e32 v1, s42348; SI-NEXT:    v_cvt_f32_f16_e32 v8, s202349; SI-NEXT:    v_cvt_f32_f16_e32 v6, s192350; SI-NEXT:    v_cvt_f32_f16_e32 v4, s182351; SI-NEXT:    v_cvt_f32_f16_e32 v2, s172352; SI-NEXT:    v_cvt_f32_f16_e32 v0, s162353; SI-NEXT:    s_cbranch_execnz .LBB17_32354; SI-NEXT:  .LBB17_2: ; %cmp.true2355; SI-NEXT:    v_add_f32_e64 v1, s16, 1.02356; SI-NEXT:    v_add_f32_e64 v3, s17, 1.02357; SI-NEXT:    v_add_f32_e64 v5, s18, 1.02358; SI-NEXT:    v_add_f32_e64 v7, s19, 1.02359; SI-NEXT:    v_add_f32_e64 v9, s20, 1.02360; SI-NEXT:    v_cvt_f32_f16_e32 v8, v92361; SI-NEXT:    v_cvt_f32_f16_e32 v6, v72362; SI-NEXT:    v_cvt_f32_f16_e32 v4, v52363; SI-NEXT:    v_cvt_f32_f16_e32 v2, v32364; SI-NEXT:    v_cvt_f32_f16_e32 v0, v12365; SI-NEXT:    v_lshrrev_b32_e32 v9, 16, v92366; SI-NEXT:    v_lshrrev_b32_e32 v7, 16, v72367; SI-NEXT:    v_lshrrev_b32_e32 v5, 16, v52368; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v32369; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v12370; SI-NEXT:    v_cvt_f32_f16_e32 v9, v92371; SI-NEXT:    v_cvt_f32_f16_e32 v7, v72372; SI-NEXT:    v_cvt_f32_f16_e32 v5, v52373; SI-NEXT:    v_cvt_f32_f16_e32 v3, v32374; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12375; SI-NEXT:  .LBB17_3: ; %end2376; SI-NEXT:    s_setpc_b64 s[30:31]2377; SI-NEXT:  .LBB17_4:2378; SI-NEXT:    ; implicit-def: $vgpr02379; SI-NEXT:    ; implicit-def: $vgpr12380; SI-NEXT:    ; implicit-def: $vgpr22381; SI-NEXT:    ; implicit-def: $vgpr32382; SI-NEXT:    ; implicit-def: $vgpr42383; SI-NEXT:    ; implicit-def: $vgpr52384; SI-NEXT:    ; implicit-def: $vgpr62385; SI-NEXT:    ; implicit-def: $vgpr72386; SI-NEXT:    ; implicit-def: $vgpr82387; SI-NEXT:    ; implicit-def: $vgpr92388; SI-NEXT:    s_branch .LBB17_22389;2390; VI-LABEL: bitcast_v5f32_to_v10f16_scalar:2391; VI:       ; %bb.0:2392; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2393; VI-NEXT:    s_cmp_lg_u32 s21, 02394; VI-NEXT:    s_cbranch_scc0 .LBB17_32395; VI-NEXT:  ; %bb.1: ; %cmp.false2396; VI-NEXT:    s_cbranch_execnz .LBB17_42397; VI-NEXT:  .LBB17_2: ; %cmp.true2398; VI-NEXT:    v_add_f32_e64 v4, s20, 1.02399; VI-NEXT:    v_add_f32_e64 v3, s19, 1.02400; VI-NEXT:    v_add_f32_e64 v2, s18, 1.02401; VI-NEXT:    v_add_f32_e64 v1, s17, 1.02402; VI-NEXT:    v_add_f32_e64 v0, s16, 1.02403; VI-NEXT:    s_setpc_b64 s[30:31]2404; VI-NEXT:  .LBB17_3:2405; VI-NEXT:    s_branch .LBB17_22406; VI-NEXT:  .LBB17_4:2407; VI-NEXT:    v_mov_b32_e32 v0, s162408; VI-NEXT:    v_mov_b32_e32 v1, s172409; VI-NEXT:    v_mov_b32_e32 v2, s182410; VI-NEXT:    v_mov_b32_e32 v3, s192411; VI-NEXT:    v_mov_b32_e32 v4, s202412; VI-NEXT:    v_mov_b32_e32 v5, s212413; VI-NEXT:    v_mov_b32_e32 v6, s222414; VI-NEXT:    v_mov_b32_e32 v7, s232415; VI-NEXT:    s_setpc_b64 s[30:31]2416;2417; GFX9-LABEL: bitcast_v5f32_to_v10f16_scalar:2418; GFX9:       ; %bb.0:2419; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2420; GFX9-NEXT:    s_cmp_lg_u32 s21, 02421; GFX9-NEXT:    s_cbranch_scc0 .LBB17_32422; GFX9-NEXT:  ; %bb.1: ; %cmp.false2423; GFX9-NEXT:    s_cbranch_execnz .LBB17_42424; GFX9-NEXT:  .LBB17_2: ; %cmp.true2425; GFX9-NEXT:    v_add_f32_e64 v4, s20, 1.02426; GFX9-NEXT:    v_add_f32_e64 v3, s19, 1.02427; GFX9-NEXT:    v_add_f32_e64 v2, s18, 1.02428; GFX9-NEXT:    v_add_f32_e64 v1, s17, 1.02429; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.02430; GFX9-NEXT:    s_setpc_b64 s[30:31]2431; GFX9-NEXT:  .LBB17_3:2432; GFX9-NEXT:    s_branch .LBB17_22433; GFX9-NEXT:  .LBB17_4:2434; GFX9-NEXT:    v_mov_b32_e32 v0, s162435; GFX9-NEXT:    v_mov_b32_e32 v1, s172436; GFX9-NEXT:    v_mov_b32_e32 v2, s182437; GFX9-NEXT:    v_mov_b32_e32 v3, s192438; GFX9-NEXT:    v_mov_b32_e32 v4, s202439; GFX9-NEXT:    v_mov_b32_e32 v5, s212440; GFX9-NEXT:    v_mov_b32_e32 v6, s222441; GFX9-NEXT:    v_mov_b32_e32 v7, s232442; GFX9-NEXT:    s_setpc_b64 s[30:31]2443;2444; GFX11-LABEL: bitcast_v5f32_to_v10f16_scalar:2445; GFX11:       ; %bb.0:2446; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2447; GFX11-NEXT:    s_mov_b32 s4, s162448; GFX11-NEXT:    s_cmp_lg_u32 s17, 02449; GFX11-NEXT:    s_mov_b32 s8, 02450; GFX11-NEXT:    s_cbranch_scc0 .LBB17_32451; GFX11-NEXT:  ; %bb.1: ; %Flow2452; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s82453; GFX11-NEXT:    s_cbranch_vccnz .LBB17_42454; GFX11-NEXT:  .LBB17_2: ; %cmp.true2455; GFX11-NEXT:    v_add_f32_e64 v4, s4, 1.02456; GFX11-NEXT:    v_add_f32_e64 v3, s3, 1.02457; GFX11-NEXT:    v_add_f32_e64 v2, s2, 1.02458; GFX11-NEXT:    v_add_f32_e64 v1, s1, 1.02459; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.02460; GFX11-NEXT:    s_setpc_b64 s[30:31]2461; GFX11-NEXT:  .LBB17_3:2462; GFX11-NEXT:    s_branch .LBB17_22463; GFX11-NEXT:  .LBB17_4:2464; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12465; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32466; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52467; GFX11-NEXT:    v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s72468; GFX11-NEXT:    s_setpc_b64 s[30:31]2469  %cmp = icmp eq i32 %b, 02470  br i1 %cmp, label %cmp.true, label %cmp.false2471 2472cmp.true:2473  %a1 = fadd <5 x float> %a, splat (float 1.000000e+00)2474  %a2 = bitcast <5 x float> %a1 to <10 x half>2475  br label %end2476 2477cmp.false:2478  %a3 = bitcast <5 x float> %a to <10 x half>2479  br label %end2480 2481end:2482  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2483  ret <10 x half> %phi2484}2485 2486define <5 x float> @bitcast_v10f16_to_v5f32(<10 x half> %a, i32 %b) {2487; SI-LABEL: bitcast_v10f16_to_v5f32:2488; SI:       ; %bb.0:2489; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2490; SI-NEXT:    v_cvt_f16_f32_e32 v17, v12491; SI-NEXT:    v_cvt_f16_f32_e32 v16, v02492; SI-NEXT:    v_cvt_f16_f32_e32 v15, v32493; SI-NEXT:    v_cvt_f16_f32_e32 v14, v22494; SI-NEXT:    v_cvt_f16_f32_e32 v13, v52495; SI-NEXT:    v_cvt_f16_f32_e32 v12, v42496; SI-NEXT:    v_cvt_f16_f32_e32 v11, v72497; SI-NEXT:    v_cvt_f16_f32_e32 v7, v62498; SI-NEXT:    v_cvt_f16_f32_e32 v6, v92499; SI-NEXT:    v_cvt_f16_f32_e32 v5, v82500; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v102501; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr42502; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2503; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2504; SI-NEXT:    s_cbranch_execnz .LBB18_32505; SI-NEXT:  ; %bb.1: ; %Flow2506; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2507; SI-NEXT:    s_cbranch_execnz .LBB18_42508; SI-NEXT:  .LBB18_2: ; %end2509; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2510; SI-NEXT:    s_setpc_b64 s[30:31]2511; SI-NEXT:  .LBB18_3: ; %cmp.false2512; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v172513; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v152514; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v132515; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v112516; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v62517; SI-NEXT:    v_or_b32_e32 v0, v16, v02518; SI-NEXT:    v_or_b32_e32 v1, v14, v12519; SI-NEXT:    v_or_b32_e32 v2, v12, v22520; SI-NEXT:    v_or_b32_e32 v3, v7, v32521; SI-NEXT:    v_or_b32_e32 v4, v5, v42522; SI-NEXT:    ; implicit-def: $vgpr172523; SI-NEXT:    ; implicit-def: $vgpr162524; SI-NEXT:    ; implicit-def: $vgpr152525; SI-NEXT:    ; implicit-def: $vgpr142526; SI-NEXT:    ; implicit-def: $vgpr132527; SI-NEXT:    ; implicit-def: $vgpr122528; SI-NEXT:    ; implicit-def: $vgpr112529; SI-NEXT:    ; implicit-def: $vgpr72530; SI-NEXT:    ; implicit-def: $vgpr62531; SI-NEXT:    ; implicit-def: $vgpr52532; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2533; SI-NEXT:    s_cbranch_execz .LBB18_22534; SI-NEXT:  .LBB18_4: ; %cmp.true2535; SI-NEXT:    v_cvt_f32_f16_e32 v0, v172536; SI-NEXT:    v_cvt_f32_f16_e32 v1, v162537; SI-NEXT:    v_cvt_f32_f16_e32 v2, v152538; SI-NEXT:    v_cvt_f32_f16_e32 v3, v142539; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v02540; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v12541; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02542; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22543; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12544; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22545; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v02546; SI-NEXT:    v_cvt_f32_f16_e32 v4, v122547; SI-NEXT:    v_or_b32_e32 v0, v1, v02548; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v22549; SI-NEXT:    v_cvt_f32_f16_e32 v2, v132550; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32551; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32552; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42553; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22554; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22555; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42556; SI-NEXT:    v_or_b32_e32 v1, v3, v12557; SI-NEXT:    v_cvt_f32_f16_e32 v3, v112558; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22559; SI-NEXT:    v_or_b32_e32 v2, v4, v22560; SI-NEXT:    v_cvt_f32_f16_e32 v4, v72561; SI-NEXT:    v_cvt_f32_f16_e32 v6, v62562; SI-NEXT:    v_cvt_f32_f16_e32 v5, v52563; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32564; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32565; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42566; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62567; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42568; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62569; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52570; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52571; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v32572; SI-NEXT:    v_or_b32_e32 v3, v4, v32573; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v62574; SI-NEXT:    v_or_b32_e32 v4, v5, v42575; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2576; SI-NEXT:    s_setpc_b64 s[30:31]2577;2578; VI-LABEL: bitcast_v10f16_to_v5f32:2579; VI:       ; %bb.0:2580; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2581; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52582; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2583; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2584; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2585; VI-NEXT:    s_cbranch_execz .LBB18_22586; VI-NEXT:  ; %bb.1: ; %cmp.true2587; VI-NEXT:    v_mov_b32_e32 v5, 0x2002588; VI-NEXT:    v_add_f16_sdwa v6, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2589; VI-NEXT:    v_add_f16_e32 v4, 0x200, v42590; VI-NEXT:    v_or_b32_e32 v4, v4, v62591; VI-NEXT:    v_add_f16_sdwa v6, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2592; VI-NEXT:    v_add_f16_e32 v3, 0x200, v32593; VI-NEXT:    v_or_b32_e32 v3, v3, v62594; VI-NEXT:    v_add_f16_sdwa v6, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2595; VI-NEXT:    v_add_f16_e32 v2, 0x200, v22596; VI-NEXT:    v_or_b32_e32 v2, v2, v62597; VI-NEXT:    v_add_f16_sdwa v6, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2598; VI-NEXT:    v_add_f16_e32 v1, 0x200, v12599; VI-NEXT:    v_add_f16_sdwa v5, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2600; VI-NEXT:    v_add_f16_e32 v0, 0x200, v02601; VI-NEXT:    v_or_b32_e32 v1, v1, v62602; VI-NEXT:    v_or_b32_e32 v0, v0, v52603; VI-NEXT:  .LBB18_2: ; %end2604; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2605; VI-NEXT:    s_setpc_b64 s[30:31]2606;2607; GFX9-LABEL: bitcast_v10f16_to_v5f32:2608; GFX9:       ; %bb.0:2609; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2610; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52611; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2612; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2613; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2614; GFX9-NEXT:  ; %bb.1: ; %cmp.true2615; GFX9-NEXT:    s_movk_i32 s6, 0x2002616; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]2617; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]2618; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]2619; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]2620; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]2621; GFX9-NEXT:  ; %bb.2: ; %end2622; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2623; GFX9-NEXT:    s_setpc_b64 s[30:31]2624;2625; GFX11-LABEL: bitcast_v10f16_to_v5f32:2626; GFX11:       ; %bb.0:2627; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2628; GFX11-NEXT:    s_mov_b32 s0, exec_lo2629; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v52630; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02631; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2632; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02633; GFX11-NEXT:  ; %bb.1: ; %cmp.true2634; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]2635; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]2636; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]2637; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]2638; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]2639; GFX11-NEXT:  ; %bb.2: ; %end2640; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02641; GFX11-NEXT:    s_setpc_b64 s[30:31]2642  %cmp = icmp eq i32 %b, 02643  br i1 %cmp, label %cmp.true, label %cmp.false2644 2645cmp.true:2646  %a1 = fadd <10 x half> %a, splat (half 0xH0200)2647  %a2 = bitcast <10 x half> %a1 to <5 x float>2648  br label %end2649 2650cmp.false:2651  %a3 = bitcast <10 x half> %a to <5 x float>2652  br label %end2653 2654end:2655  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2656  ret <5 x float> %phi2657}2658 2659define inreg <5 x float> @bitcast_v10f16_to_v5f32_scalar(<10 x half> inreg %a, i32 inreg %b) {2660; SI-LABEL: bitcast_v10f16_to_v5f32_scalar:2661; SI:       ; %bb.0:2662; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2663; SI-NEXT:    v_cvt_f16_f32_e32 v14, s172664; SI-NEXT:    v_cvt_f16_f32_e32 v13, s162665; SI-NEXT:    v_cvt_f16_f32_e32 v12, s192666; SI-NEXT:    v_cvt_f16_f32_e32 v11, s182667; SI-NEXT:    v_cvt_f16_f32_e32 v10, s212668; SI-NEXT:    v_cvt_f16_f32_e32 v9, s202669; SI-NEXT:    v_cvt_f16_f32_e32 v8, s232670; SI-NEXT:    v_cvt_f16_f32_e32 v7, s222671; SI-NEXT:    v_cvt_f16_f32_e32 v6, s252672; SI-NEXT:    v_cvt_f16_f32_e32 v5, s242673; SI-NEXT:    s_cmp_lg_u32 s26, 02674; SI-NEXT:    s_cbranch_scc0 .LBB19_42675; SI-NEXT:  ; %bb.1: ; %cmp.false2676; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v142677; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v122678; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v102679; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v82680; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v62681; SI-NEXT:    v_or_b32_e32 v0, v13, v02682; SI-NEXT:    v_or_b32_e32 v1, v11, v12683; SI-NEXT:    v_or_b32_e32 v2, v9, v22684; SI-NEXT:    v_or_b32_e32 v3, v7, v32685; SI-NEXT:    v_or_b32_e32 v4, v5, v42686; SI-NEXT:    s_cbranch_execnz .LBB19_32687; SI-NEXT:  .LBB19_2: ; %cmp.true2688; SI-NEXT:    v_cvt_f32_f16_e32 v0, v142689; SI-NEXT:    v_cvt_f32_f16_e32 v1, v132690; SI-NEXT:    v_cvt_f32_f16_e32 v2, v122691; SI-NEXT:    v_cvt_f32_f16_e32 v3, v112692; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v02693; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v12694; SI-NEXT:    v_cvt_f16_f32_e32 v0, v02695; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22696; SI-NEXT:    v_cvt_f16_f32_e32 v1, v12697; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22698; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v02699; SI-NEXT:    v_cvt_f32_f16_e32 v4, v92700; SI-NEXT:    v_or_b32_e32 v0, v1, v02701; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v22702; SI-NEXT:    v_cvt_f32_f16_e32 v2, v102703; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32704; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32705; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42706; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v22707; SI-NEXT:    v_cvt_f16_f32_e32 v2, v22708; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42709; SI-NEXT:    v_or_b32_e32 v1, v3, v12710; SI-NEXT:    v_cvt_f32_f16_e32 v3, v82711; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22712; SI-NEXT:    v_or_b32_e32 v2, v4, v22713; SI-NEXT:    v_cvt_f32_f16_e32 v4, v72714; SI-NEXT:    v_cvt_f32_f16_e32 v6, v62715; SI-NEXT:    v_cvt_f32_f16_e32 v5, v52716; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v32717; SI-NEXT:    v_cvt_f16_f32_e32 v3, v32718; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v42719; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v62720; SI-NEXT:    v_cvt_f16_f32_e32 v4, v42721; SI-NEXT:    v_cvt_f16_f32_e32 v6, v62722; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v52723; SI-NEXT:    v_cvt_f16_f32_e32 v5, v52724; SI-NEXT:    v_lshlrev_b32_e32 v3, 16, v32725; SI-NEXT:    v_or_b32_e32 v3, v4, v32726; SI-NEXT:    v_lshlrev_b32_e32 v4, 16, v62727; SI-NEXT:    v_or_b32_e32 v4, v5, v42728; SI-NEXT:  .LBB19_3: ; %end2729; SI-NEXT:    s_setpc_b64 s[30:31]2730; SI-NEXT:  .LBB19_4:2731; SI-NEXT:    ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr42732; SI-NEXT:    s_branch .LBB19_22733;2734; VI-LABEL: bitcast_v10f16_to_v5f32_scalar:2735; VI:       ; %bb.0:2736; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2737; VI-NEXT:    s_cmp_lg_u32 s21, 02738; VI-NEXT:    s_cbranch_scc0 .LBB19_32739; VI-NEXT:  ; %bb.1: ; %cmp.false2740; VI-NEXT:    s_cbranch_execnz .LBB19_42741; VI-NEXT:  .LBB19_2: ; %cmp.true2742; VI-NEXT:    s_lshr_b32 s4, s20, 162743; VI-NEXT:    v_mov_b32_e32 v0, 0x2002744; VI-NEXT:    v_mov_b32_e32 v1, s42745; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2746; VI-NEXT:    v_add_f16_e32 v2, s20, v02747; VI-NEXT:    s_lshr_b32 s4, s19, 162748; VI-NEXT:    v_or_b32_e32 v4, v2, v12749; VI-NEXT:    v_mov_b32_e32 v1, s42750; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2751; VI-NEXT:    v_add_f16_e32 v2, s19, v02752; VI-NEXT:    s_lshr_b32 s4, s18, 162753; VI-NEXT:    v_or_b32_e32 v3, v2, v12754; VI-NEXT:    v_mov_b32_e32 v1, s42755; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2756; VI-NEXT:    v_add_f16_e32 v2, s18, v02757; VI-NEXT:    s_lshr_b32 s4, s17, 162758; VI-NEXT:    v_or_b32_e32 v2, v2, v12759; VI-NEXT:    v_mov_b32_e32 v1, s42760; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2761; VI-NEXT:    v_add_f16_e32 v5, s17, v02762; VI-NEXT:    s_lshr_b32 s4, s16, 162763; VI-NEXT:    v_or_b32_e32 v1, v5, v12764; VI-NEXT:    v_mov_b32_e32 v5, s42765; VI-NEXT:    v_add_f16_sdwa v5, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2766; VI-NEXT:    v_add_f16_e32 v0, s16, v02767; VI-NEXT:    v_or_b32_e32 v0, v0, v52768; VI-NEXT:    s_setpc_b64 s[30:31]2769; VI-NEXT:  .LBB19_3:2770; VI-NEXT:    s_branch .LBB19_22771; VI-NEXT:  .LBB19_4:2772; VI-NEXT:    v_mov_b32_e32 v0, s162773; VI-NEXT:    v_mov_b32_e32 v1, s172774; VI-NEXT:    v_mov_b32_e32 v2, s182775; VI-NEXT:    v_mov_b32_e32 v3, s192776; VI-NEXT:    v_mov_b32_e32 v4, s202777; VI-NEXT:    s_setpc_b64 s[30:31]2778;2779; GFX9-LABEL: bitcast_v10f16_to_v5f32_scalar:2780; GFX9:       ; %bb.0:2781; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2782; GFX9-NEXT:    s_cmp_lg_u32 s21, 02783; GFX9-NEXT:    s_cbranch_scc0 .LBB19_32784; GFX9-NEXT:  ; %bb.1: ; %cmp.false2785; GFX9-NEXT:    s_cbranch_execnz .LBB19_42786; GFX9-NEXT:  .LBB19_2: ; %cmp.true2787; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2002788; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]2789; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]2790; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]2791; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]2792; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]2793; GFX9-NEXT:    s_setpc_b64 s[30:31]2794; GFX9-NEXT:  .LBB19_3:2795; GFX9-NEXT:    s_branch .LBB19_22796; GFX9-NEXT:  .LBB19_4:2797; GFX9-NEXT:    v_mov_b32_e32 v0, s162798; GFX9-NEXT:    v_mov_b32_e32 v1, s172799; GFX9-NEXT:    v_mov_b32_e32 v2, s182800; GFX9-NEXT:    v_mov_b32_e32 v3, s192801; GFX9-NEXT:    v_mov_b32_e32 v4, s202802; GFX9-NEXT:    s_setpc_b64 s[30:31]2803;2804; GFX11-LABEL: bitcast_v10f16_to_v5f32_scalar:2805; GFX11:       ; %bb.0:2806; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2807; GFX11-NEXT:    s_mov_b32 s4, s162808; GFX11-NEXT:    s_cmp_lg_u32 s17, 02809; GFX11-NEXT:    s_mov_b32 s5, 02810; GFX11-NEXT:    s_cbranch_scc0 .LBB19_32811; GFX11-NEXT:  ; %bb.1: ; %Flow2812; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s52813; GFX11-NEXT:    s_cbranch_vccnz .LBB19_42814; GFX11-NEXT:  .LBB19_2: ; %cmp.true2815; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]2816; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]2817; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]2818; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]2819; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]2820; GFX11-NEXT:    s_setpc_b64 s[30:31]2821; GFX11-NEXT:  .LBB19_3:2822; GFX11-NEXT:    s_branch .LBB19_22823; GFX11-NEXT:  .LBB19_4:2824; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12825; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32826; GFX11-NEXT:    v_mov_b32_e32 v4, s42827; GFX11-NEXT:    s_setpc_b64 s[30:31]2828  %cmp = icmp eq i32 %b, 02829  br i1 %cmp, label %cmp.true, label %cmp.false2830 2831cmp.true:2832  %a1 = fadd <10 x half> %a, splat (half 0xH0200)2833  %a2 = bitcast <10 x half> %a1 to <5 x float>2834  br label %end2835 2836cmp.false:2837  %a3 = bitcast <10 x half> %a to <5 x float>2838  br label %end2839 2840end:2841  %phi = phi <5 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2842  ret <5 x float> %phi2843}2844 2845define <10 x half> @bitcast_v10i16_to_v10f16(<10 x i16> %a, i32 %b) {2846; SI-LABEL: bitcast_v10i16_to_v10f16:2847; SI:       ; %bb.0:2848; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2849; SI-NEXT:    v_mov_b32_e32 v19, v92850; SI-NEXT:    v_mov_b32_e32 v18, v82851; SI-NEXT:    v_mov_b32_e32 v17, v72852; SI-NEXT:    v_mov_b32_e32 v16, v62853; SI-NEXT:    v_mov_b32_e32 v15, v52854; SI-NEXT:    v_mov_b32_e32 v14, v42855; SI-NEXT:    v_mov_b32_e32 v13, v32856; SI-NEXT:    v_mov_b32_e32 v12, v22857; SI-NEXT:    v_mov_b32_e32 v11, v12858; SI-NEXT:    v_mov_b32_e32 v20, v02859; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v102860; SI-NEXT:    ; implicit-def: $vgpr02861; SI-NEXT:    ; implicit-def: $vgpr12862; SI-NEXT:    ; implicit-def: $vgpr22863; SI-NEXT:    ; implicit-def: $vgpr32864; SI-NEXT:    ; implicit-def: $vgpr42865; SI-NEXT:    ; implicit-def: $vgpr52866; SI-NEXT:    ; implicit-def: $vgpr62867; SI-NEXT:    ; implicit-def: $vgpr72868; SI-NEXT:    ; implicit-def: $vgpr82869; SI-NEXT:    ; implicit-def: $vgpr92870; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2871; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2872; SI-NEXT:    s_cbranch_execnz .LBB20_32873; SI-NEXT:  ; %bb.1: ; %Flow2874; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2875; SI-NEXT:    s_cbranch_execnz .LBB20_42876; SI-NEXT:  .LBB20_2: ; %end2877; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2878; SI-NEXT:    s_setpc_b64 s[30:31]2879; SI-NEXT:  .LBB20_3: ; %cmp.false2880; SI-NEXT:    v_cvt_f32_f16_e32 v0, v202881; SI-NEXT:    v_cvt_f32_f16_e32 v1, v112882; SI-NEXT:    v_cvt_f32_f16_e32 v2, v122883; SI-NEXT:    v_cvt_f32_f16_e32 v3, v132884; SI-NEXT:    v_cvt_f32_f16_e32 v4, v142885; SI-NEXT:    v_cvt_f32_f16_e32 v5, v152886; SI-NEXT:    v_cvt_f32_f16_e32 v6, v162887; SI-NEXT:    v_cvt_f32_f16_e32 v7, v172888; SI-NEXT:    v_cvt_f32_f16_e32 v8, v182889; SI-NEXT:    v_cvt_f32_f16_e32 v9, v192890; SI-NEXT:    ; implicit-def: $vgpr202891; SI-NEXT:    ; implicit-def: $vgpr112892; SI-NEXT:    ; implicit-def: $vgpr122893; SI-NEXT:    ; implicit-def: $vgpr132894; SI-NEXT:    ; implicit-def: $vgpr142895; SI-NEXT:    ; implicit-def: $vgpr152896; SI-NEXT:    ; implicit-def: $vgpr162897; SI-NEXT:    ; implicit-def: $vgpr172898; SI-NEXT:    ; implicit-def: $vgpr182899; SI-NEXT:    ; implicit-def: $vgpr192900; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2901; SI-NEXT:    s_cbranch_execz .LBB20_22902; SI-NEXT:  .LBB20_4: ; %cmp.true2903; SI-NEXT:    v_add_i32_e32 v9, vcc, 3, v192904; SI-NEXT:    v_add_i32_e32 v8, vcc, 3, v182905; SI-NEXT:    v_add_i32_e32 v7, vcc, 3, v172906; SI-NEXT:    v_add_i32_e32 v6, vcc, 3, v162907; SI-NEXT:    v_add_i32_e32 v5, vcc, 3, v152908; SI-NEXT:    v_add_i32_e32 v4, vcc, 3, v142909; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v132910; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v122911; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v112912; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v202913; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02914; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12915; SI-NEXT:    v_cvt_f32_f16_e32 v2, v22916; SI-NEXT:    v_cvt_f32_f16_e32 v3, v32917; SI-NEXT:    v_cvt_f32_f16_e32 v4, v42918; SI-NEXT:    v_cvt_f32_f16_e32 v5, v52919; SI-NEXT:    v_cvt_f32_f16_e32 v6, v62920; SI-NEXT:    v_cvt_f32_f16_e32 v7, v72921; SI-NEXT:    v_cvt_f32_f16_e32 v8, v82922; SI-NEXT:    v_cvt_f32_f16_e32 v9, v92923; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2924; SI-NEXT:    s_setpc_b64 s[30:31]2925;2926; VI-LABEL: bitcast_v10i16_to_v10f16:2927; VI:       ; %bb.0:2928; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2929; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52930; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2931; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2932; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2933; VI-NEXT:    s_cbranch_execz .LBB20_22934; VI-NEXT:  ; %bb.1: ; %cmp.true2935; VI-NEXT:    v_mov_b32_e32 v5, 32936; VI-NEXT:    v_add_u16_sdwa v6, v0, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2937; VI-NEXT:    v_add_u16_sdwa v7, v1, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2938; VI-NEXT:    v_add_u16_sdwa v8, v2, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2939; VI-NEXT:    v_add_u16_sdwa v9, v3, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2940; VI-NEXT:    v_add_u16_sdwa v5, v4, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2941; VI-NEXT:    v_add_u16_e32 v4, 3, v42942; VI-NEXT:    v_add_u16_e32 v3, 3, v32943; VI-NEXT:    v_add_u16_e32 v2, 3, v22944; VI-NEXT:    v_add_u16_e32 v1, 3, v12945; VI-NEXT:    v_add_u16_e32 v0, 3, v02946; VI-NEXT:    v_or_b32_e32 v4, v4, v52947; VI-NEXT:    v_or_b32_e32 v3, v3, v92948; VI-NEXT:    v_or_b32_e32 v2, v2, v82949; VI-NEXT:    v_or_b32_e32 v1, v1, v72950; VI-NEXT:    v_or_b32_e32 v0, v0, v62951; VI-NEXT:  .LBB20_2: ; %end2952; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2953; VI-NEXT:    s_setpc_b64 s[30:31]2954;2955; GFX9-LABEL: bitcast_v10i16_to_v10f16:2956; GFX9:       ; %bb.0:2957; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2958; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v52959; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2960; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2961; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2962; GFX9-NEXT:  ; %bb.1: ; %cmp.true2963; GFX9-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2964; GFX9-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2965; GFX9-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2966; GFX9-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2967; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2968; GFX9-NEXT:  ; %bb.2: ; %end2969; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2970; GFX9-NEXT:    s_setpc_b64 s[30:31]2971;2972; GFX11-LABEL: bitcast_v10i16_to_v10f16:2973; GFX11:       ; %bb.0:2974; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2975; GFX11-NEXT:    s_mov_b32 s0, exec_lo2976; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v52977; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02978; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2979; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02980; GFX11-NEXT:  ; %bb.1: ; %cmp.true2981; GFX11-NEXT:    v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2982; GFX11-NEXT:    v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2983; GFX11-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2984; GFX11-NEXT:    v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2985; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2986; GFX11-NEXT:  ; %bb.2: ; %end2987; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02988; GFX11-NEXT:    s_setpc_b64 s[30:31]2989  %cmp = icmp eq i32 %b, 02990  br i1 %cmp, label %cmp.true, label %cmp.false2991 2992cmp.true:2993  %a1 = add <10 x i16> %a, splat (i16 3)2994  %a2 = bitcast <10 x i16> %a1 to <10 x half>2995  br label %end2996 2997cmp.false:2998  %a3 = bitcast <10 x i16> %a to <10 x half>2999  br label %end3000 3001end:3002  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3003  ret <10 x half> %phi3004}3005 3006define inreg <10 x half> @bitcast_v10i16_to_v10f16_scalar(<10 x i16> inreg %a, i32 inreg %b) {3007; SI-LABEL: bitcast_v10i16_to_v10f16_scalar:3008; SI:       ; %bb.0:3009; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3010; SI-NEXT:    s_cmp_lg_u32 s26, 03011; SI-NEXT:    s_cbranch_scc0 .LBB21_43012; SI-NEXT:  ; %bb.1: ; %cmp.false3013; SI-NEXT:    v_cvt_f32_f16_e32 v0, s163014; SI-NEXT:    v_cvt_f32_f16_e32 v1, s173015; SI-NEXT:    v_cvt_f32_f16_e32 v2, s183016; SI-NEXT:    v_cvt_f32_f16_e32 v3, s193017; SI-NEXT:    v_cvt_f32_f16_e32 v4, s203018; SI-NEXT:    v_cvt_f32_f16_e32 v5, s213019; SI-NEXT:    v_cvt_f32_f16_e32 v6, s223020; SI-NEXT:    v_cvt_f32_f16_e32 v7, s233021; SI-NEXT:    v_cvt_f32_f16_e32 v8, s243022; SI-NEXT:    v_cvt_f32_f16_e32 v9, s253023; SI-NEXT:    s_cbranch_execnz .LBB21_33024; SI-NEXT:  .LBB21_2: ; %cmp.true3025; SI-NEXT:    s_add_i32 s25, s25, 33026; SI-NEXT:    s_add_i32 s24, s24, 33027; SI-NEXT:    s_add_i32 s23, s23, 33028; SI-NEXT:    s_add_i32 s22, s22, 33029; SI-NEXT:    s_add_i32 s21, s21, 33030; SI-NEXT:    s_add_i32 s20, s20, 33031; SI-NEXT:    s_add_i32 s19, s19, 33032; SI-NEXT:    s_add_i32 s18, s18, 33033; SI-NEXT:    s_add_i32 s17, s17, 33034; SI-NEXT:    s_add_i32 s16, s16, 33035; SI-NEXT:    v_cvt_f32_f16_e32 v0, s163036; SI-NEXT:    v_cvt_f32_f16_e32 v1, s173037; SI-NEXT:    v_cvt_f32_f16_e32 v2, s183038; SI-NEXT:    v_cvt_f32_f16_e32 v3, s193039; SI-NEXT:    v_cvt_f32_f16_e32 v4, s203040; SI-NEXT:    v_cvt_f32_f16_e32 v5, s213041; SI-NEXT:    v_cvt_f32_f16_e32 v6, s223042; SI-NEXT:    v_cvt_f32_f16_e32 v7, s233043; SI-NEXT:    v_cvt_f32_f16_e32 v8, s243044; SI-NEXT:    v_cvt_f32_f16_e32 v9, s253045; SI-NEXT:  .LBB21_3: ; %end3046; SI-NEXT:    s_setpc_b64 s[30:31]3047; SI-NEXT:  .LBB21_4:3048; SI-NEXT:    ; implicit-def: $vgpr03049; SI-NEXT:    ; implicit-def: $vgpr13050; SI-NEXT:    ; implicit-def: $vgpr23051; SI-NEXT:    ; implicit-def: $vgpr33052; SI-NEXT:    ; implicit-def: $vgpr43053; SI-NEXT:    ; implicit-def: $vgpr53054; SI-NEXT:    ; implicit-def: $vgpr63055; SI-NEXT:    ; implicit-def: $vgpr73056; SI-NEXT:    ; implicit-def: $vgpr83057; SI-NEXT:    ; implicit-def: $vgpr93058; SI-NEXT:    s_branch .LBB21_23059;3060; VI-LABEL: bitcast_v10i16_to_v10f16_scalar:3061; VI:       ; %bb.0:3062; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3063; VI-NEXT:    s_cmp_lg_u32 s21, 03064; VI-NEXT:    s_cbranch_scc0 .LBB21_43065; VI-NEXT:  ; %bb.1: ; %cmp.false3066; VI-NEXT:    s_cbranch_execnz .LBB21_33067; VI-NEXT:  .LBB21_2: ; %cmp.true3068; VI-NEXT:    s_add_i32 s5, s16, 33069; VI-NEXT:    s_add_i32 s7, s17, 33070; VI-NEXT:    s_add_i32 s9, s18, 33071; VI-NEXT:    s_add_i32 s11, s19, 33072; VI-NEXT:    s_add_i32 s13, s20, 33073; VI-NEXT:    s_and_b32 s4, s16, 0xffff00003074; VI-NEXT:    s_and_b32 s6, s17, 0xffff00003075; VI-NEXT:    s_and_b32 s8, s18, 0xffff00003076; VI-NEXT:    s_and_b32 s10, s19, 0xffff00003077; VI-NEXT:    s_and_b32 s12, s20, 0xffff00003078; VI-NEXT:    s_and_b32 s13, s13, 0xffff3079; VI-NEXT:    s_and_b32 s11, s11, 0xffff3080; VI-NEXT:    s_and_b32 s9, s9, 0xffff3081; VI-NEXT:    s_and_b32 s7, s7, 0xffff3082; VI-NEXT:    s_and_b32 s5, s5, 0xffff3083; VI-NEXT:    s_or_b32 s12, s12, s133084; VI-NEXT:    s_or_b32 s10, s10, s113085; VI-NEXT:    s_or_b32 s8, s8, s93086; VI-NEXT:    s_or_b32 s6, s6, s73087; VI-NEXT:    s_or_b32 s4, s4, s53088; VI-NEXT:    s_add_i32 s20, s12, 0x300003089; VI-NEXT:    s_add_i32 s19, s10, 0x300003090; VI-NEXT:    s_add_i32 s18, s8, 0x300003091; VI-NEXT:    s_add_i32 s17, s6, 0x300003092; VI-NEXT:    s_add_i32 s16, s4, 0x300003093; VI-NEXT:  .LBB21_3: ; %end3094; VI-NEXT:    v_mov_b32_e32 v0, s163095; VI-NEXT:    v_mov_b32_e32 v1, s173096; VI-NEXT:    v_mov_b32_e32 v2, s183097; VI-NEXT:    v_mov_b32_e32 v3, s193098; VI-NEXT:    v_mov_b32_e32 v4, s203099; VI-NEXT:    s_setpc_b64 s[30:31]3100; VI-NEXT:  .LBB21_4:3101; VI-NEXT:    s_branch .LBB21_23102;3103; GFX9-LABEL: bitcast_v10i16_to_v10f16_scalar:3104; GFX9:       ; %bb.0:3105; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3106; GFX9-NEXT:    s_cmp_lg_u32 s21, 03107; GFX9-NEXT:    s_cbranch_scc0 .LBB21_33108; GFX9-NEXT:  ; %bb.1: ; %cmp.false3109; GFX9-NEXT:    s_cbranch_execnz .LBB21_43110; GFX9-NEXT:  .LBB21_2: ; %cmp.true3111; GFX9-NEXT:    v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]3112; GFX9-NEXT:    v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]3113; GFX9-NEXT:    v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]3114; GFX9-NEXT:    v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]3115; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]3116; GFX9-NEXT:    s_setpc_b64 s[30:31]3117; GFX9-NEXT:  .LBB21_3:3118; GFX9-NEXT:    s_branch .LBB21_23119; GFX9-NEXT:  .LBB21_4:3120; GFX9-NEXT:    v_mov_b32_e32 v0, s163121; GFX9-NEXT:    v_mov_b32_e32 v1, s173122; GFX9-NEXT:    v_mov_b32_e32 v2, s183123; GFX9-NEXT:    v_mov_b32_e32 v3, s193124; GFX9-NEXT:    v_mov_b32_e32 v4, s203125; GFX9-NEXT:    v_mov_b32_e32 v5, s213126; GFX9-NEXT:    v_mov_b32_e32 v6, s223127; GFX9-NEXT:    v_mov_b32_e32 v7, s233128; GFX9-NEXT:    s_setpc_b64 s[30:31]3129;3130; GFX11-LABEL: bitcast_v10i16_to_v10f16_scalar:3131; GFX11:       ; %bb.0:3132; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3133; GFX11-NEXT:    s_mov_b32 s4, s163134; GFX11-NEXT:    s_cmp_lg_u32 s17, 03135; GFX11-NEXT:    s_mov_b32 s8, 03136; GFX11-NEXT:    s_cbranch_scc0 .LBB21_33137; GFX11-NEXT:  ; %bb.1: ; %Flow3138; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s83139; GFX11-NEXT:    s_cbranch_vccnz .LBB21_43140; GFX11-NEXT:  .LBB21_2: ; %cmp.true3141; GFX11-NEXT:    v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]3142; GFX11-NEXT:    v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]3143; GFX11-NEXT:    v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]3144; GFX11-NEXT:    v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]3145; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]3146; GFX11-NEXT:    s_setpc_b64 s[30:31]3147; GFX11-NEXT:  .LBB21_3:3148; GFX11-NEXT:    s_branch .LBB21_23149; GFX11-NEXT:  .LBB21_4:3150; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13151; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33152; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53153; GFX11-NEXT:    v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s73154; GFX11-NEXT:    s_setpc_b64 s[30:31]3155  %cmp = icmp eq i32 %b, 03156  br i1 %cmp, label %cmp.true, label %cmp.false3157 3158cmp.true:3159  %a1 = add <10 x i16> %a, splat (i16 3)3160  %a2 = bitcast <10 x i16> %a1 to <10 x half>3161  br label %end3162 3163cmp.false:3164  %a3 = bitcast <10 x i16> %a to <10 x half>3165  br label %end3166 3167end:3168  %phi = phi <10 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3169  ret <10 x half> %phi3170}3171 3172define <10 x i16> @bitcast_v10f16_to_v10i16(<10 x half> %a, i32 %b) {3173; SI-LABEL: bitcast_v10f16_to_v10i16:3174; SI:       ; %bb.0:3175; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3176; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03177; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13178; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23179; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33180; SI-NEXT:    v_cvt_f16_f32_e32 v4, v43181; SI-NEXT:    v_cvt_f16_f32_e32 v5, v53182; SI-NEXT:    v_cvt_f16_f32_e32 v6, v63183; SI-NEXT:    v_cvt_f16_f32_e32 v7, v73184; SI-NEXT:    v_cvt_f16_f32_e32 v8, v83185; SI-NEXT:    v_cvt_f16_f32_e32 v9, v93186; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v103187; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3188; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3189; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3190; SI-NEXT:    s_cbranch_execz .LBB22_23191; SI-NEXT:  ; %bb.1: ; %cmp.true3192; SI-NEXT:    v_cvt_f32_f16_e32 v9, v93193; SI-NEXT:    v_cvt_f32_f16_e32 v8, v83194; SI-NEXT:    v_cvt_f32_f16_e32 v7, v73195; SI-NEXT:    v_cvt_f32_f16_e32 v6, v63196; SI-NEXT:    v_cvt_f32_f16_e32 v3, v33197; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13198; SI-NEXT:    v_cvt_f32_f16_e32 v5, v53199; SI-NEXT:    v_cvt_f32_f16_e32 v2, v23200; SI-NEXT:    v_cvt_f32_f16_e32 v0, v03201; SI-NEXT:    v_cvt_f32_f16_e32 v4, v43202; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v93203; SI-NEXT:    v_cvt_f16_f32_e32 v9, v93204; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v83205; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v73206; SI-NEXT:    v_cvt_f16_f32_e32 v8, v83207; SI-NEXT:    v_cvt_f16_f32_e32 v7, v73208; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v63209; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v33210; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v13211; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v53212; SI-NEXT:    v_cvt_f16_f32_e32 v6, v63213; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33214; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v23215; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v03216; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13217; SI-NEXT:    v_cvt_f16_f32_e32 v5, v53218; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v43219; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23220; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03221; SI-NEXT:    v_cvt_f16_f32_e32 v4, v43222; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v93223; SI-NEXT:    v_or_b32_e32 v8, v8, v103224; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v73225; SI-NEXT:    v_or_b32_e32 v6, v6, v103226; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v33227; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v13228; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v53229; SI-NEXT:    v_or_b32_e32 v2, v2, v103230; SI-NEXT:    v_or_b32_e32 v0, v0, v13231; SI-NEXT:    v_or_b32_e32 v4, v4, v53232; SI-NEXT:    v_alignbit_b32 v1, v2, v1, 163233; SI-NEXT:    v_alignbit_b32 v5, v6, v5, 163234; SI-NEXT:  .LBB22_2: ; %end3235; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3236; SI-NEXT:    s_setpc_b64 s[30:31]3237;3238; VI-LABEL: bitcast_v10f16_to_v10i16:3239; VI:       ; %bb.0:3240; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3241; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v53242; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3243; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3244; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3245; VI-NEXT:    s_cbranch_execz .LBB22_23246; VI-NEXT:  ; %bb.1: ; %cmp.true3247; VI-NEXT:    v_mov_b32_e32 v6, 0x2003248; VI-NEXT:    v_add_f16_e32 v5, 0x200, v03249; VI-NEXT:    v_add_f16_sdwa v0, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3250; VI-NEXT:    v_add_f16_e32 v7, 0x200, v13251; VI-NEXT:    v_add_f16_sdwa v1, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3252; VI-NEXT:    v_add_f16_e32 v8, 0x200, v23253; VI-NEXT:    v_add_f16_sdwa v2, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3254; VI-NEXT:    v_add_f16_e32 v9, 0x200, v33255; VI-NEXT:    v_add_f16_sdwa v3, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3256; VI-NEXT:    v_add_f16_e32 v10, 0x200, v43257; VI-NEXT:    v_add_f16_sdwa v4, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3258; VI-NEXT:    v_or_b32_e32 v4, v10, v43259; VI-NEXT:    v_or_b32_e32 v3, v9, v33260; VI-NEXT:    v_or_b32_e32 v2, v8, v23261; VI-NEXT:    v_or_b32_e32 v1, v7, v13262; VI-NEXT:    v_or_b32_e32 v0, v5, v03263; VI-NEXT:  .LBB22_2: ; %end3264; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3265; VI-NEXT:    s_setpc_b64 s[30:31]3266;3267; GFX9-LABEL: bitcast_v10f16_to_v10i16:3268; GFX9:       ; %bb.0:3269; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3270; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v53271; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3272; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3273; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3274; GFX9-NEXT:  ; %bb.1: ; %cmp.true3275; GFX9-NEXT:    s_movk_i32 s6, 0x2003276; GFX9-NEXT:    v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]3277; GFX9-NEXT:    v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]3278; GFX9-NEXT:    v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]3279; GFX9-NEXT:    v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]3280; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3281; GFX9-NEXT:  ; %bb.2: ; %end3282; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3283; GFX9-NEXT:    s_setpc_b64 s[30:31]3284;3285; GFX11-LABEL: bitcast_v10f16_to_v10i16:3286; GFX11:       ; %bb.0:3287; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3288; GFX11-NEXT:    s_mov_b32 s0, exec_lo3289; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v53290; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03291; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3292; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03293; GFX11-NEXT:  ; %bb.1: ; %cmp.true3294; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]3295; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]3296; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]3297; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]3298; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3299; GFX11-NEXT:  ; %bb.2: ; %end3300; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03301; GFX11-NEXT:    s_setpc_b64 s[30:31]3302  %cmp = icmp eq i32 %b, 03303  br i1 %cmp, label %cmp.true, label %cmp.false3304 3305cmp.true:3306  %a1 = fadd <10 x half> %a, splat (half 0xH0200)3307  %a2 = bitcast <10 x half> %a1 to <10 x i16>3308  br label %end3309 3310cmp.false:3311  %a3 = bitcast <10 x half> %a to <10 x i16>3312  br label %end3313 3314end:3315  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3316  ret <10 x i16> %phi3317}3318 3319define inreg <10 x i16> @bitcast_v10f16_to_v10i16_scalar(<10 x half> inreg %a, i32 inreg %b) {3320; SI-LABEL: bitcast_v10f16_to_v10i16_scalar:3321; SI:       ; %bb.0:3322; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3323; SI-NEXT:    v_cvt_f16_f32_e32 v0, s163324; SI-NEXT:    v_cvt_f16_f32_e32 v10, s173325; SI-NEXT:    v_cvt_f16_f32_e32 v2, s183326; SI-NEXT:    v_cvt_f16_f32_e32 v3, s193327; SI-NEXT:    v_cvt_f16_f32_e32 v4, s203328; SI-NEXT:    v_cvt_f16_f32_e32 v11, s213329; SI-NEXT:    v_cvt_f16_f32_e32 v6, s223330; SI-NEXT:    v_cvt_f16_f32_e32 v7, s233331; SI-NEXT:    v_cvt_f16_f32_e32 v8, s243332; SI-NEXT:    v_cvt_f16_f32_e32 v9, s253333; SI-NEXT:    s_cmp_lg_u32 s26, 03334; SI-NEXT:    s_cbranch_scc0 .LBB23_43335; SI-NEXT:  ; %bb.1: ; %cmp.false3336; SI-NEXT:    s_cbranch_execnz .LBB23_33337; SI-NEXT:  .LBB23_2: ; %cmp.true3338; SI-NEXT:    v_cvt_f32_f16_e32 v7, v73339; SI-NEXT:    v_cvt_f32_f16_e32 v6, v63340; SI-NEXT:    v_cvt_f32_f16_e32 v3, v33341; SI-NEXT:    v_cvt_f32_f16_e32 v1, v103342; SI-NEXT:    v_cvt_f32_f16_e32 v2, v23343; SI-NEXT:    v_cvt_f32_f16_e32 v5, v113344; SI-NEXT:    v_cvt_f32_f16_e32 v9, v93345; SI-NEXT:    v_add_f32_e32 v7, 0x38000000, v73346; SI-NEXT:    v_cvt_f32_f16_e32 v0, v03347; SI-NEXT:    v_cvt_f32_f16_e32 v4, v43348; SI-NEXT:    v_cvt_f32_f16_e32 v8, v83349; SI-NEXT:    v_cvt_f16_f32_e32 v7, v73350; SI-NEXT:    v_add_f32_e32 v6, 0x38000000, v63351; SI-NEXT:    v_add_f32_e32 v3, 0x38000000, v33352; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v13353; SI-NEXT:    v_cvt_f16_f32_e32 v6, v63354; SI-NEXT:    v_cvt_f16_f32_e32 v3, v33355; SI-NEXT:    v_add_f32_e32 v2, 0x38000000, v23356; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13357; SI-NEXT:    v_add_f32_e32 v5, 0x38000000, v53358; SI-NEXT:    v_cvt_f16_f32_e32 v2, v23359; SI-NEXT:    v_cvt_f16_f32_e32 v5, v53360; SI-NEXT:    v_add_f32_e32 v9, 0x38000000, v93361; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v03362; SI-NEXT:    v_add_f32_e32 v4, 0x38000000, v43363; SI-NEXT:    v_cvt_f16_f32_e32 v9, v93364; SI-NEXT:    v_add_f32_e32 v8, 0x38000000, v83365; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v73366; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03367; SI-NEXT:    v_cvt_f16_f32_e32 v4, v43368; SI-NEXT:    v_cvt_f16_f32_e32 v8, v83369; SI-NEXT:    v_or_b32_e32 v6, v6, v103370; SI-NEXT:    v_lshlrev_b32_e32 v10, 16, v33371; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v13372; SI-NEXT:    v_or_b32_e32 v2, v2, v103373; SI-NEXT:    v_lshlrev_b32_e32 v5, 16, v53374; SI-NEXT:    v_lshr_b64 v[10:11], v[1:2], 163375; SI-NEXT:    v_lshlrev_b32_e32 v13, 16, v93376; SI-NEXT:    v_lshr_b64 v[11:12], v[5:6], 163377; SI-NEXT:    v_or_b32_e32 v0, v0, v13378; SI-NEXT:    v_or_b32_e32 v4, v4, v53379; SI-NEXT:    v_or_b32_e32 v8, v8, v133380; SI-NEXT:  .LBB23_3: ; %end3381; SI-NEXT:    v_mov_b32_e32 v1, v103382; SI-NEXT:    v_mov_b32_e32 v5, v113383; SI-NEXT:    s_setpc_b64 s[30:31]3384; SI-NEXT:  .LBB23_4:3385; SI-NEXT:    s_branch .LBB23_23386;3387; VI-LABEL: bitcast_v10f16_to_v10i16_scalar:3388; VI:       ; %bb.0:3389; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3390; VI-NEXT:    s_cmp_lg_u32 s21, 03391; VI-NEXT:    s_cbranch_scc0 .LBB23_33392; VI-NEXT:  ; %bb.1: ; %cmp.false3393; VI-NEXT:    s_cbranch_execnz .LBB23_43394; VI-NEXT:  .LBB23_2: ; %cmp.true3395; VI-NEXT:    s_lshr_b32 s4, s16, 163396; VI-NEXT:    v_mov_b32_e32 v1, s43397; VI-NEXT:    s_lshr_b32 s4, s17, 163398; VI-NEXT:    v_mov_b32_e32 v2, s43399; VI-NEXT:    s_lshr_b32 s4, s18, 163400; VI-NEXT:    v_mov_b32_e32 v3, s43401; VI-NEXT:    s_lshr_b32 s4, s19, 163402; VI-NEXT:    v_mov_b32_e32 v4, s43403; VI-NEXT:    s_lshr_b32 s4, s20, 163404; VI-NEXT:    v_mov_b32_e32 v0, 0x2003405; VI-NEXT:    v_mov_b32_e32 v10, s43406; VI-NEXT:    v_add_f16_e32 v5, s16, v03407; VI-NEXT:    v_add_f16_sdwa v6, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3408; VI-NEXT:    v_add_f16_e32 v1, s17, v03409; VI-NEXT:    v_add_f16_sdwa v7, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3410; VI-NEXT:    v_add_f16_e32 v2, s18, v03411; VI-NEXT:    v_add_f16_sdwa v8, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3412; VI-NEXT:    v_add_f16_e32 v3, s19, v03413; VI-NEXT:    v_add_f16_sdwa v9, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3414; VI-NEXT:    v_add_f16_e32 v4, s20, v03415; VI-NEXT:    v_add_f16_sdwa v0, v10, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3416; VI-NEXT:    v_or_b32_e32 v4, v4, v03417; VI-NEXT:    v_or_b32_e32 v3, v3, v93418; VI-NEXT:    v_or_b32_e32 v2, v2, v83419; VI-NEXT:    v_or_b32_e32 v1, v1, v73420; VI-NEXT:    v_or_b32_e32 v0, v5, v63421; VI-NEXT:    s_setpc_b64 s[30:31]3422; VI-NEXT:  .LBB23_3:3423; VI-NEXT:    s_branch .LBB23_23424; VI-NEXT:  .LBB23_4:3425; VI-NEXT:    v_mov_b32_e32 v0, s163426; VI-NEXT:    v_mov_b32_e32 v1, s173427; VI-NEXT:    v_mov_b32_e32 v2, s183428; VI-NEXT:    v_mov_b32_e32 v3, s193429; VI-NEXT:    v_mov_b32_e32 v4, s203430; VI-NEXT:    v_mov_b32_e32 v5, s213431; VI-NEXT:    v_mov_b32_e32 v6, s223432; VI-NEXT:    v_mov_b32_e32 v7, s233433; VI-NEXT:    s_setpc_b64 s[30:31]3434;3435; GFX9-LABEL: bitcast_v10f16_to_v10i16_scalar:3436; GFX9:       ; %bb.0:3437; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3438; GFX9-NEXT:    s_cmp_lg_u32 s21, 03439; GFX9-NEXT:    s_cbranch_scc0 .LBB23_33440; GFX9-NEXT:  ; %bb.1: ; %cmp.false3441; GFX9-NEXT:    s_cbranch_execnz .LBB23_43442; GFX9-NEXT:  .LBB23_2: ; %cmp.true3443; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2003444; GFX9-NEXT:    v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]3445; GFX9-NEXT:    v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]3446; GFX9-NEXT:    v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]3447; GFX9-NEXT:    v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]3448; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]3449; GFX9-NEXT:    s_setpc_b64 s[30:31]3450; GFX9-NEXT:  .LBB23_3:3451; GFX9-NEXT:    s_branch .LBB23_23452; GFX9-NEXT:  .LBB23_4:3453; GFX9-NEXT:    v_mov_b32_e32 v0, s163454; GFX9-NEXT:    v_mov_b32_e32 v1, s173455; GFX9-NEXT:    v_mov_b32_e32 v2, s183456; GFX9-NEXT:    v_mov_b32_e32 v3, s193457; GFX9-NEXT:    v_mov_b32_e32 v4, s203458; GFX9-NEXT:    v_mov_b32_e32 v5, s213459; GFX9-NEXT:    v_mov_b32_e32 v6, s223460; GFX9-NEXT:    v_mov_b32_e32 v7, s233461; GFX9-NEXT:    s_setpc_b64 s[30:31]3462;3463; GFX11-LABEL: bitcast_v10f16_to_v10i16_scalar:3464; GFX11:       ; %bb.0:3465; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3466; GFX11-NEXT:    s_mov_b32 s4, s163467; GFX11-NEXT:    s_cmp_lg_u32 s17, 03468; GFX11-NEXT:    s_mov_b32 s8, 03469; GFX11-NEXT:    s_cbranch_scc0 .LBB23_33470; GFX11-NEXT:  ; %bb.1: ; %Flow3471; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s83472; GFX11-NEXT:    s_cbranch_vccnz .LBB23_43473; GFX11-NEXT:  .LBB23_2: ; %cmp.true3474; GFX11-NEXT:    v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]3475; GFX11-NEXT:    v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]3476; GFX11-NEXT:    v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]3477; GFX11-NEXT:    v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]3478; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]3479; GFX11-NEXT:    s_setpc_b64 s[30:31]3480; GFX11-NEXT:  .LBB23_3:3481; GFX11-NEXT:    s_branch .LBB23_23482; GFX11-NEXT:  .LBB23_4:3483; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13484; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33485; GFX11-NEXT:    v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53486; GFX11-NEXT:    v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s73487; GFX11-NEXT:    s_setpc_b64 s[30:31]3488  %cmp = icmp eq i32 %b, 03489  br i1 %cmp, label %cmp.true, label %cmp.false3490 3491cmp.true:3492  %a1 = fadd <10 x half> %a, splat (half 0xH0200)3493  %a2 = bitcast <10 x half> %a1 to <10 x i16>3494  br label %end3495 3496cmp.false:3497  %a3 = bitcast <10 x half> %a to <10 x i16>3498  br label %end3499 3500end:3501  %phi = phi <10 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3502  ret <10 x i16> %phi3503}3504;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:3505; GFX11-FAKE16: {{.*}}3506; GFX11-TRUE16: {{.*}}3507