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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define half @bitcast_i16_to_f16(i16 %a, i32 %b) {10; SI-LABEL: bitcast_i16_to_f16:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_and_b32_e32 v2, 0xffff, v014; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v115; SI-NEXT: ; implicit-def: $vgpr016; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc17; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]18; SI-NEXT: s_cbranch_execnz .LBB0_319; SI-NEXT: ; %bb.1: ; %Flow20; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]21; SI-NEXT: s_cbranch_execnz .LBB0_422; SI-NEXT: .LBB0_2: ; %end23; SI-NEXT: s_or_b64 exec, exec, s[4:5]24; SI-NEXT: s_setpc_b64 s[30:31]25; SI-NEXT: .LBB0_3: ; %cmp.false26; SI-NEXT: v_cvt_f32_f16_e32 v0, v227; SI-NEXT: ; implicit-def: $vgpr228; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]29; SI-NEXT: s_cbranch_execz .LBB0_230; SI-NEXT: .LBB0_4: ; %cmp.true31; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v232; SI-NEXT: v_cvt_f32_f16_e32 v0, v033; SI-NEXT: s_or_b64 exec, exec, s[4:5]34; SI-NEXT: s_setpc_b64 s[30:31]35;36; VI-LABEL: bitcast_i16_to_f16:37; VI: ; %bb.0:38; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v140; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc41; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]42; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]43; VI-NEXT: ; %bb.1: ; %cmp.true44; VI-NEXT: v_add_u16_e32 v0, 3, v045; VI-NEXT: ; %bb.2: ; %end46; VI-NEXT: s_or_b64 exec, exec, s[4:5]47; VI-NEXT: s_setpc_b64 s[30:31]48;49; GFX9-LABEL: bitcast_i16_to_f16:50; GFX9: ; %bb.0:51; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v153; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc54; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]55; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]56; GFX9-NEXT: ; %bb.1: ; %cmp.true57; GFX9-NEXT: v_add_u16_e32 v0, 3, v058; GFX9-NEXT: ; %bb.2: ; %end59; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]60; GFX9-NEXT: s_setpc_b64 s[30:31]61;62; GFX11-TRUE16-LABEL: bitcast_i16_to_f16:63; GFX11-TRUE16: ; %bb.0:64; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)65; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v166; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo1667; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo68; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)69; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s070; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false71; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l72; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr073; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow74; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s075; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB0_476; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true77; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v0.l, 378; GFX11-TRUE16-NEXT: .LBB0_4: ; %end79; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s080; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)81; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l82; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]83;84; GFX11-FAKE16-LABEL: bitcast_i16_to_f16:85; GFX11-FAKE16: ; %bb.0:86; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)87; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo88; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v189; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s090; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)91; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s092; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true93; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v0, 394; GFX11-FAKE16-NEXT: ; %bb.2: ; %end95; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s096; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]97 %cmp = icmp eq i32 %b, 098 br i1 %cmp, label %cmp.true, label %cmp.false99 100cmp.true:101 %a1 = add i16 %a, 3102 %a2 = bitcast i16 %a1 to half103 br label %end104 105cmp.false:106 %a3 = bitcast i16 %a to half107 br label %end108 109end:110 %phi = phi half [ %a2, %cmp.true ], [ %a3, %cmp.false ]111 ret half %phi112}113 114define inreg half @bitcast_i16_to_f16_scalar(i16 inreg %a, i32 inreg %b) {115; SI-LABEL: bitcast_i16_to_f16_scalar:116; SI: ; %bb.0:117; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; SI-NEXT: s_and_b32 s6, s16, 0xffff119; SI-NEXT: s_cmp_lg_u32 s17, 0120; SI-NEXT: s_cbranch_scc0 .LBB1_4121; SI-NEXT: ; %bb.1: ; %cmp.false122; SI-NEXT: v_cvt_f32_f16_e32 v0, s6123; SI-NEXT: s_cbranch_execnz .LBB1_3124; SI-NEXT: .LBB1_2: ; %cmp.true125; SI-NEXT: s_add_i32 s6, s6, 3126; SI-NEXT: v_cvt_f32_f16_e32 v0, s6127; SI-NEXT: .LBB1_3: ; %end128; SI-NEXT: s_setpc_b64 s[30:31]129; SI-NEXT: .LBB1_4:130; SI-NEXT: ; implicit-def: $vgpr0131; SI-NEXT: s_branch .LBB1_2132;133; VI-LABEL: bitcast_i16_to_f16_scalar:134; VI: ; %bb.0:135; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)136; VI-NEXT: s_cmp_lg_u32 s17, 0137; VI-NEXT: s_cbranch_scc0 .LBB1_4138; VI-NEXT: ; %bb.1: ; %cmp.false139; VI-NEXT: s_cbranch_execnz .LBB1_3140; VI-NEXT: .LBB1_2: ; %cmp.true141; VI-NEXT: s_add_i32 s16, s16, 3142; VI-NEXT: .LBB1_3: ; %end143; VI-NEXT: v_mov_b32_e32 v0, s16144; VI-NEXT: s_setpc_b64 s[30:31]145; VI-NEXT: .LBB1_4:146; VI-NEXT: s_branch .LBB1_2147;148; GFX9-LABEL: bitcast_i16_to_f16_scalar:149; GFX9: ; %bb.0:150; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)151; GFX9-NEXT: s_cmp_lg_u32 s17, 0152; GFX9-NEXT: s_cbranch_scc0 .LBB1_4153; GFX9-NEXT: ; %bb.1: ; %cmp.false154; GFX9-NEXT: s_cbranch_execnz .LBB1_3155; GFX9-NEXT: .LBB1_2: ; %cmp.true156; GFX9-NEXT: s_add_i32 s16, s16, 3157; GFX9-NEXT: .LBB1_3: ; %end158; GFX9-NEXT: v_mov_b32_e32 v0, s16159; GFX9-NEXT: s_setpc_b64 s[30:31]160; GFX9-NEXT: .LBB1_4:161; GFX9-NEXT: s_branch .LBB1_2162;163; GFX11-LABEL: bitcast_i16_to_f16_scalar:164; GFX11: ; %bb.0:165; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)166; GFX11-NEXT: s_cmp_lg_u32 s1, 0167; GFX11-NEXT: s_mov_b32 s1, 0168; GFX11-NEXT: s_cbranch_scc0 .LBB1_3169; GFX11-NEXT: ; %bb.1: ; %Flow170; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s1171; GFX11-NEXT: s_cbranch_vccz .LBB1_4172; GFX11-NEXT: ; %bb.2: ; %end173; GFX11-NEXT: v_mov_b32_e32 v0, s0174; GFX11-NEXT: s_setpc_b64 s[30:31]175; GFX11-NEXT: .LBB1_3:176; GFX11-NEXT: .LBB1_4: ; %cmp.true177; GFX11-NEXT: s_add_i32 s0, s0, 3178; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)179; GFX11-NEXT: v_mov_b32_e32 v0, s0180; GFX11-NEXT: s_setpc_b64 s[30:31]181 %cmp = icmp eq i32 %b, 0182 br i1 %cmp, label %cmp.true, label %cmp.false183 184cmp.true:185 %a1 = add i16 %a, 3186 %a2 = bitcast i16 %a1 to half187 br label %end188 189cmp.false:190 %a3 = bitcast i16 %a to half191 br label %end192 193end:194 %phi = phi half [ %a2, %cmp.true ], [ %a3, %cmp.false ]195 ret half %phi196}197 198define i16 @bitcast_f16_to_i16(half %a, i32 %b) {199; SI-LABEL: bitcast_f16_to_i16:200; SI: ; %bb.0:201; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)202; SI-NEXT: v_cvt_f16_f32_e32 v0, v0203; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1204; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc205; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]206; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]207; SI-NEXT: ; %bb.1: ; %cmp.true208; SI-NEXT: v_cvt_f32_f16_e32 v0, v0209; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0210; SI-NEXT: v_cvt_f16_f32_e32 v0, v0211; SI-NEXT: ; %bb.2: ; %end212; SI-NEXT: s_or_b64 exec, exec, s[4:5]213; SI-NEXT: s_setpc_b64 s[30:31]214;215; VI-LABEL: bitcast_f16_to_i16:216; VI: ; %bb.0:217; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)218; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1219; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc220; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]221; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]222; VI-NEXT: ; %bb.1: ; %cmp.true223; VI-NEXT: v_add_f16_e32 v0, 0x200, v0224; VI-NEXT: ; %bb.2: ; %end225; VI-NEXT: s_or_b64 exec, exec, s[4:5]226; VI-NEXT: s_setpc_b64 s[30:31]227;228; GFX9-LABEL: bitcast_f16_to_i16:229; GFX9: ; %bb.0:230; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)231; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1232; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc233; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]234; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]235; GFX9-NEXT: ; %bb.1: ; %cmp.true236; GFX9-NEXT: v_add_f16_e32 v0, 0x200, v0237; GFX9-NEXT: ; %bb.2: ; %end238; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]239; GFX9-NEXT: s_setpc_b64 s[30:31]240;241; GFX11-TRUE16-LABEL: bitcast_f16_to_i16:242; GFX11-TRUE16: ; %bb.0:243; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)244; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1245; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16246; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo247; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)248; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0249; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false250; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l251; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0252; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow253; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0254; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB2_4255; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true256; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, 0x200, v0.l257; GFX11-TRUE16-NEXT: .LBB2_4: ; %end258; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0259; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)260; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l261; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]262;263; GFX11-FAKE16-LABEL: bitcast_f16_to_i16:264; GFX11-FAKE16: ; %bb.0:265; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo267; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1268; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0269; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)270; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0271; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true272; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 0x200, v0273; GFX11-FAKE16-NEXT: ; %bb.2: ; %end274; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0275; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]276 %cmp = icmp eq i32 %b, 0277 br i1 %cmp, label %cmp.true, label %cmp.false278 279cmp.true:280 %a1 = fadd half %a, 0xH0200281 %a2 = bitcast half %a1 to i16282 br label %end283 284cmp.false:285 %a3 = bitcast half %a to i16286 br label %end287 288end:289 %phi = phi i16 [ %a2, %cmp.true ], [ %a3, %cmp.false ]290 ret i16 %phi291}292 293define inreg i16 @bitcast_f16_to_i16_scalar(half inreg %a, i32 inreg %b) {294; SI-LABEL: bitcast_f16_to_i16_scalar:295; SI: ; %bb.0:296; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)297; SI-NEXT: v_cvt_f16_f32_e32 v0, s16298; SI-NEXT: s_cmp_lg_u32 s17, 0299; SI-NEXT: s_cbranch_scc0 .LBB3_4300; SI-NEXT: ; %bb.1: ; %cmp.false301; SI-NEXT: s_cbranch_execnz .LBB3_3302; SI-NEXT: .LBB3_2: ; %cmp.true303; SI-NEXT: v_cvt_f32_f16_e32 v0, v0304; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0305; SI-NEXT: v_cvt_f16_f32_e32 v0, v0306; SI-NEXT: .LBB3_3: ; %end307; SI-NEXT: s_setpc_b64 s[30:31]308; SI-NEXT: .LBB3_4:309; SI-NEXT: s_branch .LBB3_2310;311; VI-LABEL: bitcast_f16_to_i16_scalar:312; VI: ; %bb.0:313; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)314; VI-NEXT: s_cmp_lg_u32 s17, 0315; VI-NEXT: s_cbranch_scc0 .LBB3_3316; VI-NEXT: ; %bb.1: ; %cmp.false317; VI-NEXT: s_cbranch_execnz .LBB3_4318; VI-NEXT: .LBB3_2: ; %cmp.true319; VI-NEXT: v_mov_b32_e32 v0, 0x200320; VI-NEXT: v_add_f16_e32 v0, s16, v0321; VI-NEXT: s_setpc_b64 s[30:31]322; VI-NEXT: .LBB3_3:323; VI-NEXT: s_branch .LBB3_2324; VI-NEXT: .LBB3_4:325; VI-NEXT: v_mov_b32_e32 v0, s16326; VI-NEXT: s_setpc_b64 s[30:31]327;328; GFX9-LABEL: bitcast_f16_to_i16_scalar:329; GFX9: ; %bb.0:330; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)331; GFX9-NEXT: s_cmp_lg_u32 s17, 0332; GFX9-NEXT: s_cbranch_scc0 .LBB3_3333; GFX9-NEXT: ; %bb.1: ; %cmp.false334; GFX9-NEXT: s_cbranch_execnz .LBB3_4335; GFX9-NEXT: .LBB3_2: ; %cmp.true336; GFX9-NEXT: v_mov_b32_e32 v0, 0x200337; GFX9-NEXT: v_add_f16_e32 v0, s16, v0338; GFX9-NEXT: s_setpc_b64 s[30:31]339; GFX9-NEXT: .LBB3_3:340; GFX9-NEXT: s_branch .LBB3_2341; GFX9-NEXT: .LBB3_4:342; GFX9-NEXT: v_mov_b32_e32 v0, s16343; GFX9-NEXT: s_setpc_b64 s[30:31]344;345; GFX11-TRUE16-LABEL: bitcast_f16_to_i16_scalar:346; GFX11-TRUE16: ; %bb.0:347; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)348; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s1, 0349; GFX11-TRUE16-NEXT: s_mov_b32 s1, 0350; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB3_3351; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow352; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s1353; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB3_4354; GFX11-TRUE16-NEXT: .LBB3_2: ; %cmp.true355; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, 0x200, s0356; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]357; GFX11-TRUE16-NEXT: .LBB3_3:358; GFX11-TRUE16-NEXT: s_branch .LBB3_2359; GFX11-TRUE16-NEXT: .LBB3_4:360; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s0361; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]362;363; GFX11-FAKE16-LABEL: bitcast_f16_to_i16_scalar:364; GFX11-FAKE16: ; %bb.0:365; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)366; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s1, 0367; GFX11-FAKE16-NEXT: s_mov_b32 s1, 0368; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB3_3369; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow370; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s1371; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB3_4372; GFX11-FAKE16-NEXT: .LBB3_2: ; %cmp.true373; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, 0x200, s0374; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]375; GFX11-FAKE16-NEXT: .LBB3_3:376; GFX11-FAKE16-NEXT: s_branch .LBB3_2377; GFX11-FAKE16-NEXT: .LBB3_4:378; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s0379; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]380 %cmp = icmp eq i32 %b, 0381 br i1 %cmp, label %cmp.true, label %cmp.false382 383cmp.true:384 %a1 = fadd half %a, 0xH0200385 %a2 = bitcast half %a1 to i16386 br label %end387 388cmp.false:389 %a3 = bitcast half %a to i16390 br label %end391 392end:393 %phi = phi i16 [ %a2, %cmp.true ], [ %a3, %cmp.false ]394 ret i16 %phi395}396 397define bfloat @bitcast_i16_to_bf16(i16 %a, i32 %b) {398; SI-LABEL: bitcast_i16_to_bf16:399; SI: ; %bb.0:400; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)401; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0402; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1403; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0404; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc405; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]406; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]407; SI-NEXT: ; %bb.1: ; %cmp.true408; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0409; SI-NEXT: ; %bb.2: ; %end410; SI-NEXT: s_or_b64 exec, exec, s[4:5]411; SI-NEXT: s_setpc_b64 s[30:31]412;413; VI-LABEL: bitcast_i16_to_bf16:414; VI: ; %bb.0:415; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)416; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1417; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc418; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]419; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]420; VI-NEXT: ; %bb.1: ; %cmp.true421; VI-NEXT: v_add_u16_e32 v0, 3, v0422; VI-NEXT: ; %bb.2: ; %end423; VI-NEXT: s_or_b64 exec, exec, s[4:5]424; VI-NEXT: s_setpc_b64 s[30:31]425;426; GFX9-LABEL: bitcast_i16_to_bf16:427; GFX9: ; %bb.0:428; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)429; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1430; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc431; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]432; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]433; GFX9-NEXT: ; %bb.1: ; %cmp.true434; GFX9-NEXT: v_add_u16_e32 v0, 3, v0435; GFX9-NEXT: ; %bb.2: ; %end436; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]437; GFX9-NEXT: s_setpc_b64 s[30:31]438;439; GFX11-TRUE16-LABEL: bitcast_i16_to_bf16:440; GFX11-TRUE16: ; %bb.0:441; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)442; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1443; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16444; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo445; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)446; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0447; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false448; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l449; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0450; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow451; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0452; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB4_4453; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true454; GFX11-TRUE16-NEXT: v_add_nc_u16 v1.l, v0.l, 3455; GFX11-TRUE16-NEXT: .LBB4_4: ; %end456; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0457; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)458; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l459; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]460;461; GFX11-FAKE16-LABEL: bitcast_i16_to_bf16:462; GFX11-FAKE16: ; %bb.0:463; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)464; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo465; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1466; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0467; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)468; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0469; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true470; GFX11-FAKE16-NEXT: v_add_nc_u16 v0, v0, 3471; GFX11-FAKE16-NEXT: ; %bb.2: ; %end472; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0473; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]474 %cmp = icmp eq i32 %b, 0475 br i1 %cmp, label %cmp.true, label %cmp.false476 477cmp.true:478 %a1 = add i16 %a, 3479 %a2 = bitcast i16 %a1 to bfloat480 br label %end481 482cmp.false:483 %a3 = bitcast i16 %a to bfloat484 br label %end485 486end:487 %phi = phi bfloat [ %a2, %cmp.true ], [ %a3, %cmp.false ]488 ret bfloat %phi489}490 491define inreg bfloat @bitcast_i16_to_bf16_scalar(i16 inreg %a, i32 inreg %b) {492; SI-LABEL: bitcast_i16_to_bf16_scalar:493; SI: ; %bb.0:494; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)495; SI-NEXT: s_and_b32 s6, s16, 0xffff496; SI-NEXT: s_cmp_lg_u32 s17, 0497; SI-NEXT: s_cbranch_scc0 .LBB5_4498; SI-NEXT: ; %bb.1: ; %cmp.false499; SI-NEXT: s_lshl_b32 s7, s6, 16500; SI-NEXT: s_cbranch_execnz .LBB5_3501; SI-NEXT: .LBB5_2: ; %cmp.true502; SI-NEXT: s_lshl_b32 s4, s6, 16503; SI-NEXT: s_add_i32 s7, s4, 0x30000504; SI-NEXT: .LBB5_3: ; %end505; SI-NEXT: v_mov_b32_e32 v0, s7506; SI-NEXT: s_setpc_b64 s[30:31]507; SI-NEXT: .LBB5_4:508; SI-NEXT: ; implicit-def: $sgpr7509; SI-NEXT: s_branch .LBB5_2510;511; VI-LABEL: bitcast_i16_to_bf16_scalar:512; VI: ; %bb.0:513; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)514; VI-NEXT: s_cmp_lg_u32 s17, 0515; VI-NEXT: s_cbranch_scc0 .LBB5_4516; VI-NEXT: ; %bb.1: ; %cmp.false517; VI-NEXT: s_cbranch_execnz .LBB5_3518; VI-NEXT: .LBB5_2: ; %cmp.true519; VI-NEXT: s_add_i32 s16, s16, 3520; VI-NEXT: .LBB5_3: ; %end521; VI-NEXT: v_mov_b32_e32 v0, s16522; VI-NEXT: s_setpc_b64 s[30:31]523; VI-NEXT: .LBB5_4:524; VI-NEXT: s_branch .LBB5_2525;526; GFX9-LABEL: bitcast_i16_to_bf16_scalar:527; GFX9: ; %bb.0:528; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)529; GFX9-NEXT: s_cmp_lg_u32 s17, 0530; GFX9-NEXT: s_cbranch_scc0 .LBB5_4531; GFX9-NEXT: ; %bb.1: ; %cmp.false532; GFX9-NEXT: s_cbranch_execnz .LBB5_3533; GFX9-NEXT: .LBB5_2: ; %cmp.true534; GFX9-NEXT: s_add_i32 s16, s16, 3535; GFX9-NEXT: .LBB5_3: ; %end536; GFX9-NEXT: v_mov_b32_e32 v0, s16537; GFX9-NEXT: s_setpc_b64 s[30:31]538; GFX9-NEXT: .LBB5_4:539; GFX9-NEXT: s_branch .LBB5_2540;541; GFX11-LABEL: bitcast_i16_to_bf16_scalar:542; GFX11: ; %bb.0:543; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)544; GFX11-NEXT: s_cmp_lg_u32 s1, 0545; GFX11-NEXT: s_mov_b32 s1, 0546; GFX11-NEXT: s_cbranch_scc0 .LBB5_3547; GFX11-NEXT: ; %bb.1: ; %Flow548; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s1549; GFX11-NEXT: s_cbranch_vccz .LBB5_4550; GFX11-NEXT: ; %bb.2: ; %end551; GFX11-NEXT: v_mov_b32_e32 v0, s0552; GFX11-NEXT: s_setpc_b64 s[30:31]553; GFX11-NEXT: .LBB5_3:554; GFX11-NEXT: .LBB5_4: ; %cmp.true555; GFX11-NEXT: s_add_i32 s0, s0, 3556; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)557; GFX11-NEXT: v_mov_b32_e32 v0, s0558; GFX11-NEXT: s_setpc_b64 s[30:31]559 %cmp = icmp eq i32 %b, 0560 br i1 %cmp, label %cmp.true, label %cmp.false561 562cmp.true:563 %a1 = add i16 %a, 3564 %a2 = bitcast i16 %a1 to bfloat565 br label %end566 567cmp.false:568 %a3 = bitcast i16 %a to bfloat569 br label %end570 571end:572 %phi = phi bfloat [ %a2, %cmp.true ], [ %a3, %cmp.false ]573 ret bfloat %phi574}575 576define i16 @bitcast_bf16_to_i16(bfloat %a, i32 %b) {577; SI-LABEL: bitcast_bf16_to_i16:578; SI: ; %bb.0:579; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)580; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1581; SI-NEXT: v_mul_f32_e32 v1, 1.0, v0582; SI-NEXT: ; implicit-def: $vgpr0583; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc584; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]585; SI-NEXT: s_cbranch_execnz .LBB6_3586; SI-NEXT: ; %bb.1: ; %Flow587; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]588; SI-NEXT: s_cbranch_execnz .LBB6_4589; SI-NEXT: .LBB6_2: ; %end590; SI-NEXT: s_or_b64 exec, exec, s[4:5]591; SI-NEXT: s_setpc_b64 s[30:31]592; SI-NEXT: .LBB6_3: ; %cmp.false593; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1594; SI-NEXT: ; implicit-def: $vgpr1595; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]596; SI-NEXT: s_cbranch_execz .LBB6_2597; SI-NEXT: .LBB6_4: ; %cmp.true598; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1599; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0600; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0601; SI-NEXT: s_or_b64 exec, exec, s[4:5]602; SI-NEXT: s_setpc_b64 s[30:31]603;604; VI-LABEL: bitcast_bf16_to_i16:605; VI: ; %bb.0:606; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)607; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1608; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc609; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]610; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]611; VI-NEXT: ; %bb.1: ; %cmp.true612; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0613; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0614; VI-NEXT: v_bfe_u32 v1, v0, 16, 1615; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0616; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1617; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0618; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0619; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc620; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0621; VI-NEXT: ; %bb.2: ; %end622; VI-NEXT: s_or_b64 exec, exec, s[4:5]623; VI-NEXT: s_setpc_b64 s[30:31]624;625; GFX9-LABEL: bitcast_bf16_to_i16:626; GFX9: ; %bb.0:627; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)628; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1629; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc630; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]631; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]632; GFX9-NEXT: ; %bb.1: ; %cmp.true633; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v0634; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v0635; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1636; GFX9-NEXT: s_movk_i32 s6, 0x7fff637; GFX9-NEXT: v_add3_u32 v1, v1, v0, s6638; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0639; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0640; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc641; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0642; GFX9-NEXT: ; %bb.2: ; %end643; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]644; GFX9-NEXT: s_setpc_b64 s[30:31]645;646; GFX11-TRUE16-LABEL: bitcast_bf16_to_i16:647; GFX11-TRUE16: ; %bb.0:648; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)649; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v0650; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo651; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi16652; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v1653; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0654; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false655; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)656; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l657; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2658; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow659; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0660; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB6_4661; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true662; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 0663; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l664; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)665; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0666; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 1667; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v0668; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0669; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)670; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff671; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo672; GFX11-TRUE16-NEXT: .LBB6_4: ; %end673; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0674; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)675; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h676; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]677;678; GFX11-FAKE16-LABEL: bitcast_bf16_to_i16:679; GFX11-FAKE16: ; %bb.0:680; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)681; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo682; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1683; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0684; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)685; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0686; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB6_2687; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true688; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0689; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)690; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v0691; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 1692; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v0693; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0694; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)695; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff696; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo697; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)698; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v0699; GFX11-FAKE16-NEXT: .LBB6_2: ; %end700; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0701; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]702 %cmp = icmp eq i32 %b, 0703 br i1 %cmp, label %cmp.true, label %cmp.false704 705cmp.true:706 %a1 = fadd bfloat %a, 0xR40C0707 %a2 = bitcast bfloat %a1 to i16708 br label %end709 710cmp.false:711 %a3 = bitcast bfloat %a to i16712 br label %end713 714end:715 %phi = phi i16 [ %a2, %cmp.true ], [ %a3, %cmp.false ]716 ret i16 %phi717}718 719define inreg i16 @bitcast_bf16_to_i16_scalar(bfloat inreg %a, i32 inreg %b) {720; SI-LABEL: bitcast_bf16_to_i16_scalar:721; SI: ; %bb.0:722; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)723; SI-NEXT: s_cmp_lg_u32 s17, 0724; SI-NEXT: v_mul_f32_e64 v1, 1.0, s16725; SI-NEXT: s_cbranch_scc0 .LBB7_4726; SI-NEXT: ; %bb.1: ; %cmp.false727; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v1728; SI-NEXT: s_cbranch_execnz .LBB7_3729; SI-NEXT: .LBB7_2: ; %cmp.true730; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v1731; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v0732; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0733; SI-NEXT: .LBB7_3: ; %end734; SI-NEXT: s_setpc_b64 s[30:31]735; SI-NEXT: .LBB7_4:736; SI-NEXT: ; implicit-def: $vgpr0737; SI-NEXT: s_branch .LBB7_2738;739; VI-LABEL: bitcast_bf16_to_i16_scalar:740; VI: ; %bb.0:741; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)742; VI-NEXT: s_cmp_lg_u32 s17, 0743; VI-NEXT: s_cbranch_scc0 .LBB7_3744; VI-NEXT: ; %bb.1: ; %cmp.false745; VI-NEXT: s_cbranch_execnz .LBB7_4746; VI-NEXT: .LBB7_2: ; %cmp.true747; VI-NEXT: s_lshl_b32 s4, s16, 16748; VI-NEXT: v_mov_b32_e32 v0, 0x40c00000749; VI-NEXT: v_add_f32_e32 v0, s4, v0750; VI-NEXT: v_bfe_u32 v1, v0, 16, 1751; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v0752; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v1753; VI-NEXT: v_or_b32_e32 v2, 0x400000, v0754; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v0755; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc756; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v0757; VI-NEXT: s_setpc_b64 s[30:31]758; VI-NEXT: .LBB7_3:759; VI-NEXT: s_branch .LBB7_2760; VI-NEXT: .LBB7_4:761; VI-NEXT: v_mov_b32_e32 v0, s16762; VI-NEXT: s_setpc_b64 s[30:31]763;764; GFX9-LABEL: bitcast_bf16_to_i16_scalar:765; GFX9: ; %bb.0:766; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)767; GFX9-NEXT: s_cmp_lg_u32 s17, 0768; GFX9-NEXT: s_cbranch_scc0 .LBB7_3769; GFX9-NEXT: ; %bb.1: ; %cmp.false770; GFX9-NEXT: s_cbranch_execnz .LBB7_4771; GFX9-NEXT: .LBB7_2: ; %cmp.true772; GFX9-NEXT: s_lshl_b32 s4, s16, 16773; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c00000774; GFX9-NEXT: v_add_f32_e32 v0, s4, v0775; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 1776; GFX9-NEXT: v_add_u32_e32 v1, v1, v0777; GFX9-NEXT: v_add_u32_e32 v1, 0x7fff, v1778; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v0779; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v0780; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc781; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v0782; GFX9-NEXT: s_setpc_b64 s[30:31]783; GFX9-NEXT: .LBB7_3:784; GFX9-NEXT: s_branch .LBB7_2785; GFX9-NEXT: .LBB7_4:786; GFX9-NEXT: v_mov_b32_e32 v0, s16787; GFX9-NEXT: s_setpc_b64 s[30:31]788;789; GFX11-LABEL: bitcast_bf16_to_i16_scalar:790; GFX11: ; %bb.0:791; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)792; GFX11-NEXT: s_cmp_lg_u32 s1, 0793; GFX11-NEXT: s_mov_b32 s1, 0794; GFX11-NEXT: s_cbranch_scc0 .LBB7_3795; GFX11-NEXT: ; %bb.1: ; %Flow796; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s1797; GFX11-NEXT: s_cbranch_vccnz .LBB7_4798; GFX11-NEXT: .LBB7_2: ; %cmp.true799; GFX11-NEXT: s_lshl_b32 s0, s0, 16800; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)801; GFX11-NEXT: v_add_f32_e64 v0, 0x40c00000, s0802; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 1803; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v0804; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v0805; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)806; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v0807; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v1808; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)809; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo810; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v0811; GFX11-NEXT: s_setpc_b64 s[30:31]812; GFX11-NEXT: .LBB7_3:813; GFX11-NEXT: s_branch .LBB7_2814; GFX11-NEXT: .LBB7_4:815; GFX11-NEXT: v_mov_b32_e32 v0, s0816; GFX11-NEXT: s_setpc_b64 s[30:31]817 %cmp = icmp eq i32 %b, 0818 br i1 %cmp, label %cmp.true, label %cmp.false819 820cmp.true:821 %a1 = fadd bfloat %a, 0xR40C0822 %a2 = bitcast bfloat %a1 to i16823 br label %end824 825cmp.false:826 %a3 = bitcast bfloat %a to i16827 br label %end828 829end:830 %phi = phi i16 [ %a2, %cmp.true ], [ %a3, %cmp.false ]831 ret i16 %phi832}833 834define bfloat @bitcast_f16_to_bf16(half %a, i32 %b) {835; SI-LABEL: bitcast_f16_to_bf16:836; SI: ; %bb.0:837; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)838; SI-NEXT: v_cvt_f16_f32_e32 v2, v0839; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1840; SI-NEXT: ; implicit-def: $vgpr0841; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc842; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]843; SI-NEXT: s_cbranch_execnz .LBB8_3844; SI-NEXT: ; %bb.1: ; %Flow845; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]846; SI-NEXT: s_cbranch_execnz .LBB8_4847; SI-NEXT: .LBB8_2: ; %end848; SI-NEXT: s_or_b64 exec, exec, s[4:5]849; SI-NEXT: s_setpc_b64 s[30:31]850; SI-NEXT: .LBB8_3: ; %cmp.false851; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v2852; SI-NEXT: ; implicit-def: $vgpr2853; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]854; SI-NEXT: s_cbranch_execz .LBB8_2855; SI-NEXT: .LBB8_4: ; %cmp.true856; SI-NEXT: v_cvt_f32_f16_e32 v0, v2857; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0858; SI-NEXT: v_cvt_f16_f32_e32 v0, v0859; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0860; SI-NEXT: s_or_b64 exec, exec, s[4:5]861; SI-NEXT: s_setpc_b64 s[30:31]862;863; VI-LABEL: bitcast_f16_to_bf16:864; VI: ; %bb.0:865; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)866; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1867; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc868; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]869; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]870; VI-NEXT: ; %bb.1: ; %cmp.true871; VI-NEXT: v_add_f16_e32 v0, 0x200, v0872; VI-NEXT: ; %bb.2: ; %end873; VI-NEXT: s_or_b64 exec, exec, s[4:5]874; VI-NEXT: s_setpc_b64 s[30:31]875;876; GFX9-LABEL: bitcast_f16_to_bf16:877; GFX9: ; %bb.0:878; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)879; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v1880; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc881; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]882; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]883; GFX9-NEXT: ; %bb.1: ; %cmp.true884; GFX9-NEXT: v_add_f16_e32 v0, 0x200, v0885; GFX9-NEXT: ; %bb.2: ; %end886; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]887; GFX9-NEXT: s_setpc_b64 s[30:31]888;889; GFX11-TRUE16-LABEL: bitcast_f16_to_bf16:890; GFX11-TRUE16: ; %bb.0:891; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)892; GFX11-TRUE16-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v1893; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr1_lo16894; GFX11-TRUE16-NEXT: s_and_saveexec_b32 s0, vcc_lo895; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)896; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s0897; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false898; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, v0.l899; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0900; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow901; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s0902; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB8_4903; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true904; GFX11-TRUE16-NEXT: v_add_f16_e32 v1.l, 0x200, v0.l905; GFX11-TRUE16-NEXT: .LBB8_4: ; %end906; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s0907; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)908; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v1.l909; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]910;911; GFX11-FAKE16-LABEL: bitcast_f16_to_bf16:912; GFX11-FAKE16: ; %bb.0:913; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)914; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo915; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v1916; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s0917; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)918; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s0919; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true920; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 0x200, v0921; GFX11-FAKE16-NEXT: ; %bb.2: ; %end922; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s0923; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]924 %cmp = icmp eq i32 %b, 0925 br i1 %cmp, label %cmp.true, label %cmp.false926 927cmp.true:928 %a1 = fadd half %a, 0xH0200929 %a2 = bitcast half %a1 to bfloat930 br label %end931 932cmp.false:933 %a3 = bitcast half %a to bfloat934 br label %end935 936end:937 %phi = phi bfloat [ %a2, %cmp.true ], [ %a3, %cmp.false ]938 ret bfloat %phi939}940 941define inreg bfloat @bitcast_f16_to_bf16_scalar(half inreg %a, i32 inreg %b) {942; SI-LABEL: bitcast_f16_to_bf16_scalar:943; SI: ; %bb.0:944; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)945; SI-NEXT: v_cvt_f16_f32_e32 v1, s16946; SI-NEXT: s_cmp_lg_u32 s17, 0947; SI-NEXT: s_cbranch_scc0 .LBB9_4948; SI-NEXT: ; %bb.1: ; %cmp.false949; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v1950; SI-NEXT: s_cbranch_execnz .LBB9_3951; SI-NEXT: .LBB9_2: ; %cmp.true952; SI-NEXT: v_cvt_f32_f16_e32 v0, v1953; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v0954; SI-NEXT: v_cvt_f16_f32_e32 v0, v0955; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0956; SI-NEXT: .LBB9_3: ; %end957; SI-NEXT: s_setpc_b64 s[30:31]958; SI-NEXT: .LBB9_4:959; SI-NEXT: ; implicit-def: $vgpr0960; SI-NEXT: s_branch .LBB9_2961;962; VI-LABEL: bitcast_f16_to_bf16_scalar:963; VI: ; %bb.0:964; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; VI-NEXT: s_cmp_lg_u32 s17, 0966; VI-NEXT: s_cbranch_scc0 .LBB9_3967; VI-NEXT: ; %bb.1: ; %cmp.false968; VI-NEXT: s_cbranch_execnz .LBB9_4969; VI-NEXT: .LBB9_2: ; %cmp.true970; VI-NEXT: v_mov_b32_e32 v0, 0x200971; VI-NEXT: v_add_f16_e32 v0, s16, v0972; VI-NEXT: s_setpc_b64 s[30:31]973; VI-NEXT: .LBB9_3:974; VI-NEXT: s_branch .LBB9_2975; VI-NEXT: .LBB9_4:976; VI-NEXT: v_mov_b32_e32 v0, s16977; VI-NEXT: s_setpc_b64 s[30:31]978;979; GFX9-LABEL: bitcast_f16_to_bf16_scalar:980; GFX9: ; %bb.0:981; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)982; GFX9-NEXT: s_cmp_lg_u32 s17, 0983; GFX9-NEXT: s_cbranch_scc0 .LBB9_3984; GFX9-NEXT: ; %bb.1: ; %cmp.false985; GFX9-NEXT: s_cbranch_execnz .LBB9_4986; GFX9-NEXT: .LBB9_2: ; %cmp.true987; GFX9-NEXT: v_mov_b32_e32 v0, 0x200988; GFX9-NEXT: v_add_f16_e32 v0, s16, v0989; GFX9-NEXT: s_setpc_b64 s[30:31]990; GFX9-NEXT: .LBB9_3:991; GFX9-NEXT: s_branch .LBB9_2992; GFX9-NEXT: .LBB9_4:993; GFX9-NEXT: v_mov_b32_e32 v0, s16994; GFX9-NEXT: s_setpc_b64 s[30:31]995;996; GFX11-TRUE16-LABEL: bitcast_f16_to_bf16_scalar:997; GFX11-TRUE16: ; %bb.0:998; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)999; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s1, 01000; GFX11-TRUE16-NEXT: s_mov_b32 s1, 01001; GFX11-TRUE16-NEXT: s_cbranch_scc0 .LBB9_31002; GFX11-TRUE16-NEXT: ; %bb.1: ; %Flow1003; GFX11-TRUE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s11004; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_41005; GFX11-TRUE16-NEXT: .LBB9_2: ; %cmp.true1006; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, 0x200, s01007; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1008; GFX11-TRUE16-NEXT: .LBB9_3:1009; GFX11-TRUE16-NEXT: s_branch .LBB9_21010; GFX11-TRUE16-NEXT: .LBB9_4:1011; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, s01012; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1013;1014; GFX11-FAKE16-LABEL: bitcast_f16_to_bf16_scalar:1015; GFX11-FAKE16: ; %bb.0:1016; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1017; GFX11-FAKE16-NEXT: s_cmp_lg_u32 s1, 01018; GFX11-FAKE16-NEXT: s_mov_b32 s1, 01019; GFX11-FAKE16-NEXT: s_cbranch_scc0 .LBB9_31020; GFX11-FAKE16-NEXT: ; %bb.1: ; %Flow1021; GFX11-FAKE16-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s11022; GFX11-FAKE16-NEXT: s_cbranch_vccnz .LBB9_41023; GFX11-FAKE16-NEXT: .LBB9_2: ; %cmp.true1024; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, 0x200, s01025; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1026; GFX11-FAKE16-NEXT: .LBB9_3:1027; GFX11-FAKE16-NEXT: s_branch .LBB9_21028; GFX11-FAKE16-NEXT: .LBB9_4:1029; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, s01030; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1031 %cmp = icmp eq i32 %b, 01032 br i1 %cmp, label %cmp.true, label %cmp.false1033 1034cmp.true:1035 %a1 = fadd half %a, 0xH02001036 %a2 = bitcast half %a1 to bfloat1037 br label %end1038 1039cmp.false:1040 %a3 = bitcast half %a to bfloat1041 br label %end1042 1043end:1044 %phi = phi bfloat [ %a2, %cmp.true ], [ %a3, %cmp.false ]1045 ret bfloat %phi1046}1047 1048define half @bitcast_bf16_to_f16(bfloat %a, i32 %b) {1049; SI-LABEL: bitcast_bf16_to_f16:1050; SI: ; %bb.0:1051; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1052; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11053; SI-NEXT: v_mul_f32_e32 v1, 1.0, v01054; SI-NEXT: ; implicit-def: $vgpr01055; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1056; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1057; SI-NEXT: s_cbranch_execnz .LBB10_31058; SI-NEXT: ; %bb.1: ; %Flow1059; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1060; SI-NEXT: s_cbranch_execnz .LBB10_41061; SI-NEXT: .LBB10_2: ; %end1062; SI-NEXT: s_or_b64 exec, exec, s[4:5]1063; SI-NEXT: s_setpc_b64 s[30:31]1064; SI-NEXT: .LBB10_3: ; %cmp.false1065; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v11066; SI-NEXT: v_cvt_f32_f16_e32 v0, v01067; SI-NEXT: ; implicit-def: $vgpr11068; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1069; SI-NEXT: s_cbranch_execz .LBB10_21070; SI-NEXT: .LBB10_4: ; %cmp.true1071; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11072; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v01073; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v01074; SI-NEXT: v_cvt_f32_f16_e32 v0, v01075; SI-NEXT: s_or_b64 exec, exec, s[4:5]1076; SI-NEXT: s_setpc_b64 s[30:31]1077;1078; VI-LABEL: bitcast_bf16_to_f16:1079; VI: ; %bb.0:1080; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1081; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11082; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1083; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1084; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1085; VI-NEXT: ; %bb.1: ; %cmp.true1086; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v01087; VI-NEXT: v_add_f32_e32 v0, 0x40c00000, v01088; VI-NEXT: v_bfe_u32 v1, v0, 16, 11089; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v01090; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v11091; VI-NEXT: v_or_b32_e32 v2, 0x400000, v01092; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v01093; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1094; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v01095; VI-NEXT: ; %bb.2: ; %end1096; VI-NEXT: s_or_b64 exec, exec, s[4:5]1097; VI-NEXT: s_setpc_b64 s[30:31]1098;1099; GFX9-LABEL: bitcast_bf16_to_f16:1100; GFX9: ; %bb.0:1101; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1102; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v11103; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1104; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1105; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1106; GFX9-NEXT: ; %bb.1: ; %cmp.true1107; GFX9-NEXT: v_lshlrev_b32_e32 v0, 16, v01108; GFX9-NEXT: v_add_f32_e32 v0, 0x40c00000, v01109; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 11110; GFX9-NEXT: s_movk_i32 s6, 0x7fff1111; GFX9-NEXT: v_add3_u32 v1, v1, v0, s61112; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v01113; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v01114; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1115; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v01116; GFX9-NEXT: ; %bb.2: ; %end1117; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1118; GFX9-NEXT: s_setpc_b64 s[30:31]1119;1120; GFX11-TRUE16-LABEL: bitcast_bf16_to_f16:1121; GFX11-TRUE16: ; %bb.0:1122; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1123; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v01124; GFX11-TRUE16-NEXT: s_mov_b32 s0, exec_lo1125; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr0_hi161126; GFX11-TRUE16-NEXT: v_cmpx_ne_u32_e32 0, v11127; GFX11-TRUE16-NEXT: s_xor_b32 s0, exec_lo, s01128; GFX11-TRUE16-NEXT: ; %bb.1: ; %cmp.false1129; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)1130; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l1131; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr21132; GFX11-TRUE16-NEXT: ; %bb.2: ; %Flow1133; GFX11-TRUE16-NEXT: s_and_not1_saveexec_b32 s0, s01134; GFX11-TRUE16-NEXT: s_cbranch_execz .LBB10_41135; GFX11-TRUE16-NEXT: ; %bb.3: ; %cmp.true1136; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, 01137; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.l1138; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1139; GFX11-TRUE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v01140; GFX11-TRUE16-NEXT: v_bfe_u32 v1, v0, 16, 11141; GFX11-TRUE16-NEXT: v_or_b32_e32 v2, 0x400000, v01142; GFX11-TRUE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v01143; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)1144; GFX11-TRUE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff1145; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo1146; GFX11-TRUE16-NEXT: .LBB10_4: ; %end1147; GFX11-TRUE16-NEXT: s_or_b32 exec_lo, exec_lo, s01148; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1149; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.l, v0.h1150; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]1151;1152; GFX11-FAKE16-LABEL: bitcast_bf16_to_f16:1153; GFX11-FAKE16: ; %bb.0:1154; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1155; GFX11-FAKE16-NEXT: s_mov_b32 s0, exec_lo1156; GFX11-FAKE16-NEXT: v_cmpx_ne_u32_e32 0, v11157; GFX11-FAKE16-NEXT: s_xor_b32 s0, exec_lo, s01158; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1159; GFX11-FAKE16-NEXT: s_and_not1_saveexec_b32 s0, s01160; GFX11-FAKE16-NEXT: s_cbranch_execz .LBB10_21161; GFX11-FAKE16-NEXT: ; %bb.1: ; %cmp.true1162; GFX11-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v01163; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1164; GFX11-FAKE16-NEXT: v_add_f32_e32 v0, 0x40c00000, v01165; GFX11-FAKE16-NEXT: v_bfe_u32 v1, v0, 16, 11166; GFX11-FAKE16-NEXT: v_or_b32_e32 v2, 0x400000, v01167; GFX11-FAKE16-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v01168; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)1169; GFX11-FAKE16-NEXT: v_add3_u32 v1, v1, v0, 0x7fff1170; GFX11-FAKE16-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo1171; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1172; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v0, 16, v01173; GFX11-FAKE16-NEXT: .LBB10_2: ; %end1174; GFX11-FAKE16-NEXT: s_or_b32 exec_lo, exec_lo, s01175; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]1176 %cmp = icmp eq i32 %b, 01177 br i1 %cmp, label %cmp.true, label %cmp.false1178 1179cmp.true:1180 %a1 = fadd bfloat %a, 0xR40C01181 %a2 = bitcast bfloat %a1 to half1182 br label %end1183 1184cmp.false:1185 %a3 = bitcast bfloat %a to half1186 br label %end1187 1188end:1189 %phi = phi half [ %a2, %cmp.true ], [ %a3, %cmp.false ]1190 ret half %phi1191}1192 1193define inreg half @bitcast_bf16_to_f16_scalar(bfloat inreg %a, i32 inreg %b) {1194; SI-LABEL: bitcast_bf16_to_f16_scalar:1195; SI: ; %bb.0:1196; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1197; SI-NEXT: s_cmp_lg_u32 s17, 01198; SI-NEXT: v_mul_f32_e64 v1, 1.0, s161199; SI-NEXT: s_cbranch_scc0 .LBB11_41200; SI-NEXT: ; %bb.1: ; %cmp.false1201; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v11202; SI-NEXT: v_cvt_f32_f16_e32 v0, v01203; SI-NEXT: s_cbranch_execnz .LBB11_31204; SI-NEXT: .LBB11_2: ; %cmp.true1205; SI-NEXT: v_and_b32_e32 v0, 0xffff0000, v11206; SI-NEXT: v_add_f32_e32 v0, 0x40c00000, v01207; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v01208; SI-NEXT: v_cvt_f32_f16_e32 v0, v01209; SI-NEXT: .LBB11_3: ; %end1210; SI-NEXT: s_setpc_b64 s[30:31]1211; SI-NEXT: .LBB11_4:1212; SI-NEXT: ; implicit-def: $vgpr01213; SI-NEXT: s_branch .LBB11_21214;1215; VI-LABEL: bitcast_bf16_to_f16_scalar:1216; VI: ; %bb.0:1217; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1218; VI-NEXT: s_cmp_lg_u32 s17, 01219; VI-NEXT: s_cbranch_scc0 .LBB11_31220; VI-NEXT: ; %bb.1: ; %cmp.false1221; VI-NEXT: s_cbranch_execnz .LBB11_41222; VI-NEXT: .LBB11_2: ; %cmp.true1223; VI-NEXT: s_lshl_b32 s4, s16, 161224; VI-NEXT: v_mov_b32_e32 v0, 0x40c000001225; VI-NEXT: v_add_f32_e32 v0, s4, v01226; VI-NEXT: v_bfe_u32 v1, v0, 16, 11227; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v01228; VI-NEXT: v_add_u32_e32 v1, vcc, 0x7fff, v11229; VI-NEXT: v_or_b32_e32 v2, 0x400000, v01230; VI-NEXT: v_cmp_u_f32_e32 vcc, v0, v01231; VI-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1232; VI-NEXT: v_lshrrev_b32_e32 v0, 16, v01233; VI-NEXT: s_setpc_b64 s[30:31]1234; VI-NEXT: .LBB11_3:1235; VI-NEXT: s_branch .LBB11_21236; VI-NEXT: .LBB11_4:1237; VI-NEXT: v_mov_b32_e32 v0, s161238; VI-NEXT: s_setpc_b64 s[30:31]1239;1240; GFX9-LABEL: bitcast_bf16_to_f16_scalar:1241; GFX9: ; %bb.0:1242; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1243; GFX9-NEXT: s_cmp_lg_u32 s17, 01244; GFX9-NEXT: s_cbranch_scc0 .LBB11_31245; GFX9-NEXT: ; %bb.1: ; %cmp.false1246; GFX9-NEXT: s_cbranch_execnz .LBB11_41247; GFX9-NEXT: .LBB11_2: ; %cmp.true1248; GFX9-NEXT: s_lshl_b32 s4, s16, 161249; GFX9-NEXT: v_mov_b32_e32 v0, 0x40c000001250; GFX9-NEXT: v_add_f32_e32 v0, s4, v01251; GFX9-NEXT: v_bfe_u32 v1, v0, 16, 11252; GFX9-NEXT: v_add_u32_e32 v1, v1, v01253; GFX9-NEXT: v_add_u32_e32 v1, 0x7fff, v11254; GFX9-NEXT: v_or_b32_e32 v2, 0x400000, v01255; GFX9-NEXT: v_cmp_u_f32_e32 vcc, v0, v01256; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc1257; GFX9-NEXT: v_lshrrev_b32_e32 v0, 16, v01258; GFX9-NEXT: s_setpc_b64 s[30:31]1259; GFX9-NEXT: .LBB11_3:1260; GFX9-NEXT: s_branch .LBB11_21261; GFX9-NEXT: .LBB11_4:1262; GFX9-NEXT: v_mov_b32_e32 v0, s161263; GFX9-NEXT: s_setpc_b64 s[30:31]1264;1265; GFX11-LABEL: bitcast_bf16_to_f16_scalar:1266; GFX11: ; %bb.0:1267; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1268; GFX11-NEXT: s_cmp_lg_u32 s1, 01269; GFX11-NEXT: s_mov_b32 s1, 01270; GFX11-NEXT: s_cbranch_scc0 .LBB11_31271; GFX11-NEXT: ; %bb.1: ; %Flow1272; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s11273; GFX11-NEXT: s_cbranch_vccnz .LBB11_41274; GFX11-NEXT: .LBB11_2: ; %cmp.true1275; GFX11-NEXT: s_lshl_b32 s0, s0, 161276; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)1277; GFX11-NEXT: v_add_f32_e64 v0, 0x40c00000, s01278; GFX11-NEXT: v_bfe_u32 v1, v0, 16, 11279; GFX11-NEXT: v_or_b32_e32 v2, 0x400000, v01280; GFX11-NEXT: v_cmp_u_f32_e32 vcc_lo, v0, v01281; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)1282; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v01283; GFX11-NEXT: v_add_nc_u32_e32 v1, 0x7fff, v11284; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1285; GFX11-NEXT: v_cndmask_b32_e32 v0, v1, v2, vcc_lo1286; GFX11-NEXT: v_lshrrev_b32_e32 v0, 16, v01287; GFX11-NEXT: s_setpc_b64 s[30:31]1288; GFX11-NEXT: .LBB11_3:1289; GFX11-NEXT: s_branch .LBB11_21290; GFX11-NEXT: .LBB11_4:1291; GFX11-NEXT: v_mov_b32_e32 v0, s01292; GFX11-NEXT: s_setpc_b64 s[30:31]1293 %cmp = icmp eq i32 %b, 01294 br i1 %cmp, label %cmp.true, label %cmp.false1295 1296cmp.true:1297 %a1 = fadd bfloat %a, 0xR40C01298 %a2 = bitcast bfloat %a1 to half1299 br label %end1300 1301cmp.false:1302 %a3 = bitcast bfloat %a to half1303 br label %end1304 1305end:1306 %phi = phi half [ %a2, %cmp.true ], [ %a3, %cmp.false ]1307 ret half %phi1308}1309