8503 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <6 x float> @bitcast_v6i32_to_v6f32(<6 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v6i32_to_v6f32:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v614; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT: ; %bb.1: ; %cmp.true18; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v519; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v420; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v321; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v222; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v123; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v024; SI-NEXT: ; %bb.2: ; %end25; SI-NEXT: s_or_b64 exec, exec, s[4:5]26; SI-NEXT: s_setpc_b64 s[30:31]27;28; VI-LABEL: bitcast_v6i32_to_v6f32:29; VI: ; %bb.0:30; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)31; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v632; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc33; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]34; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]35; VI-NEXT: ; %bb.1: ; %cmp.true36; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v537; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v438; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v339; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v240; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v141; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v042; VI-NEXT: ; %bb.2: ; %end43; VI-NEXT: s_or_b64 exec, exec, s[4:5]44; VI-NEXT: s_setpc_b64 s[30:31]45;46; GFX9-LABEL: bitcast_v6i32_to_v6f32:47; GFX9: ; %bb.0:48; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)49; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v650; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc51; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]52; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]53; GFX9-NEXT: ; %bb.1: ; %cmp.true54; GFX9-NEXT: v_add_u32_e32 v5, 3, v555; GFX9-NEXT: v_add_u32_e32 v4, 3, v456; GFX9-NEXT: v_add_u32_e32 v3, 3, v357; GFX9-NEXT: v_add_u32_e32 v2, 3, v258; GFX9-NEXT: v_add_u32_e32 v1, 3, v159; GFX9-NEXT: v_add_u32_e32 v0, 3, v060; GFX9-NEXT: ; %bb.2: ; %end61; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]62; GFX9-NEXT: s_setpc_b64 s[30:31]63;64; GFX11-LABEL: bitcast_v6i32_to_v6f32:65; GFX11: ; %bb.0:66; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; GFX11-NEXT: s_mov_b32 s0, exec_lo68; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v669; GFX11-NEXT: s_xor_b32 s0, exec_lo, s070; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)71; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s072; GFX11-NEXT: ; %bb.1: ; %cmp.true73; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v574; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v475; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v376; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v277; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v178; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v079; GFX11-NEXT: ; %bb.2: ; %end80; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s081; GFX11-NEXT: s_setpc_b64 s[30:31]82 %cmp = icmp eq i32 %b, 083 br i1 %cmp, label %cmp.true, label %cmp.false84 85cmp.true:86 %a1 = add <6 x i32> %a, splat (i32 3)87 %a2 = bitcast <6 x i32> %a1 to <6 x float>88 br label %end89 90cmp.false:91 %a3 = bitcast <6 x i32> %a to <6 x float>92 br label %end93 94end:95 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]96 ret <6 x float> %phi97}98 99define inreg <6 x float> @bitcast_v6i32_to_v6f32_scalar(<6 x i32> inreg %a, i32 inreg %b) {100; SI-LABEL: bitcast_v6i32_to_v6f32_scalar:101; SI: ; %bb.0:102; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)103; SI-NEXT: s_cmp_lg_u32 s22, 0104; SI-NEXT: s_cbranch_scc0 .LBB1_4105; SI-NEXT: ; %bb.1: ; %cmp.false106; SI-NEXT: s_cbranch_execnz .LBB1_3107; SI-NEXT: .LBB1_2: ; %cmp.true108; SI-NEXT: s_add_i32 s21, s21, 3109; SI-NEXT: s_add_i32 s20, s20, 3110; SI-NEXT: s_add_i32 s19, s19, 3111; SI-NEXT: s_add_i32 s18, s18, 3112; SI-NEXT: s_add_i32 s17, s17, 3113; SI-NEXT: s_add_i32 s16, s16, 3114; SI-NEXT: .LBB1_3: ; %end115; SI-NEXT: v_mov_b32_e32 v0, s16116; SI-NEXT: v_mov_b32_e32 v1, s17117; SI-NEXT: v_mov_b32_e32 v2, s18118; SI-NEXT: v_mov_b32_e32 v3, s19119; SI-NEXT: v_mov_b32_e32 v4, s20120; SI-NEXT: v_mov_b32_e32 v5, s21121; SI-NEXT: s_setpc_b64 s[30:31]122; SI-NEXT: .LBB1_4:123; SI-NEXT: s_branch .LBB1_2124;125; VI-LABEL: bitcast_v6i32_to_v6f32_scalar:126; VI: ; %bb.0:127; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; VI-NEXT: s_cmp_lg_u32 s22, 0129; VI-NEXT: s_cbranch_scc0 .LBB1_4130; VI-NEXT: ; %bb.1: ; %cmp.false131; VI-NEXT: s_cbranch_execnz .LBB1_3132; VI-NEXT: .LBB1_2: ; %cmp.true133; VI-NEXT: s_add_i32 s21, s21, 3134; VI-NEXT: s_add_i32 s20, s20, 3135; VI-NEXT: s_add_i32 s19, s19, 3136; VI-NEXT: s_add_i32 s18, s18, 3137; VI-NEXT: s_add_i32 s17, s17, 3138; VI-NEXT: s_add_i32 s16, s16, 3139; VI-NEXT: .LBB1_3: ; %end140; VI-NEXT: v_mov_b32_e32 v0, s16141; VI-NEXT: v_mov_b32_e32 v1, s17142; VI-NEXT: v_mov_b32_e32 v2, s18143; VI-NEXT: v_mov_b32_e32 v3, s19144; VI-NEXT: v_mov_b32_e32 v4, s20145; VI-NEXT: v_mov_b32_e32 v5, s21146; VI-NEXT: s_setpc_b64 s[30:31]147; VI-NEXT: .LBB1_4:148; VI-NEXT: s_branch .LBB1_2149;150; GFX9-LABEL: bitcast_v6i32_to_v6f32_scalar:151; GFX9: ; %bb.0:152; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)153; GFX9-NEXT: s_cmp_lg_u32 s22, 0154; GFX9-NEXT: s_cbranch_scc0 .LBB1_4155; GFX9-NEXT: ; %bb.1: ; %cmp.false156; GFX9-NEXT: s_cbranch_execnz .LBB1_3157; GFX9-NEXT: .LBB1_2: ; %cmp.true158; GFX9-NEXT: s_add_i32 s21, s21, 3159; GFX9-NEXT: s_add_i32 s20, s20, 3160; GFX9-NEXT: s_add_i32 s19, s19, 3161; GFX9-NEXT: s_add_i32 s18, s18, 3162; GFX9-NEXT: s_add_i32 s17, s17, 3163; GFX9-NEXT: s_add_i32 s16, s16, 3164; GFX9-NEXT: .LBB1_3: ; %end165; GFX9-NEXT: v_mov_b32_e32 v0, s16166; GFX9-NEXT: v_mov_b32_e32 v1, s17167; GFX9-NEXT: v_mov_b32_e32 v2, s18168; GFX9-NEXT: v_mov_b32_e32 v3, s19169; GFX9-NEXT: v_mov_b32_e32 v4, s20170; GFX9-NEXT: v_mov_b32_e32 v5, s21171; GFX9-NEXT: s_setpc_b64 s[30:31]172; GFX9-NEXT: .LBB1_4:173; GFX9-NEXT: s_branch .LBB1_2174;175; GFX11-LABEL: bitcast_v6i32_to_v6f32_scalar:176; GFX11: ; %bb.0:177; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)178; GFX11-NEXT: s_cmp_lg_u32 s18, 0179; GFX11-NEXT: s_mov_b32 s4, 0180; GFX11-NEXT: s_cbranch_scc0 .LBB1_4181; GFX11-NEXT: ; %bb.1: ; %Flow182; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4183; GFX11-NEXT: s_cbranch_vccnz .LBB1_3184; GFX11-NEXT: .LBB1_2: ; %cmp.true185; GFX11-NEXT: s_add_i32 s17, s17, 3186; GFX11-NEXT: s_add_i32 s16, s16, 3187; GFX11-NEXT: s_add_i32 s3, s3, 3188; GFX11-NEXT: s_add_i32 s2, s2, 3189; GFX11-NEXT: s_add_i32 s1, s1, 3190; GFX11-NEXT: s_add_i32 s0, s0, 3191; GFX11-NEXT: .LBB1_3: ; %end192; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)193; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1194; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3195; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17196; GFX11-NEXT: s_setpc_b64 s[30:31]197; GFX11-NEXT: .LBB1_4:198; GFX11-NEXT: s_branch .LBB1_2199 %cmp = icmp eq i32 %b, 0200 br i1 %cmp, label %cmp.true, label %cmp.false201 202cmp.true:203 %a1 = add <6 x i32> %a, splat (i32 3)204 %a2 = bitcast <6 x i32> %a1 to <6 x float>205 br label %end206 207cmp.false:208 %a3 = bitcast <6 x i32> %a to <6 x float>209 br label %end210 211end:212 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]213 ret <6 x float> %phi214}215 216define <6 x i32> @bitcast_v6f32_to_v6i32(<6 x float> %a, i32 %b) {217; SI-LABEL: bitcast_v6f32_to_v6i32:218; SI: ; %bb.0:219; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)220; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6221; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc222; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]223; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]224; SI-NEXT: ; %bb.1: ; %cmp.true225; SI-NEXT: v_add_f32_e32 v5, 1.0, v5226; SI-NEXT: v_add_f32_e32 v4, 1.0, v4227; SI-NEXT: v_add_f32_e32 v3, 1.0, v3228; SI-NEXT: v_add_f32_e32 v2, 1.0, v2229; SI-NEXT: v_add_f32_e32 v1, 1.0, v1230; SI-NEXT: v_add_f32_e32 v0, 1.0, v0231; SI-NEXT: ; %bb.2: ; %end232; SI-NEXT: s_or_b64 exec, exec, s[4:5]233; SI-NEXT: s_setpc_b64 s[30:31]234;235; VI-LABEL: bitcast_v6f32_to_v6i32:236; VI: ; %bb.0:237; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)238; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6239; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc240; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]241; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]242; VI-NEXT: ; %bb.1: ; %cmp.true243; VI-NEXT: v_add_f32_e32 v5, 1.0, v5244; VI-NEXT: v_add_f32_e32 v4, 1.0, v4245; VI-NEXT: v_add_f32_e32 v3, 1.0, v3246; VI-NEXT: v_add_f32_e32 v2, 1.0, v2247; VI-NEXT: v_add_f32_e32 v1, 1.0, v1248; VI-NEXT: v_add_f32_e32 v0, 1.0, v0249; VI-NEXT: ; %bb.2: ; %end250; VI-NEXT: s_or_b64 exec, exec, s[4:5]251; VI-NEXT: s_setpc_b64 s[30:31]252;253; GFX9-LABEL: bitcast_v6f32_to_v6i32:254; GFX9: ; %bb.0:255; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)256; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6257; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc258; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]259; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]260; GFX9-NEXT: ; %bb.1: ; %cmp.true261; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5262; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4263; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3264; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2265; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1266; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0267; GFX9-NEXT: ; %bb.2: ; %end268; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]269; GFX9-NEXT: s_setpc_b64 s[30:31]270;271; GFX11-LABEL: bitcast_v6f32_to_v6i32:272; GFX11: ; %bb.0:273; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)274; GFX11-NEXT: s_mov_b32 s0, exec_lo275; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6276; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0277; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)278; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0279; GFX11-NEXT: ; %bb.1: ; %cmp.true280; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v4281; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v2282; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v0283; GFX11-NEXT: ; %bb.2: ; %end284; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0285; GFX11-NEXT: s_setpc_b64 s[30:31]286 %cmp = icmp eq i32 %b, 0287 br i1 %cmp, label %cmp.true, label %cmp.false288 289cmp.true:290 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)291 %a2 = bitcast <6 x float> %a1 to <6 x i32>292 br label %end293 294cmp.false:295 %a3 = bitcast <6 x float> %a to <6 x i32>296 br label %end297 298end:299 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]300 ret <6 x i32> %phi301}302 303define inreg <6 x i32> @bitcast_v6f32_to_v6i32_scalar(<6 x float> inreg %a, i32 inreg %b) {304; SI-LABEL: bitcast_v6f32_to_v6i32_scalar:305; SI: ; %bb.0:306; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)307; SI-NEXT: s_cmp_lg_u32 s22, 0308; SI-NEXT: s_cbranch_scc0 .LBB3_3309; SI-NEXT: ; %bb.1: ; %cmp.false310; SI-NEXT: s_cbranch_execnz .LBB3_4311; SI-NEXT: .LBB3_2: ; %cmp.true312; SI-NEXT: v_add_f32_e64 v5, s21, 1.0313; SI-NEXT: v_add_f32_e64 v4, s20, 1.0314; SI-NEXT: v_add_f32_e64 v3, s19, 1.0315; SI-NEXT: v_add_f32_e64 v2, s18, 1.0316; SI-NEXT: v_add_f32_e64 v1, s17, 1.0317; SI-NEXT: v_add_f32_e64 v0, s16, 1.0318; SI-NEXT: s_setpc_b64 s[30:31]319; SI-NEXT: .LBB3_3:320; SI-NEXT: s_branch .LBB3_2321; SI-NEXT: .LBB3_4:322; SI-NEXT: v_mov_b32_e32 v0, s16323; SI-NEXT: v_mov_b32_e32 v1, s17324; SI-NEXT: v_mov_b32_e32 v2, s18325; SI-NEXT: v_mov_b32_e32 v3, s19326; SI-NEXT: v_mov_b32_e32 v4, s20327; SI-NEXT: v_mov_b32_e32 v5, s21328; SI-NEXT: s_setpc_b64 s[30:31]329;330; VI-LABEL: bitcast_v6f32_to_v6i32_scalar:331; VI: ; %bb.0:332; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)333; VI-NEXT: s_cmp_lg_u32 s22, 0334; VI-NEXT: s_cbranch_scc0 .LBB3_3335; VI-NEXT: ; %bb.1: ; %cmp.false336; VI-NEXT: s_cbranch_execnz .LBB3_4337; VI-NEXT: .LBB3_2: ; %cmp.true338; VI-NEXT: v_add_f32_e64 v5, s21, 1.0339; VI-NEXT: v_add_f32_e64 v4, s20, 1.0340; VI-NEXT: v_add_f32_e64 v3, s19, 1.0341; VI-NEXT: v_add_f32_e64 v2, s18, 1.0342; VI-NEXT: v_add_f32_e64 v1, s17, 1.0343; VI-NEXT: v_add_f32_e64 v0, s16, 1.0344; VI-NEXT: s_setpc_b64 s[30:31]345; VI-NEXT: .LBB3_3:346; VI-NEXT: s_branch .LBB3_2347; VI-NEXT: .LBB3_4:348; VI-NEXT: v_mov_b32_e32 v0, s16349; VI-NEXT: v_mov_b32_e32 v1, s17350; VI-NEXT: v_mov_b32_e32 v2, s18351; VI-NEXT: v_mov_b32_e32 v3, s19352; VI-NEXT: v_mov_b32_e32 v4, s20353; VI-NEXT: v_mov_b32_e32 v5, s21354; VI-NEXT: s_setpc_b64 s[30:31]355;356; GFX9-LABEL: bitcast_v6f32_to_v6i32_scalar:357; GFX9: ; %bb.0:358; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)359; GFX9-NEXT: s_cmp_lg_u32 s22, 0360; GFX9-NEXT: s_cbranch_scc0 .LBB3_3361; GFX9-NEXT: ; %bb.1: ; %cmp.false362; GFX9-NEXT: s_cbranch_execnz .LBB3_4363; GFX9-NEXT: .LBB3_2: ; %cmp.true364; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0365; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0366; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0367; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0368; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0369; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0370; GFX9-NEXT: s_setpc_b64 s[30:31]371; GFX9-NEXT: .LBB3_3:372; GFX9-NEXT: s_branch .LBB3_2373; GFX9-NEXT: .LBB3_4:374; GFX9-NEXT: v_mov_b32_e32 v0, s16375; GFX9-NEXT: v_mov_b32_e32 v1, s17376; GFX9-NEXT: v_mov_b32_e32 v2, s18377; GFX9-NEXT: v_mov_b32_e32 v3, s19378; GFX9-NEXT: v_mov_b32_e32 v4, s20379; GFX9-NEXT: v_mov_b32_e32 v5, s21380; GFX9-NEXT: s_setpc_b64 s[30:31]381;382; GFX11-LABEL: bitcast_v6f32_to_v6i32_scalar:383; GFX11: ; %bb.0:384; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)385; GFX11-NEXT: s_mov_b32 s5, s17386; GFX11-NEXT: s_mov_b32 s4, s16387; GFX11-NEXT: s_cmp_lg_u32 s18, 0388; GFX11-NEXT: s_mov_b32 s6, 0389; GFX11-NEXT: s_cbranch_scc0 .LBB3_3390; GFX11-NEXT: ; %bb.1: ; %Flow391; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s6392; GFX11-NEXT: s_cbranch_vccnz .LBB3_4393; GFX11-NEXT: .LBB3_2: ; %cmp.true394; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.0395; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.0396; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.0397; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0398; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0399; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0400; GFX11-NEXT: s_setpc_b64 s[30:31]401; GFX11-NEXT: .LBB3_3:402; GFX11-NEXT: s_branch .LBB3_2403; GFX11-NEXT: .LBB3_4:404; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1405; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3406; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5407; GFX11-NEXT: s_setpc_b64 s[30:31]408 %cmp = icmp eq i32 %b, 0409 br i1 %cmp, label %cmp.true, label %cmp.false410 411cmp.true:412 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)413 %a2 = bitcast <6 x float> %a1 to <6 x i32>414 br label %end415 416cmp.false:417 %a3 = bitcast <6 x float> %a to <6 x i32>418 br label %end419 420end:421 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]422 ret <6 x i32> %phi423}424 425define <3 x i64> @bitcast_v6i32_to_v3i64(<6 x i32> %a, i32 %b) {426; SI-LABEL: bitcast_v6i32_to_v3i64:427; SI: ; %bb.0:428; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)429; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6430; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc431; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]432; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]433; SI-NEXT: ; %bb.1: ; %cmp.true434; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5435; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4436; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3437; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2438; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1439; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0440; SI-NEXT: ; %bb.2: ; %end441; SI-NEXT: s_or_b64 exec, exec, s[4:5]442; SI-NEXT: s_setpc_b64 s[30:31]443;444; VI-LABEL: bitcast_v6i32_to_v3i64:445; VI: ; %bb.0:446; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)447; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6448; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc449; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]450; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]451; VI-NEXT: ; %bb.1: ; %cmp.true452; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5453; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4454; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3455; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2456; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1457; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0458; VI-NEXT: ; %bb.2: ; %end459; VI-NEXT: s_or_b64 exec, exec, s[4:5]460; VI-NEXT: s_setpc_b64 s[30:31]461;462; GFX9-LABEL: bitcast_v6i32_to_v3i64:463; GFX9: ; %bb.0:464; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)465; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6466; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc467; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]468; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]469; GFX9-NEXT: ; %bb.1: ; %cmp.true470; GFX9-NEXT: v_add_u32_e32 v5, 3, v5471; GFX9-NEXT: v_add_u32_e32 v4, 3, v4472; GFX9-NEXT: v_add_u32_e32 v3, 3, v3473; GFX9-NEXT: v_add_u32_e32 v2, 3, v2474; GFX9-NEXT: v_add_u32_e32 v1, 3, v1475; GFX9-NEXT: v_add_u32_e32 v0, 3, v0476; GFX9-NEXT: ; %bb.2: ; %end477; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]478; GFX9-NEXT: s_setpc_b64 s[30:31]479;480; GFX11-LABEL: bitcast_v6i32_to_v3i64:481; GFX11: ; %bb.0:482; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; GFX11-NEXT: s_mov_b32 s0, exec_lo484; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6485; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0486; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)487; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0488; GFX11-NEXT: ; %bb.1: ; %cmp.true489; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5490; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4491; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3492; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2493; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1494; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0495; GFX11-NEXT: ; %bb.2: ; %end496; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0497; GFX11-NEXT: s_setpc_b64 s[30:31]498 %cmp = icmp eq i32 %b, 0499 br i1 %cmp, label %cmp.true, label %cmp.false500 501cmp.true:502 %a1 = add <6 x i32> %a, splat (i32 3)503 %a2 = bitcast <6 x i32> %a1 to <3 x i64>504 br label %end505 506cmp.false:507 %a3 = bitcast <6 x i32> %a to <3 x i64>508 br label %end509 510end:511 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]512 ret <3 x i64> %phi513}514 515define inreg <3 x i64> @bitcast_v6i32_to_v3i64_scalar(<6 x i32> inreg %a, i32 inreg %b) {516; SI-LABEL: bitcast_v6i32_to_v3i64_scalar:517; SI: ; %bb.0:518; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)519; SI-NEXT: s_cmp_lg_u32 s22, 0520; SI-NEXT: s_cbranch_scc0 .LBB5_4521; SI-NEXT: ; %bb.1: ; %cmp.false522; SI-NEXT: s_cbranch_execnz .LBB5_3523; SI-NEXT: .LBB5_2: ; %cmp.true524; SI-NEXT: s_add_i32 s21, s21, 3525; SI-NEXT: s_add_i32 s20, s20, 3526; SI-NEXT: s_add_i32 s19, s19, 3527; SI-NEXT: s_add_i32 s18, s18, 3528; SI-NEXT: s_add_i32 s17, s17, 3529; SI-NEXT: s_add_i32 s16, s16, 3530; SI-NEXT: .LBB5_3: ; %end531; SI-NEXT: v_mov_b32_e32 v0, s16532; SI-NEXT: v_mov_b32_e32 v1, s17533; SI-NEXT: v_mov_b32_e32 v2, s18534; SI-NEXT: v_mov_b32_e32 v3, s19535; SI-NEXT: v_mov_b32_e32 v4, s20536; SI-NEXT: v_mov_b32_e32 v5, s21537; SI-NEXT: s_setpc_b64 s[30:31]538; SI-NEXT: .LBB5_4:539; SI-NEXT: s_branch .LBB5_2540;541; VI-LABEL: bitcast_v6i32_to_v3i64_scalar:542; VI: ; %bb.0:543; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)544; VI-NEXT: s_cmp_lg_u32 s22, 0545; VI-NEXT: s_cbranch_scc0 .LBB5_4546; VI-NEXT: ; %bb.1: ; %cmp.false547; VI-NEXT: s_cbranch_execnz .LBB5_3548; VI-NEXT: .LBB5_2: ; %cmp.true549; VI-NEXT: s_add_i32 s21, s21, 3550; VI-NEXT: s_add_i32 s20, s20, 3551; VI-NEXT: s_add_i32 s19, s19, 3552; VI-NEXT: s_add_i32 s18, s18, 3553; VI-NEXT: s_add_i32 s17, s17, 3554; VI-NEXT: s_add_i32 s16, s16, 3555; VI-NEXT: .LBB5_3: ; %end556; VI-NEXT: v_mov_b32_e32 v0, s16557; VI-NEXT: v_mov_b32_e32 v1, s17558; VI-NEXT: v_mov_b32_e32 v2, s18559; VI-NEXT: v_mov_b32_e32 v3, s19560; VI-NEXT: v_mov_b32_e32 v4, s20561; VI-NEXT: v_mov_b32_e32 v5, s21562; VI-NEXT: s_setpc_b64 s[30:31]563; VI-NEXT: .LBB5_4:564; VI-NEXT: s_branch .LBB5_2565;566; GFX9-LABEL: bitcast_v6i32_to_v3i64_scalar:567; GFX9: ; %bb.0:568; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)569; GFX9-NEXT: s_cmp_lg_u32 s22, 0570; GFX9-NEXT: s_cbranch_scc0 .LBB5_4571; GFX9-NEXT: ; %bb.1: ; %cmp.false572; GFX9-NEXT: s_cbranch_execnz .LBB5_3573; GFX9-NEXT: .LBB5_2: ; %cmp.true574; GFX9-NEXT: s_add_i32 s21, s21, 3575; GFX9-NEXT: s_add_i32 s20, s20, 3576; GFX9-NEXT: s_add_i32 s19, s19, 3577; GFX9-NEXT: s_add_i32 s18, s18, 3578; GFX9-NEXT: s_add_i32 s17, s17, 3579; GFX9-NEXT: s_add_i32 s16, s16, 3580; GFX9-NEXT: .LBB5_3: ; %end581; GFX9-NEXT: v_mov_b32_e32 v0, s16582; GFX9-NEXT: v_mov_b32_e32 v1, s17583; GFX9-NEXT: v_mov_b32_e32 v2, s18584; GFX9-NEXT: v_mov_b32_e32 v3, s19585; GFX9-NEXT: v_mov_b32_e32 v4, s20586; GFX9-NEXT: v_mov_b32_e32 v5, s21587; GFX9-NEXT: s_setpc_b64 s[30:31]588; GFX9-NEXT: .LBB5_4:589; GFX9-NEXT: s_branch .LBB5_2590;591; GFX11-LABEL: bitcast_v6i32_to_v3i64_scalar:592; GFX11: ; %bb.0:593; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)594; GFX11-NEXT: s_cmp_lg_u32 s18, 0595; GFX11-NEXT: s_mov_b32 s4, 0596; GFX11-NEXT: s_cbranch_scc0 .LBB5_4597; GFX11-NEXT: ; %bb.1: ; %Flow598; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4599; GFX11-NEXT: s_cbranch_vccnz .LBB5_3600; GFX11-NEXT: .LBB5_2: ; %cmp.true601; GFX11-NEXT: s_add_i32 s17, s17, 3602; GFX11-NEXT: s_add_i32 s16, s16, 3603; GFX11-NEXT: s_add_i32 s3, s3, 3604; GFX11-NEXT: s_add_i32 s2, s2, 3605; GFX11-NEXT: s_add_i32 s1, s1, 3606; GFX11-NEXT: s_add_i32 s0, s0, 3607; GFX11-NEXT: .LBB5_3: ; %end608; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)609; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1610; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3611; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17612; GFX11-NEXT: s_setpc_b64 s[30:31]613; GFX11-NEXT: .LBB5_4:614; GFX11-NEXT: s_branch .LBB5_2615 %cmp = icmp eq i32 %b, 0616 br i1 %cmp, label %cmp.true, label %cmp.false617 618cmp.true:619 %a1 = add <6 x i32> %a, splat (i32 3)620 %a2 = bitcast <6 x i32> %a1 to <3 x i64>621 br label %end622 623cmp.false:624 %a3 = bitcast <6 x i32> %a to <3 x i64>625 br label %end626 627end:628 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]629 ret <3 x i64> %phi630}631 632define <6 x i32> @bitcast_v3i64_to_v6i32(<3 x i64> %a, i32 %b) {633; SI-LABEL: bitcast_v3i64_to_v6i32:634; SI: ; %bb.0:635; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)636; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6637; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc638; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]639; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]640; SI-NEXT: ; %bb.1: ; %cmp.true641; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4642; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc643; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2644; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc645; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0646; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc647; SI-NEXT: ; %bb.2: ; %end648; SI-NEXT: s_or_b64 exec, exec, s[4:5]649; SI-NEXT: s_setpc_b64 s[30:31]650;651; VI-LABEL: bitcast_v3i64_to_v6i32:652; VI: ; %bb.0:653; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)654; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6655; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc656; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]657; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]658; VI-NEXT: ; %bb.1: ; %cmp.true659; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4660; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc661; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2662; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc663; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0664; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc665; VI-NEXT: ; %bb.2: ; %end666; VI-NEXT: s_or_b64 exec, exec, s[4:5]667; VI-NEXT: s_setpc_b64 s[30:31]668;669; GFX9-LABEL: bitcast_v3i64_to_v6i32:670; GFX9: ; %bb.0:671; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)672; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6673; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc674; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]675; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]676; GFX9-NEXT: ; %bb.1: ; %cmp.true677; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v4678; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc679; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v2680; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc681; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v0682; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc683; GFX9-NEXT: ; %bb.2: ; %end684; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]685; GFX9-NEXT: s_setpc_b64 s[30:31]686;687; GFX11-LABEL: bitcast_v3i64_to_v6i32:688; GFX11: ; %bb.0:689; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)690; GFX11-NEXT: s_mov_b32 s0, exec_lo691; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6692; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0693; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)694; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0695; GFX11-NEXT: ; %bb.1: ; %cmp.true696; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 3697; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)698; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo699; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 3700; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo701; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 3702; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)703; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo704; GFX11-NEXT: ; %bb.2: ; %end705; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0706; GFX11-NEXT: s_setpc_b64 s[30:31]707 %cmp = icmp eq i32 %b, 0708 br i1 %cmp, label %cmp.true, label %cmp.false709 710cmp.true:711 %a1 = add <3 x i64> %a, splat (i64 3)712 %a2 = bitcast <3 x i64> %a1 to <6 x i32>713 br label %end714 715cmp.false:716 %a3 = bitcast <3 x i64> %a to <6 x i32>717 br label %end718 719end:720 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]721 ret <6 x i32> %phi722}723 724define inreg <6 x i32> @bitcast_v3i64_to_v6i32_scalar(<3 x i64> inreg %a, i32 inreg %b) {725; SI-LABEL: bitcast_v3i64_to_v6i32_scalar:726; SI: ; %bb.0:727; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)728; SI-NEXT: s_cmp_lg_u32 s22, 0729; SI-NEXT: s_cbranch_scc0 .LBB7_4730; SI-NEXT: ; %bb.1: ; %cmp.false731; SI-NEXT: s_cbranch_execnz .LBB7_3732; SI-NEXT: .LBB7_2: ; %cmp.true733; SI-NEXT: s_add_u32 s20, s20, 3734; SI-NEXT: s_addc_u32 s21, s21, 0735; SI-NEXT: s_add_u32 s18, s18, 3736; SI-NEXT: s_addc_u32 s19, s19, 0737; SI-NEXT: s_add_u32 s16, s16, 3738; SI-NEXT: s_addc_u32 s17, s17, 0739; SI-NEXT: .LBB7_3: ; %end740; SI-NEXT: v_mov_b32_e32 v0, s16741; SI-NEXT: v_mov_b32_e32 v1, s17742; SI-NEXT: v_mov_b32_e32 v2, s18743; SI-NEXT: v_mov_b32_e32 v3, s19744; SI-NEXT: v_mov_b32_e32 v4, s20745; SI-NEXT: v_mov_b32_e32 v5, s21746; SI-NEXT: s_setpc_b64 s[30:31]747; SI-NEXT: .LBB7_4:748; SI-NEXT: s_branch .LBB7_2749;750; VI-LABEL: bitcast_v3i64_to_v6i32_scalar:751; VI: ; %bb.0:752; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)753; VI-NEXT: s_cmp_lg_u32 s22, 0754; VI-NEXT: s_cbranch_scc0 .LBB7_4755; VI-NEXT: ; %bb.1: ; %cmp.false756; VI-NEXT: s_cbranch_execnz .LBB7_3757; VI-NEXT: .LBB7_2: ; %cmp.true758; VI-NEXT: s_add_u32 s20, s20, 3759; VI-NEXT: s_addc_u32 s21, s21, 0760; VI-NEXT: s_add_u32 s18, s18, 3761; VI-NEXT: s_addc_u32 s19, s19, 0762; VI-NEXT: s_add_u32 s16, s16, 3763; VI-NEXT: s_addc_u32 s17, s17, 0764; VI-NEXT: .LBB7_3: ; %end765; VI-NEXT: v_mov_b32_e32 v0, s16766; VI-NEXT: v_mov_b32_e32 v1, s17767; VI-NEXT: v_mov_b32_e32 v2, s18768; VI-NEXT: v_mov_b32_e32 v3, s19769; VI-NEXT: v_mov_b32_e32 v4, s20770; VI-NEXT: v_mov_b32_e32 v5, s21771; VI-NEXT: s_setpc_b64 s[30:31]772; VI-NEXT: .LBB7_4:773; VI-NEXT: s_branch .LBB7_2774;775; GFX9-LABEL: bitcast_v3i64_to_v6i32_scalar:776; GFX9: ; %bb.0:777; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)778; GFX9-NEXT: s_cmp_lg_u32 s22, 0779; GFX9-NEXT: s_cbranch_scc0 .LBB7_4780; GFX9-NEXT: ; %bb.1: ; %cmp.false781; GFX9-NEXT: s_cbranch_execnz .LBB7_3782; GFX9-NEXT: .LBB7_2: ; %cmp.true783; GFX9-NEXT: s_add_u32 s20, s20, 3784; GFX9-NEXT: s_addc_u32 s21, s21, 0785; GFX9-NEXT: s_add_u32 s18, s18, 3786; GFX9-NEXT: s_addc_u32 s19, s19, 0787; GFX9-NEXT: s_add_u32 s16, s16, 3788; GFX9-NEXT: s_addc_u32 s17, s17, 0789; GFX9-NEXT: .LBB7_3: ; %end790; GFX9-NEXT: v_mov_b32_e32 v0, s16791; GFX9-NEXT: v_mov_b32_e32 v1, s17792; GFX9-NEXT: v_mov_b32_e32 v2, s18793; GFX9-NEXT: v_mov_b32_e32 v3, s19794; GFX9-NEXT: v_mov_b32_e32 v4, s20795; GFX9-NEXT: v_mov_b32_e32 v5, s21796; GFX9-NEXT: s_setpc_b64 s[30:31]797; GFX9-NEXT: .LBB7_4:798; GFX9-NEXT: s_branch .LBB7_2799;800; GFX11-LABEL: bitcast_v3i64_to_v6i32_scalar:801; GFX11: ; %bb.0:802; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)803; GFX11-NEXT: s_cmp_lg_u32 s18, 0804; GFX11-NEXT: s_mov_b32 s4, 0805; GFX11-NEXT: s_cbranch_scc0 .LBB7_4806; GFX11-NEXT: ; %bb.1: ; %Flow807; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4808; GFX11-NEXT: s_cbranch_vccnz .LBB7_3809; GFX11-NEXT: .LBB7_2: ; %cmp.true810; GFX11-NEXT: s_add_u32 s16, s16, 3811; GFX11-NEXT: s_addc_u32 s17, s17, 0812; GFX11-NEXT: s_add_u32 s2, s2, 3813; GFX11-NEXT: s_addc_u32 s3, s3, 0814; GFX11-NEXT: s_add_u32 s0, s0, 3815; GFX11-NEXT: s_addc_u32 s1, s1, 0816; GFX11-NEXT: .LBB7_3: ; %end817; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)818; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1819; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3820; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17821; GFX11-NEXT: s_setpc_b64 s[30:31]822; GFX11-NEXT: .LBB7_4:823; GFX11-NEXT: s_branch .LBB7_2824 %cmp = icmp eq i32 %b, 0825 br i1 %cmp, label %cmp.true, label %cmp.false826 827cmp.true:828 %a1 = add <3 x i64> %a, splat (i64 3)829 %a2 = bitcast <3 x i64> %a1 to <6 x i32>830 br label %end831 832cmp.false:833 %a3 = bitcast <3 x i64> %a to <6 x i32>834 br label %end835 836end:837 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]838 ret <6 x i32> %phi839}840 841define <3 x double> @bitcast_v6i32_to_v3f64(<6 x i32> %a, i32 %b) {842; SI-LABEL: bitcast_v6i32_to_v3f64:843; SI: ; %bb.0:844; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)845; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6846; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc847; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]848; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]849; SI-NEXT: ; %bb.1: ; %cmp.true850; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v5851; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4852; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v3853; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2854; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v1855; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0856; SI-NEXT: ; %bb.2: ; %end857; SI-NEXT: s_or_b64 exec, exec, s[4:5]858; SI-NEXT: s_setpc_b64 s[30:31]859;860; VI-LABEL: bitcast_v6i32_to_v3f64:861; VI: ; %bb.0:862; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)863; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6864; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc865; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]866; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]867; VI-NEXT: ; %bb.1: ; %cmp.true868; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5869; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4870; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3871; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2872; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1873; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0874; VI-NEXT: ; %bb.2: ; %end875; VI-NEXT: s_or_b64 exec, exec, s[4:5]876; VI-NEXT: s_setpc_b64 s[30:31]877;878; GFX9-LABEL: bitcast_v6i32_to_v3f64:879; GFX9: ; %bb.0:880; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)881; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v6882; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc883; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]884; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]885; GFX9-NEXT: ; %bb.1: ; %cmp.true886; GFX9-NEXT: v_add_u32_e32 v5, 3, v5887; GFX9-NEXT: v_add_u32_e32 v4, 3, v4888; GFX9-NEXT: v_add_u32_e32 v3, 3, v3889; GFX9-NEXT: v_add_u32_e32 v2, 3, v2890; GFX9-NEXT: v_add_u32_e32 v1, 3, v1891; GFX9-NEXT: v_add_u32_e32 v0, 3, v0892; GFX9-NEXT: ; %bb.2: ; %end893; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]894; GFX9-NEXT: s_setpc_b64 s[30:31]895;896; GFX11-LABEL: bitcast_v6i32_to_v3f64:897; GFX11: ; %bb.0:898; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)899; GFX11-NEXT: s_mov_b32 s0, exec_lo900; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v6901; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0902; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)903; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0904; GFX11-NEXT: ; %bb.1: ; %cmp.true905; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5906; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4907; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3908; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2909; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1910; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0911; GFX11-NEXT: ; %bb.2: ; %end912; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0913; GFX11-NEXT: s_setpc_b64 s[30:31]914 %cmp = icmp eq i32 %b, 0915 br i1 %cmp, label %cmp.true, label %cmp.false916 917cmp.true:918 %a1 = add <6 x i32> %a, splat (i32 3)919 %a2 = bitcast <6 x i32> %a1 to <3 x double>920 br label %end921 922cmp.false:923 %a3 = bitcast <6 x i32> %a to <3 x double>924 br label %end925 926end:927 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]928 ret <3 x double> %phi929}930 931define inreg <3 x double> @bitcast_v6i32_to_v3f64_scalar(<6 x i32> inreg %a, i32 inreg %b) {932; SI-LABEL: bitcast_v6i32_to_v3f64_scalar:933; SI: ; %bb.0:934; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)935; SI-NEXT: s_cmp_lg_u32 s22, 0936; SI-NEXT: s_cbranch_scc0 .LBB9_4937; SI-NEXT: ; %bb.1: ; %cmp.false938; SI-NEXT: s_cbranch_execnz .LBB9_3939; SI-NEXT: .LBB9_2: ; %cmp.true940; SI-NEXT: s_add_i32 s21, s21, 3941; SI-NEXT: s_add_i32 s20, s20, 3942; SI-NEXT: s_add_i32 s19, s19, 3943; SI-NEXT: s_add_i32 s18, s18, 3944; SI-NEXT: s_add_i32 s17, s17, 3945; SI-NEXT: s_add_i32 s16, s16, 3946; SI-NEXT: .LBB9_3: ; %end947; SI-NEXT: v_mov_b32_e32 v0, s16948; SI-NEXT: v_mov_b32_e32 v1, s17949; SI-NEXT: v_mov_b32_e32 v2, s18950; SI-NEXT: v_mov_b32_e32 v3, s19951; SI-NEXT: v_mov_b32_e32 v4, s20952; SI-NEXT: v_mov_b32_e32 v5, s21953; SI-NEXT: s_setpc_b64 s[30:31]954; SI-NEXT: .LBB9_4:955; SI-NEXT: s_branch .LBB9_2956;957; VI-LABEL: bitcast_v6i32_to_v3f64_scalar:958; VI: ; %bb.0:959; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)960; VI-NEXT: s_cmp_lg_u32 s22, 0961; VI-NEXT: s_cbranch_scc0 .LBB9_4962; VI-NEXT: ; %bb.1: ; %cmp.false963; VI-NEXT: s_cbranch_execnz .LBB9_3964; VI-NEXT: .LBB9_2: ; %cmp.true965; VI-NEXT: s_add_i32 s21, s21, 3966; VI-NEXT: s_add_i32 s20, s20, 3967; VI-NEXT: s_add_i32 s19, s19, 3968; VI-NEXT: s_add_i32 s18, s18, 3969; VI-NEXT: s_add_i32 s17, s17, 3970; VI-NEXT: s_add_i32 s16, s16, 3971; VI-NEXT: .LBB9_3: ; %end972; VI-NEXT: v_mov_b32_e32 v0, s16973; VI-NEXT: v_mov_b32_e32 v1, s17974; VI-NEXT: v_mov_b32_e32 v2, s18975; VI-NEXT: v_mov_b32_e32 v3, s19976; VI-NEXT: v_mov_b32_e32 v4, s20977; VI-NEXT: v_mov_b32_e32 v5, s21978; VI-NEXT: s_setpc_b64 s[30:31]979; VI-NEXT: .LBB9_4:980; VI-NEXT: s_branch .LBB9_2981;982; GFX9-LABEL: bitcast_v6i32_to_v3f64_scalar:983; GFX9: ; %bb.0:984; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)985; GFX9-NEXT: s_cmp_lg_u32 s22, 0986; GFX9-NEXT: s_cbranch_scc0 .LBB9_4987; GFX9-NEXT: ; %bb.1: ; %cmp.false988; GFX9-NEXT: s_cbranch_execnz .LBB9_3989; GFX9-NEXT: .LBB9_2: ; %cmp.true990; GFX9-NEXT: s_add_i32 s21, s21, 3991; GFX9-NEXT: s_add_i32 s20, s20, 3992; GFX9-NEXT: s_add_i32 s19, s19, 3993; GFX9-NEXT: s_add_i32 s18, s18, 3994; GFX9-NEXT: s_add_i32 s17, s17, 3995; GFX9-NEXT: s_add_i32 s16, s16, 3996; GFX9-NEXT: .LBB9_3: ; %end997; GFX9-NEXT: v_mov_b32_e32 v0, s16998; GFX9-NEXT: v_mov_b32_e32 v1, s17999; GFX9-NEXT: v_mov_b32_e32 v2, s181000; GFX9-NEXT: v_mov_b32_e32 v3, s191001; GFX9-NEXT: v_mov_b32_e32 v4, s201002; GFX9-NEXT: v_mov_b32_e32 v5, s211003; GFX9-NEXT: s_setpc_b64 s[30:31]1004; GFX9-NEXT: .LBB9_4:1005; GFX9-NEXT: s_branch .LBB9_21006;1007; GFX11-LABEL: bitcast_v6i32_to_v3f64_scalar:1008; GFX11: ; %bb.0:1009; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1010; GFX11-NEXT: s_cmp_lg_u32 s18, 01011; GFX11-NEXT: s_mov_b32 s4, 01012; GFX11-NEXT: s_cbranch_scc0 .LBB9_41013; GFX11-NEXT: ; %bb.1: ; %Flow1014; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41015; GFX11-NEXT: s_cbranch_vccnz .LBB9_31016; GFX11-NEXT: .LBB9_2: ; %cmp.true1017; GFX11-NEXT: s_add_i32 s17, s17, 31018; GFX11-NEXT: s_add_i32 s16, s16, 31019; GFX11-NEXT: s_add_i32 s3, s3, 31020; GFX11-NEXT: s_add_i32 s2, s2, 31021; GFX11-NEXT: s_add_i32 s1, s1, 31022; GFX11-NEXT: s_add_i32 s0, s0, 31023; GFX11-NEXT: .LBB9_3: ; %end1024; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1025; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11026; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31027; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171028; GFX11-NEXT: s_setpc_b64 s[30:31]1029; GFX11-NEXT: .LBB9_4:1030; GFX11-NEXT: s_branch .LBB9_21031 %cmp = icmp eq i32 %b, 01032 br i1 %cmp, label %cmp.true, label %cmp.false1033 1034cmp.true:1035 %a1 = add <6 x i32> %a, splat (i32 3)1036 %a2 = bitcast <6 x i32> %a1 to <3 x double>1037 br label %end1038 1039cmp.false:1040 %a3 = bitcast <6 x i32> %a to <3 x double>1041 br label %end1042 1043end:1044 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1045 ret <3 x double> %phi1046}1047 1048define <6 x i32> @bitcast_v3f64_to_v6i32(<3 x double> %a, i32 %b) {1049; SI-LABEL: bitcast_v3f64_to_v6i32:1050; SI: ; %bb.0:1051; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1052; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61053; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1054; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1055; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1056; SI-NEXT: ; %bb.1: ; %cmp.true1057; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.01058; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.01059; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01060; SI-NEXT: ; %bb.2: ; %end1061; SI-NEXT: s_or_b64 exec, exec, s[4:5]1062; SI-NEXT: s_setpc_b64 s[30:31]1063;1064; VI-LABEL: bitcast_v3f64_to_v6i32:1065; VI: ; %bb.0:1066; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1067; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61068; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1069; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1070; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1071; VI-NEXT: s_cbranch_execz .LBB10_21072; VI-NEXT: ; %bb.1: ; %cmp.true1073; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.01074; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.01075; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01076; VI-NEXT: .LBB10_2: ; %end1077; VI-NEXT: s_or_b64 exec, exec, s[4:5]1078; VI-NEXT: s_setpc_b64 s[30:31]1079;1080; GFX9-LABEL: bitcast_v3f64_to_v6i32:1081; GFX9: ; %bb.0:1082; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1083; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61084; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1085; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1086; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1087; GFX9-NEXT: s_cbranch_execz .LBB10_21088; GFX9-NEXT: ; %bb.1: ; %cmp.true1089; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.01090; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.01091; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.01092; GFX9-NEXT: .LBB10_2: ; %end1093; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1094; GFX9-NEXT: s_setpc_b64 s[30:31]1095;1096; GFX11-LABEL: bitcast_v3f64_to_v6i32:1097; GFX11: ; %bb.0:1098; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1099; GFX11-NEXT: s_mov_b32 s0, exec_lo1100; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v61101; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01102; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1103; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01104; GFX11-NEXT: s_cbranch_execz .LBB10_21105; GFX11-NEXT: ; %bb.1: ; %cmp.true1106; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.01107; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.01108; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.01109; GFX11-NEXT: .LBB10_2: ; %end1110; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01111; GFX11-NEXT: s_setpc_b64 s[30:31]1112 %cmp = icmp eq i32 %b, 01113 br i1 %cmp, label %cmp.true, label %cmp.false1114 1115cmp.true:1116 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)1117 %a2 = bitcast <3 x double> %a1 to <6 x i32>1118 br label %end1119 1120cmp.false:1121 %a3 = bitcast <3 x double> %a to <6 x i32>1122 br label %end1123 1124end:1125 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1126 ret <6 x i32> %phi1127}1128 1129define inreg <6 x i32> @bitcast_v3f64_to_v6i32_scalar(<3 x double> inreg %a, i32 inreg %b) {1130; SI-LABEL: bitcast_v3f64_to_v6i32_scalar:1131; SI: ; %bb.0:1132; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1133; SI-NEXT: s_cmp_lg_u32 s22, 01134; SI-NEXT: s_cbranch_scc0 .LBB11_31135; SI-NEXT: ; %bb.1: ; %cmp.false1136; SI-NEXT: s_cbranch_execnz .LBB11_41137; SI-NEXT: .LBB11_2: ; %cmp.true1138; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.01139; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.01140; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.01141; SI-NEXT: s_setpc_b64 s[30:31]1142; SI-NEXT: .LBB11_3:1143; SI-NEXT: s_branch .LBB11_21144; SI-NEXT: .LBB11_4:1145; SI-NEXT: v_mov_b32_e32 v0, s161146; SI-NEXT: v_mov_b32_e32 v1, s171147; SI-NEXT: v_mov_b32_e32 v2, s181148; SI-NEXT: v_mov_b32_e32 v3, s191149; SI-NEXT: v_mov_b32_e32 v4, s201150; SI-NEXT: v_mov_b32_e32 v5, s211151; SI-NEXT: s_setpc_b64 s[30:31]1152;1153; VI-LABEL: bitcast_v3f64_to_v6i32_scalar:1154; VI: ; %bb.0:1155; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1156; VI-NEXT: s_cmp_lg_u32 s22, 01157; VI-NEXT: s_cbranch_scc0 .LBB11_31158; VI-NEXT: ; %bb.1: ; %cmp.false1159; VI-NEXT: s_cbranch_execnz .LBB11_41160; VI-NEXT: .LBB11_2: ; %cmp.true1161; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.01162; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.01163; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.01164; VI-NEXT: s_setpc_b64 s[30:31]1165; VI-NEXT: .LBB11_3:1166; VI-NEXT: s_branch .LBB11_21167; VI-NEXT: .LBB11_4:1168; VI-NEXT: v_mov_b32_e32 v0, s161169; VI-NEXT: v_mov_b32_e32 v1, s171170; VI-NEXT: v_mov_b32_e32 v2, s181171; VI-NEXT: v_mov_b32_e32 v3, s191172; VI-NEXT: v_mov_b32_e32 v4, s201173; VI-NEXT: v_mov_b32_e32 v5, s211174; VI-NEXT: s_setpc_b64 s[30:31]1175;1176; GFX9-LABEL: bitcast_v3f64_to_v6i32_scalar:1177; GFX9: ; %bb.0:1178; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1179; GFX9-NEXT: s_cmp_lg_u32 s22, 01180; GFX9-NEXT: s_cbranch_scc0 .LBB11_31181; GFX9-NEXT: ; %bb.1: ; %cmp.false1182; GFX9-NEXT: s_cbranch_execnz .LBB11_41183; GFX9-NEXT: .LBB11_2: ; %cmp.true1184; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.01185; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.01186; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.01187; GFX9-NEXT: s_setpc_b64 s[30:31]1188; GFX9-NEXT: .LBB11_3:1189; GFX9-NEXT: s_branch .LBB11_21190; GFX9-NEXT: .LBB11_4:1191; GFX9-NEXT: v_mov_b32_e32 v0, s161192; GFX9-NEXT: v_mov_b32_e32 v1, s171193; GFX9-NEXT: v_mov_b32_e32 v2, s181194; GFX9-NEXT: v_mov_b32_e32 v3, s191195; GFX9-NEXT: v_mov_b32_e32 v4, s201196; GFX9-NEXT: v_mov_b32_e32 v5, s211197; GFX9-NEXT: s_setpc_b64 s[30:31]1198;1199; GFX11-LABEL: bitcast_v3f64_to_v6i32_scalar:1200; GFX11: ; %bb.0:1201; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1202; GFX11-NEXT: s_mov_b32 s5, s171203; GFX11-NEXT: s_mov_b32 s4, s161204; GFX11-NEXT: s_cmp_lg_u32 s18, 01205; GFX11-NEXT: s_mov_b32 s6, 01206; GFX11-NEXT: s_cbranch_scc0 .LBB11_31207; GFX11-NEXT: ; %bb.1: ; %Flow1208; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s61209; GFX11-NEXT: s_cbranch_vccnz .LBB11_41210; GFX11-NEXT: .LBB11_2: ; %cmp.true1211; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.01212; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.01213; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.01214; GFX11-NEXT: s_setpc_b64 s[30:31]1215; GFX11-NEXT: .LBB11_3:1216; GFX11-NEXT: s_branch .LBB11_21217; GFX11-NEXT: .LBB11_4:1218; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11219; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31220; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s51221; GFX11-NEXT: s_setpc_b64 s[30:31]1222 %cmp = icmp eq i32 %b, 01223 br i1 %cmp, label %cmp.true, label %cmp.false1224 1225cmp.true:1226 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)1227 %a2 = bitcast <3 x double> %a1 to <6 x i32>1228 br label %end1229 1230cmp.false:1231 %a3 = bitcast <3 x double> %a to <6 x i32>1232 br label %end1233 1234end:1235 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1236 ret <6 x i32> %phi1237}1238 1239define <12 x i16> @bitcast_v6i32_to_v12i16(<6 x i32> %a, i32 %b) {1240; SI-LABEL: bitcast_v6i32_to_v12i16:1241; SI: ; %bb.0:1242; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1243; SI-NEXT: v_mov_b32_e32 v10, v51244; SI-NEXT: v_mov_b32_e32 v8, v41245; SI-NEXT: v_mov_b32_e32 v12, v31246; SI-NEXT: v_mov_b32_e32 v4, v21247; SI-NEXT: v_mov_b32_e32 v2, v11248; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61249; SI-NEXT: ; implicit-def: $vgpr11250; SI-NEXT: ; implicit-def: $vgpr31251; SI-NEXT: ; implicit-def: $vgpr51252; SI-NEXT: ; implicit-def: $vgpr71253; SI-NEXT: ; implicit-def: $vgpr91254; SI-NEXT: ; implicit-def: $vgpr111255; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1256; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1257; SI-NEXT: ; %bb.1: ; %cmp.false1258; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161259; SI-NEXT: v_alignbit_b32 v5, v12, v4, 161260; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161261; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101262; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v121263; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21264; SI-NEXT: ; %bb.2: ; %Flow1265; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1266; SI-NEXT: s_cbranch_execz .LBB12_41267; SI-NEXT: ; %bb.3: ; %cmp.true1268; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21269; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v01270; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v121271; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v41272; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v101273; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v81274; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161275; SI-NEXT: v_alignbit_b32 v5, v12, v4, 161276; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161277; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101278; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v121279; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21280; SI-NEXT: .LBB12_4: ; %end1281; SI-NEXT: s_or_b64 exec, exec, s[4:5]1282; SI-NEXT: v_mov_b32_e32 v6, v121283; SI-NEXT: s_setpc_b64 s[30:31]1284;1285; VI-LABEL: bitcast_v6i32_to_v12i16:1286; VI: ; %bb.0:1287; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1288; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61289; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1290; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1291; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1292; VI-NEXT: ; %bb.1: ; %cmp.true1293; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51294; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41295; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31296; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21297; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11298; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01299; VI-NEXT: ; %bb.2: ; %end1300; VI-NEXT: s_or_b64 exec, exec, s[4:5]1301; VI-NEXT: s_setpc_b64 s[30:31]1302;1303; GFX9-LABEL: bitcast_v6i32_to_v12i16:1304; GFX9: ; %bb.0:1305; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1306; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61307; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1308; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1309; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1310; GFX9-NEXT: ; %bb.1: ; %cmp.true1311; GFX9-NEXT: v_add_u32_e32 v5, 3, v51312; GFX9-NEXT: v_add_u32_e32 v4, 3, v41313; GFX9-NEXT: v_add_u32_e32 v3, 3, v31314; GFX9-NEXT: v_add_u32_e32 v2, 3, v21315; GFX9-NEXT: v_add_u32_e32 v1, 3, v11316; GFX9-NEXT: v_add_u32_e32 v0, 3, v01317; GFX9-NEXT: ; %bb.2: ; %end1318; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1319; GFX9-NEXT: s_setpc_b64 s[30:31]1320;1321; GFX11-LABEL: bitcast_v6i32_to_v12i16:1322; GFX11: ; %bb.0:1323; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1324; GFX11-NEXT: s_mov_b32 s0, exec_lo1325; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v61326; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01327; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1328; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01329; GFX11-NEXT: ; %bb.1: ; %cmp.true1330; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51331; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41332; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31333; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21334; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11335; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01336; GFX11-NEXT: ; %bb.2: ; %end1337; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01338; GFX11-NEXT: s_setpc_b64 s[30:31]1339 %cmp = icmp eq i32 %b, 01340 br i1 %cmp, label %cmp.true, label %cmp.false1341 1342cmp.true:1343 %a1 = add <6 x i32> %a, splat (i32 3)1344 %a2 = bitcast <6 x i32> %a1 to <12 x i16>1345 br label %end1346 1347cmp.false:1348 %a3 = bitcast <6 x i32> %a to <12 x i16>1349 br label %end1350 1351end:1352 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1353 ret <12 x i16> %phi1354}1355 1356define inreg <12 x i16> @bitcast_v6i32_to_v12i16_scalar(<6 x i32> inreg %a, i32 inreg %b) {1357; SI-LABEL: bitcast_v6i32_to_v12i16_scalar:1358; SI: ; %bb.0:1359; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1360; SI-NEXT: s_cmp_lg_u32 s22, 01361; SI-NEXT: s_cbranch_scc0 .LBB13_41362; SI-NEXT: ; %bb.1: ; %cmp.false1363; SI-NEXT: s_lshr_b32 s12, s21, 161364; SI-NEXT: s_lshr_b32 s13, s19, 161365; SI-NEXT: s_lshr_b32 s14, s17, 161366; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 161367; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 161368; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 161369; SI-NEXT: s_cbranch_execnz .LBB13_31370; SI-NEXT: .LBB13_2: ; %cmp.true1371; SI-NEXT: s_add_i32 s17, s17, 31372; SI-NEXT: s_add_i32 s16, s16, 31373; SI-NEXT: s_add_i32 s19, s19, 31374; SI-NEXT: s_add_i32 s18, s18, 31375; SI-NEXT: s_add_i32 s21, s21, 31376; SI-NEXT: s_add_i32 s20, s20, 31377; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 161378; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 161379; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 161380; SI-NEXT: s_lshr_b32 s12, s21, 161381; SI-NEXT: s_lshr_b32 s13, s19, 161382; SI-NEXT: s_lshr_b32 s14, s17, 161383; SI-NEXT: .LBB13_3: ; %end1384; SI-NEXT: v_mov_b32_e32 v0, s161385; SI-NEXT: v_mov_b32_e32 v1, s81386; SI-NEXT: v_mov_b32_e32 v2, s171387; SI-NEXT: v_mov_b32_e32 v3, s141388; SI-NEXT: v_mov_b32_e32 v4, s181389; SI-NEXT: v_mov_b32_e32 v5, s61390; SI-NEXT: v_mov_b32_e32 v6, s191391; SI-NEXT: v_mov_b32_e32 v7, s131392; SI-NEXT: v_mov_b32_e32 v8, s201393; SI-NEXT: v_mov_b32_e32 v9, s41394; SI-NEXT: v_mov_b32_e32 v10, s211395; SI-NEXT: v_mov_b32_e32 v11, s121396; SI-NEXT: s_setpc_b64 s[30:31]1397; SI-NEXT: .LBB13_4:1398; SI-NEXT: ; implicit-def: $sgpr81399; SI-NEXT: ; implicit-def: $sgpr141400; SI-NEXT: ; implicit-def: $sgpr61401; SI-NEXT: ; implicit-def: $sgpr131402; SI-NEXT: ; implicit-def: $sgpr41403; SI-NEXT: ; implicit-def: $sgpr121404; SI-NEXT: s_branch .LBB13_21405;1406; VI-LABEL: bitcast_v6i32_to_v12i16_scalar:1407; VI: ; %bb.0:1408; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1409; VI-NEXT: s_cmp_lg_u32 s22, 01410; VI-NEXT: s_cbranch_scc0 .LBB13_41411; VI-NEXT: ; %bb.1: ; %cmp.false1412; VI-NEXT: s_cbranch_execnz .LBB13_31413; VI-NEXT: .LBB13_2: ; %cmp.true1414; VI-NEXT: s_add_i32 s21, s21, 31415; VI-NEXT: s_add_i32 s20, s20, 31416; VI-NEXT: s_add_i32 s19, s19, 31417; VI-NEXT: s_add_i32 s18, s18, 31418; VI-NEXT: s_add_i32 s17, s17, 31419; VI-NEXT: s_add_i32 s16, s16, 31420; VI-NEXT: .LBB13_3: ; %end1421; VI-NEXT: v_mov_b32_e32 v0, s161422; VI-NEXT: v_mov_b32_e32 v1, s171423; VI-NEXT: v_mov_b32_e32 v2, s181424; VI-NEXT: v_mov_b32_e32 v3, s191425; VI-NEXT: v_mov_b32_e32 v4, s201426; VI-NEXT: v_mov_b32_e32 v5, s211427; VI-NEXT: s_setpc_b64 s[30:31]1428; VI-NEXT: .LBB13_4:1429; VI-NEXT: s_branch .LBB13_21430;1431; GFX9-LABEL: bitcast_v6i32_to_v12i16_scalar:1432; GFX9: ; %bb.0:1433; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1434; GFX9-NEXT: s_cmp_lg_u32 s22, 01435; GFX9-NEXT: s_cbranch_scc0 .LBB13_41436; GFX9-NEXT: ; %bb.1: ; %cmp.false1437; GFX9-NEXT: s_cbranch_execnz .LBB13_31438; GFX9-NEXT: .LBB13_2: ; %cmp.true1439; GFX9-NEXT: s_add_i32 s21, s21, 31440; GFX9-NEXT: s_add_i32 s20, s20, 31441; GFX9-NEXT: s_add_i32 s19, s19, 31442; GFX9-NEXT: s_add_i32 s18, s18, 31443; GFX9-NEXT: s_add_i32 s17, s17, 31444; GFX9-NEXT: s_add_i32 s16, s16, 31445; GFX9-NEXT: .LBB13_3: ; %end1446; GFX9-NEXT: v_mov_b32_e32 v0, s161447; GFX9-NEXT: v_mov_b32_e32 v1, s171448; GFX9-NEXT: v_mov_b32_e32 v2, s181449; GFX9-NEXT: v_mov_b32_e32 v3, s191450; GFX9-NEXT: v_mov_b32_e32 v4, s201451; GFX9-NEXT: v_mov_b32_e32 v5, s211452; GFX9-NEXT: s_setpc_b64 s[30:31]1453; GFX9-NEXT: .LBB13_4:1454; GFX9-NEXT: s_branch .LBB13_21455;1456; GFX11-LABEL: bitcast_v6i32_to_v12i16_scalar:1457; GFX11: ; %bb.0:1458; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1459; GFX11-NEXT: s_cmp_lg_u32 s18, 01460; GFX11-NEXT: s_mov_b32 s4, 01461; GFX11-NEXT: s_cbranch_scc0 .LBB13_41462; GFX11-NEXT: ; %bb.1: ; %Flow1463; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41464; GFX11-NEXT: s_cbranch_vccnz .LBB13_31465; GFX11-NEXT: .LBB13_2: ; %cmp.true1466; GFX11-NEXT: s_add_i32 s17, s17, 31467; GFX11-NEXT: s_add_i32 s16, s16, 31468; GFX11-NEXT: s_add_i32 s3, s3, 31469; GFX11-NEXT: s_add_i32 s2, s2, 31470; GFX11-NEXT: s_add_i32 s1, s1, 31471; GFX11-NEXT: s_add_i32 s0, s0, 31472; GFX11-NEXT: .LBB13_3: ; %end1473; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1474; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11475; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31476; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171477; GFX11-NEXT: s_setpc_b64 s[30:31]1478; GFX11-NEXT: .LBB13_4:1479; GFX11-NEXT: s_branch .LBB13_21480 %cmp = icmp eq i32 %b, 01481 br i1 %cmp, label %cmp.true, label %cmp.false1482 1483cmp.true:1484 %a1 = add <6 x i32> %a, splat (i32 3)1485 %a2 = bitcast <6 x i32> %a1 to <12 x i16>1486 br label %end1487 1488cmp.false:1489 %a3 = bitcast <6 x i32> %a to <12 x i16>1490 br label %end1491 1492end:1493 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1494 ret <12 x i16> %phi1495}1496 1497define <6 x i32> @bitcast_v12i16_to_v6i32(<12 x i16> %a, i32 %b) {1498; SI-LABEL: bitcast_v12i16_to_v6i32:1499; SI: ; %bb.0:1500; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1501; SI-NEXT: v_mov_b32_e32 v15, v41502; SI-NEXT: v_mov_b32_e32 v14, v21503; SI-NEXT: v_mov_b32_e32 v13, v01504; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v121505; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v11506; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v31507; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v51508; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v71509; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v91510; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v111511; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr51512; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1513; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1514; SI-NEXT: s_cbranch_execnz .LBB14_31515; SI-NEXT: ; %bb.1: ; %Flow1516; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1517; SI-NEXT: s_cbranch_execnz .LBB14_41518; SI-NEXT: .LBB14_2: ; %end1519; SI-NEXT: s_or_b64 exec, exec, s[4:5]1520; SI-NEXT: s_setpc_b64 s[30:31]1521; SI-NEXT: .LBB14_3: ; %cmp.false1522; SI-NEXT: v_and_b32_e32 v0, 0xffff, v131523; SI-NEXT: v_and_b32_e32 v1, 0xffff, v141524; SI-NEXT: v_and_b32_e32 v2, 0xffff, v151525; SI-NEXT: v_and_b32_e32 v3, 0xffff, v61526; SI-NEXT: v_and_b32_e32 v4, 0xffff, v81527; SI-NEXT: v_and_b32_e32 v5, 0xffff, v101528; SI-NEXT: v_or_b32_e32 v0, v0, v181529; SI-NEXT: v_or_b32_e32 v1, v1, v171530; SI-NEXT: v_or_b32_e32 v2, v2, v161531; SI-NEXT: v_or_b32_e32 v3, v3, v121532; SI-NEXT: v_or_b32_e32 v4, v4, v91533; SI-NEXT: v_or_b32_e32 v5, v5, v71534; SI-NEXT: ; implicit-def: $vgpr131535; SI-NEXT: ; implicit-def: $vgpr141536; SI-NEXT: ; implicit-def: $vgpr151537; SI-NEXT: ; implicit-def: $vgpr61538; SI-NEXT: ; implicit-def: $vgpr81539; SI-NEXT: ; implicit-def: $vgpr101540; SI-NEXT: ; implicit-def: $vgpr181541; SI-NEXT: ; implicit-def: $vgpr171542; SI-NEXT: ; implicit-def: $vgpr161543; SI-NEXT: ; implicit-def: $vgpr121544; SI-NEXT: ; implicit-def: $vgpr91545; SI-NEXT: ; implicit-def: $vgpr71546; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1547; SI-NEXT: s_cbranch_execz .LBB14_21548; SI-NEXT: .LBB14_4: ; %cmp.true1549; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v131550; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v141551; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v151552; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v61553; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v81554; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v101555; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01556; SI-NEXT: v_and_b32_e32 v1, 0xffff, v11557; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21558; SI-NEXT: v_and_b32_e32 v3, 0xffff, v31559; SI-NEXT: v_and_b32_e32 v4, 0xffff, v41560; SI-NEXT: v_and_b32_e32 v5, 0xffff, v51561; SI-NEXT: v_or_b32_e32 v0, v18, v01562; SI-NEXT: s_mov_b32 s6, 0x300001563; SI-NEXT: v_or_b32_e32 v1, v17, v11564; SI-NEXT: v_or_b32_e32 v2, v16, v21565; SI-NEXT: v_or_b32_e32 v3, v12, v31566; SI-NEXT: v_or_b32_e32 v4, v9, v41567; SI-NEXT: v_or_b32_e32 v5, v7, v51568; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v01569; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v11570; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v21571; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v31572; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v41573; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v51574; SI-NEXT: s_or_b64 exec, exec, s[4:5]1575; SI-NEXT: s_setpc_b64 s[30:31]1576;1577; VI-LABEL: bitcast_v12i16_to_v6i32:1578; VI: ; %bb.0:1579; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1580; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61581; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1582; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1583; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1584; VI-NEXT: s_cbranch_execz .LBB14_21585; VI-NEXT: ; %bb.1: ; %cmp.true1586; VI-NEXT: v_mov_b32_e32 v7, 31587; VI-NEXT: v_add_u16_e32 v6, 3, v51588; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1589; VI-NEXT: v_or_b32_e32 v5, v6, v51590; VI-NEXT: v_add_u16_e32 v6, 3, v41591; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1592; VI-NEXT: v_or_b32_e32 v4, v6, v41593; VI-NEXT: v_add_u16_e32 v6, 3, v31594; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1595; VI-NEXT: v_or_b32_e32 v3, v6, v31596; VI-NEXT: v_add_u16_e32 v6, 3, v21597; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1598; VI-NEXT: v_or_b32_e32 v2, v6, v21599; VI-NEXT: v_add_u16_e32 v6, 3, v11600; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1601; VI-NEXT: v_or_b32_e32 v1, v6, v11602; VI-NEXT: v_add_u16_e32 v6, 3, v01603; VI-NEXT: v_add_u16_sdwa v0, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1604; VI-NEXT: v_or_b32_e32 v0, v6, v01605; VI-NEXT: .LBB14_2: ; %end1606; VI-NEXT: s_or_b64 exec, exec, s[4:5]1607; VI-NEXT: s_setpc_b64 s[30:31]1608;1609; GFX9-LABEL: bitcast_v12i16_to_v6i32:1610; GFX9: ; %bb.0:1611; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1612; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61613; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1614; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1615; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1616; GFX9-NEXT: ; %bb.1: ; %cmp.true1617; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]1618; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1619; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1620; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1621; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1622; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1623; GFX9-NEXT: ; %bb.2: ; %end1624; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1625; GFX9-NEXT: s_setpc_b64 s[30:31]1626;1627; GFX11-LABEL: bitcast_v12i16_to_v6i32:1628; GFX11: ; %bb.0:1629; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1630; GFX11-NEXT: s_mov_b32 s0, exec_lo1631; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v61632; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01633; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1634; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01635; GFX11-NEXT: ; %bb.1: ; %cmp.true1636; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]1637; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1638; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1639; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1640; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1641; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1642; GFX11-NEXT: ; %bb.2: ; %end1643; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01644; GFX11-NEXT: s_setpc_b64 s[30:31]1645 %cmp = icmp eq i32 %b, 01646 br i1 %cmp, label %cmp.true, label %cmp.false1647 1648cmp.true:1649 %a1 = add <12 x i16> %a, splat (i16 3)1650 %a2 = bitcast <12 x i16> %a1 to <6 x i32>1651 br label %end1652 1653cmp.false:1654 %a3 = bitcast <12 x i16> %a to <6 x i32>1655 br label %end1656 1657end:1658 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1659 ret <6 x i32> %phi1660}1661 1662define inreg <6 x i32> @bitcast_v12i16_to_v6i32_scalar(<12 x i16> inreg %a, i32 inreg %b) {1663; SI-LABEL: bitcast_v12i16_to_v6i32_scalar:1664; SI: ; %bb.0:1665; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1666; SI-NEXT: s_cmp_lg_u32 s28, 01667; SI-NEXT: s_cbranch_scc0 .LBB15_41668; SI-NEXT: ; %bb.1: ; %cmp.false1669; SI-NEXT: s_and_b32 s4, s16, 0xffff1670; SI-NEXT: s_lshl_b32 s5, s17, 161671; SI-NEXT: s_or_b32 s4, s4, s51672; SI-NEXT: s_and_b32 s5, s18, 0xffff1673; SI-NEXT: s_lshl_b32 s6, s19, 161674; SI-NEXT: s_or_b32 s5, s5, s61675; SI-NEXT: s_and_b32 s6, s20, 0xffff1676; SI-NEXT: s_lshl_b32 s7, s21, 161677; SI-NEXT: s_or_b32 s6, s6, s71678; SI-NEXT: s_and_b32 s7, s22, 0xffff1679; SI-NEXT: s_lshl_b32 s8, s23, 161680; SI-NEXT: s_or_b32 s7, s7, s81681; SI-NEXT: s_and_b32 s8, s24, 0xffff1682; SI-NEXT: s_lshl_b32 s9, s25, 161683; SI-NEXT: s_or_b32 s8, s8, s91684; SI-NEXT: s_and_b32 s9, s26, 0xffff1685; SI-NEXT: s_lshl_b32 s10, s27, 161686; SI-NEXT: s_or_b32 s9, s9, s101687; SI-NEXT: s_cbranch_execnz .LBB15_31688; SI-NEXT: .LBB15_2: ; %cmp.true1689; SI-NEXT: s_add_i32 s16, s16, 31690; SI-NEXT: s_and_b32 s4, s16, 0xffff1691; SI-NEXT: s_lshl_b32 s5, s17, 161692; SI-NEXT: s_add_i32 s18, s18, 31693; SI-NEXT: s_or_b32 s4, s5, s41694; SI-NEXT: s_and_b32 s5, s18, 0xffff1695; SI-NEXT: s_lshl_b32 s6, s19, 161696; SI-NEXT: s_add_i32 s20, s20, 31697; SI-NEXT: s_or_b32 s5, s6, s51698; SI-NEXT: s_and_b32 s6, s20, 0xffff1699; SI-NEXT: s_lshl_b32 s7, s21, 161700; SI-NEXT: s_add_i32 s22, s22, 31701; SI-NEXT: s_or_b32 s6, s7, s61702; SI-NEXT: s_and_b32 s7, s22, 0xffff1703; SI-NEXT: s_lshl_b32 s8, s23, 161704; SI-NEXT: s_add_i32 s24, s24, 31705; SI-NEXT: s_or_b32 s7, s8, s71706; SI-NEXT: s_and_b32 s8, s24, 0xffff1707; SI-NEXT: s_lshl_b32 s9, s25, 161708; SI-NEXT: s_add_i32 s26, s26, 31709; SI-NEXT: s_or_b32 s8, s9, s81710; SI-NEXT: s_and_b32 s9, s26, 0xffff1711; SI-NEXT: s_lshl_b32 s10, s27, 161712; SI-NEXT: s_or_b32 s9, s10, s91713; SI-NEXT: s_add_i32 s4, s4, 0x300001714; SI-NEXT: s_add_i32 s5, s5, 0x300001715; SI-NEXT: s_add_i32 s6, s6, 0x300001716; SI-NEXT: s_add_i32 s7, s7, 0x300001717; SI-NEXT: s_add_i32 s8, s8, 0x300001718; SI-NEXT: s_add_i32 s9, s9, 0x300001719; SI-NEXT: .LBB15_3: ; %end1720; SI-NEXT: v_mov_b32_e32 v0, s41721; SI-NEXT: v_mov_b32_e32 v1, s51722; SI-NEXT: v_mov_b32_e32 v2, s61723; SI-NEXT: v_mov_b32_e32 v3, s71724; SI-NEXT: v_mov_b32_e32 v4, s81725; SI-NEXT: v_mov_b32_e32 v5, s91726; SI-NEXT: s_setpc_b64 s[30:31]1727; SI-NEXT: .LBB15_4:1728; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr91729; SI-NEXT: s_branch .LBB15_21730;1731; VI-LABEL: bitcast_v12i16_to_v6i32_scalar:1732; VI: ; %bb.0:1733; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1734; VI-NEXT: s_cmp_lg_u32 s22, 01735; VI-NEXT: s_cbranch_scc0 .LBB15_41736; VI-NEXT: ; %bb.1: ; %cmp.false1737; VI-NEXT: s_cbranch_execnz .LBB15_31738; VI-NEXT: .LBB15_2: ; %cmp.true1739; VI-NEXT: s_add_i32 s5, s21, 31740; VI-NEXT: s_and_b32 s4, s21, 0xffff00001741; VI-NEXT: s_and_b32 s5, s5, 0xffff1742; VI-NEXT: s_or_b32 s4, s4, s51743; VI-NEXT: s_add_i32 s5, s20, 31744; VI-NEXT: s_add_i32 s21, s4, 0x300001745; VI-NEXT: s_and_b32 s4, s20, 0xffff00001746; VI-NEXT: s_and_b32 s5, s5, 0xffff1747; VI-NEXT: s_or_b32 s4, s4, s51748; VI-NEXT: s_add_i32 s5, s19, 31749; VI-NEXT: s_add_i32 s20, s4, 0x300001750; VI-NEXT: s_and_b32 s4, s19, 0xffff00001751; VI-NEXT: s_and_b32 s5, s5, 0xffff1752; VI-NEXT: s_or_b32 s4, s4, s51753; VI-NEXT: s_add_i32 s5, s18, 31754; VI-NEXT: s_add_i32 s19, s4, 0x300001755; VI-NEXT: s_and_b32 s4, s18, 0xffff00001756; VI-NEXT: s_and_b32 s5, s5, 0xffff1757; VI-NEXT: s_or_b32 s4, s4, s51758; VI-NEXT: s_add_i32 s5, s17, 31759; VI-NEXT: s_add_i32 s18, s4, 0x300001760; VI-NEXT: s_and_b32 s4, s17, 0xffff00001761; VI-NEXT: s_and_b32 s5, s5, 0xffff1762; VI-NEXT: s_or_b32 s4, s4, s51763; VI-NEXT: s_add_i32 s5, s16, 31764; VI-NEXT: s_add_i32 s17, s4, 0x300001765; VI-NEXT: s_and_b32 s4, s16, 0xffff00001766; VI-NEXT: s_and_b32 s5, s5, 0xffff1767; VI-NEXT: s_or_b32 s4, s4, s51768; VI-NEXT: s_add_i32 s16, s4, 0x300001769; VI-NEXT: .LBB15_3: ; %end1770; VI-NEXT: v_mov_b32_e32 v0, s161771; VI-NEXT: v_mov_b32_e32 v1, s171772; VI-NEXT: v_mov_b32_e32 v2, s181773; VI-NEXT: v_mov_b32_e32 v3, s191774; VI-NEXT: v_mov_b32_e32 v4, s201775; VI-NEXT: v_mov_b32_e32 v5, s211776; VI-NEXT: s_setpc_b64 s[30:31]1777; VI-NEXT: .LBB15_4:1778; VI-NEXT: s_branch .LBB15_21779;1780; GFX9-LABEL: bitcast_v12i16_to_v6i32_scalar:1781; GFX9: ; %bb.0:1782; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1783; GFX9-NEXT: s_cmp_lg_u32 s22, 01784; GFX9-NEXT: s_cbranch_scc0 .LBB15_31785; GFX9-NEXT: ; %bb.1: ; %cmp.false1786; GFX9-NEXT: s_cbranch_execnz .LBB15_41787; GFX9-NEXT: .LBB15_2: ; %cmp.true1788; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]1789; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]1790; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]1791; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]1792; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]1793; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1794; GFX9-NEXT: s_setpc_b64 s[30:31]1795; GFX9-NEXT: .LBB15_3:1796; GFX9-NEXT: s_branch .LBB15_21797; GFX9-NEXT: .LBB15_4:1798; GFX9-NEXT: v_mov_b32_e32 v0, s161799; GFX9-NEXT: v_mov_b32_e32 v1, s171800; GFX9-NEXT: v_mov_b32_e32 v2, s181801; GFX9-NEXT: v_mov_b32_e32 v3, s191802; GFX9-NEXT: v_mov_b32_e32 v4, s201803; GFX9-NEXT: v_mov_b32_e32 v5, s211804; GFX9-NEXT: s_setpc_b64 s[30:31]1805;1806; GFX11-LABEL: bitcast_v12i16_to_v6i32_scalar:1807; GFX11: ; %bb.0:1808; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1809; GFX11-NEXT: s_mov_b32 s5, s171810; GFX11-NEXT: s_mov_b32 s4, s161811; GFX11-NEXT: s_cmp_lg_u32 s18, 01812; GFX11-NEXT: s_mov_b32 s6, 01813; GFX11-NEXT: s_cbranch_scc0 .LBB15_31814; GFX11-NEXT: ; %bb.1: ; %Flow1815; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s61816; GFX11-NEXT: s_cbranch_vccnz .LBB15_41817; GFX11-NEXT: .LBB15_2: ; %cmp.true1818; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]1819; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]1820; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]1821; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]1822; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]1823; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]1824; GFX11-NEXT: s_setpc_b64 s[30:31]1825; GFX11-NEXT: .LBB15_3:1826; GFX11-NEXT: s_branch .LBB15_21827; GFX11-NEXT: .LBB15_4:1828; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11829; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31830; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s51831; GFX11-NEXT: s_setpc_b64 s[30:31]1832 %cmp = icmp eq i32 %b, 01833 br i1 %cmp, label %cmp.true, label %cmp.false1834 1835cmp.true:1836 %a1 = add <12 x i16> %a, splat (i16 3)1837 %a2 = bitcast <12 x i16> %a1 to <6 x i32>1838 br label %end1839 1840cmp.false:1841 %a3 = bitcast <12 x i16> %a to <6 x i32>1842 br label %end1843 1844end:1845 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1846 ret <6 x i32> %phi1847}1848 1849define <12 x half> @bitcast_v6i32_to_v12f16(<6 x i32> %a, i32 %b) {1850; SI-LABEL: bitcast_v6i32_to_v12f16:1851; SI: ; %bb.0:1852; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1853; SI-NEXT: v_mov_b32_e32 v17, v51854; SI-NEXT: v_mov_b32_e32 v16, v41855; SI-NEXT: v_mov_b32_e32 v15, v31856; SI-NEXT: v_mov_b32_e32 v14, v21857; SI-NEXT: v_mov_b32_e32 v13, v11858; SI-NEXT: v_mov_b32_e32 v12, v01859; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61860; SI-NEXT: ; implicit-def: $vgpr01861; SI-NEXT: ; implicit-def: $vgpr11862; SI-NEXT: ; implicit-def: $vgpr21863; SI-NEXT: ; implicit-def: $vgpr31864; SI-NEXT: ; implicit-def: $vgpr41865; SI-NEXT: ; implicit-def: $vgpr51866; SI-NEXT: ; implicit-def: $vgpr61867; SI-NEXT: ; implicit-def: $vgpr71868; SI-NEXT: ; implicit-def: $vgpr81869; SI-NEXT: ; implicit-def: $vgpr91870; SI-NEXT: ; implicit-def: $vgpr101871; SI-NEXT: ; implicit-def: $vgpr111872; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1873; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1874; SI-NEXT: s_cbranch_execnz .LBB16_31875; SI-NEXT: ; %bb.1: ; %Flow1876; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1877; SI-NEXT: s_cbranch_execnz .LBB16_41878; SI-NEXT: .LBB16_2: ; %end1879; SI-NEXT: s_or_b64 exec, exec, s[4:5]1880; SI-NEXT: s_setpc_b64 s[30:31]1881; SI-NEXT: .LBB16_3: ; %cmp.false1882; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v171883; SI-NEXT: v_cvt_f32_f16_e32 v11, v01884; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v161885; SI-NEXT: v_cvt_f32_f16_e32 v9, v01886; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v151887; SI-NEXT: v_cvt_f32_f16_e32 v7, v01888; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v141889; SI-NEXT: v_cvt_f32_f16_e32 v5, v01890; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v131891; SI-NEXT: v_cvt_f32_f16_e32 v3, v01892; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v121893; SI-NEXT: v_cvt_f32_f16_e32 v1, v01894; SI-NEXT: v_cvt_f32_f16_e32 v10, v171895; SI-NEXT: v_cvt_f32_f16_e32 v8, v161896; SI-NEXT: v_cvt_f32_f16_e32 v6, v151897; SI-NEXT: v_cvt_f32_f16_e32 v4, v141898; SI-NEXT: v_cvt_f32_f16_e32 v2, v131899; SI-NEXT: v_cvt_f32_f16_e32 v0, v121900; SI-NEXT: ; implicit-def: $vgpr121901; SI-NEXT: ; implicit-def: $vgpr131902; SI-NEXT: ; implicit-def: $vgpr141903; SI-NEXT: ; implicit-def: $vgpr151904; SI-NEXT: ; implicit-def: $vgpr161905; SI-NEXT: ; implicit-def: $vgpr171906; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1907; SI-NEXT: s_cbranch_execz .LBB16_21908; SI-NEXT: .LBB16_4: ; %cmp.true1909; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v121910; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v131911; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v141912; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v151913; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v161914; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v171915; SI-NEXT: v_cvt_f32_f16_e32 v10, v111916; SI-NEXT: v_cvt_f32_f16_e32 v8, v91917; SI-NEXT: v_cvt_f32_f16_e32 v6, v71918; SI-NEXT: v_cvt_f32_f16_e32 v4, v51919; SI-NEXT: v_cvt_f32_f16_e32 v2, v31920; SI-NEXT: v_cvt_f32_f16_e32 v0, v11921; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v111922; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v91923; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v71924; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v51925; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v31926; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11927; SI-NEXT: v_cvt_f32_f16_e32 v11, v111928; SI-NEXT: v_cvt_f32_f16_e32 v9, v91929; SI-NEXT: v_cvt_f32_f16_e32 v7, v71930; SI-NEXT: v_cvt_f32_f16_e32 v5, v51931; SI-NEXT: v_cvt_f32_f16_e32 v3, v31932; SI-NEXT: v_cvt_f32_f16_e32 v1, v11933; SI-NEXT: s_or_b64 exec, exec, s[4:5]1934; SI-NEXT: s_setpc_b64 s[30:31]1935;1936; VI-LABEL: bitcast_v6i32_to_v12f16:1937; VI: ; %bb.0:1938; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1939; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61940; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1941; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1942; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1943; VI-NEXT: ; %bb.1: ; %cmp.true1944; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51945; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41946; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31947; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21948; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11949; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01950; VI-NEXT: ; %bb.2: ; %end1951; VI-NEXT: s_or_b64 exec, exec, s[4:5]1952; VI-NEXT: s_setpc_b64 s[30:31]1953;1954; GFX9-LABEL: bitcast_v6i32_to_v12f16:1955; GFX9: ; %bb.0:1956; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1957; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v61958; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1959; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1960; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1961; GFX9-NEXT: ; %bb.1: ; %cmp.true1962; GFX9-NEXT: v_add_u32_e32 v5, 3, v51963; GFX9-NEXT: v_add_u32_e32 v4, 3, v41964; GFX9-NEXT: v_add_u32_e32 v3, 3, v31965; GFX9-NEXT: v_add_u32_e32 v2, 3, v21966; GFX9-NEXT: v_add_u32_e32 v1, 3, v11967; GFX9-NEXT: v_add_u32_e32 v0, 3, v01968; GFX9-NEXT: ; %bb.2: ; %end1969; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1970; GFX9-NEXT: s_setpc_b64 s[30:31]1971;1972; GFX11-LABEL: bitcast_v6i32_to_v12f16:1973; GFX11: ; %bb.0:1974; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1975; GFX11-NEXT: s_mov_b32 s0, exec_lo1976; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v61977; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01978; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1979; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01980; GFX11-NEXT: ; %bb.1: ; %cmp.true1981; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51982; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41983; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31984; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21985; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11986; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01987; GFX11-NEXT: ; %bb.2: ; %end1988; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01989; GFX11-NEXT: s_setpc_b64 s[30:31]1990 %cmp = icmp eq i32 %b, 01991 br i1 %cmp, label %cmp.true, label %cmp.false1992 1993cmp.true:1994 %a1 = add <6 x i32> %a, splat (i32 3)1995 %a2 = bitcast <6 x i32> %a1 to <12 x half>1996 br label %end1997 1998cmp.false:1999 %a3 = bitcast <6 x i32> %a to <12 x half>2000 br label %end2001 2002end:2003 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2004 ret <12 x half> %phi2005}2006 2007define inreg <12 x half> @bitcast_v6i32_to_v12f16_scalar(<6 x i32> inreg %a, i32 inreg %b) {2008; SI-LABEL: bitcast_v6i32_to_v12f16_scalar:2009; SI: ; %bb.0:2010; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2011; SI-NEXT: s_cmp_lg_u32 s22, 02012; SI-NEXT: s_cbranch_scc0 .LBB17_42013; SI-NEXT: ; %bb.1: ; %cmp.false2014; SI-NEXT: s_lshr_b32 s4, s21, 162015; SI-NEXT: v_cvt_f32_f16_e32 v11, s42016; SI-NEXT: s_lshr_b32 s4, s20, 162017; SI-NEXT: v_cvt_f32_f16_e32 v9, s42018; SI-NEXT: s_lshr_b32 s4, s19, 162019; SI-NEXT: v_cvt_f32_f16_e32 v7, s42020; SI-NEXT: s_lshr_b32 s4, s18, 162021; SI-NEXT: v_cvt_f32_f16_e32 v5, s42022; SI-NEXT: s_lshr_b32 s4, s17, 162023; SI-NEXT: v_cvt_f32_f16_e32 v3, s42024; SI-NEXT: s_lshr_b32 s4, s16, 162025; SI-NEXT: v_cvt_f32_f16_e32 v1, s42026; SI-NEXT: v_cvt_f32_f16_e32 v10, s212027; SI-NEXT: v_cvt_f32_f16_e32 v8, s202028; SI-NEXT: v_cvt_f32_f16_e32 v6, s192029; SI-NEXT: v_cvt_f32_f16_e32 v4, s182030; SI-NEXT: v_cvt_f32_f16_e32 v2, s172031; SI-NEXT: v_cvt_f32_f16_e32 v0, s162032; SI-NEXT: s_cbranch_execnz .LBB17_32033; SI-NEXT: .LBB17_2: ; %cmp.true2034; SI-NEXT: s_add_i32 s21, s21, 32035; SI-NEXT: s_add_i32 s20, s20, 32036; SI-NEXT: s_lshr_b32 s4, s21, 162037; SI-NEXT: s_add_i32 s19, s19, 32038; SI-NEXT: v_cvt_f32_f16_e32 v11, s42039; SI-NEXT: s_lshr_b32 s4, s20, 162040; SI-NEXT: s_add_i32 s18, s18, 32041; SI-NEXT: v_cvt_f32_f16_e32 v9, s42042; SI-NEXT: s_lshr_b32 s4, s19, 162043; SI-NEXT: s_add_i32 s17, s17, 32044; SI-NEXT: v_cvt_f32_f16_e32 v7, s42045; SI-NEXT: s_lshr_b32 s4, s18, 162046; SI-NEXT: s_add_i32 s16, s16, 32047; SI-NEXT: v_cvt_f32_f16_e32 v5, s42048; SI-NEXT: s_lshr_b32 s4, s17, 162049; SI-NEXT: v_cvt_f32_f16_e32 v3, s42050; SI-NEXT: s_lshr_b32 s4, s16, 162051; SI-NEXT: v_cvt_f32_f16_e32 v10, s212052; SI-NEXT: v_cvt_f32_f16_e32 v8, s202053; SI-NEXT: v_cvt_f32_f16_e32 v6, s192054; SI-NEXT: v_cvt_f32_f16_e32 v4, s182055; SI-NEXT: v_cvt_f32_f16_e32 v2, s172056; SI-NEXT: v_cvt_f32_f16_e32 v0, s162057; SI-NEXT: v_cvt_f32_f16_e32 v1, s42058; SI-NEXT: .LBB17_3: ; %end2059; SI-NEXT: s_setpc_b64 s[30:31]2060; SI-NEXT: .LBB17_4:2061; SI-NEXT: ; implicit-def: $vgpr02062; SI-NEXT: ; implicit-def: $vgpr12063; SI-NEXT: ; implicit-def: $vgpr22064; SI-NEXT: ; implicit-def: $vgpr32065; SI-NEXT: ; implicit-def: $vgpr42066; SI-NEXT: ; implicit-def: $vgpr52067; SI-NEXT: ; implicit-def: $vgpr62068; SI-NEXT: ; implicit-def: $vgpr72069; SI-NEXT: ; implicit-def: $vgpr82070; SI-NEXT: ; implicit-def: $vgpr92071; SI-NEXT: ; implicit-def: $vgpr102072; SI-NEXT: ; implicit-def: $vgpr112073; SI-NEXT: s_branch .LBB17_22074;2075; VI-LABEL: bitcast_v6i32_to_v12f16_scalar:2076; VI: ; %bb.0:2077; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2078; VI-NEXT: s_cmp_lg_u32 s22, 02079; VI-NEXT: s_cbranch_scc0 .LBB17_42080; VI-NEXT: ; %bb.1: ; %cmp.false2081; VI-NEXT: s_cbranch_execnz .LBB17_32082; VI-NEXT: .LBB17_2: ; %cmp.true2083; VI-NEXT: s_add_i32 s21, s21, 32084; VI-NEXT: s_add_i32 s20, s20, 32085; VI-NEXT: s_add_i32 s19, s19, 32086; VI-NEXT: s_add_i32 s18, s18, 32087; VI-NEXT: s_add_i32 s17, s17, 32088; VI-NEXT: s_add_i32 s16, s16, 32089; VI-NEXT: .LBB17_3: ; %end2090; VI-NEXT: v_mov_b32_e32 v0, s162091; VI-NEXT: v_mov_b32_e32 v1, s172092; VI-NEXT: v_mov_b32_e32 v2, s182093; VI-NEXT: v_mov_b32_e32 v3, s192094; VI-NEXT: v_mov_b32_e32 v4, s202095; VI-NEXT: v_mov_b32_e32 v5, s212096; VI-NEXT: s_setpc_b64 s[30:31]2097; VI-NEXT: .LBB17_4:2098; VI-NEXT: s_branch .LBB17_22099;2100; GFX9-LABEL: bitcast_v6i32_to_v12f16_scalar:2101; GFX9: ; %bb.0:2102; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2103; GFX9-NEXT: s_cmp_lg_u32 s22, 02104; GFX9-NEXT: s_cbranch_scc0 .LBB17_42105; GFX9-NEXT: ; %bb.1: ; %cmp.false2106; GFX9-NEXT: s_cbranch_execnz .LBB17_32107; GFX9-NEXT: .LBB17_2: ; %cmp.true2108; GFX9-NEXT: s_add_i32 s21, s21, 32109; GFX9-NEXT: s_add_i32 s20, s20, 32110; GFX9-NEXT: s_add_i32 s19, s19, 32111; GFX9-NEXT: s_add_i32 s18, s18, 32112; GFX9-NEXT: s_add_i32 s17, s17, 32113; GFX9-NEXT: s_add_i32 s16, s16, 32114; GFX9-NEXT: .LBB17_3: ; %end2115; GFX9-NEXT: v_mov_b32_e32 v0, s162116; GFX9-NEXT: v_mov_b32_e32 v1, s172117; GFX9-NEXT: v_mov_b32_e32 v2, s182118; GFX9-NEXT: v_mov_b32_e32 v3, s192119; GFX9-NEXT: v_mov_b32_e32 v4, s202120; GFX9-NEXT: v_mov_b32_e32 v5, s212121; GFX9-NEXT: s_setpc_b64 s[30:31]2122; GFX9-NEXT: .LBB17_4:2123; GFX9-NEXT: s_branch .LBB17_22124;2125; GFX11-LABEL: bitcast_v6i32_to_v12f16_scalar:2126; GFX11: ; %bb.0:2127; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2128; GFX11-NEXT: s_cmp_lg_u32 s18, 02129; GFX11-NEXT: s_mov_b32 s4, 02130; GFX11-NEXT: s_cbranch_scc0 .LBB17_42131; GFX11-NEXT: ; %bb.1: ; %Flow2132; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42133; GFX11-NEXT: s_cbranch_vccnz .LBB17_32134; GFX11-NEXT: .LBB17_2: ; %cmp.true2135; GFX11-NEXT: s_add_i32 s17, s17, 32136; GFX11-NEXT: s_add_i32 s16, s16, 32137; GFX11-NEXT: s_add_i32 s3, s3, 32138; GFX11-NEXT: s_add_i32 s2, s2, 32139; GFX11-NEXT: s_add_i32 s1, s1, 32140; GFX11-NEXT: s_add_i32 s0, s0, 32141; GFX11-NEXT: .LBB17_3: ; %end2142; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2143; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12144; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32145; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172146; GFX11-NEXT: s_setpc_b64 s[30:31]2147; GFX11-NEXT: .LBB17_4:2148; GFX11-NEXT: s_branch .LBB17_22149 %cmp = icmp eq i32 %b, 02150 br i1 %cmp, label %cmp.true, label %cmp.false2151 2152cmp.true:2153 %a1 = add <6 x i32> %a, splat (i32 3)2154 %a2 = bitcast <6 x i32> %a1 to <12 x half>2155 br label %end2156 2157cmp.false:2158 %a3 = bitcast <6 x i32> %a to <12 x half>2159 br label %end2160 2161end:2162 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2163 ret <12 x half> %phi2164}2165 2166define <6 x i32> @bitcast_v12f16_to_v6i32(<12 x half> %a, i32 %b) {2167; SI-LABEL: bitcast_v12f16_to_v6i32:2168; SI: ; %bb.0:2169; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2170; SI-NEXT: v_cvt_f16_f32_e32 v20, v12171; SI-NEXT: v_cvt_f16_f32_e32 v19, v02172; SI-NEXT: v_cvt_f16_f32_e32 v18, v32173; SI-NEXT: v_cvt_f16_f32_e32 v17, v22174; SI-NEXT: v_cvt_f16_f32_e32 v16, v52175; SI-NEXT: v_cvt_f16_f32_e32 v15, v42176; SI-NEXT: v_cvt_f16_f32_e32 v14, v72177; SI-NEXT: v_cvt_f16_f32_e32 v13, v62178; SI-NEXT: v_cvt_f16_f32_e32 v9, v92179; SI-NEXT: v_cvt_f16_f32_e32 v8, v82180; SI-NEXT: v_cvt_f16_f32_e32 v7, v112181; SI-NEXT: v_cvt_f16_f32_e32 v6, v102182; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v122183; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr52184; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2185; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2186; SI-NEXT: s_cbranch_execnz .LBB18_32187; SI-NEXT: ; %bb.1: ; %Flow2188; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2189; SI-NEXT: s_cbranch_execnz .LBB18_42190; SI-NEXT: .LBB18_2: ; %end2191; SI-NEXT: s_or_b64 exec, exec, s[4:5]2192; SI-NEXT: s_setpc_b64 s[30:31]2193; SI-NEXT: .LBB18_3: ; %cmp.false2194; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v202195; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v182196; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v162197; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v142198; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v92199; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v72200; SI-NEXT: v_or_b32_e32 v0, v19, v02201; SI-NEXT: v_or_b32_e32 v1, v17, v12202; SI-NEXT: v_or_b32_e32 v2, v15, v22203; SI-NEXT: v_or_b32_e32 v3, v13, v32204; SI-NEXT: v_or_b32_e32 v4, v8, v42205; SI-NEXT: v_or_b32_e32 v5, v6, v52206; SI-NEXT: ; implicit-def: $vgpr202207; SI-NEXT: ; implicit-def: $vgpr192208; SI-NEXT: ; implicit-def: $vgpr182209; SI-NEXT: ; implicit-def: $vgpr172210; SI-NEXT: ; implicit-def: $vgpr162211; SI-NEXT: ; implicit-def: $vgpr152212; SI-NEXT: ; implicit-def: $vgpr142213; SI-NEXT: ; implicit-def: $vgpr132214; SI-NEXT: ; implicit-def: $vgpr92215; SI-NEXT: ; implicit-def: $vgpr82216; SI-NEXT: ; implicit-def: $vgpr72217; SI-NEXT: ; implicit-def: $vgpr62218; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2219; SI-NEXT: s_cbranch_execz .LBB18_22220; SI-NEXT: .LBB18_4: ; %cmp.true2221; SI-NEXT: v_cvt_f32_f16_e32 v0, v202222; SI-NEXT: v_cvt_f32_f16_e32 v1, v192223; SI-NEXT: v_cvt_f32_f16_e32 v2, v182224; SI-NEXT: v_cvt_f32_f16_e32 v3, v172225; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v02226; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v12227; SI-NEXT: v_cvt_f16_f32_e32 v0, v02228; SI-NEXT: v_cvt_f16_f32_e32 v1, v12229; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v22230; SI-NEXT: v_cvt_f16_f32_e32 v2, v22231; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v02232; SI-NEXT: v_or_b32_e32 v0, v1, v02233; SI-NEXT: v_cvt_f32_f16_e32 v1, v162234; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v32235; SI-NEXT: v_cvt_f16_f32_e32 v3, v32236; SI-NEXT: v_cvt_f32_f16_e32 v5, v132237; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v12238; SI-NEXT: v_cvt_f16_f32_e32 v4, v12239; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v22240; SI-NEXT: v_cvt_f32_f16_e32 v2, v152241; SI-NEXT: v_or_b32_e32 v1, v3, v12242; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42243; SI-NEXT: v_cvt_f32_f16_e32 v4, v142244; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v22245; SI-NEXT: v_cvt_f16_f32_e32 v2, v22246; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v52247; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42248; SI-NEXT: v_cvt_f16_f32_e32 v4, v42249; SI-NEXT: v_cvt_f16_f32_e32 v5, v52250; SI-NEXT: v_cvt_f32_f16_e32 v9, v92251; SI-NEXT: v_or_b32_e32 v2, v2, v32252; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42253; SI-NEXT: v_cvt_f32_f16_e32 v4, v82254; SI-NEXT: v_cvt_f32_f16_e32 v7, v72255; SI-NEXT: v_cvt_f32_f16_e32 v6, v62256; SI-NEXT: v_or_b32_e32 v3, v5, v32257; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v92258; SI-NEXT: v_cvt_f16_f32_e32 v5, v52259; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42260; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v72261; SI-NEXT: v_cvt_f16_f32_e32 v4, v42262; SI-NEXT: v_cvt_f16_f32_e32 v7, v72263; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v62264; SI-NEXT: v_cvt_f16_f32_e32 v6, v62265; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52266; SI-NEXT: v_or_b32_e32 v4, v4, v52267; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v72268; SI-NEXT: v_or_b32_e32 v5, v6, v52269; SI-NEXT: s_or_b64 exec, exec, s[4:5]2270; SI-NEXT: s_setpc_b64 s[30:31]2271;2272; VI-LABEL: bitcast_v12f16_to_v6i32:2273; VI: ; %bb.0:2274; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2275; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62276; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2277; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2278; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2279; VI-NEXT: s_cbranch_execz .LBB18_22280; VI-NEXT: ; %bb.1: ; %cmp.true2281; VI-NEXT: v_mov_b32_e32 v6, 0x2002282; VI-NEXT: v_add_f16_sdwa v7, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2283; VI-NEXT: v_add_f16_e32 v5, 0x200, v52284; VI-NEXT: v_or_b32_e32 v5, v5, v72285; VI-NEXT: v_add_f16_sdwa v7, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2286; VI-NEXT: v_add_f16_e32 v4, 0x200, v42287; VI-NEXT: v_or_b32_e32 v4, v4, v72288; VI-NEXT: v_add_f16_sdwa v7, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2289; VI-NEXT: v_add_f16_e32 v3, 0x200, v32290; VI-NEXT: v_or_b32_e32 v3, v3, v72291; VI-NEXT: v_add_f16_sdwa v7, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2292; VI-NEXT: v_add_f16_e32 v2, 0x200, v22293; VI-NEXT: v_or_b32_e32 v2, v2, v72294; VI-NEXT: v_add_f16_sdwa v7, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2295; VI-NEXT: v_add_f16_e32 v1, 0x200, v12296; VI-NEXT: v_add_f16_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2297; VI-NEXT: v_add_f16_e32 v0, 0x200, v02298; VI-NEXT: v_or_b32_e32 v1, v1, v72299; VI-NEXT: v_or_b32_e32 v0, v0, v62300; VI-NEXT: .LBB18_2: ; %end2301; VI-NEXT: s_or_b64 exec, exec, s[4:5]2302; VI-NEXT: s_setpc_b64 s[30:31]2303;2304; GFX9-LABEL: bitcast_v12f16_to_v6i32:2305; GFX9: ; %bb.0:2306; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2307; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62308; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2309; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2310; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2311; GFX9-NEXT: ; %bb.1: ; %cmp.true2312; GFX9-NEXT: s_movk_i32 s6, 0x2002313; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]2314; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]2315; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]2316; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]2317; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]2318; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]2319; GFX9-NEXT: ; %bb.2: ; %end2320; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2321; GFX9-NEXT: s_setpc_b64 s[30:31]2322;2323; GFX11-LABEL: bitcast_v12f16_to_v6i32:2324; GFX11: ; %bb.0:2325; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2326; GFX11-NEXT: s_mov_b32 s0, exec_lo2327; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v62328; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02329; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2330; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02331; GFX11-NEXT: ; %bb.1: ; %cmp.true2332; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]2333; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]2334; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]2335; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]2336; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]2337; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]2338; GFX11-NEXT: ; %bb.2: ; %end2339; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02340; GFX11-NEXT: s_setpc_b64 s[30:31]2341 %cmp = icmp eq i32 %b, 02342 br i1 %cmp, label %cmp.true, label %cmp.false2343 2344cmp.true:2345 %a1 = fadd <12 x half> %a, splat (half 0xH0200)2346 %a2 = bitcast <12 x half> %a1 to <6 x i32>2347 br label %end2348 2349cmp.false:2350 %a3 = bitcast <12 x half> %a to <6 x i32>2351 br label %end2352 2353end:2354 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2355 ret <6 x i32> %phi2356}2357 2358define inreg <6 x i32> @bitcast_v12f16_to_v6i32_scalar(<12 x half> inreg %a, i32 inreg %b) {2359; SI-LABEL: bitcast_v12f16_to_v6i32_scalar:2360; SI: ; %bb.0:2361; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2362; SI-NEXT: v_cvt_f16_f32_e32 v17, s172363; SI-NEXT: v_cvt_f16_f32_e32 v16, s162364; SI-NEXT: v_cvt_f16_f32_e32 v15, s192365; SI-NEXT: v_cvt_f16_f32_e32 v14, s182366; SI-NEXT: v_cvt_f16_f32_e32 v13, s212367; SI-NEXT: v_cvt_f16_f32_e32 v12, s202368; SI-NEXT: v_cvt_f16_f32_e32 v11, s232369; SI-NEXT: v_cvt_f16_f32_e32 v10, s222370; SI-NEXT: v_cvt_f16_f32_e32 v9, s252371; SI-NEXT: v_cvt_f16_f32_e32 v8, s242372; SI-NEXT: v_cvt_f16_f32_e32 v7, s272373; SI-NEXT: v_cvt_f16_f32_e32 v6, s262374; SI-NEXT: s_cmp_lg_u32 s28, 02375; SI-NEXT: s_cbranch_scc0 .LBB19_42376; SI-NEXT: ; %bb.1: ; %cmp.false2377; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v172378; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v152379; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v132380; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v112381; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v92382; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v72383; SI-NEXT: v_or_b32_e32 v0, v16, v02384; SI-NEXT: v_or_b32_e32 v1, v14, v12385; SI-NEXT: v_or_b32_e32 v2, v12, v22386; SI-NEXT: v_or_b32_e32 v3, v10, v32387; SI-NEXT: v_or_b32_e32 v4, v8, v42388; SI-NEXT: v_or_b32_e32 v5, v6, v52389; SI-NEXT: s_cbranch_execnz .LBB19_32390; SI-NEXT: .LBB19_2: ; %cmp.true2391; SI-NEXT: v_cvt_f32_f16_e32 v0, v172392; SI-NEXT: v_cvt_f32_f16_e32 v1, v162393; SI-NEXT: v_cvt_f32_f16_e32 v2, v152394; SI-NEXT: v_cvt_f32_f16_e32 v3, v142395; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v02396; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v12397; SI-NEXT: v_cvt_f16_f32_e32 v0, v02398; SI-NEXT: v_cvt_f16_f32_e32 v1, v12399; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v22400; SI-NEXT: v_cvt_f16_f32_e32 v2, v22401; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v02402; SI-NEXT: v_or_b32_e32 v0, v1, v02403; SI-NEXT: v_cvt_f32_f16_e32 v1, v132404; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v32405; SI-NEXT: v_cvt_f16_f32_e32 v3, v32406; SI-NEXT: v_cvt_f32_f16_e32 v5, v102407; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v12408; SI-NEXT: v_cvt_f16_f32_e32 v4, v12409; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v22410; SI-NEXT: v_cvt_f32_f16_e32 v2, v122411; SI-NEXT: v_or_b32_e32 v1, v3, v12412; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42413; SI-NEXT: v_cvt_f32_f16_e32 v4, v112414; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v22415; SI-NEXT: v_cvt_f16_f32_e32 v2, v22416; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v52417; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42418; SI-NEXT: v_cvt_f16_f32_e32 v4, v42419; SI-NEXT: v_cvt_f16_f32_e32 v5, v52420; SI-NEXT: v_cvt_f32_f16_e32 v9, v92421; SI-NEXT: v_or_b32_e32 v2, v2, v32422; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42423; SI-NEXT: v_cvt_f32_f16_e32 v4, v82424; SI-NEXT: v_cvt_f32_f16_e32 v7, v72425; SI-NEXT: v_cvt_f32_f16_e32 v6, v62426; SI-NEXT: v_or_b32_e32 v3, v5, v32427; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v92428; SI-NEXT: v_cvt_f16_f32_e32 v5, v52429; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42430; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v72431; SI-NEXT: v_cvt_f16_f32_e32 v4, v42432; SI-NEXT: v_cvt_f16_f32_e32 v7, v72433; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v62434; SI-NEXT: v_cvt_f16_f32_e32 v6, v62435; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52436; SI-NEXT: v_or_b32_e32 v4, v4, v52437; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v72438; SI-NEXT: v_or_b32_e32 v5, v6, v52439; SI-NEXT: .LBB19_3: ; %end2440; SI-NEXT: s_setpc_b64 s[30:31]2441; SI-NEXT: .LBB19_4:2442; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr52443; SI-NEXT: s_branch .LBB19_22444;2445; VI-LABEL: bitcast_v12f16_to_v6i32_scalar:2446; VI: ; %bb.0:2447; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2448; VI-NEXT: s_cmp_lg_u32 s22, 02449; VI-NEXT: s_cbranch_scc0 .LBB19_32450; VI-NEXT: ; %bb.1: ; %cmp.false2451; VI-NEXT: s_cbranch_execnz .LBB19_42452; VI-NEXT: .LBB19_2: ; %cmp.true2453; VI-NEXT: s_lshr_b32 s4, s21, 162454; VI-NEXT: v_mov_b32_e32 v0, 0x2002455; VI-NEXT: v_mov_b32_e32 v1, s42456; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2457; VI-NEXT: v_add_f16_e32 v2, s21, v02458; VI-NEXT: s_lshr_b32 s4, s20, 162459; VI-NEXT: v_or_b32_e32 v5, v2, v12460; VI-NEXT: v_mov_b32_e32 v1, s42461; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2462; VI-NEXT: v_add_f16_e32 v2, s20, v02463; VI-NEXT: s_lshr_b32 s4, s19, 162464; VI-NEXT: v_or_b32_e32 v4, v2, v12465; VI-NEXT: v_mov_b32_e32 v1, s42466; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2467; VI-NEXT: v_add_f16_e32 v2, s19, v02468; VI-NEXT: s_lshr_b32 s4, s18, 162469; VI-NEXT: v_or_b32_e32 v3, v2, v12470; VI-NEXT: v_mov_b32_e32 v1, s42471; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2472; VI-NEXT: v_add_f16_e32 v2, s18, v02473; VI-NEXT: s_lshr_b32 s4, s17, 162474; VI-NEXT: v_or_b32_e32 v2, v2, v12475; VI-NEXT: v_mov_b32_e32 v1, s42476; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2477; VI-NEXT: v_add_f16_e32 v6, s17, v02478; VI-NEXT: s_lshr_b32 s4, s16, 162479; VI-NEXT: v_or_b32_e32 v1, v6, v12480; VI-NEXT: v_mov_b32_e32 v6, s42481; VI-NEXT: v_add_f16_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2482; VI-NEXT: v_add_f16_e32 v0, s16, v02483; VI-NEXT: v_or_b32_e32 v0, v0, v62484; VI-NEXT: s_setpc_b64 s[30:31]2485; VI-NEXT: .LBB19_3:2486; VI-NEXT: s_branch .LBB19_22487; VI-NEXT: .LBB19_4:2488; VI-NEXT: v_mov_b32_e32 v0, s162489; VI-NEXT: v_mov_b32_e32 v1, s172490; VI-NEXT: v_mov_b32_e32 v2, s182491; VI-NEXT: v_mov_b32_e32 v3, s192492; VI-NEXT: v_mov_b32_e32 v4, s202493; VI-NEXT: v_mov_b32_e32 v5, s212494; VI-NEXT: s_setpc_b64 s[30:31]2495;2496; GFX9-LABEL: bitcast_v12f16_to_v6i32_scalar:2497; GFX9: ; %bb.0:2498; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2499; GFX9-NEXT: s_cmp_lg_u32 s22, 02500; GFX9-NEXT: s_cbranch_scc0 .LBB19_32501; GFX9-NEXT: ; %bb.1: ; %cmp.false2502; GFX9-NEXT: s_cbranch_execnz .LBB19_42503; GFX9-NEXT: .LBB19_2: ; %cmp.true2504; GFX9-NEXT: v_mov_b32_e32 v0, 0x2002505; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]2506; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]2507; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]2508; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]2509; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]2510; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]2511; GFX9-NEXT: s_setpc_b64 s[30:31]2512; GFX9-NEXT: .LBB19_3:2513; GFX9-NEXT: s_branch .LBB19_22514; GFX9-NEXT: .LBB19_4:2515; GFX9-NEXT: v_mov_b32_e32 v0, s162516; GFX9-NEXT: v_mov_b32_e32 v1, s172517; GFX9-NEXT: v_mov_b32_e32 v2, s182518; GFX9-NEXT: v_mov_b32_e32 v3, s192519; GFX9-NEXT: v_mov_b32_e32 v4, s202520; GFX9-NEXT: v_mov_b32_e32 v5, s212521; GFX9-NEXT: s_setpc_b64 s[30:31]2522;2523; GFX11-LABEL: bitcast_v12f16_to_v6i32_scalar:2524; GFX11: ; %bb.0:2525; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2526; GFX11-NEXT: s_mov_b32 s5, s172527; GFX11-NEXT: s_mov_b32 s4, s162528; GFX11-NEXT: s_cmp_lg_u32 s18, 02529; GFX11-NEXT: s_mov_b32 s6, 02530; GFX11-NEXT: s_cbranch_scc0 .LBB19_32531; GFX11-NEXT: ; %bb.1: ; %Flow2532; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s62533; GFX11-NEXT: s_cbranch_vccnz .LBB19_42534; GFX11-NEXT: .LBB19_2: ; %cmp.true2535; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]2536; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]2537; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]2538; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]2539; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]2540; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]2541; GFX11-NEXT: s_setpc_b64 s[30:31]2542; GFX11-NEXT: .LBB19_3:2543; GFX11-NEXT: s_branch .LBB19_22544; GFX11-NEXT: .LBB19_4:2545; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12546; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32547; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52548; GFX11-NEXT: s_setpc_b64 s[30:31]2549 %cmp = icmp eq i32 %b, 02550 br i1 %cmp, label %cmp.true, label %cmp.false2551 2552cmp.true:2553 %a1 = fadd <12 x half> %a, splat (half 0xH0200)2554 %a2 = bitcast <12 x half> %a1 to <6 x i32>2555 br label %end2556 2557cmp.false:2558 %a3 = bitcast <12 x half> %a to <6 x i32>2559 br label %end2560 2561end:2562 %phi = phi <6 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2563 ret <6 x i32> %phi2564}2565 2566define <3 x i64> @bitcast_v6f32_to_v3i64(<6 x float> %a, i32 %b) {2567; SI-LABEL: bitcast_v6f32_to_v3i64:2568; SI: ; %bb.0:2569; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2570; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62571; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2572; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2573; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2574; SI-NEXT: ; %bb.1: ; %cmp.true2575; SI-NEXT: v_add_f32_e32 v5, 1.0, v52576; SI-NEXT: v_add_f32_e32 v4, 1.0, v42577; SI-NEXT: v_add_f32_e32 v3, 1.0, v32578; SI-NEXT: v_add_f32_e32 v2, 1.0, v22579; SI-NEXT: v_add_f32_e32 v1, 1.0, v12580; SI-NEXT: v_add_f32_e32 v0, 1.0, v02581; SI-NEXT: ; %bb.2: ; %end2582; SI-NEXT: s_or_b64 exec, exec, s[4:5]2583; SI-NEXT: s_setpc_b64 s[30:31]2584;2585; VI-LABEL: bitcast_v6f32_to_v3i64:2586; VI: ; %bb.0:2587; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2588; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62589; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2590; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2591; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2592; VI-NEXT: ; %bb.1: ; %cmp.true2593; VI-NEXT: v_add_f32_e32 v5, 1.0, v52594; VI-NEXT: v_add_f32_e32 v4, 1.0, v42595; VI-NEXT: v_add_f32_e32 v3, 1.0, v32596; VI-NEXT: v_add_f32_e32 v2, 1.0, v22597; VI-NEXT: v_add_f32_e32 v1, 1.0, v12598; VI-NEXT: v_add_f32_e32 v0, 1.0, v02599; VI-NEXT: ; %bb.2: ; %end2600; VI-NEXT: s_or_b64 exec, exec, s[4:5]2601; VI-NEXT: s_setpc_b64 s[30:31]2602;2603; GFX9-LABEL: bitcast_v6f32_to_v3i64:2604; GFX9: ; %bb.0:2605; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2606; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62607; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2608; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2609; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2610; GFX9-NEXT: ; %bb.1: ; %cmp.true2611; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v52612; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v42613; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v32614; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v22615; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v12616; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v02617; GFX9-NEXT: ; %bb.2: ; %end2618; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2619; GFX9-NEXT: s_setpc_b64 s[30:31]2620;2621; GFX11-LABEL: bitcast_v6f32_to_v3i64:2622; GFX11: ; %bb.0:2623; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2624; GFX11-NEXT: s_mov_b32 s0, exec_lo2625; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v62626; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02627; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2628; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02629; GFX11-NEXT: ; %bb.1: ; %cmp.true2630; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v42631; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v22632; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v02633; GFX11-NEXT: ; %bb.2: ; %end2634; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02635; GFX11-NEXT: s_setpc_b64 s[30:31]2636 %cmp = icmp eq i32 %b, 02637 br i1 %cmp, label %cmp.true, label %cmp.false2638 2639cmp.true:2640 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)2641 %a2 = bitcast <6 x float> %a1 to <3 x i64>2642 br label %end2643 2644cmp.false:2645 %a3 = bitcast <6 x float> %a to <3 x i64>2646 br label %end2647 2648end:2649 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2650 ret <3 x i64> %phi2651}2652 2653define inreg <3 x i64> @bitcast_v6f32_to_v3i64_scalar(<6 x float> inreg %a, i32 inreg %b) {2654; SI-LABEL: bitcast_v6f32_to_v3i64_scalar:2655; SI: ; %bb.0:2656; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2657; SI-NEXT: s_cmp_lg_u32 s22, 02658; SI-NEXT: s_cbranch_scc0 .LBB21_32659; SI-NEXT: ; %bb.1: ; %cmp.false2660; SI-NEXT: s_cbranch_execnz .LBB21_42661; SI-NEXT: .LBB21_2: ; %cmp.true2662; SI-NEXT: v_add_f32_e64 v5, s21, 1.02663; SI-NEXT: v_add_f32_e64 v4, s20, 1.02664; SI-NEXT: v_add_f32_e64 v3, s19, 1.02665; SI-NEXT: v_add_f32_e64 v2, s18, 1.02666; SI-NEXT: v_add_f32_e64 v1, s17, 1.02667; SI-NEXT: v_add_f32_e64 v0, s16, 1.02668; SI-NEXT: s_setpc_b64 s[30:31]2669; SI-NEXT: .LBB21_3:2670; SI-NEXT: s_branch .LBB21_22671; SI-NEXT: .LBB21_4:2672; SI-NEXT: v_mov_b32_e32 v0, s162673; SI-NEXT: v_mov_b32_e32 v1, s172674; SI-NEXT: v_mov_b32_e32 v2, s182675; SI-NEXT: v_mov_b32_e32 v3, s192676; SI-NEXT: v_mov_b32_e32 v4, s202677; SI-NEXT: v_mov_b32_e32 v5, s212678; SI-NEXT: s_setpc_b64 s[30:31]2679;2680; VI-LABEL: bitcast_v6f32_to_v3i64_scalar:2681; VI: ; %bb.0:2682; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2683; VI-NEXT: s_cmp_lg_u32 s22, 02684; VI-NEXT: s_cbranch_scc0 .LBB21_32685; VI-NEXT: ; %bb.1: ; %cmp.false2686; VI-NEXT: s_cbranch_execnz .LBB21_42687; VI-NEXT: .LBB21_2: ; %cmp.true2688; VI-NEXT: v_add_f32_e64 v5, s21, 1.02689; VI-NEXT: v_add_f32_e64 v4, s20, 1.02690; VI-NEXT: v_add_f32_e64 v3, s19, 1.02691; VI-NEXT: v_add_f32_e64 v2, s18, 1.02692; VI-NEXT: v_add_f32_e64 v1, s17, 1.02693; VI-NEXT: v_add_f32_e64 v0, s16, 1.02694; VI-NEXT: s_setpc_b64 s[30:31]2695; VI-NEXT: .LBB21_3:2696; VI-NEXT: s_branch .LBB21_22697; VI-NEXT: .LBB21_4:2698; VI-NEXT: v_mov_b32_e32 v0, s162699; VI-NEXT: v_mov_b32_e32 v1, s172700; VI-NEXT: v_mov_b32_e32 v2, s182701; VI-NEXT: v_mov_b32_e32 v3, s192702; VI-NEXT: v_mov_b32_e32 v4, s202703; VI-NEXT: v_mov_b32_e32 v5, s212704; VI-NEXT: s_setpc_b64 s[30:31]2705;2706; GFX9-LABEL: bitcast_v6f32_to_v3i64_scalar:2707; GFX9: ; %bb.0:2708; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2709; GFX9-NEXT: s_cmp_lg_u32 s22, 02710; GFX9-NEXT: s_cbranch_scc0 .LBB21_32711; GFX9-NEXT: ; %bb.1: ; %cmp.false2712; GFX9-NEXT: s_cbranch_execnz .LBB21_42713; GFX9-NEXT: .LBB21_2: ; %cmp.true2714; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.02715; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.02716; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.02717; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.02718; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.02719; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.02720; GFX9-NEXT: s_setpc_b64 s[30:31]2721; GFX9-NEXT: .LBB21_3:2722; GFX9-NEXT: s_branch .LBB21_22723; GFX9-NEXT: .LBB21_4:2724; GFX9-NEXT: v_mov_b32_e32 v0, s162725; GFX9-NEXT: v_mov_b32_e32 v1, s172726; GFX9-NEXT: v_mov_b32_e32 v2, s182727; GFX9-NEXT: v_mov_b32_e32 v3, s192728; GFX9-NEXT: v_mov_b32_e32 v4, s202729; GFX9-NEXT: v_mov_b32_e32 v5, s212730; GFX9-NEXT: s_setpc_b64 s[30:31]2731;2732; GFX11-LABEL: bitcast_v6f32_to_v3i64_scalar:2733; GFX11: ; %bb.0:2734; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2735; GFX11-NEXT: s_mov_b32 s5, s172736; GFX11-NEXT: s_mov_b32 s4, s162737; GFX11-NEXT: s_cmp_lg_u32 s18, 02738; GFX11-NEXT: s_mov_b32 s6, 02739; GFX11-NEXT: s_cbranch_scc0 .LBB21_32740; GFX11-NEXT: ; %bb.1: ; %Flow2741; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s62742; GFX11-NEXT: s_cbranch_vccnz .LBB21_42743; GFX11-NEXT: .LBB21_2: ; %cmp.true2744; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.02745; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.02746; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.02747; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.02748; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.02749; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.02750; GFX11-NEXT: s_setpc_b64 s[30:31]2751; GFX11-NEXT: .LBB21_3:2752; GFX11-NEXT: s_branch .LBB21_22753; GFX11-NEXT: .LBB21_4:2754; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12755; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32756; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52757; GFX11-NEXT: s_setpc_b64 s[30:31]2758 %cmp = icmp eq i32 %b, 02759 br i1 %cmp, label %cmp.true, label %cmp.false2760 2761cmp.true:2762 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)2763 %a2 = bitcast <6 x float> %a1 to <3 x i64>2764 br label %end2765 2766cmp.false:2767 %a3 = bitcast <6 x float> %a to <3 x i64>2768 br label %end2769 2770end:2771 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2772 ret <3 x i64> %phi2773}2774 2775define <6 x float> @bitcast_v3i64_to_v6f32(<3 x i64> %a, i32 %b) {2776; SI-LABEL: bitcast_v3i64_to_v6f32:2777; SI: ; %bb.0:2778; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2779; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62780; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2781; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2782; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2783; SI-NEXT: ; %bb.1: ; %cmp.true2784; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v42785; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2786; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v22787; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2788; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v02789; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2790; SI-NEXT: ; %bb.2: ; %end2791; SI-NEXT: s_or_b64 exec, exec, s[4:5]2792; SI-NEXT: s_setpc_b64 s[30:31]2793;2794; VI-LABEL: bitcast_v3i64_to_v6f32:2795; VI: ; %bb.0:2796; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2797; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62798; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2799; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2800; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2801; VI-NEXT: ; %bb.1: ; %cmp.true2802; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v42803; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc2804; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v22805; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc2806; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v02807; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc2808; VI-NEXT: ; %bb.2: ; %end2809; VI-NEXT: s_or_b64 exec, exec, s[4:5]2810; VI-NEXT: s_setpc_b64 s[30:31]2811;2812; GFX9-LABEL: bitcast_v3i64_to_v6f32:2813; GFX9: ; %bb.0:2814; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2815; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62816; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2817; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2818; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2819; GFX9-NEXT: ; %bb.1: ; %cmp.true2820; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v42821; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc2822; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v22823; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc2824; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v02825; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc2826; GFX9-NEXT: ; %bb.2: ; %end2827; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2828; GFX9-NEXT: s_setpc_b64 s[30:31]2829;2830; GFX11-LABEL: bitcast_v3i64_to_v6f32:2831; GFX11: ; %bb.0:2832; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2833; GFX11-NEXT: s_mov_b32 s0, exec_lo2834; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v62835; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02836; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2837; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02838; GFX11-NEXT: ; %bb.1: ; %cmp.true2839; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 32840; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)2841; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo2842; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 32843; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo2844; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 32845; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)2846; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo2847; GFX11-NEXT: ; %bb.2: ; %end2848; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02849; GFX11-NEXT: s_setpc_b64 s[30:31]2850 %cmp = icmp eq i32 %b, 02851 br i1 %cmp, label %cmp.true, label %cmp.false2852 2853cmp.true:2854 %a1 = add <3 x i64> %a, splat (i64 3)2855 %a2 = bitcast <3 x i64> %a1 to <6 x float>2856 br label %end2857 2858cmp.false:2859 %a3 = bitcast <3 x i64> %a to <6 x float>2860 br label %end2861 2862end:2863 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2864 ret <6 x float> %phi2865}2866 2867define inreg <6 x float> @bitcast_v3i64_to_v6f32_scalar(<3 x i64> inreg %a, i32 inreg %b) {2868; SI-LABEL: bitcast_v3i64_to_v6f32_scalar:2869; SI: ; %bb.0:2870; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2871; SI-NEXT: s_cmp_lg_u32 s22, 02872; SI-NEXT: s_cbranch_scc0 .LBB23_42873; SI-NEXT: ; %bb.1: ; %cmp.false2874; SI-NEXT: s_cbranch_execnz .LBB23_32875; SI-NEXT: .LBB23_2: ; %cmp.true2876; SI-NEXT: s_add_u32 s20, s20, 32877; SI-NEXT: s_addc_u32 s21, s21, 02878; SI-NEXT: s_add_u32 s18, s18, 32879; SI-NEXT: s_addc_u32 s19, s19, 02880; SI-NEXT: s_add_u32 s16, s16, 32881; SI-NEXT: s_addc_u32 s17, s17, 02882; SI-NEXT: .LBB23_3: ; %end2883; SI-NEXT: v_mov_b32_e32 v0, s162884; SI-NEXT: v_mov_b32_e32 v1, s172885; SI-NEXT: v_mov_b32_e32 v2, s182886; SI-NEXT: v_mov_b32_e32 v3, s192887; SI-NEXT: v_mov_b32_e32 v4, s202888; SI-NEXT: v_mov_b32_e32 v5, s212889; SI-NEXT: s_setpc_b64 s[30:31]2890; SI-NEXT: .LBB23_4:2891; SI-NEXT: s_branch .LBB23_22892;2893; VI-LABEL: bitcast_v3i64_to_v6f32_scalar:2894; VI: ; %bb.0:2895; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2896; VI-NEXT: s_cmp_lg_u32 s22, 02897; VI-NEXT: s_cbranch_scc0 .LBB23_42898; VI-NEXT: ; %bb.1: ; %cmp.false2899; VI-NEXT: s_cbranch_execnz .LBB23_32900; VI-NEXT: .LBB23_2: ; %cmp.true2901; VI-NEXT: s_add_u32 s20, s20, 32902; VI-NEXT: s_addc_u32 s21, s21, 02903; VI-NEXT: s_add_u32 s18, s18, 32904; VI-NEXT: s_addc_u32 s19, s19, 02905; VI-NEXT: s_add_u32 s16, s16, 32906; VI-NEXT: s_addc_u32 s17, s17, 02907; VI-NEXT: .LBB23_3: ; %end2908; VI-NEXT: v_mov_b32_e32 v0, s162909; VI-NEXT: v_mov_b32_e32 v1, s172910; VI-NEXT: v_mov_b32_e32 v2, s182911; VI-NEXT: v_mov_b32_e32 v3, s192912; VI-NEXT: v_mov_b32_e32 v4, s202913; VI-NEXT: v_mov_b32_e32 v5, s212914; VI-NEXT: s_setpc_b64 s[30:31]2915; VI-NEXT: .LBB23_4:2916; VI-NEXT: s_branch .LBB23_22917;2918; GFX9-LABEL: bitcast_v3i64_to_v6f32_scalar:2919; GFX9: ; %bb.0:2920; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2921; GFX9-NEXT: s_cmp_lg_u32 s22, 02922; GFX9-NEXT: s_cbranch_scc0 .LBB23_42923; GFX9-NEXT: ; %bb.1: ; %cmp.false2924; GFX9-NEXT: s_cbranch_execnz .LBB23_32925; GFX9-NEXT: .LBB23_2: ; %cmp.true2926; GFX9-NEXT: s_add_u32 s20, s20, 32927; GFX9-NEXT: s_addc_u32 s21, s21, 02928; GFX9-NEXT: s_add_u32 s18, s18, 32929; GFX9-NEXT: s_addc_u32 s19, s19, 02930; GFX9-NEXT: s_add_u32 s16, s16, 32931; GFX9-NEXT: s_addc_u32 s17, s17, 02932; GFX9-NEXT: .LBB23_3: ; %end2933; GFX9-NEXT: v_mov_b32_e32 v0, s162934; GFX9-NEXT: v_mov_b32_e32 v1, s172935; GFX9-NEXT: v_mov_b32_e32 v2, s182936; GFX9-NEXT: v_mov_b32_e32 v3, s192937; GFX9-NEXT: v_mov_b32_e32 v4, s202938; GFX9-NEXT: v_mov_b32_e32 v5, s212939; GFX9-NEXT: s_setpc_b64 s[30:31]2940; GFX9-NEXT: .LBB23_4:2941; GFX9-NEXT: s_branch .LBB23_22942;2943; GFX11-LABEL: bitcast_v3i64_to_v6f32_scalar:2944; GFX11: ; %bb.0:2945; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2946; GFX11-NEXT: s_cmp_lg_u32 s18, 02947; GFX11-NEXT: s_mov_b32 s4, 02948; GFX11-NEXT: s_cbranch_scc0 .LBB23_42949; GFX11-NEXT: ; %bb.1: ; %Flow2950; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s42951; GFX11-NEXT: s_cbranch_vccnz .LBB23_32952; GFX11-NEXT: .LBB23_2: ; %cmp.true2953; GFX11-NEXT: s_add_u32 s16, s16, 32954; GFX11-NEXT: s_addc_u32 s17, s17, 02955; GFX11-NEXT: s_add_u32 s2, s2, 32956; GFX11-NEXT: s_addc_u32 s3, s3, 02957; GFX11-NEXT: s_add_u32 s0, s0, 32958; GFX11-NEXT: s_addc_u32 s1, s1, 02959; GFX11-NEXT: .LBB23_3: ; %end2960; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2961; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12962; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32963; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172964; GFX11-NEXT: s_setpc_b64 s[30:31]2965; GFX11-NEXT: .LBB23_4:2966; GFX11-NEXT: s_branch .LBB23_22967 %cmp = icmp eq i32 %b, 02968 br i1 %cmp, label %cmp.true, label %cmp.false2969 2970cmp.true:2971 %a1 = add <3 x i64> %a, splat (i64 3)2972 %a2 = bitcast <3 x i64> %a1 to <6 x float>2973 br label %end2974 2975cmp.false:2976 %a3 = bitcast <3 x i64> %a to <6 x float>2977 br label %end2978 2979end:2980 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2981 ret <6 x float> %phi2982}2983 2984define <3 x double> @bitcast_v6f32_to_v3f64(<6 x float> %a, i32 %b) {2985; SI-LABEL: bitcast_v6f32_to_v3f64:2986; SI: ; %bb.0:2987; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2988; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v62989; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2990; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2991; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2992; SI-NEXT: ; %bb.1: ; %cmp.true2993; SI-NEXT: v_add_f32_e32 v5, 1.0, v52994; SI-NEXT: v_add_f32_e32 v4, 1.0, v42995; SI-NEXT: v_add_f32_e32 v3, 1.0, v32996; SI-NEXT: v_add_f32_e32 v2, 1.0, v22997; SI-NEXT: v_add_f32_e32 v1, 1.0, v12998; SI-NEXT: v_add_f32_e32 v0, 1.0, v02999; SI-NEXT: ; %bb.2: ; %end3000; SI-NEXT: s_or_b64 exec, exec, s[4:5]3001; SI-NEXT: s_setpc_b64 s[30:31]3002;3003; VI-LABEL: bitcast_v6f32_to_v3f64:3004; VI: ; %bb.0:3005; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3006; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63007; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3008; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3009; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3010; VI-NEXT: ; %bb.1: ; %cmp.true3011; VI-NEXT: v_add_f32_e32 v5, 1.0, v53012; VI-NEXT: v_add_f32_e32 v4, 1.0, v43013; VI-NEXT: v_add_f32_e32 v3, 1.0, v33014; VI-NEXT: v_add_f32_e32 v2, 1.0, v23015; VI-NEXT: v_add_f32_e32 v1, 1.0, v13016; VI-NEXT: v_add_f32_e32 v0, 1.0, v03017; VI-NEXT: ; %bb.2: ; %end3018; VI-NEXT: s_or_b64 exec, exec, s[4:5]3019; VI-NEXT: s_setpc_b64 s[30:31]3020;3021; GFX9-LABEL: bitcast_v6f32_to_v3f64:3022; GFX9: ; %bb.0:3023; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3024; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63025; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3026; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3027; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3028; GFX9-NEXT: ; %bb.1: ; %cmp.true3029; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v53030; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v43031; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v33032; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v23033; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v13034; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v03035; GFX9-NEXT: ; %bb.2: ; %end3036; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3037; GFX9-NEXT: s_setpc_b64 s[30:31]3038;3039; GFX11-LABEL: bitcast_v6f32_to_v3f64:3040; GFX11: ; %bb.0:3041; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3042; GFX11-NEXT: s_mov_b32 s0, exec_lo3043; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v63044; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03045; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3046; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03047; GFX11-NEXT: ; %bb.1: ; %cmp.true3048; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v43049; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v23050; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v03051; GFX11-NEXT: ; %bb.2: ; %end3052; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03053; GFX11-NEXT: s_setpc_b64 s[30:31]3054 %cmp = icmp eq i32 %b, 03055 br i1 %cmp, label %cmp.true, label %cmp.false3056 3057cmp.true:3058 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)3059 %a2 = bitcast <6 x float> %a1 to <3 x double>3060 br label %end3061 3062cmp.false:3063 %a3 = bitcast <6 x float> %a to <3 x double>3064 br label %end3065 3066end:3067 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3068 ret <3 x double> %phi3069}3070 3071define inreg <3 x double> @bitcast_v6f32_to_v3f64_scalar(<6 x float> inreg %a, i32 inreg %b) {3072; SI-LABEL: bitcast_v6f32_to_v3f64_scalar:3073; SI: ; %bb.0:3074; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3075; SI-NEXT: s_cmp_lg_u32 s22, 03076; SI-NEXT: s_cbranch_scc0 .LBB25_33077; SI-NEXT: ; %bb.1: ; %cmp.false3078; SI-NEXT: s_cbranch_execnz .LBB25_43079; SI-NEXT: .LBB25_2: ; %cmp.true3080; SI-NEXT: v_add_f32_e64 v5, s21, 1.03081; SI-NEXT: v_add_f32_e64 v4, s20, 1.03082; SI-NEXT: v_add_f32_e64 v3, s19, 1.03083; SI-NEXT: v_add_f32_e64 v2, s18, 1.03084; SI-NEXT: v_add_f32_e64 v1, s17, 1.03085; SI-NEXT: v_add_f32_e64 v0, s16, 1.03086; SI-NEXT: s_setpc_b64 s[30:31]3087; SI-NEXT: .LBB25_3:3088; SI-NEXT: s_branch .LBB25_23089; SI-NEXT: .LBB25_4:3090; SI-NEXT: v_mov_b32_e32 v0, s163091; SI-NEXT: v_mov_b32_e32 v1, s173092; SI-NEXT: v_mov_b32_e32 v2, s183093; SI-NEXT: v_mov_b32_e32 v3, s193094; SI-NEXT: v_mov_b32_e32 v4, s203095; SI-NEXT: v_mov_b32_e32 v5, s213096; SI-NEXT: s_setpc_b64 s[30:31]3097;3098; VI-LABEL: bitcast_v6f32_to_v3f64_scalar:3099; VI: ; %bb.0:3100; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3101; VI-NEXT: s_cmp_lg_u32 s22, 03102; VI-NEXT: s_cbranch_scc0 .LBB25_33103; VI-NEXT: ; %bb.1: ; %cmp.false3104; VI-NEXT: s_cbranch_execnz .LBB25_43105; VI-NEXT: .LBB25_2: ; %cmp.true3106; VI-NEXT: v_add_f32_e64 v5, s21, 1.03107; VI-NEXT: v_add_f32_e64 v4, s20, 1.03108; VI-NEXT: v_add_f32_e64 v3, s19, 1.03109; VI-NEXT: v_add_f32_e64 v2, s18, 1.03110; VI-NEXT: v_add_f32_e64 v1, s17, 1.03111; VI-NEXT: v_add_f32_e64 v0, s16, 1.03112; VI-NEXT: s_setpc_b64 s[30:31]3113; VI-NEXT: .LBB25_3:3114; VI-NEXT: s_branch .LBB25_23115; VI-NEXT: .LBB25_4:3116; VI-NEXT: v_mov_b32_e32 v0, s163117; VI-NEXT: v_mov_b32_e32 v1, s173118; VI-NEXT: v_mov_b32_e32 v2, s183119; VI-NEXT: v_mov_b32_e32 v3, s193120; VI-NEXT: v_mov_b32_e32 v4, s203121; VI-NEXT: v_mov_b32_e32 v5, s213122; VI-NEXT: s_setpc_b64 s[30:31]3123;3124; GFX9-LABEL: bitcast_v6f32_to_v3f64_scalar:3125; GFX9: ; %bb.0:3126; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3127; GFX9-NEXT: s_cmp_lg_u32 s22, 03128; GFX9-NEXT: s_cbranch_scc0 .LBB25_33129; GFX9-NEXT: ; %bb.1: ; %cmp.false3130; GFX9-NEXT: s_cbranch_execnz .LBB25_43131; GFX9-NEXT: .LBB25_2: ; %cmp.true3132; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.03133; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.03134; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.03135; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.03136; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.03137; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.03138; GFX9-NEXT: s_setpc_b64 s[30:31]3139; GFX9-NEXT: .LBB25_3:3140; GFX9-NEXT: s_branch .LBB25_23141; GFX9-NEXT: .LBB25_4:3142; GFX9-NEXT: v_mov_b32_e32 v0, s163143; GFX9-NEXT: v_mov_b32_e32 v1, s173144; GFX9-NEXT: v_mov_b32_e32 v2, s183145; GFX9-NEXT: v_mov_b32_e32 v3, s193146; GFX9-NEXT: v_mov_b32_e32 v4, s203147; GFX9-NEXT: v_mov_b32_e32 v5, s213148; GFX9-NEXT: s_setpc_b64 s[30:31]3149;3150; GFX11-LABEL: bitcast_v6f32_to_v3f64_scalar:3151; GFX11: ; %bb.0:3152; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3153; GFX11-NEXT: s_mov_b32 s5, s173154; GFX11-NEXT: s_mov_b32 s4, s163155; GFX11-NEXT: s_cmp_lg_u32 s18, 03156; GFX11-NEXT: s_mov_b32 s6, 03157; GFX11-NEXT: s_cbranch_scc0 .LBB25_33158; GFX11-NEXT: ; %bb.1: ; %Flow3159; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s63160; GFX11-NEXT: s_cbranch_vccnz .LBB25_43161; GFX11-NEXT: .LBB25_2: ; %cmp.true3162; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.03163; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.03164; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.03165; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.03166; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.03167; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.03168; GFX11-NEXT: s_setpc_b64 s[30:31]3169; GFX11-NEXT: .LBB25_3:3170; GFX11-NEXT: s_branch .LBB25_23171; GFX11-NEXT: .LBB25_4:3172; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13173; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33174; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53175; GFX11-NEXT: s_setpc_b64 s[30:31]3176 %cmp = icmp eq i32 %b, 03177 br i1 %cmp, label %cmp.true, label %cmp.false3178 3179cmp.true:3180 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)3181 %a2 = bitcast <6 x float> %a1 to <3 x double>3182 br label %end3183 3184cmp.false:3185 %a3 = bitcast <6 x float> %a to <3 x double>3186 br label %end3187 3188end:3189 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3190 ret <3 x double> %phi3191}3192 3193define <6 x float> @bitcast_v3f64_to_v6f32(<3 x double> %a, i32 %b) {3194; SI-LABEL: bitcast_v3f64_to_v6f32:3195; SI: ; %bb.0:3196; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3197; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63198; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3199; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3200; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3201; SI-NEXT: ; %bb.1: ; %cmp.true3202; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.03203; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.03204; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.03205; SI-NEXT: ; %bb.2: ; %end3206; SI-NEXT: s_or_b64 exec, exec, s[4:5]3207; SI-NEXT: s_setpc_b64 s[30:31]3208;3209; VI-LABEL: bitcast_v3f64_to_v6f32:3210; VI: ; %bb.0:3211; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3212; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63213; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3214; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3215; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3216; VI-NEXT: s_cbranch_execz .LBB26_23217; VI-NEXT: ; %bb.1: ; %cmp.true3218; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.03219; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.03220; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.03221; VI-NEXT: .LBB26_2: ; %end3222; VI-NEXT: s_or_b64 exec, exec, s[4:5]3223; VI-NEXT: s_setpc_b64 s[30:31]3224;3225; GFX9-LABEL: bitcast_v3f64_to_v6f32:3226; GFX9: ; %bb.0:3227; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3228; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63229; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3230; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3231; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3232; GFX9-NEXT: s_cbranch_execz .LBB26_23233; GFX9-NEXT: ; %bb.1: ; %cmp.true3234; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.03235; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.03236; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.03237; GFX9-NEXT: .LBB26_2: ; %end3238; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3239; GFX9-NEXT: s_setpc_b64 s[30:31]3240;3241; GFX11-LABEL: bitcast_v3f64_to_v6f32:3242; GFX11: ; %bb.0:3243; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3244; GFX11-NEXT: s_mov_b32 s0, exec_lo3245; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v63246; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03247; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3248; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03249; GFX11-NEXT: s_cbranch_execz .LBB26_23250; GFX11-NEXT: ; %bb.1: ; %cmp.true3251; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.03252; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.03253; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.03254; GFX11-NEXT: .LBB26_2: ; %end3255; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03256; GFX11-NEXT: s_setpc_b64 s[30:31]3257 %cmp = icmp eq i32 %b, 03258 br i1 %cmp, label %cmp.true, label %cmp.false3259 3260cmp.true:3261 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)3262 %a2 = bitcast <3 x double> %a1 to <6 x float>3263 br label %end3264 3265cmp.false:3266 %a3 = bitcast <3 x double> %a to <6 x float>3267 br label %end3268 3269end:3270 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3271 ret <6 x float> %phi3272}3273 3274define inreg <6 x float> @bitcast_v3f64_to_v6f32_scalar(<3 x double> inreg %a, i32 inreg %b) {3275; SI-LABEL: bitcast_v3f64_to_v6f32_scalar:3276; SI: ; %bb.0:3277; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3278; SI-NEXT: s_cmp_lg_u32 s22, 03279; SI-NEXT: s_cbranch_scc0 .LBB27_33280; SI-NEXT: ; %bb.1: ; %cmp.false3281; SI-NEXT: s_cbranch_execnz .LBB27_43282; SI-NEXT: .LBB27_2: ; %cmp.true3283; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.03284; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.03285; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.03286; SI-NEXT: s_setpc_b64 s[30:31]3287; SI-NEXT: .LBB27_3:3288; SI-NEXT: s_branch .LBB27_23289; SI-NEXT: .LBB27_4:3290; SI-NEXT: v_mov_b32_e32 v0, s163291; SI-NEXT: v_mov_b32_e32 v1, s173292; SI-NEXT: v_mov_b32_e32 v2, s183293; SI-NEXT: v_mov_b32_e32 v3, s193294; SI-NEXT: v_mov_b32_e32 v4, s203295; SI-NEXT: v_mov_b32_e32 v5, s213296; SI-NEXT: s_setpc_b64 s[30:31]3297;3298; VI-LABEL: bitcast_v3f64_to_v6f32_scalar:3299; VI: ; %bb.0:3300; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3301; VI-NEXT: s_cmp_lg_u32 s22, 03302; VI-NEXT: s_cbranch_scc0 .LBB27_33303; VI-NEXT: ; %bb.1: ; %cmp.false3304; VI-NEXT: s_cbranch_execnz .LBB27_43305; VI-NEXT: .LBB27_2: ; %cmp.true3306; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.03307; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.03308; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.03309; VI-NEXT: s_setpc_b64 s[30:31]3310; VI-NEXT: .LBB27_3:3311; VI-NEXT: s_branch .LBB27_23312; VI-NEXT: .LBB27_4:3313; VI-NEXT: v_mov_b32_e32 v0, s163314; VI-NEXT: v_mov_b32_e32 v1, s173315; VI-NEXT: v_mov_b32_e32 v2, s183316; VI-NEXT: v_mov_b32_e32 v3, s193317; VI-NEXT: v_mov_b32_e32 v4, s203318; VI-NEXT: v_mov_b32_e32 v5, s213319; VI-NEXT: s_setpc_b64 s[30:31]3320;3321; GFX9-LABEL: bitcast_v3f64_to_v6f32_scalar:3322; GFX9: ; %bb.0:3323; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3324; GFX9-NEXT: s_cmp_lg_u32 s22, 03325; GFX9-NEXT: s_cbranch_scc0 .LBB27_33326; GFX9-NEXT: ; %bb.1: ; %cmp.false3327; GFX9-NEXT: s_cbranch_execnz .LBB27_43328; GFX9-NEXT: .LBB27_2: ; %cmp.true3329; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.03330; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.03331; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.03332; GFX9-NEXT: s_setpc_b64 s[30:31]3333; GFX9-NEXT: .LBB27_3:3334; GFX9-NEXT: s_branch .LBB27_23335; GFX9-NEXT: .LBB27_4:3336; GFX9-NEXT: v_mov_b32_e32 v0, s163337; GFX9-NEXT: v_mov_b32_e32 v1, s173338; GFX9-NEXT: v_mov_b32_e32 v2, s183339; GFX9-NEXT: v_mov_b32_e32 v3, s193340; GFX9-NEXT: v_mov_b32_e32 v4, s203341; GFX9-NEXT: v_mov_b32_e32 v5, s213342; GFX9-NEXT: s_setpc_b64 s[30:31]3343;3344; GFX11-LABEL: bitcast_v3f64_to_v6f32_scalar:3345; GFX11: ; %bb.0:3346; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3347; GFX11-NEXT: s_mov_b32 s5, s173348; GFX11-NEXT: s_mov_b32 s4, s163349; GFX11-NEXT: s_cmp_lg_u32 s18, 03350; GFX11-NEXT: s_mov_b32 s6, 03351; GFX11-NEXT: s_cbranch_scc0 .LBB27_33352; GFX11-NEXT: ; %bb.1: ; %Flow3353; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s63354; GFX11-NEXT: s_cbranch_vccnz .LBB27_43355; GFX11-NEXT: .LBB27_2: ; %cmp.true3356; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.03357; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.03358; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.03359; GFX11-NEXT: s_setpc_b64 s[30:31]3360; GFX11-NEXT: .LBB27_3:3361; GFX11-NEXT: s_branch .LBB27_23362; GFX11-NEXT: .LBB27_4:3363; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13364; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33365; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53366; GFX11-NEXT: s_setpc_b64 s[30:31]3367 %cmp = icmp eq i32 %b, 03368 br i1 %cmp, label %cmp.true, label %cmp.false3369 3370cmp.true:3371 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)3372 %a2 = bitcast <3 x double> %a1 to <6 x float>3373 br label %end3374 3375cmp.false:3376 %a3 = bitcast <3 x double> %a to <6 x float>3377 br label %end3378 3379end:3380 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3381 ret <6 x float> %phi3382}3383 3384define <12 x i16> @bitcast_v6f32_to_v12i16(<6 x float> %a, i32 %b) {3385; SI-LABEL: bitcast_v6f32_to_v12i16:3386; SI: ; %bb.0:3387; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3388; SI-NEXT: v_mov_b32_e32 v10, v53389; SI-NEXT: v_mov_b32_e32 v8, v43390; SI-NEXT: v_mov_b32_e32 v12, v33391; SI-NEXT: v_mov_b32_e32 v4, v23392; SI-NEXT: v_mov_b32_e32 v2, v13393; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63394; SI-NEXT: ; implicit-def: $vgpr13395; SI-NEXT: ; implicit-def: $vgpr33396; SI-NEXT: ; implicit-def: $vgpr53397; SI-NEXT: ; implicit-def: $vgpr73398; SI-NEXT: ; implicit-def: $vgpr93399; SI-NEXT: ; implicit-def: $vgpr113400; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3401; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3402; SI-NEXT: ; %bb.1: ; %cmp.false3403; SI-NEXT: v_alignbit_b32 v9, v10, v8, 163404; SI-NEXT: v_alignbit_b32 v5, v12, v4, 163405; SI-NEXT: v_alignbit_b32 v1, v2, v0, 163406; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v103407; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v123408; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v23409; SI-NEXT: ; %bb.2: ; %Flow3410; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3411; SI-NEXT: s_cbranch_execz .LBB28_43412; SI-NEXT: ; %bb.3: ; %cmp.true3413; SI-NEXT: v_add_f32_e32 v2, 1.0, v23414; SI-NEXT: v_add_f32_e32 v0, 1.0, v03415; SI-NEXT: v_add_f32_e32 v12, 1.0, v123416; SI-NEXT: v_add_f32_e32 v4, 1.0, v43417; SI-NEXT: v_add_f32_e32 v10, 1.0, v103418; SI-NEXT: v_add_f32_e32 v8, 1.0, v83419; SI-NEXT: v_alignbit_b32 v9, v10, v8, 163420; SI-NEXT: v_alignbit_b32 v5, v12, v4, 163421; SI-NEXT: v_alignbit_b32 v1, v2, v0, 163422; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v103423; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v123424; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v23425; SI-NEXT: .LBB28_4: ; %end3426; SI-NEXT: s_or_b64 exec, exec, s[4:5]3427; SI-NEXT: v_mov_b32_e32 v6, v123428; SI-NEXT: s_setpc_b64 s[30:31]3429;3430; VI-LABEL: bitcast_v6f32_to_v12i16:3431; VI: ; %bb.0:3432; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3433; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63434; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3435; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3436; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3437; VI-NEXT: ; %bb.1: ; %cmp.true3438; VI-NEXT: v_add_f32_e32 v5, 1.0, v53439; VI-NEXT: v_add_f32_e32 v4, 1.0, v43440; VI-NEXT: v_add_f32_e32 v3, 1.0, v33441; VI-NEXT: v_add_f32_e32 v2, 1.0, v23442; VI-NEXT: v_add_f32_e32 v1, 1.0, v13443; VI-NEXT: v_add_f32_e32 v0, 1.0, v03444; VI-NEXT: ; %bb.2: ; %end3445; VI-NEXT: s_or_b64 exec, exec, s[4:5]3446; VI-NEXT: s_setpc_b64 s[30:31]3447;3448; GFX9-LABEL: bitcast_v6f32_to_v12i16:3449; GFX9: ; %bb.0:3450; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3451; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63452; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3453; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3454; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3455; GFX9-NEXT: ; %bb.1: ; %cmp.true3456; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v53457; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v43458; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v33459; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v23460; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v13461; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v03462; GFX9-NEXT: ; %bb.2: ; %end3463; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3464; GFX9-NEXT: s_setpc_b64 s[30:31]3465;3466; GFX11-LABEL: bitcast_v6f32_to_v12i16:3467; GFX11: ; %bb.0:3468; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3469; GFX11-NEXT: s_mov_b32 s0, exec_lo3470; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v63471; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03472; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3473; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03474; GFX11-NEXT: ; %bb.1: ; %cmp.true3475; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v43476; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v23477; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v03478; GFX11-NEXT: ; %bb.2: ; %end3479; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03480; GFX11-NEXT: s_setpc_b64 s[30:31]3481 %cmp = icmp eq i32 %b, 03482 br i1 %cmp, label %cmp.true, label %cmp.false3483 3484cmp.true:3485 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)3486 %a2 = bitcast <6 x float> %a1 to <12 x i16>3487 br label %end3488 3489cmp.false:3490 %a3 = bitcast <6 x float> %a to <12 x i16>3491 br label %end3492 3493end:3494 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3495 ret <12 x i16> %phi3496}3497 3498define inreg <12 x i16> @bitcast_v6f32_to_v12i16_scalar(<6 x float> inreg %a, i32 inreg %b) {3499; SI-LABEL: bitcast_v6f32_to_v12i16_scalar:3500; SI: ; %bb.0:3501; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3502; SI-NEXT: s_cmp_lg_u32 s22, 03503; SI-NEXT: s_cbranch_scc0 .LBB29_33504; SI-NEXT: ; %bb.1: ; %cmp.false3505; SI-NEXT: s_lshr_b32 s14, s21, 163506; SI-NEXT: s_lshr_b32 s13, s19, 163507; SI-NEXT: s_lshr_b32 s12, s17, 163508; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 163509; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 163510; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 163511; SI-NEXT: s_cbranch_execnz .LBB29_43512; SI-NEXT: .LBB29_2: ; %cmp.true3513; SI-NEXT: v_add_f32_e64 v17, s17, 1.03514; SI-NEXT: v_add_f32_e64 v16, s16, 1.03515; SI-NEXT: v_add_f32_e64 v15, s19, 1.03516; SI-NEXT: v_add_f32_e64 v14, s18, 1.03517; SI-NEXT: v_add_f32_e64 v13, s21, 1.03518; SI-NEXT: v_add_f32_e64 v12, s20, 1.03519; SI-NEXT: v_lshr_b64 v[9:10], v[12:13], 163520; SI-NEXT: v_lshr_b64 v[5:6], v[14:15], 163521; SI-NEXT: v_lshr_b64 v[1:2], v[16:17], 163522; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v133523; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v153524; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v173525; SI-NEXT: s_branch .LBB29_53526; SI-NEXT: .LBB29_3:3527; SI-NEXT: ; implicit-def: $sgpr83528; SI-NEXT: ; implicit-def: $sgpr123529; SI-NEXT: ; implicit-def: $sgpr63530; SI-NEXT: ; implicit-def: $sgpr133531; SI-NEXT: ; implicit-def: $sgpr43532; SI-NEXT: ; implicit-def: $sgpr143533; SI-NEXT: s_branch .LBB29_23534; SI-NEXT: .LBB29_4:3535; SI-NEXT: v_mov_b32_e32 v16, s163536; SI-NEXT: v_mov_b32_e32 v17, s173537; SI-NEXT: v_mov_b32_e32 v14, s183538; SI-NEXT: v_mov_b32_e32 v15, s193539; SI-NEXT: v_mov_b32_e32 v12, s203540; SI-NEXT: v_mov_b32_e32 v13, s213541; SI-NEXT: v_mov_b32_e32 v3, s123542; SI-NEXT: v_mov_b32_e32 v7, s133543; SI-NEXT: v_mov_b32_e32 v11, s143544; SI-NEXT: v_mov_b32_e32 v1, s83545; SI-NEXT: v_mov_b32_e32 v5, s63546; SI-NEXT: v_mov_b32_e32 v9, s43547; SI-NEXT: .LBB29_5: ; %end3548; SI-NEXT: v_mov_b32_e32 v0, v163549; SI-NEXT: v_mov_b32_e32 v2, v173550; SI-NEXT: v_mov_b32_e32 v4, v143551; SI-NEXT: v_mov_b32_e32 v6, v153552; SI-NEXT: v_mov_b32_e32 v8, v123553; SI-NEXT: v_mov_b32_e32 v10, v133554; SI-NEXT: s_setpc_b64 s[30:31]3555;3556; VI-LABEL: bitcast_v6f32_to_v12i16_scalar:3557; VI: ; %bb.0:3558; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3559; VI-NEXT: s_cmp_lg_u32 s22, 03560; VI-NEXT: s_cbranch_scc0 .LBB29_33561; VI-NEXT: ; %bb.1: ; %cmp.false3562; VI-NEXT: s_cbranch_execnz .LBB29_43563; VI-NEXT: .LBB29_2: ; %cmp.true3564; VI-NEXT: v_add_f32_e64 v5, s21, 1.03565; VI-NEXT: v_add_f32_e64 v4, s20, 1.03566; VI-NEXT: v_add_f32_e64 v3, s19, 1.03567; VI-NEXT: v_add_f32_e64 v2, s18, 1.03568; VI-NEXT: v_add_f32_e64 v1, s17, 1.03569; VI-NEXT: v_add_f32_e64 v0, s16, 1.03570; VI-NEXT: s_setpc_b64 s[30:31]3571; VI-NEXT: .LBB29_3:3572; VI-NEXT: s_branch .LBB29_23573; VI-NEXT: .LBB29_4:3574; VI-NEXT: v_mov_b32_e32 v0, s163575; VI-NEXT: v_mov_b32_e32 v1, s173576; VI-NEXT: v_mov_b32_e32 v2, s183577; VI-NEXT: v_mov_b32_e32 v3, s193578; VI-NEXT: v_mov_b32_e32 v4, s203579; VI-NEXT: v_mov_b32_e32 v5, s213580; VI-NEXT: v_mov_b32_e32 v6, s223581; VI-NEXT: v_mov_b32_e32 v7, s233582; VI-NEXT: s_setpc_b64 s[30:31]3583;3584; GFX9-LABEL: bitcast_v6f32_to_v12i16_scalar:3585; GFX9: ; %bb.0:3586; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3587; GFX9-NEXT: s_cmp_lg_u32 s22, 03588; GFX9-NEXT: s_cbranch_scc0 .LBB29_33589; GFX9-NEXT: ; %bb.1: ; %cmp.false3590; GFX9-NEXT: s_cbranch_execnz .LBB29_43591; GFX9-NEXT: .LBB29_2: ; %cmp.true3592; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.03593; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.03594; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.03595; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.03596; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.03597; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.03598; GFX9-NEXT: s_setpc_b64 s[30:31]3599; GFX9-NEXT: .LBB29_3:3600; GFX9-NEXT: s_branch .LBB29_23601; GFX9-NEXT: .LBB29_4:3602; GFX9-NEXT: v_mov_b32_e32 v0, s163603; GFX9-NEXT: v_mov_b32_e32 v1, s173604; GFX9-NEXT: v_mov_b32_e32 v2, s183605; GFX9-NEXT: v_mov_b32_e32 v3, s193606; GFX9-NEXT: v_mov_b32_e32 v4, s203607; GFX9-NEXT: v_mov_b32_e32 v5, s213608; GFX9-NEXT: v_mov_b32_e32 v6, s223609; GFX9-NEXT: v_mov_b32_e32 v7, s233610; GFX9-NEXT: s_setpc_b64 s[30:31]3611;3612; GFX11-LABEL: bitcast_v6f32_to_v12i16_scalar:3613; GFX11: ; %bb.0:3614; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3615; GFX11-NEXT: s_mov_b32 s5, s173616; GFX11-NEXT: s_mov_b32 s4, s163617; GFX11-NEXT: s_cmp_lg_u32 s18, 03618; GFX11-NEXT: s_mov_b32 s8, 03619; GFX11-NEXT: s_cbranch_scc0 .LBB29_33620; GFX11-NEXT: ; %bb.1: ; %Flow3621; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s83622; GFX11-NEXT: s_cbranch_vccnz .LBB29_43623; GFX11-NEXT: .LBB29_2: ; %cmp.true3624; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.03625; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.03626; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.03627; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.03628; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.03629; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.03630; GFX11-NEXT: s_setpc_b64 s[30:31]3631; GFX11-NEXT: .LBB29_3:3632; GFX11-NEXT: s_branch .LBB29_23633; GFX11-NEXT: .LBB29_4:3634; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13635; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33636; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53637; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s73638; GFX11-NEXT: s_setpc_b64 s[30:31]3639 %cmp = icmp eq i32 %b, 03640 br i1 %cmp, label %cmp.true, label %cmp.false3641 3642cmp.true:3643 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)3644 %a2 = bitcast <6 x float> %a1 to <12 x i16>3645 br label %end3646 3647cmp.false:3648 %a3 = bitcast <6 x float> %a to <12 x i16>3649 br label %end3650 3651end:3652 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3653 ret <12 x i16> %phi3654}3655 3656define <6 x float> @bitcast_v12i16_to_v6f32(<12 x i16> %a, i32 %b) {3657; SI-LABEL: bitcast_v12i16_to_v6f32:3658; SI: ; %bb.0:3659; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3660; SI-NEXT: v_mov_b32_e32 v15, v43661; SI-NEXT: v_mov_b32_e32 v14, v23662; SI-NEXT: v_mov_b32_e32 v13, v03663; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v123664; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v13665; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v33666; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v53667; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v73668; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v93669; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v113670; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr53671; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3672; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3673; SI-NEXT: s_cbranch_execnz .LBB30_33674; SI-NEXT: ; %bb.1: ; %Flow3675; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3676; SI-NEXT: s_cbranch_execnz .LBB30_43677; SI-NEXT: .LBB30_2: ; %end3678; SI-NEXT: s_or_b64 exec, exec, s[4:5]3679; SI-NEXT: s_setpc_b64 s[30:31]3680; SI-NEXT: .LBB30_3: ; %cmp.false3681; SI-NEXT: v_and_b32_e32 v0, 0xffff, v133682; SI-NEXT: v_and_b32_e32 v1, 0xffff, v143683; SI-NEXT: v_and_b32_e32 v2, 0xffff, v153684; SI-NEXT: v_and_b32_e32 v3, 0xffff, v63685; SI-NEXT: v_and_b32_e32 v4, 0xffff, v83686; SI-NEXT: v_and_b32_e32 v5, 0xffff, v103687; SI-NEXT: v_or_b32_e32 v0, v0, v183688; SI-NEXT: v_or_b32_e32 v1, v1, v173689; SI-NEXT: v_or_b32_e32 v2, v2, v163690; SI-NEXT: v_or_b32_e32 v3, v3, v123691; SI-NEXT: v_or_b32_e32 v4, v4, v93692; SI-NEXT: v_or_b32_e32 v5, v5, v73693; SI-NEXT: ; implicit-def: $vgpr133694; SI-NEXT: ; implicit-def: $vgpr143695; SI-NEXT: ; implicit-def: $vgpr153696; SI-NEXT: ; implicit-def: $vgpr63697; SI-NEXT: ; implicit-def: $vgpr83698; SI-NEXT: ; implicit-def: $vgpr103699; SI-NEXT: ; implicit-def: $vgpr183700; SI-NEXT: ; implicit-def: $vgpr173701; SI-NEXT: ; implicit-def: $vgpr163702; SI-NEXT: ; implicit-def: $vgpr123703; SI-NEXT: ; implicit-def: $vgpr93704; SI-NEXT: ; implicit-def: $vgpr73705; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3706; SI-NEXT: s_cbranch_execz .LBB30_23707; SI-NEXT: .LBB30_4: ; %cmp.true3708; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v133709; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v143710; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v153711; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v63712; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v83713; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v103714; SI-NEXT: v_and_b32_e32 v0, 0xffff, v03715; SI-NEXT: v_and_b32_e32 v1, 0xffff, v13716; SI-NEXT: v_and_b32_e32 v2, 0xffff, v23717; SI-NEXT: v_and_b32_e32 v3, 0xffff, v33718; SI-NEXT: v_and_b32_e32 v4, 0xffff, v43719; SI-NEXT: v_and_b32_e32 v5, 0xffff, v53720; SI-NEXT: v_or_b32_e32 v0, v18, v03721; SI-NEXT: s_mov_b32 s6, 0x300003722; SI-NEXT: v_or_b32_e32 v1, v17, v13723; SI-NEXT: v_or_b32_e32 v2, v16, v23724; SI-NEXT: v_or_b32_e32 v3, v12, v33725; SI-NEXT: v_or_b32_e32 v4, v9, v43726; SI-NEXT: v_or_b32_e32 v5, v7, v53727; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v03728; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v13729; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v23730; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v33731; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v43732; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v53733; SI-NEXT: s_or_b64 exec, exec, s[4:5]3734; SI-NEXT: s_setpc_b64 s[30:31]3735;3736; VI-LABEL: bitcast_v12i16_to_v6f32:3737; VI: ; %bb.0:3738; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3739; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63740; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3741; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3742; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3743; VI-NEXT: s_cbranch_execz .LBB30_23744; VI-NEXT: ; %bb.1: ; %cmp.true3745; VI-NEXT: v_mov_b32_e32 v7, 33746; VI-NEXT: v_add_u16_e32 v6, 3, v53747; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3748; VI-NEXT: v_or_b32_e32 v5, v6, v53749; VI-NEXT: v_add_u16_e32 v6, 3, v43750; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3751; VI-NEXT: v_or_b32_e32 v4, v6, v43752; VI-NEXT: v_add_u16_e32 v6, 3, v33753; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3754; VI-NEXT: v_or_b32_e32 v3, v6, v33755; VI-NEXT: v_add_u16_e32 v6, 3, v23756; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3757; VI-NEXT: v_or_b32_e32 v2, v6, v23758; VI-NEXT: v_add_u16_e32 v6, 3, v13759; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3760; VI-NEXT: v_or_b32_e32 v1, v6, v13761; VI-NEXT: v_add_u16_e32 v6, 3, v03762; VI-NEXT: v_add_u16_sdwa v0, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3763; VI-NEXT: v_or_b32_e32 v0, v6, v03764; VI-NEXT: .LBB30_2: ; %end3765; VI-NEXT: s_or_b64 exec, exec, s[4:5]3766; VI-NEXT: s_setpc_b64 s[30:31]3767;3768; GFX9-LABEL: bitcast_v12i16_to_v6f32:3769; GFX9: ; %bb.0:3770; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3771; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v63772; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3773; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3774; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3775; GFX9-NEXT: ; %bb.1: ; %cmp.true3776; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3777; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3778; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3779; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3780; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3781; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3782; GFX9-NEXT: ; %bb.2: ; %end3783; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3784; GFX9-NEXT: s_setpc_b64 s[30:31]3785;3786; GFX11-LABEL: bitcast_v12i16_to_v6f32:3787; GFX11: ; %bb.0:3788; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3789; GFX11-NEXT: s_mov_b32 s0, exec_lo3790; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v63791; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03792; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3793; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03794; GFX11-NEXT: ; %bb.1: ; %cmp.true3795; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3796; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3797; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3798; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3799; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3800; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3801; GFX11-NEXT: ; %bb.2: ; %end3802; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03803; GFX11-NEXT: s_setpc_b64 s[30:31]3804 %cmp = icmp eq i32 %b, 03805 br i1 %cmp, label %cmp.true, label %cmp.false3806 3807cmp.true:3808 %a1 = add <12 x i16> %a, splat (i16 3)3809 %a2 = bitcast <12 x i16> %a1 to <6 x float>3810 br label %end3811 3812cmp.false:3813 %a3 = bitcast <12 x i16> %a to <6 x float>3814 br label %end3815 3816end:3817 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3818 ret <6 x float> %phi3819}3820 3821define inreg <6 x float> @bitcast_v12i16_to_v6f32_scalar(<12 x i16> inreg %a, i32 inreg %b) {3822; SI-LABEL: bitcast_v12i16_to_v6f32_scalar:3823; SI: ; %bb.0:3824; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3825; SI-NEXT: s_cmp_lg_u32 s28, 03826; SI-NEXT: s_cbranch_scc0 .LBB31_43827; SI-NEXT: ; %bb.1: ; %cmp.false3828; SI-NEXT: s_and_b32 s4, s16, 0xffff3829; SI-NEXT: s_lshl_b32 s5, s17, 163830; SI-NEXT: s_or_b32 s4, s4, s53831; SI-NEXT: s_and_b32 s5, s18, 0xffff3832; SI-NEXT: s_lshl_b32 s6, s19, 163833; SI-NEXT: s_or_b32 s5, s5, s63834; SI-NEXT: s_and_b32 s6, s20, 0xffff3835; SI-NEXT: s_lshl_b32 s7, s21, 163836; SI-NEXT: s_or_b32 s6, s6, s73837; SI-NEXT: s_and_b32 s7, s22, 0xffff3838; SI-NEXT: s_lshl_b32 s8, s23, 163839; SI-NEXT: s_or_b32 s7, s7, s83840; SI-NEXT: s_and_b32 s8, s24, 0xffff3841; SI-NEXT: s_lshl_b32 s9, s25, 163842; SI-NEXT: s_or_b32 s8, s8, s93843; SI-NEXT: s_and_b32 s9, s26, 0xffff3844; SI-NEXT: s_lshl_b32 s10, s27, 163845; SI-NEXT: s_or_b32 s9, s9, s103846; SI-NEXT: s_cbranch_execnz .LBB31_33847; SI-NEXT: .LBB31_2: ; %cmp.true3848; SI-NEXT: s_add_i32 s16, s16, 33849; SI-NEXT: s_and_b32 s4, s16, 0xffff3850; SI-NEXT: s_lshl_b32 s5, s17, 163851; SI-NEXT: s_add_i32 s18, s18, 33852; SI-NEXT: s_or_b32 s4, s5, s43853; SI-NEXT: s_and_b32 s5, s18, 0xffff3854; SI-NEXT: s_lshl_b32 s6, s19, 163855; SI-NEXT: s_add_i32 s20, s20, 33856; SI-NEXT: s_or_b32 s5, s6, s53857; SI-NEXT: s_and_b32 s6, s20, 0xffff3858; SI-NEXT: s_lshl_b32 s7, s21, 163859; SI-NEXT: s_add_i32 s22, s22, 33860; SI-NEXT: s_or_b32 s6, s7, s63861; SI-NEXT: s_and_b32 s7, s22, 0xffff3862; SI-NEXT: s_lshl_b32 s8, s23, 163863; SI-NEXT: s_add_i32 s24, s24, 33864; SI-NEXT: s_or_b32 s7, s8, s73865; SI-NEXT: s_and_b32 s8, s24, 0xffff3866; SI-NEXT: s_lshl_b32 s9, s25, 163867; SI-NEXT: s_add_i32 s26, s26, 33868; SI-NEXT: s_or_b32 s8, s9, s83869; SI-NEXT: s_and_b32 s9, s26, 0xffff3870; SI-NEXT: s_lshl_b32 s10, s27, 163871; SI-NEXT: s_or_b32 s9, s10, s93872; SI-NEXT: s_add_i32 s4, s4, 0x300003873; SI-NEXT: s_add_i32 s5, s5, 0x300003874; SI-NEXT: s_add_i32 s6, s6, 0x300003875; SI-NEXT: s_add_i32 s7, s7, 0x300003876; SI-NEXT: s_add_i32 s8, s8, 0x300003877; SI-NEXT: s_add_i32 s9, s9, 0x300003878; SI-NEXT: .LBB31_3: ; %end3879; SI-NEXT: v_mov_b32_e32 v0, s43880; SI-NEXT: v_mov_b32_e32 v1, s53881; SI-NEXT: v_mov_b32_e32 v2, s63882; SI-NEXT: v_mov_b32_e32 v3, s73883; SI-NEXT: v_mov_b32_e32 v4, s83884; SI-NEXT: v_mov_b32_e32 v5, s93885; SI-NEXT: s_setpc_b64 s[30:31]3886; SI-NEXT: .LBB31_4:3887; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr93888; SI-NEXT: s_branch .LBB31_23889;3890; VI-LABEL: bitcast_v12i16_to_v6f32_scalar:3891; VI: ; %bb.0:3892; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3893; VI-NEXT: s_cmp_lg_u32 s22, 03894; VI-NEXT: s_cbranch_scc0 .LBB31_43895; VI-NEXT: ; %bb.1: ; %cmp.false3896; VI-NEXT: s_cbranch_execnz .LBB31_33897; VI-NEXT: .LBB31_2: ; %cmp.true3898; VI-NEXT: s_add_i32 s5, s21, 33899; VI-NEXT: s_and_b32 s4, s21, 0xffff00003900; VI-NEXT: s_and_b32 s5, s5, 0xffff3901; VI-NEXT: s_or_b32 s4, s4, s53902; VI-NEXT: s_add_i32 s5, s20, 33903; VI-NEXT: s_add_i32 s21, s4, 0x300003904; VI-NEXT: s_and_b32 s4, s20, 0xffff00003905; VI-NEXT: s_and_b32 s5, s5, 0xffff3906; VI-NEXT: s_or_b32 s4, s4, s53907; VI-NEXT: s_add_i32 s5, s19, 33908; VI-NEXT: s_add_i32 s20, s4, 0x300003909; VI-NEXT: s_and_b32 s4, s19, 0xffff00003910; VI-NEXT: s_and_b32 s5, s5, 0xffff3911; VI-NEXT: s_or_b32 s4, s4, s53912; VI-NEXT: s_add_i32 s5, s18, 33913; VI-NEXT: s_add_i32 s19, s4, 0x300003914; VI-NEXT: s_and_b32 s4, s18, 0xffff00003915; VI-NEXT: s_and_b32 s5, s5, 0xffff3916; VI-NEXT: s_or_b32 s4, s4, s53917; VI-NEXT: s_add_i32 s5, s17, 33918; VI-NEXT: s_add_i32 s18, s4, 0x300003919; VI-NEXT: s_and_b32 s4, s17, 0xffff00003920; VI-NEXT: s_and_b32 s5, s5, 0xffff3921; VI-NEXT: s_or_b32 s4, s4, s53922; VI-NEXT: s_add_i32 s5, s16, 33923; VI-NEXT: s_add_i32 s17, s4, 0x300003924; VI-NEXT: s_and_b32 s4, s16, 0xffff00003925; VI-NEXT: s_and_b32 s5, s5, 0xffff3926; VI-NEXT: s_or_b32 s4, s4, s53927; VI-NEXT: s_add_i32 s16, s4, 0x300003928; VI-NEXT: .LBB31_3: ; %end3929; VI-NEXT: v_mov_b32_e32 v0, s163930; VI-NEXT: v_mov_b32_e32 v1, s173931; VI-NEXT: v_mov_b32_e32 v2, s183932; VI-NEXT: v_mov_b32_e32 v3, s193933; VI-NEXT: v_mov_b32_e32 v4, s203934; VI-NEXT: v_mov_b32_e32 v5, s213935; VI-NEXT: s_setpc_b64 s[30:31]3936; VI-NEXT: .LBB31_4:3937; VI-NEXT: s_branch .LBB31_23938;3939; GFX9-LABEL: bitcast_v12i16_to_v6f32_scalar:3940; GFX9: ; %bb.0:3941; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3942; GFX9-NEXT: s_cmp_lg_u32 s22, 03943; GFX9-NEXT: s_cbranch_scc0 .LBB31_33944; GFX9-NEXT: ; %bb.1: ; %cmp.false3945; GFX9-NEXT: s_cbranch_execnz .LBB31_43946; GFX9-NEXT: .LBB31_2: ; %cmp.true3947; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]3948; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]3949; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]3950; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]3951; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]3952; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]3953; GFX9-NEXT: s_setpc_b64 s[30:31]3954; GFX9-NEXT: .LBB31_3:3955; GFX9-NEXT: s_branch .LBB31_23956; GFX9-NEXT: .LBB31_4:3957; GFX9-NEXT: v_mov_b32_e32 v0, s163958; GFX9-NEXT: v_mov_b32_e32 v1, s173959; GFX9-NEXT: v_mov_b32_e32 v2, s183960; GFX9-NEXT: v_mov_b32_e32 v3, s193961; GFX9-NEXT: v_mov_b32_e32 v4, s203962; GFX9-NEXT: v_mov_b32_e32 v5, s213963; GFX9-NEXT: s_setpc_b64 s[30:31]3964;3965; GFX11-LABEL: bitcast_v12i16_to_v6f32_scalar:3966; GFX11: ; %bb.0:3967; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3968; GFX11-NEXT: s_mov_b32 s5, s173969; GFX11-NEXT: s_mov_b32 s4, s163970; GFX11-NEXT: s_cmp_lg_u32 s18, 03971; GFX11-NEXT: s_mov_b32 s6, 03972; GFX11-NEXT: s_cbranch_scc0 .LBB31_33973; GFX11-NEXT: ; %bb.1: ; %Flow3974; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s63975; GFX11-NEXT: s_cbranch_vccnz .LBB31_43976; GFX11-NEXT: .LBB31_2: ; %cmp.true3977; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]3978; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]3979; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]3980; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]3981; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]3982; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]3983; GFX11-NEXT: s_setpc_b64 s[30:31]3984; GFX11-NEXT: .LBB31_3:3985; GFX11-NEXT: s_branch .LBB31_23986; GFX11-NEXT: .LBB31_4:3987; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13988; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33989; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53990; GFX11-NEXT: s_setpc_b64 s[30:31]3991 %cmp = icmp eq i32 %b, 03992 br i1 %cmp, label %cmp.true, label %cmp.false3993 3994cmp.true:3995 %a1 = add <12 x i16> %a, splat (i16 3)3996 %a2 = bitcast <12 x i16> %a1 to <6 x float>3997 br label %end3998 3999cmp.false:4000 %a3 = bitcast <12 x i16> %a to <6 x float>4001 br label %end4002 4003end:4004 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4005 ret <6 x float> %phi4006}4007 4008define <12 x half> @bitcast_v6f32_to_v12f16(<6 x float> %a, i32 %b) {4009; SI-LABEL: bitcast_v6f32_to_v12f16:4010; SI: ; %bb.0:4011; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4012; SI-NEXT: v_mov_b32_e32 v17, v54013; SI-NEXT: v_mov_b32_e32 v16, v44014; SI-NEXT: v_mov_b32_e32 v15, v34015; SI-NEXT: v_mov_b32_e32 v14, v24016; SI-NEXT: v_mov_b32_e32 v13, v14017; SI-NEXT: v_mov_b32_e32 v12, v04018; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64019; SI-NEXT: ; implicit-def: $vgpr04020; SI-NEXT: ; implicit-def: $vgpr14021; SI-NEXT: ; implicit-def: $vgpr24022; SI-NEXT: ; implicit-def: $vgpr34023; SI-NEXT: ; implicit-def: $vgpr44024; SI-NEXT: ; implicit-def: $vgpr54025; SI-NEXT: ; implicit-def: $vgpr64026; SI-NEXT: ; implicit-def: $vgpr74027; SI-NEXT: ; implicit-def: $vgpr84028; SI-NEXT: ; implicit-def: $vgpr94029; SI-NEXT: ; implicit-def: $vgpr104030; SI-NEXT: ; implicit-def: $vgpr114031; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4032; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4033; SI-NEXT: s_cbranch_execnz .LBB32_34034; SI-NEXT: ; %bb.1: ; %Flow4035; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4036; SI-NEXT: s_cbranch_execnz .LBB32_44037; SI-NEXT: .LBB32_2: ; %end4038; SI-NEXT: s_or_b64 exec, exec, s[4:5]4039; SI-NEXT: s_setpc_b64 s[30:31]4040; SI-NEXT: .LBB32_3: ; %cmp.false4041; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v174042; SI-NEXT: v_cvt_f32_f16_e32 v11, v04043; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v164044; SI-NEXT: v_cvt_f32_f16_e32 v9, v04045; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v154046; SI-NEXT: v_cvt_f32_f16_e32 v7, v04047; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v144048; SI-NEXT: v_cvt_f32_f16_e32 v5, v04049; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v134050; SI-NEXT: v_cvt_f32_f16_e32 v3, v04051; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v124052; SI-NEXT: v_cvt_f32_f16_e32 v1, v04053; SI-NEXT: v_cvt_f32_f16_e32 v10, v174054; SI-NEXT: v_cvt_f32_f16_e32 v8, v164055; SI-NEXT: v_cvt_f32_f16_e32 v6, v154056; SI-NEXT: v_cvt_f32_f16_e32 v4, v144057; SI-NEXT: v_cvt_f32_f16_e32 v2, v134058; SI-NEXT: v_cvt_f32_f16_e32 v0, v124059; SI-NEXT: ; implicit-def: $vgpr124060; SI-NEXT: ; implicit-def: $vgpr134061; SI-NEXT: ; implicit-def: $vgpr144062; SI-NEXT: ; implicit-def: $vgpr154063; SI-NEXT: ; implicit-def: $vgpr164064; SI-NEXT: ; implicit-def: $vgpr174065; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4066; SI-NEXT: s_cbranch_execz .LBB32_24067; SI-NEXT: .LBB32_4: ; %cmp.true4068; SI-NEXT: v_add_f32_e32 v1, 1.0, v124069; SI-NEXT: v_add_f32_e32 v3, 1.0, v134070; SI-NEXT: v_add_f32_e32 v5, 1.0, v144071; SI-NEXT: v_add_f32_e32 v7, 1.0, v154072; SI-NEXT: v_add_f32_e32 v9, 1.0, v164073; SI-NEXT: v_add_f32_e32 v11, 1.0, v174074; SI-NEXT: v_cvt_f32_f16_e32 v10, v114075; SI-NEXT: v_cvt_f32_f16_e32 v8, v94076; SI-NEXT: v_cvt_f32_f16_e32 v6, v74077; SI-NEXT: v_cvt_f32_f16_e32 v4, v54078; SI-NEXT: v_cvt_f32_f16_e32 v2, v34079; SI-NEXT: v_cvt_f32_f16_e32 v0, v14080; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v114081; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v94082; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v74083; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v54084; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34085; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14086; SI-NEXT: v_cvt_f32_f16_e32 v11, v114087; SI-NEXT: v_cvt_f32_f16_e32 v9, v94088; SI-NEXT: v_cvt_f32_f16_e32 v7, v74089; SI-NEXT: v_cvt_f32_f16_e32 v5, v54090; SI-NEXT: v_cvt_f32_f16_e32 v3, v34091; SI-NEXT: v_cvt_f32_f16_e32 v1, v14092; SI-NEXT: s_or_b64 exec, exec, s[4:5]4093; SI-NEXT: s_setpc_b64 s[30:31]4094;4095; VI-LABEL: bitcast_v6f32_to_v12f16:4096; VI: ; %bb.0:4097; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4098; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64099; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4100; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4101; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4102; VI-NEXT: ; %bb.1: ; %cmp.true4103; VI-NEXT: v_add_f32_e32 v5, 1.0, v54104; VI-NEXT: v_add_f32_e32 v4, 1.0, v44105; VI-NEXT: v_add_f32_e32 v3, 1.0, v34106; VI-NEXT: v_add_f32_e32 v2, 1.0, v24107; VI-NEXT: v_add_f32_e32 v1, 1.0, v14108; VI-NEXT: v_add_f32_e32 v0, 1.0, v04109; VI-NEXT: ; %bb.2: ; %end4110; VI-NEXT: s_or_b64 exec, exec, s[4:5]4111; VI-NEXT: s_setpc_b64 s[30:31]4112;4113; GFX9-LABEL: bitcast_v6f32_to_v12f16:4114; GFX9: ; %bb.0:4115; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4116; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64117; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4118; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4119; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4120; GFX9-NEXT: ; %bb.1: ; %cmp.true4121; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v54122; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v44123; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v34124; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v24125; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v14126; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v04127; GFX9-NEXT: ; %bb.2: ; %end4128; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4129; GFX9-NEXT: s_setpc_b64 s[30:31]4130;4131; GFX11-LABEL: bitcast_v6f32_to_v12f16:4132; GFX11: ; %bb.0:4133; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4134; GFX11-NEXT: s_mov_b32 s0, exec_lo4135; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v64136; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04137; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4138; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04139; GFX11-NEXT: ; %bb.1: ; %cmp.true4140; GFX11-NEXT: v_dual_add_f32 v5, 1.0, v5 :: v_dual_add_f32 v4, 1.0, v44141; GFX11-NEXT: v_dual_add_f32 v3, 1.0, v3 :: v_dual_add_f32 v2, 1.0, v24142; GFX11-NEXT: v_dual_add_f32 v1, 1.0, v1 :: v_dual_add_f32 v0, 1.0, v04143; GFX11-NEXT: ; %bb.2: ; %end4144; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04145; GFX11-NEXT: s_setpc_b64 s[30:31]4146 %cmp = icmp eq i32 %b, 04147 br i1 %cmp, label %cmp.true, label %cmp.false4148 4149cmp.true:4150 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)4151 %a2 = bitcast <6 x float> %a1 to <12 x half>4152 br label %end4153 4154cmp.false:4155 %a3 = bitcast <6 x float> %a to <12 x half>4156 br label %end4157 4158end:4159 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4160 ret <12 x half> %phi4161}4162 4163define inreg <12 x half> @bitcast_v6f32_to_v12f16_scalar(<6 x float> inreg %a, i32 inreg %b) {4164; SI-LABEL: bitcast_v6f32_to_v12f16_scalar:4165; SI: ; %bb.0:4166; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4167; SI-NEXT: s_cmp_lg_u32 s22, 04168; SI-NEXT: s_cbranch_scc0 .LBB33_44169; SI-NEXT: ; %bb.1: ; %cmp.false4170; SI-NEXT: s_lshr_b32 s4, s21, 164171; SI-NEXT: v_cvt_f32_f16_e32 v11, s44172; SI-NEXT: s_lshr_b32 s4, s20, 164173; SI-NEXT: v_cvt_f32_f16_e32 v9, s44174; SI-NEXT: s_lshr_b32 s4, s19, 164175; SI-NEXT: v_cvt_f32_f16_e32 v7, s44176; SI-NEXT: s_lshr_b32 s4, s18, 164177; SI-NEXT: v_cvt_f32_f16_e32 v5, s44178; SI-NEXT: s_lshr_b32 s4, s17, 164179; SI-NEXT: v_cvt_f32_f16_e32 v3, s44180; SI-NEXT: s_lshr_b32 s4, s16, 164181; SI-NEXT: v_cvt_f32_f16_e32 v1, s44182; SI-NEXT: v_cvt_f32_f16_e32 v10, s214183; SI-NEXT: v_cvt_f32_f16_e32 v8, s204184; SI-NEXT: v_cvt_f32_f16_e32 v6, s194185; SI-NEXT: v_cvt_f32_f16_e32 v4, s184186; SI-NEXT: v_cvt_f32_f16_e32 v2, s174187; SI-NEXT: v_cvt_f32_f16_e32 v0, s164188; SI-NEXT: s_cbranch_execnz .LBB33_34189; SI-NEXT: .LBB33_2: ; %cmp.true4190; SI-NEXT: v_add_f32_e64 v1, s16, 1.04191; SI-NEXT: v_add_f32_e64 v3, s17, 1.04192; SI-NEXT: v_add_f32_e64 v5, s18, 1.04193; SI-NEXT: v_add_f32_e64 v7, s19, 1.04194; SI-NEXT: v_add_f32_e64 v9, s20, 1.04195; SI-NEXT: v_add_f32_e64 v11, s21, 1.04196; SI-NEXT: v_cvt_f32_f16_e32 v10, v114197; SI-NEXT: v_cvt_f32_f16_e32 v8, v94198; SI-NEXT: v_cvt_f32_f16_e32 v6, v74199; SI-NEXT: v_cvt_f32_f16_e32 v4, v54200; SI-NEXT: v_cvt_f32_f16_e32 v2, v34201; SI-NEXT: v_cvt_f32_f16_e32 v0, v14202; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v114203; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v94204; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v74205; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v54206; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v34207; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v14208; SI-NEXT: v_cvt_f32_f16_e32 v11, v114209; SI-NEXT: v_cvt_f32_f16_e32 v9, v94210; SI-NEXT: v_cvt_f32_f16_e32 v7, v74211; SI-NEXT: v_cvt_f32_f16_e32 v5, v54212; SI-NEXT: v_cvt_f32_f16_e32 v3, v34213; SI-NEXT: v_cvt_f32_f16_e32 v1, v14214; SI-NEXT: .LBB33_3: ; %end4215; SI-NEXT: s_setpc_b64 s[30:31]4216; SI-NEXT: .LBB33_4:4217; SI-NEXT: ; implicit-def: $vgpr04218; SI-NEXT: ; implicit-def: $vgpr14219; SI-NEXT: ; implicit-def: $vgpr24220; SI-NEXT: ; implicit-def: $vgpr34221; SI-NEXT: ; implicit-def: $vgpr44222; SI-NEXT: ; implicit-def: $vgpr54223; SI-NEXT: ; implicit-def: $vgpr64224; SI-NEXT: ; implicit-def: $vgpr74225; SI-NEXT: ; implicit-def: $vgpr84226; SI-NEXT: ; implicit-def: $vgpr94227; SI-NEXT: ; implicit-def: $vgpr104228; SI-NEXT: ; implicit-def: $vgpr114229; SI-NEXT: s_branch .LBB33_24230;4231; VI-LABEL: bitcast_v6f32_to_v12f16_scalar:4232; VI: ; %bb.0:4233; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4234; VI-NEXT: s_cmp_lg_u32 s22, 04235; VI-NEXT: s_cbranch_scc0 .LBB33_34236; VI-NEXT: ; %bb.1: ; %cmp.false4237; VI-NEXT: s_cbranch_execnz .LBB33_44238; VI-NEXT: .LBB33_2: ; %cmp.true4239; VI-NEXT: v_add_f32_e64 v5, s21, 1.04240; VI-NEXT: v_add_f32_e64 v4, s20, 1.04241; VI-NEXT: v_add_f32_e64 v3, s19, 1.04242; VI-NEXT: v_add_f32_e64 v2, s18, 1.04243; VI-NEXT: v_add_f32_e64 v1, s17, 1.04244; VI-NEXT: v_add_f32_e64 v0, s16, 1.04245; VI-NEXT: s_setpc_b64 s[30:31]4246; VI-NEXT: .LBB33_3:4247; VI-NEXT: s_branch .LBB33_24248; VI-NEXT: .LBB33_4:4249; VI-NEXT: v_mov_b32_e32 v0, s164250; VI-NEXT: v_mov_b32_e32 v1, s174251; VI-NEXT: v_mov_b32_e32 v2, s184252; VI-NEXT: v_mov_b32_e32 v3, s194253; VI-NEXT: v_mov_b32_e32 v4, s204254; VI-NEXT: v_mov_b32_e32 v5, s214255; VI-NEXT: v_mov_b32_e32 v6, s224256; VI-NEXT: v_mov_b32_e32 v7, s234257; VI-NEXT: s_setpc_b64 s[30:31]4258;4259; GFX9-LABEL: bitcast_v6f32_to_v12f16_scalar:4260; GFX9: ; %bb.0:4261; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4262; GFX9-NEXT: s_cmp_lg_u32 s22, 04263; GFX9-NEXT: s_cbranch_scc0 .LBB33_34264; GFX9-NEXT: ; %bb.1: ; %cmp.false4265; GFX9-NEXT: s_cbranch_execnz .LBB33_44266; GFX9-NEXT: .LBB33_2: ; %cmp.true4267; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.04268; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.04269; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.04270; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.04271; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.04272; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.04273; GFX9-NEXT: s_setpc_b64 s[30:31]4274; GFX9-NEXT: .LBB33_3:4275; GFX9-NEXT: s_branch .LBB33_24276; GFX9-NEXT: .LBB33_4:4277; GFX9-NEXT: v_mov_b32_e32 v0, s164278; GFX9-NEXT: v_mov_b32_e32 v1, s174279; GFX9-NEXT: v_mov_b32_e32 v2, s184280; GFX9-NEXT: v_mov_b32_e32 v3, s194281; GFX9-NEXT: v_mov_b32_e32 v4, s204282; GFX9-NEXT: v_mov_b32_e32 v5, s214283; GFX9-NEXT: v_mov_b32_e32 v6, s224284; GFX9-NEXT: v_mov_b32_e32 v7, s234285; GFX9-NEXT: s_setpc_b64 s[30:31]4286;4287; GFX11-LABEL: bitcast_v6f32_to_v12f16_scalar:4288; GFX11: ; %bb.0:4289; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4290; GFX11-NEXT: s_mov_b32 s5, s174291; GFX11-NEXT: s_mov_b32 s4, s164292; GFX11-NEXT: s_cmp_lg_u32 s18, 04293; GFX11-NEXT: s_mov_b32 s8, 04294; GFX11-NEXT: s_cbranch_scc0 .LBB33_34295; GFX11-NEXT: ; %bb.1: ; %Flow4296; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s84297; GFX11-NEXT: s_cbranch_vccnz .LBB33_44298; GFX11-NEXT: .LBB33_2: ; %cmp.true4299; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.04300; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.04301; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.04302; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.04303; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.04304; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.04305; GFX11-NEXT: s_setpc_b64 s[30:31]4306; GFX11-NEXT: .LBB33_3:4307; GFX11-NEXT: s_branch .LBB33_24308; GFX11-NEXT: .LBB33_4:4309; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14310; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s34311; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s54312; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s74313; GFX11-NEXT: s_setpc_b64 s[30:31]4314 %cmp = icmp eq i32 %b, 04315 br i1 %cmp, label %cmp.true, label %cmp.false4316 4317cmp.true:4318 %a1 = fadd <6 x float> %a, splat (float 1.000000e+00)4319 %a2 = bitcast <6 x float> %a1 to <12 x half>4320 br label %end4321 4322cmp.false:4323 %a3 = bitcast <6 x float> %a to <12 x half>4324 br label %end4325 4326end:4327 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4328 ret <12 x half> %phi4329}4330 4331define <6 x float> @bitcast_v12f16_to_v6f32(<12 x half> %a, i32 %b) {4332; SI-LABEL: bitcast_v12f16_to_v6f32:4333; SI: ; %bb.0:4334; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4335; SI-NEXT: v_cvt_f16_f32_e32 v20, v14336; SI-NEXT: v_cvt_f16_f32_e32 v19, v04337; SI-NEXT: v_cvt_f16_f32_e32 v18, v34338; SI-NEXT: v_cvt_f16_f32_e32 v17, v24339; SI-NEXT: v_cvt_f16_f32_e32 v16, v54340; SI-NEXT: v_cvt_f16_f32_e32 v15, v44341; SI-NEXT: v_cvt_f16_f32_e32 v14, v74342; SI-NEXT: v_cvt_f16_f32_e32 v13, v64343; SI-NEXT: v_cvt_f16_f32_e32 v9, v94344; SI-NEXT: v_cvt_f16_f32_e32 v8, v84345; SI-NEXT: v_cvt_f16_f32_e32 v7, v114346; SI-NEXT: v_cvt_f16_f32_e32 v6, v104347; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v124348; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr54349; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4350; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4351; SI-NEXT: s_cbranch_execnz .LBB34_34352; SI-NEXT: ; %bb.1: ; %Flow4353; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4354; SI-NEXT: s_cbranch_execnz .LBB34_44355; SI-NEXT: .LBB34_2: ; %end4356; SI-NEXT: s_or_b64 exec, exec, s[4:5]4357; SI-NEXT: s_setpc_b64 s[30:31]4358; SI-NEXT: .LBB34_3: ; %cmp.false4359; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v204360; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v184361; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v164362; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v144363; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v94364; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v74365; SI-NEXT: v_or_b32_e32 v0, v19, v04366; SI-NEXT: v_or_b32_e32 v1, v17, v14367; SI-NEXT: v_or_b32_e32 v2, v15, v24368; SI-NEXT: v_or_b32_e32 v3, v13, v34369; SI-NEXT: v_or_b32_e32 v4, v8, v44370; SI-NEXT: v_or_b32_e32 v5, v6, v54371; SI-NEXT: ; implicit-def: $vgpr204372; SI-NEXT: ; implicit-def: $vgpr194373; SI-NEXT: ; implicit-def: $vgpr184374; SI-NEXT: ; implicit-def: $vgpr174375; SI-NEXT: ; implicit-def: $vgpr164376; SI-NEXT: ; implicit-def: $vgpr154377; SI-NEXT: ; implicit-def: $vgpr144378; SI-NEXT: ; implicit-def: $vgpr134379; SI-NEXT: ; implicit-def: $vgpr94380; SI-NEXT: ; implicit-def: $vgpr84381; SI-NEXT: ; implicit-def: $vgpr74382; SI-NEXT: ; implicit-def: $vgpr64383; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4384; SI-NEXT: s_cbranch_execz .LBB34_24385; SI-NEXT: .LBB34_4: ; %cmp.true4386; SI-NEXT: v_cvt_f32_f16_e32 v0, v204387; SI-NEXT: v_cvt_f32_f16_e32 v1, v194388; SI-NEXT: v_cvt_f32_f16_e32 v2, v184389; SI-NEXT: v_cvt_f32_f16_e32 v3, v174390; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v04391; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14392; SI-NEXT: v_cvt_f16_f32_e32 v0, v04393; SI-NEXT: v_cvt_f16_f32_e32 v1, v14394; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24395; SI-NEXT: v_cvt_f16_f32_e32 v2, v24396; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v04397; SI-NEXT: v_or_b32_e32 v0, v1, v04398; SI-NEXT: v_cvt_f32_f16_e32 v1, v164399; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v34400; SI-NEXT: v_cvt_f16_f32_e32 v3, v34401; SI-NEXT: v_cvt_f32_f16_e32 v5, v134402; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14403; SI-NEXT: v_cvt_f16_f32_e32 v4, v14404; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24405; SI-NEXT: v_cvt_f32_f16_e32 v2, v154406; SI-NEXT: v_or_b32_e32 v1, v3, v14407; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44408; SI-NEXT: v_cvt_f32_f16_e32 v4, v144409; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24410; SI-NEXT: v_cvt_f16_f32_e32 v2, v24411; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v54412; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44413; SI-NEXT: v_cvt_f16_f32_e32 v4, v44414; SI-NEXT: v_cvt_f16_f32_e32 v5, v54415; SI-NEXT: v_cvt_f32_f16_e32 v9, v94416; SI-NEXT: v_or_b32_e32 v2, v2, v34417; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44418; SI-NEXT: v_cvt_f32_f16_e32 v4, v84419; SI-NEXT: v_cvt_f32_f16_e32 v7, v74420; SI-NEXT: v_cvt_f32_f16_e32 v6, v64421; SI-NEXT: v_or_b32_e32 v3, v5, v34422; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v94423; SI-NEXT: v_cvt_f16_f32_e32 v5, v54424; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44425; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v74426; SI-NEXT: v_cvt_f16_f32_e32 v4, v44427; SI-NEXT: v_cvt_f16_f32_e32 v7, v74428; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v64429; SI-NEXT: v_cvt_f16_f32_e32 v6, v64430; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54431; SI-NEXT: v_or_b32_e32 v4, v4, v54432; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v74433; SI-NEXT: v_or_b32_e32 v5, v6, v54434; SI-NEXT: s_or_b64 exec, exec, s[4:5]4435; SI-NEXT: s_setpc_b64 s[30:31]4436;4437; VI-LABEL: bitcast_v12f16_to_v6f32:4438; VI: ; %bb.0:4439; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4440; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64441; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4442; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4443; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4444; VI-NEXT: s_cbranch_execz .LBB34_24445; VI-NEXT: ; %bb.1: ; %cmp.true4446; VI-NEXT: v_mov_b32_e32 v6, 0x2004447; VI-NEXT: v_add_f16_sdwa v7, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4448; VI-NEXT: v_add_f16_e32 v5, 0x200, v54449; VI-NEXT: v_or_b32_e32 v5, v5, v74450; VI-NEXT: v_add_f16_sdwa v7, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4451; VI-NEXT: v_add_f16_e32 v4, 0x200, v44452; VI-NEXT: v_or_b32_e32 v4, v4, v74453; VI-NEXT: v_add_f16_sdwa v7, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4454; VI-NEXT: v_add_f16_e32 v3, 0x200, v34455; VI-NEXT: v_or_b32_e32 v3, v3, v74456; VI-NEXT: v_add_f16_sdwa v7, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4457; VI-NEXT: v_add_f16_e32 v2, 0x200, v24458; VI-NEXT: v_or_b32_e32 v2, v2, v74459; VI-NEXT: v_add_f16_sdwa v7, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4460; VI-NEXT: v_add_f16_e32 v1, 0x200, v14461; VI-NEXT: v_add_f16_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4462; VI-NEXT: v_add_f16_e32 v0, 0x200, v04463; VI-NEXT: v_or_b32_e32 v1, v1, v74464; VI-NEXT: v_or_b32_e32 v0, v0, v64465; VI-NEXT: .LBB34_2: ; %end4466; VI-NEXT: s_or_b64 exec, exec, s[4:5]4467; VI-NEXT: s_setpc_b64 s[30:31]4468;4469; GFX9-LABEL: bitcast_v12f16_to_v6f32:4470; GFX9: ; %bb.0:4471; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4472; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64473; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4474; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4475; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4476; GFX9-NEXT: ; %bb.1: ; %cmp.true4477; GFX9-NEXT: s_movk_i32 s6, 0x2004478; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]4479; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]4480; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]4481; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]4482; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]4483; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]4484; GFX9-NEXT: ; %bb.2: ; %end4485; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4486; GFX9-NEXT: s_setpc_b64 s[30:31]4487;4488; GFX11-LABEL: bitcast_v12f16_to_v6f32:4489; GFX11: ; %bb.0:4490; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4491; GFX11-NEXT: s_mov_b32 s0, exec_lo4492; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v64493; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04494; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4495; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04496; GFX11-NEXT: ; %bb.1: ; %cmp.true4497; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]4498; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]4499; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]4500; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]4501; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]4502; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]4503; GFX11-NEXT: ; %bb.2: ; %end4504; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04505; GFX11-NEXT: s_setpc_b64 s[30:31]4506 %cmp = icmp eq i32 %b, 04507 br i1 %cmp, label %cmp.true, label %cmp.false4508 4509cmp.true:4510 %a1 = fadd <12 x half> %a, splat (half 0xH0200)4511 %a2 = bitcast <12 x half> %a1 to <6 x float>4512 br label %end4513 4514cmp.false:4515 %a3 = bitcast <12 x half> %a to <6 x float>4516 br label %end4517 4518end:4519 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4520 ret <6 x float> %phi4521}4522 4523define inreg <6 x float> @bitcast_v12f16_to_v6f32_scalar(<12 x half> inreg %a, i32 inreg %b) {4524; SI-LABEL: bitcast_v12f16_to_v6f32_scalar:4525; SI: ; %bb.0:4526; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4527; SI-NEXT: v_cvt_f16_f32_e32 v17, s174528; SI-NEXT: v_cvt_f16_f32_e32 v16, s164529; SI-NEXT: v_cvt_f16_f32_e32 v15, s194530; SI-NEXT: v_cvt_f16_f32_e32 v14, s184531; SI-NEXT: v_cvt_f16_f32_e32 v13, s214532; SI-NEXT: v_cvt_f16_f32_e32 v12, s204533; SI-NEXT: v_cvt_f16_f32_e32 v11, s234534; SI-NEXT: v_cvt_f16_f32_e32 v10, s224535; SI-NEXT: v_cvt_f16_f32_e32 v9, s254536; SI-NEXT: v_cvt_f16_f32_e32 v8, s244537; SI-NEXT: v_cvt_f16_f32_e32 v7, s274538; SI-NEXT: v_cvt_f16_f32_e32 v6, s264539; SI-NEXT: s_cmp_lg_u32 s28, 04540; SI-NEXT: s_cbranch_scc0 .LBB35_44541; SI-NEXT: ; %bb.1: ; %cmp.false4542; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v174543; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v154544; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v134545; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v114546; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v94547; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v74548; SI-NEXT: v_or_b32_e32 v0, v16, v04549; SI-NEXT: v_or_b32_e32 v1, v14, v14550; SI-NEXT: v_or_b32_e32 v2, v12, v24551; SI-NEXT: v_or_b32_e32 v3, v10, v34552; SI-NEXT: v_or_b32_e32 v4, v8, v44553; SI-NEXT: v_or_b32_e32 v5, v6, v54554; SI-NEXT: s_cbranch_execnz .LBB35_34555; SI-NEXT: .LBB35_2: ; %cmp.true4556; SI-NEXT: v_cvt_f32_f16_e32 v0, v174557; SI-NEXT: v_cvt_f32_f16_e32 v1, v164558; SI-NEXT: v_cvt_f32_f16_e32 v2, v154559; SI-NEXT: v_cvt_f32_f16_e32 v3, v144560; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v04561; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14562; SI-NEXT: v_cvt_f16_f32_e32 v0, v04563; SI-NEXT: v_cvt_f16_f32_e32 v1, v14564; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24565; SI-NEXT: v_cvt_f16_f32_e32 v2, v24566; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v04567; SI-NEXT: v_or_b32_e32 v0, v1, v04568; SI-NEXT: v_cvt_f32_f16_e32 v1, v134569; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v34570; SI-NEXT: v_cvt_f16_f32_e32 v3, v34571; SI-NEXT: v_cvt_f32_f16_e32 v5, v104572; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14573; SI-NEXT: v_cvt_f16_f32_e32 v4, v14574; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v24575; SI-NEXT: v_cvt_f32_f16_e32 v2, v124576; SI-NEXT: v_or_b32_e32 v1, v3, v14577; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44578; SI-NEXT: v_cvt_f32_f16_e32 v4, v114579; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24580; SI-NEXT: v_cvt_f16_f32_e32 v2, v24581; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v54582; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44583; SI-NEXT: v_cvt_f16_f32_e32 v4, v44584; SI-NEXT: v_cvt_f16_f32_e32 v5, v54585; SI-NEXT: v_cvt_f32_f16_e32 v9, v94586; SI-NEXT: v_or_b32_e32 v2, v2, v34587; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v44588; SI-NEXT: v_cvt_f32_f16_e32 v4, v84589; SI-NEXT: v_cvt_f32_f16_e32 v7, v74590; SI-NEXT: v_cvt_f32_f16_e32 v6, v64591; SI-NEXT: v_or_b32_e32 v3, v5, v34592; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v94593; SI-NEXT: v_cvt_f16_f32_e32 v5, v54594; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44595; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v74596; SI-NEXT: v_cvt_f16_f32_e32 v4, v44597; SI-NEXT: v_cvt_f16_f32_e32 v7, v74598; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v64599; SI-NEXT: v_cvt_f16_f32_e32 v6, v64600; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54601; SI-NEXT: v_or_b32_e32 v4, v4, v54602; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v74603; SI-NEXT: v_or_b32_e32 v5, v6, v54604; SI-NEXT: .LBB35_3: ; %end4605; SI-NEXT: s_setpc_b64 s[30:31]4606; SI-NEXT: .LBB35_4:4607; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr54608; SI-NEXT: s_branch .LBB35_24609;4610; VI-LABEL: bitcast_v12f16_to_v6f32_scalar:4611; VI: ; %bb.0:4612; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4613; VI-NEXT: s_cmp_lg_u32 s22, 04614; VI-NEXT: s_cbranch_scc0 .LBB35_34615; VI-NEXT: ; %bb.1: ; %cmp.false4616; VI-NEXT: s_cbranch_execnz .LBB35_44617; VI-NEXT: .LBB35_2: ; %cmp.true4618; VI-NEXT: s_lshr_b32 s4, s21, 164619; VI-NEXT: v_mov_b32_e32 v0, 0x2004620; VI-NEXT: v_mov_b32_e32 v1, s44621; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4622; VI-NEXT: v_add_f16_e32 v2, s21, v04623; VI-NEXT: s_lshr_b32 s4, s20, 164624; VI-NEXT: v_or_b32_e32 v5, v2, v14625; VI-NEXT: v_mov_b32_e32 v1, s44626; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4627; VI-NEXT: v_add_f16_e32 v2, s20, v04628; VI-NEXT: s_lshr_b32 s4, s19, 164629; VI-NEXT: v_or_b32_e32 v4, v2, v14630; VI-NEXT: v_mov_b32_e32 v1, s44631; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4632; VI-NEXT: v_add_f16_e32 v2, s19, v04633; VI-NEXT: s_lshr_b32 s4, s18, 164634; VI-NEXT: v_or_b32_e32 v3, v2, v14635; VI-NEXT: v_mov_b32_e32 v1, s44636; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4637; VI-NEXT: v_add_f16_e32 v2, s18, v04638; VI-NEXT: s_lshr_b32 s4, s17, 164639; VI-NEXT: v_or_b32_e32 v2, v2, v14640; VI-NEXT: v_mov_b32_e32 v1, s44641; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4642; VI-NEXT: v_add_f16_e32 v6, s17, v04643; VI-NEXT: s_lshr_b32 s4, s16, 164644; VI-NEXT: v_or_b32_e32 v1, v6, v14645; VI-NEXT: v_mov_b32_e32 v6, s44646; VI-NEXT: v_add_f16_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4647; VI-NEXT: v_add_f16_e32 v0, s16, v04648; VI-NEXT: v_or_b32_e32 v0, v0, v64649; VI-NEXT: s_setpc_b64 s[30:31]4650; VI-NEXT: .LBB35_3:4651; VI-NEXT: s_branch .LBB35_24652; VI-NEXT: .LBB35_4:4653; VI-NEXT: v_mov_b32_e32 v0, s164654; VI-NEXT: v_mov_b32_e32 v1, s174655; VI-NEXT: v_mov_b32_e32 v2, s184656; VI-NEXT: v_mov_b32_e32 v3, s194657; VI-NEXT: v_mov_b32_e32 v4, s204658; VI-NEXT: v_mov_b32_e32 v5, s214659; VI-NEXT: s_setpc_b64 s[30:31]4660;4661; GFX9-LABEL: bitcast_v12f16_to_v6f32_scalar:4662; GFX9: ; %bb.0:4663; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4664; GFX9-NEXT: s_cmp_lg_u32 s22, 04665; GFX9-NEXT: s_cbranch_scc0 .LBB35_34666; GFX9-NEXT: ; %bb.1: ; %cmp.false4667; GFX9-NEXT: s_cbranch_execnz .LBB35_44668; GFX9-NEXT: .LBB35_2: ; %cmp.true4669; GFX9-NEXT: v_mov_b32_e32 v0, 0x2004670; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]4671; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]4672; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]4673; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]4674; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4675; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4676; GFX9-NEXT: s_setpc_b64 s[30:31]4677; GFX9-NEXT: .LBB35_3:4678; GFX9-NEXT: s_branch .LBB35_24679; GFX9-NEXT: .LBB35_4:4680; GFX9-NEXT: v_mov_b32_e32 v0, s164681; GFX9-NEXT: v_mov_b32_e32 v1, s174682; GFX9-NEXT: v_mov_b32_e32 v2, s184683; GFX9-NEXT: v_mov_b32_e32 v3, s194684; GFX9-NEXT: v_mov_b32_e32 v4, s204685; GFX9-NEXT: v_mov_b32_e32 v5, s214686; GFX9-NEXT: s_setpc_b64 s[30:31]4687;4688; GFX11-LABEL: bitcast_v12f16_to_v6f32_scalar:4689; GFX11: ; %bb.0:4690; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4691; GFX11-NEXT: s_mov_b32 s5, s174692; GFX11-NEXT: s_mov_b32 s4, s164693; GFX11-NEXT: s_cmp_lg_u32 s18, 04694; GFX11-NEXT: s_mov_b32 s6, 04695; GFX11-NEXT: s_cbranch_scc0 .LBB35_34696; GFX11-NEXT: ; %bb.1: ; %Flow4697; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s64698; GFX11-NEXT: s_cbranch_vccnz .LBB35_44699; GFX11-NEXT: .LBB35_2: ; %cmp.true4700; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]4701; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]4702; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]4703; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]4704; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]4705; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]4706; GFX11-NEXT: s_setpc_b64 s[30:31]4707; GFX11-NEXT: .LBB35_3:4708; GFX11-NEXT: s_branch .LBB35_24709; GFX11-NEXT: .LBB35_4:4710; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14711; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s34712; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s54713; GFX11-NEXT: s_setpc_b64 s[30:31]4714 %cmp = icmp eq i32 %b, 04715 br i1 %cmp, label %cmp.true, label %cmp.false4716 4717cmp.true:4718 %a1 = fadd <12 x half> %a, splat (half 0xH0200)4719 %a2 = bitcast <12 x half> %a1 to <6 x float>4720 br label %end4721 4722cmp.false:4723 %a3 = bitcast <12 x half> %a to <6 x float>4724 br label %end4725 4726end:4727 %phi = phi <6 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4728 ret <6 x float> %phi4729}4730 4731define <3 x double> @bitcast_v3i64_to_v3f64(<3 x i64> %a, i32 %b) {4732; SI-LABEL: bitcast_v3i64_to_v3f64:4733; SI: ; %bb.0:4734; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4735; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64736; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4737; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4738; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4739; SI-NEXT: ; %bb.1: ; %cmp.true4740; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v04741; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4742; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v24743; SI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4744; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v44745; SI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4746; SI-NEXT: ; %bb.2: ; %end4747; SI-NEXT: s_or_b64 exec, exec, s[4:5]4748; SI-NEXT: s_setpc_b64 s[30:31]4749;4750; VI-LABEL: bitcast_v3i64_to_v3f64:4751; VI: ; %bb.0:4752; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4753; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64754; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4755; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4756; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4757; VI-NEXT: ; %bb.1: ; %cmp.true4758; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v04759; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc4760; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v24761; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc4762; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v44763; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc4764; VI-NEXT: ; %bb.2: ; %end4765; VI-NEXT: s_or_b64 exec, exec, s[4:5]4766; VI-NEXT: s_setpc_b64 s[30:31]4767;4768; GFX9-LABEL: bitcast_v3i64_to_v3f64:4769; GFX9: ; %bb.0:4770; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4771; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64772; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4773; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4774; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4775; GFX9-NEXT: ; %bb.1: ; %cmp.true4776; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v04777; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc4778; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v24779; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc4780; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v44781; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc4782; GFX9-NEXT: ; %bb.2: ; %end4783; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4784; GFX9-NEXT: s_setpc_b64 s[30:31]4785;4786; GFX11-LABEL: bitcast_v3i64_to_v3f64:4787; GFX11: ; %bb.0:4788; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4789; GFX11-NEXT: s_mov_b32 s0, exec_lo4790; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v64791; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04792; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4793; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04794; GFX11-NEXT: ; %bb.1: ; %cmp.true4795; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 34796; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)4797; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo4798; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 34799; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo4800; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 34801; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)4802; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo4803; GFX11-NEXT: ; %bb.2: ; %end4804; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04805; GFX11-NEXT: s_setpc_b64 s[30:31]4806 %cmp = icmp eq i32 %b, 04807 br i1 %cmp, label %cmp.true, label %cmp.false4808 4809cmp.true:4810 %a1 = add <3 x i64> %a, splat (i64 3)4811 %a2 = bitcast <3 x i64> %a1 to <3 x double>4812 br label %end4813 4814cmp.false:4815 %a3 = bitcast <3 x i64> %a to <3 x double>4816 br label %end4817 4818end:4819 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4820 ret <3 x double> %phi4821}4822 4823define inreg <3 x double> @bitcast_v3i64_to_v3f64_scalar(<3 x i64> inreg %a, i32 inreg %b) {4824; SI-LABEL: bitcast_v3i64_to_v3f64_scalar:4825; SI: ; %bb.0:4826; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4827; SI-NEXT: s_cmp_lg_u32 s22, 04828; SI-NEXT: s_cbranch_scc0 .LBB37_44829; SI-NEXT: ; %bb.1: ; %cmp.false4830; SI-NEXT: s_cbranch_execnz .LBB37_34831; SI-NEXT: .LBB37_2: ; %cmp.true4832; SI-NEXT: s_add_u32 s16, s16, 34833; SI-NEXT: s_addc_u32 s17, s17, 04834; SI-NEXT: s_add_u32 s18, s18, 34835; SI-NEXT: s_addc_u32 s19, s19, 04836; SI-NEXT: s_add_u32 s20, s20, 34837; SI-NEXT: s_addc_u32 s21, s21, 04838; SI-NEXT: .LBB37_3: ; %end4839; SI-NEXT: v_mov_b32_e32 v0, s164840; SI-NEXT: v_mov_b32_e32 v1, s174841; SI-NEXT: v_mov_b32_e32 v2, s184842; SI-NEXT: v_mov_b32_e32 v3, s194843; SI-NEXT: v_mov_b32_e32 v4, s204844; SI-NEXT: v_mov_b32_e32 v5, s214845; SI-NEXT: s_setpc_b64 s[30:31]4846; SI-NEXT: .LBB37_4:4847; SI-NEXT: s_branch .LBB37_24848;4849; VI-LABEL: bitcast_v3i64_to_v3f64_scalar:4850; VI: ; %bb.0:4851; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4852; VI-NEXT: s_cmp_lg_u32 s22, 04853; VI-NEXT: s_cbranch_scc0 .LBB37_44854; VI-NEXT: ; %bb.1: ; %cmp.false4855; VI-NEXT: s_cbranch_execnz .LBB37_34856; VI-NEXT: .LBB37_2: ; %cmp.true4857; VI-NEXT: s_add_u32 s16, s16, 34858; VI-NEXT: s_addc_u32 s17, s17, 04859; VI-NEXT: s_add_u32 s18, s18, 34860; VI-NEXT: s_addc_u32 s19, s19, 04861; VI-NEXT: s_add_u32 s20, s20, 34862; VI-NEXT: s_addc_u32 s21, s21, 04863; VI-NEXT: .LBB37_3: ; %end4864; VI-NEXT: v_mov_b32_e32 v0, s164865; VI-NEXT: v_mov_b32_e32 v1, s174866; VI-NEXT: v_mov_b32_e32 v2, s184867; VI-NEXT: v_mov_b32_e32 v3, s194868; VI-NEXT: v_mov_b32_e32 v4, s204869; VI-NEXT: v_mov_b32_e32 v5, s214870; VI-NEXT: s_setpc_b64 s[30:31]4871; VI-NEXT: .LBB37_4:4872; VI-NEXT: s_branch .LBB37_24873;4874; GFX9-LABEL: bitcast_v3i64_to_v3f64_scalar:4875; GFX9: ; %bb.0:4876; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4877; GFX9-NEXT: s_cmp_lg_u32 s22, 04878; GFX9-NEXT: s_cbranch_scc0 .LBB37_44879; GFX9-NEXT: ; %bb.1: ; %cmp.false4880; GFX9-NEXT: s_cbranch_execnz .LBB37_34881; GFX9-NEXT: .LBB37_2: ; %cmp.true4882; GFX9-NEXT: s_add_u32 s16, s16, 34883; GFX9-NEXT: s_addc_u32 s17, s17, 04884; GFX9-NEXT: s_add_u32 s18, s18, 34885; GFX9-NEXT: s_addc_u32 s19, s19, 04886; GFX9-NEXT: s_add_u32 s20, s20, 34887; GFX9-NEXT: s_addc_u32 s21, s21, 04888; GFX9-NEXT: .LBB37_3: ; %end4889; GFX9-NEXT: v_mov_b32_e32 v0, s164890; GFX9-NEXT: v_mov_b32_e32 v1, s174891; GFX9-NEXT: v_mov_b32_e32 v2, s184892; GFX9-NEXT: v_mov_b32_e32 v3, s194893; GFX9-NEXT: v_mov_b32_e32 v4, s204894; GFX9-NEXT: v_mov_b32_e32 v5, s214895; GFX9-NEXT: s_setpc_b64 s[30:31]4896; GFX9-NEXT: .LBB37_4:4897; GFX9-NEXT: s_branch .LBB37_24898;4899; GFX11-LABEL: bitcast_v3i64_to_v3f64_scalar:4900; GFX11: ; %bb.0:4901; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4902; GFX11-NEXT: s_cmp_lg_u32 s18, 04903; GFX11-NEXT: s_mov_b32 s4, 04904; GFX11-NEXT: s_cbranch_scc0 .LBB37_44905; GFX11-NEXT: ; %bb.1: ; %Flow4906; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s44907; GFX11-NEXT: s_cbranch_vccnz .LBB37_34908; GFX11-NEXT: .LBB37_2: ; %cmp.true4909; GFX11-NEXT: s_add_u32 s0, s0, 34910; GFX11-NEXT: s_addc_u32 s1, s1, 04911; GFX11-NEXT: s_add_u32 s2, s2, 34912; GFX11-NEXT: s_addc_u32 s3, s3, 04913; GFX11-NEXT: s_add_u32 s16, s16, 34914; GFX11-NEXT: s_addc_u32 s17, s17, 04915; GFX11-NEXT: .LBB37_3: ; %end4916; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14917; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s34918; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174919; GFX11-NEXT: s_setpc_b64 s[30:31]4920; GFX11-NEXT: .LBB37_4:4921; GFX11-NEXT: s_branch .LBB37_24922 %cmp = icmp eq i32 %b, 04923 br i1 %cmp, label %cmp.true, label %cmp.false4924 4925cmp.true:4926 %a1 = add <3 x i64> %a, splat (i64 3)4927 %a2 = bitcast <3 x i64> %a1 to <3 x double>4928 br label %end4929 4930cmp.false:4931 %a3 = bitcast <3 x i64> %a to <3 x double>4932 br label %end4933 4934end:4935 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4936 ret <3 x double> %phi4937}4938 4939define <3 x i64> @bitcast_v3f64_to_v3i64(<3 x double> %a, i32 %b) {4940; SI-LABEL: bitcast_v3f64_to_v3i64:4941; SI: ; %bb.0:4942; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4943; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64944; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4945; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4946; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4947; SI-NEXT: ; %bb.1: ; %cmp.true4948; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.04949; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.04950; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.04951; SI-NEXT: ; %bb.2: ; %end4952; SI-NEXT: s_or_b64 exec, exec, s[4:5]4953; SI-NEXT: s_setpc_b64 s[30:31]4954;4955; VI-LABEL: bitcast_v3f64_to_v3i64:4956; VI: ; %bb.0:4957; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4958; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64959; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4960; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4961; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4962; VI-NEXT: s_cbranch_execz .LBB38_24963; VI-NEXT: ; %bb.1: ; %cmp.true4964; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.04965; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.04966; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.04967; VI-NEXT: .LBB38_2: ; %end4968; VI-NEXT: s_or_b64 exec, exec, s[4:5]4969; VI-NEXT: s_setpc_b64 s[30:31]4970;4971; GFX9-LABEL: bitcast_v3f64_to_v3i64:4972; GFX9: ; %bb.0:4973; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4974; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v64975; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4976; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4977; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4978; GFX9-NEXT: s_cbranch_execz .LBB38_24979; GFX9-NEXT: ; %bb.1: ; %cmp.true4980; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.04981; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.04982; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.04983; GFX9-NEXT: .LBB38_2: ; %end4984; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4985; GFX9-NEXT: s_setpc_b64 s[30:31]4986;4987; GFX11-LABEL: bitcast_v3f64_to_v3i64:4988; GFX11: ; %bb.0:4989; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4990; GFX11-NEXT: s_mov_b32 s0, exec_lo4991; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v64992; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04993; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4994; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04995; GFX11-NEXT: s_cbranch_execz .LBB38_24996; GFX11-NEXT: ; %bb.1: ; %cmp.true4997; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.04998; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.04999; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.05000; GFX11-NEXT: .LBB38_2: ; %end5001; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05002; GFX11-NEXT: s_setpc_b64 s[30:31]5003 %cmp = icmp eq i32 %b, 05004 br i1 %cmp, label %cmp.true, label %cmp.false5005 5006cmp.true:5007 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)5008 %a2 = bitcast <3 x double> %a1 to <3 x i64>5009 br label %end5010 5011cmp.false:5012 %a3 = bitcast <3 x double> %a to <3 x i64>5013 br label %end5014 5015end:5016 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5017 ret <3 x i64> %phi5018}5019 5020define inreg <3 x i64> @bitcast_v3f64_to_v3i64_scalar(<3 x double> inreg %a, i32 inreg %b) {5021; SI-LABEL: bitcast_v3f64_to_v3i64_scalar:5022; SI: ; %bb.0:5023; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5024; SI-NEXT: s_cmp_lg_u32 s22, 05025; SI-NEXT: s_cbranch_scc0 .LBB39_35026; SI-NEXT: ; %bb.1: ; %cmp.false5027; SI-NEXT: s_cbranch_execnz .LBB39_45028; SI-NEXT: .LBB39_2: ; %cmp.true5029; SI-NEXT: v_add_f64 v[0:1], s[16:17], 1.05030; SI-NEXT: v_add_f64 v[2:3], s[18:19], 1.05031; SI-NEXT: v_add_f64 v[4:5], s[20:21], 1.05032; SI-NEXT: s_setpc_b64 s[30:31]5033; SI-NEXT: .LBB39_3:5034; SI-NEXT: s_branch .LBB39_25035; SI-NEXT: .LBB39_4:5036; SI-NEXT: v_mov_b32_e32 v0, s165037; SI-NEXT: v_mov_b32_e32 v1, s175038; SI-NEXT: v_mov_b32_e32 v2, s185039; SI-NEXT: v_mov_b32_e32 v3, s195040; SI-NEXT: v_mov_b32_e32 v4, s205041; SI-NEXT: v_mov_b32_e32 v5, s215042; SI-NEXT: s_setpc_b64 s[30:31]5043;5044; VI-LABEL: bitcast_v3f64_to_v3i64_scalar:5045; VI: ; %bb.0:5046; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5047; VI-NEXT: s_cmp_lg_u32 s22, 05048; VI-NEXT: s_cbranch_scc0 .LBB39_35049; VI-NEXT: ; %bb.1: ; %cmp.false5050; VI-NEXT: s_cbranch_execnz .LBB39_45051; VI-NEXT: .LBB39_2: ; %cmp.true5052; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.05053; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.05054; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.05055; VI-NEXT: s_setpc_b64 s[30:31]5056; VI-NEXT: .LBB39_3:5057; VI-NEXT: s_branch .LBB39_25058; VI-NEXT: .LBB39_4:5059; VI-NEXT: v_mov_b32_e32 v0, s165060; VI-NEXT: v_mov_b32_e32 v1, s175061; VI-NEXT: v_mov_b32_e32 v2, s185062; VI-NEXT: v_mov_b32_e32 v3, s195063; VI-NEXT: v_mov_b32_e32 v4, s205064; VI-NEXT: v_mov_b32_e32 v5, s215065; VI-NEXT: s_setpc_b64 s[30:31]5066;5067; GFX9-LABEL: bitcast_v3f64_to_v3i64_scalar:5068; GFX9: ; %bb.0:5069; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5070; GFX9-NEXT: s_cmp_lg_u32 s22, 05071; GFX9-NEXT: s_cbranch_scc0 .LBB39_35072; GFX9-NEXT: ; %bb.1: ; %cmp.false5073; GFX9-NEXT: s_cbranch_execnz .LBB39_45074; GFX9-NEXT: .LBB39_2: ; %cmp.true5075; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.05076; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.05077; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.05078; GFX9-NEXT: s_setpc_b64 s[30:31]5079; GFX9-NEXT: .LBB39_3:5080; GFX9-NEXT: s_branch .LBB39_25081; GFX9-NEXT: .LBB39_4:5082; GFX9-NEXT: v_mov_b32_e32 v0, s165083; GFX9-NEXT: v_mov_b32_e32 v1, s175084; GFX9-NEXT: v_mov_b32_e32 v2, s185085; GFX9-NEXT: v_mov_b32_e32 v3, s195086; GFX9-NEXT: v_mov_b32_e32 v4, s205087; GFX9-NEXT: v_mov_b32_e32 v5, s215088; GFX9-NEXT: s_setpc_b64 s[30:31]5089;5090; GFX11-LABEL: bitcast_v3f64_to_v3i64_scalar:5091; GFX11: ; %bb.0:5092; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5093; GFX11-NEXT: s_mov_b32 s5, s175094; GFX11-NEXT: s_mov_b32 s4, s165095; GFX11-NEXT: s_cmp_lg_u32 s18, 05096; GFX11-NEXT: s_mov_b32 s6, 05097; GFX11-NEXT: s_cbranch_scc0 .LBB39_35098; GFX11-NEXT: ; %bb.1: ; %Flow5099; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s65100; GFX11-NEXT: s_cbranch_vccnz .LBB39_45101; GFX11-NEXT: .LBB39_2: ; %cmp.true5102; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.05103; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.05104; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.05105; GFX11-NEXT: s_setpc_b64 s[30:31]5106; GFX11-NEXT: .LBB39_3:5107; GFX11-NEXT: s_branch .LBB39_25108; GFX11-NEXT: .LBB39_4:5109; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15110; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s35111; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s55112; GFX11-NEXT: s_setpc_b64 s[30:31]5113 %cmp = icmp eq i32 %b, 05114 br i1 %cmp, label %cmp.true, label %cmp.false5115 5116cmp.true:5117 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)5118 %a2 = bitcast <3 x double> %a1 to <3 x i64>5119 br label %end5120 5121cmp.false:5122 %a3 = bitcast <3 x double> %a to <3 x i64>5123 br label %end5124 5125end:5126 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5127 ret <3 x i64> %phi5128}5129 5130define <12 x i16> @bitcast_v3i64_to_v12i16(<3 x i64> %a, i32 %b) {5131; SI-LABEL: bitcast_v3i64_to_v12i16:5132; SI: ; %bb.0:5133; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5134; SI-NEXT: v_mov_b32_e32 v10, v55135; SI-NEXT: v_mov_b32_e32 v8, v45136; SI-NEXT: v_mov_b32_e32 v12, v35137; SI-NEXT: v_mov_b32_e32 v4, v25138; SI-NEXT: v_mov_b32_e32 v2, v15139; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65140; SI-NEXT: ; implicit-def: $vgpr15141; SI-NEXT: ; implicit-def: $vgpr35142; SI-NEXT: ; implicit-def: $vgpr55143; SI-NEXT: ; implicit-def: $vgpr75144; SI-NEXT: ; implicit-def: $vgpr95145; SI-NEXT: ; implicit-def: $vgpr115146; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5147; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5148; SI-NEXT: ; %bb.1: ; %cmp.false5149; SI-NEXT: v_alignbit_b32 v9, v10, v8, 165150; SI-NEXT: v_alignbit_b32 v5, v12, v4, 165151; SI-NEXT: v_alignbit_b32 v1, v2, v0, 165152; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v105153; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v125154; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25155; SI-NEXT: ; %bb.2: ; %Flow5156; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5157; SI-NEXT: s_cbranch_execz .LBB40_45158; SI-NEXT: ; %bb.3: ; %cmp.true5159; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v05160; SI-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc5161; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v45162; SI-NEXT: v_addc_u32_e32 v12, vcc, 0, v12, vcc5163; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v85164; SI-NEXT: v_addc_u32_e32 v10, vcc, 0, v10, vcc5165; SI-NEXT: v_alignbit_b32 v9, v10, v8, 165166; SI-NEXT: v_alignbit_b32 v5, v12, v4, 165167; SI-NEXT: v_alignbit_b32 v1, v2, v0, 165168; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v105169; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v125170; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v25171; SI-NEXT: .LBB40_4: ; %end5172; SI-NEXT: s_or_b64 exec, exec, s[4:5]5173; SI-NEXT: v_mov_b32_e32 v6, v125174; SI-NEXT: s_setpc_b64 s[30:31]5175;5176; VI-LABEL: bitcast_v3i64_to_v12i16:5177; VI: ; %bb.0:5178; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5179; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65180; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5181; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5182; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5183; VI-NEXT: ; %bb.1: ; %cmp.true5184; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v45185; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc5186; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v25187; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5188; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v05189; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5190; VI-NEXT: ; %bb.2: ; %end5191; VI-NEXT: s_or_b64 exec, exec, s[4:5]5192; VI-NEXT: s_setpc_b64 s[30:31]5193;5194; GFX9-LABEL: bitcast_v3i64_to_v12i16:5195; GFX9: ; %bb.0:5196; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5197; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65198; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc5199; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5200; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5201; GFX9-NEXT: ; %bb.1: ; %cmp.true5202; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v45203; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc5204; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v25205; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc5206; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v05207; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc5208; GFX9-NEXT: ; %bb.2: ; %end5209; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]5210; GFX9-NEXT: s_setpc_b64 s[30:31]5211;5212; GFX11-LABEL: bitcast_v3i64_to_v12i16:5213; GFX11: ; %bb.0:5214; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5215; GFX11-NEXT: s_mov_b32 s0, exec_lo5216; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v65217; GFX11-NEXT: s_xor_b32 s0, exec_lo, s05218; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5219; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s05220; GFX11-NEXT: ; %bb.1: ; %cmp.true5221; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 35222; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)5223; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo5224; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 35225; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo5226; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 35227; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)5228; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo5229; GFX11-NEXT: ; %bb.2: ; %end5230; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05231; GFX11-NEXT: s_setpc_b64 s[30:31]5232 %cmp = icmp eq i32 %b, 05233 br i1 %cmp, label %cmp.true, label %cmp.false5234 5235cmp.true:5236 %a1 = add <3 x i64> %a, splat (i64 3)5237 %a2 = bitcast <3 x i64> %a1 to <12 x i16>5238 br label %end5239 5240cmp.false:5241 %a3 = bitcast <3 x i64> %a to <12 x i16>5242 br label %end5243 5244end:5245 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5246 ret <12 x i16> %phi5247}5248 5249define inreg <12 x i16> @bitcast_v3i64_to_v12i16_scalar(<3 x i64> inreg %a, i32 inreg %b) {5250; SI-LABEL: bitcast_v3i64_to_v12i16_scalar:5251; SI: ; %bb.0:5252; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5253; SI-NEXT: s_cmp_lg_u32 s22, 05254; SI-NEXT: s_cbranch_scc0 .LBB41_45255; SI-NEXT: ; %bb.1: ; %cmp.false5256; SI-NEXT: s_lshr_b32 s12, s21, 165257; SI-NEXT: s_lshr_b32 s13, s19, 165258; SI-NEXT: s_lshr_b32 s14, s17, 165259; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 165260; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 165261; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 165262; SI-NEXT: s_cbranch_execnz .LBB41_35263; SI-NEXT: .LBB41_2: ; %cmp.true5264; SI-NEXT: s_add_u32 s20, s20, 35265; SI-NEXT: s_addc_u32 s21, s21, 05266; SI-NEXT: s_add_u32 s18, s18, 35267; SI-NEXT: s_addc_u32 s19, s19, 05268; SI-NEXT: s_add_u32 s16, s16, 35269; SI-NEXT: s_addc_u32 s17, s17, 05270; SI-NEXT: s_lshr_b32 s12, s21, 165271; SI-NEXT: s_lshr_b32 s13, s19, 165272; SI-NEXT: s_lshr_b32 s14, s17, 165273; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 165274; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 165275; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 165276; SI-NEXT: .LBB41_3: ; %end5277; SI-NEXT: v_mov_b32_e32 v0, s165278; SI-NEXT: v_mov_b32_e32 v1, s85279; SI-NEXT: v_mov_b32_e32 v2, s175280; SI-NEXT: v_mov_b32_e32 v3, s145281; SI-NEXT: v_mov_b32_e32 v4, s185282; SI-NEXT: v_mov_b32_e32 v5, s65283; SI-NEXT: v_mov_b32_e32 v6, s195284; SI-NEXT: v_mov_b32_e32 v7, s135285; SI-NEXT: v_mov_b32_e32 v8, s205286; SI-NEXT: v_mov_b32_e32 v9, s45287; SI-NEXT: v_mov_b32_e32 v10, s215288; SI-NEXT: v_mov_b32_e32 v11, s125289; SI-NEXT: s_setpc_b64 s[30:31]5290; SI-NEXT: .LBB41_4:5291; SI-NEXT: ; implicit-def: $sgpr85292; SI-NEXT: ; implicit-def: $sgpr145293; SI-NEXT: ; implicit-def: $sgpr65294; SI-NEXT: ; implicit-def: $sgpr135295; SI-NEXT: ; implicit-def: $sgpr45296; SI-NEXT: ; implicit-def: $sgpr125297; SI-NEXT: s_branch .LBB41_25298;5299; VI-LABEL: bitcast_v3i64_to_v12i16_scalar:5300; VI: ; %bb.0:5301; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5302; VI-NEXT: s_cmp_lg_u32 s22, 05303; VI-NEXT: s_cbranch_scc0 .LBB41_45304; VI-NEXT: ; %bb.1: ; %cmp.false5305; VI-NEXT: s_cbranch_execnz .LBB41_35306; VI-NEXT: .LBB41_2: ; %cmp.true5307; VI-NEXT: s_add_u32 s20, s20, 35308; VI-NEXT: s_addc_u32 s21, s21, 05309; VI-NEXT: s_add_u32 s18, s18, 35310; VI-NEXT: s_addc_u32 s19, s19, 05311; VI-NEXT: s_add_u32 s16, s16, 35312; VI-NEXT: s_addc_u32 s17, s17, 05313; VI-NEXT: .LBB41_3: ; %end5314; VI-NEXT: v_mov_b32_e32 v0, s165315; VI-NEXT: v_mov_b32_e32 v1, s175316; VI-NEXT: v_mov_b32_e32 v2, s185317; VI-NEXT: v_mov_b32_e32 v3, s195318; VI-NEXT: v_mov_b32_e32 v4, s205319; VI-NEXT: v_mov_b32_e32 v5, s215320; VI-NEXT: s_setpc_b64 s[30:31]5321; VI-NEXT: .LBB41_4:5322; VI-NEXT: s_branch .LBB41_25323;5324; GFX9-LABEL: bitcast_v3i64_to_v12i16_scalar:5325; GFX9: ; %bb.0:5326; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5327; GFX9-NEXT: s_cmp_lg_u32 s22, 05328; GFX9-NEXT: s_cbranch_scc0 .LBB41_45329; GFX9-NEXT: ; %bb.1: ; %cmp.false5330; GFX9-NEXT: s_cbranch_execnz .LBB41_35331; GFX9-NEXT: .LBB41_2: ; %cmp.true5332; GFX9-NEXT: s_add_u32 s20, s20, 35333; GFX9-NEXT: s_addc_u32 s21, s21, 05334; GFX9-NEXT: s_add_u32 s18, s18, 35335; GFX9-NEXT: s_addc_u32 s19, s19, 05336; GFX9-NEXT: s_add_u32 s16, s16, 35337; GFX9-NEXT: s_addc_u32 s17, s17, 05338; GFX9-NEXT: .LBB41_3: ; %end5339; GFX9-NEXT: v_mov_b32_e32 v0, s165340; GFX9-NEXT: v_mov_b32_e32 v1, s175341; GFX9-NEXT: v_mov_b32_e32 v2, s185342; GFX9-NEXT: v_mov_b32_e32 v3, s195343; GFX9-NEXT: v_mov_b32_e32 v4, s205344; GFX9-NEXT: v_mov_b32_e32 v5, s215345; GFX9-NEXT: s_setpc_b64 s[30:31]5346; GFX9-NEXT: .LBB41_4:5347; GFX9-NEXT: s_branch .LBB41_25348;5349; GFX11-LABEL: bitcast_v3i64_to_v12i16_scalar:5350; GFX11: ; %bb.0:5351; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5352; GFX11-NEXT: s_cmp_lg_u32 s18, 05353; GFX11-NEXT: s_mov_b32 s4, 05354; GFX11-NEXT: s_cbranch_scc0 .LBB41_45355; GFX11-NEXT: ; %bb.1: ; %Flow5356; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s45357; GFX11-NEXT: s_cbranch_vccnz .LBB41_35358; GFX11-NEXT: .LBB41_2: ; %cmp.true5359; GFX11-NEXT: s_add_u32 s16, s16, 35360; GFX11-NEXT: s_addc_u32 s17, s17, 05361; GFX11-NEXT: s_add_u32 s2, s2, 35362; GFX11-NEXT: s_addc_u32 s3, s3, 05363; GFX11-NEXT: s_add_u32 s0, s0, 35364; GFX11-NEXT: s_addc_u32 s1, s1, 05365; GFX11-NEXT: .LBB41_3: ; %end5366; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5367; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15368; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s35369; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s175370; GFX11-NEXT: s_setpc_b64 s[30:31]5371; GFX11-NEXT: .LBB41_4:5372; GFX11-NEXT: s_branch .LBB41_25373 %cmp = icmp eq i32 %b, 05374 br i1 %cmp, label %cmp.true, label %cmp.false5375 5376cmp.true:5377 %a1 = add <3 x i64> %a, splat (i64 3)5378 %a2 = bitcast <3 x i64> %a1 to <12 x i16>5379 br label %end5380 5381cmp.false:5382 %a3 = bitcast <3 x i64> %a to <12 x i16>5383 br label %end5384 5385end:5386 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5387 ret <12 x i16> %phi5388}5389 5390define <3 x i64> @bitcast_v12i16_to_v3i64(<12 x i16> %a, i32 %b) {5391; SI-LABEL: bitcast_v12i16_to_v3i64:5392; SI: ; %bb.0:5393; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5394; SI-NEXT: v_mov_b32_e32 v15, v45395; SI-NEXT: v_mov_b32_e32 v14, v25396; SI-NEXT: v_mov_b32_e32 v13, v05397; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v125398; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v15399; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v35400; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v55401; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v75402; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v95403; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v115404; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr55405; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5406; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5407; SI-NEXT: s_cbranch_execnz .LBB42_35408; SI-NEXT: ; %bb.1: ; %Flow5409; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5410; SI-NEXT: s_cbranch_execnz .LBB42_45411; SI-NEXT: .LBB42_2: ; %end5412; SI-NEXT: s_or_b64 exec, exec, s[4:5]5413; SI-NEXT: s_setpc_b64 s[30:31]5414; SI-NEXT: .LBB42_3: ; %cmp.false5415; SI-NEXT: v_and_b32_e32 v0, 0xffff, v135416; SI-NEXT: v_and_b32_e32 v1, 0xffff, v145417; SI-NEXT: v_and_b32_e32 v2, 0xffff, v155418; SI-NEXT: v_and_b32_e32 v3, 0xffff, v65419; SI-NEXT: v_and_b32_e32 v4, 0xffff, v85420; SI-NEXT: v_and_b32_e32 v5, 0xffff, v105421; SI-NEXT: v_or_b32_e32 v0, v0, v185422; SI-NEXT: v_or_b32_e32 v1, v1, v175423; SI-NEXT: v_or_b32_e32 v2, v2, v165424; SI-NEXT: v_or_b32_e32 v3, v3, v125425; SI-NEXT: v_or_b32_e32 v4, v4, v95426; SI-NEXT: v_or_b32_e32 v5, v5, v75427; SI-NEXT: ; implicit-def: $vgpr135428; SI-NEXT: ; implicit-def: $vgpr145429; SI-NEXT: ; implicit-def: $vgpr155430; SI-NEXT: ; implicit-def: $vgpr65431; SI-NEXT: ; implicit-def: $vgpr85432; SI-NEXT: ; implicit-def: $vgpr105433; SI-NEXT: ; implicit-def: $vgpr185434; SI-NEXT: ; implicit-def: $vgpr175435; SI-NEXT: ; implicit-def: $vgpr165436; SI-NEXT: ; implicit-def: $vgpr125437; SI-NEXT: ; implicit-def: $vgpr95438; SI-NEXT: ; implicit-def: $vgpr75439; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5440; SI-NEXT: s_cbranch_execz .LBB42_25441; SI-NEXT: .LBB42_4: ; %cmp.true5442; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v135443; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v145444; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v155445; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v65446; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v85447; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v105448; SI-NEXT: v_and_b32_e32 v0, 0xffff, v05449; SI-NEXT: v_and_b32_e32 v1, 0xffff, v15450; SI-NEXT: v_and_b32_e32 v2, 0xffff, v25451; SI-NEXT: v_and_b32_e32 v3, 0xffff, v35452; SI-NEXT: v_and_b32_e32 v4, 0xffff, v45453; SI-NEXT: v_and_b32_e32 v5, 0xffff, v55454; SI-NEXT: v_or_b32_e32 v0, v18, v05455; SI-NEXT: s_mov_b32 s6, 0x300005456; SI-NEXT: v_or_b32_e32 v1, v17, v15457; SI-NEXT: v_or_b32_e32 v2, v16, v25458; SI-NEXT: v_or_b32_e32 v3, v12, v35459; SI-NEXT: v_or_b32_e32 v4, v9, v45460; SI-NEXT: v_or_b32_e32 v5, v7, v55461; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v05462; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v15463; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v25464; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v35465; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v45466; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v55467; SI-NEXT: s_or_b64 exec, exec, s[4:5]5468; SI-NEXT: s_setpc_b64 s[30:31]5469;5470; VI-LABEL: bitcast_v12i16_to_v3i64:5471; VI: ; %bb.0:5472; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5473; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65474; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5475; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5476; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5477; VI-NEXT: s_cbranch_execz .LBB42_25478; VI-NEXT: ; %bb.1: ; %cmp.true5479; VI-NEXT: v_mov_b32_e32 v7, 35480; VI-NEXT: v_add_u16_e32 v6, 3, v55481; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5482; VI-NEXT: v_or_b32_e32 v5, v6, v55483; VI-NEXT: v_add_u16_e32 v6, 3, v45484; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5485; VI-NEXT: v_or_b32_e32 v4, v6, v45486; VI-NEXT: v_add_u16_e32 v6, 3, v35487; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5488; VI-NEXT: v_or_b32_e32 v3, v6, v35489; VI-NEXT: v_add_u16_e32 v6, 3, v25490; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5491; VI-NEXT: v_or_b32_e32 v2, v6, v25492; VI-NEXT: v_add_u16_e32 v6, 3, v15493; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5494; VI-NEXT: v_or_b32_e32 v1, v6, v15495; VI-NEXT: v_add_u16_e32 v6, 3, v05496; VI-NEXT: v_add_u16_sdwa v0, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5497; VI-NEXT: v_or_b32_e32 v0, v6, v05498; VI-NEXT: .LBB42_2: ; %end5499; VI-NEXT: s_or_b64 exec, exec, s[4:5]5500; VI-NEXT: s_setpc_b64 s[30:31]5501;5502; GFX9-LABEL: bitcast_v12i16_to_v3i64:5503; GFX9: ; %bb.0:5504; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5505; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65506; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc5507; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5508; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5509; GFX9-NEXT: ; %bb.1: ; %cmp.true5510; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]5511; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]5512; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]5513; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]5514; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]5515; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5516; GFX9-NEXT: ; %bb.2: ; %end5517; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]5518; GFX9-NEXT: s_setpc_b64 s[30:31]5519;5520; GFX11-LABEL: bitcast_v12i16_to_v3i64:5521; GFX11: ; %bb.0:5522; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5523; GFX11-NEXT: s_mov_b32 s0, exec_lo5524; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v65525; GFX11-NEXT: s_xor_b32 s0, exec_lo, s05526; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5527; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s05528; GFX11-NEXT: ; %bb.1: ; %cmp.true5529; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]5530; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]5531; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]5532; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]5533; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]5534; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5535; GFX11-NEXT: ; %bb.2: ; %end5536; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05537; GFX11-NEXT: s_setpc_b64 s[30:31]5538 %cmp = icmp eq i32 %b, 05539 br i1 %cmp, label %cmp.true, label %cmp.false5540 5541cmp.true:5542 %a1 = add <12 x i16> %a, splat (i16 3)5543 %a2 = bitcast <12 x i16> %a1 to <3 x i64>5544 br label %end5545 5546cmp.false:5547 %a3 = bitcast <12 x i16> %a to <3 x i64>5548 br label %end5549 5550end:5551 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5552 ret <3 x i64> %phi5553}5554 5555define inreg <3 x i64> @bitcast_v12i16_to_v3i64_scalar(<12 x i16> inreg %a, i32 inreg %b) {5556; SI-LABEL: bitcast_v12i16_to_v3i64_scalar:5557; SI: ; %bb.0:5558; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5559; SI-NEXT: s_cmp_lg_u32 s28, 05560; SI-NEXT: s_cbranch_scc0 .LBB43_45561; SI-NEXT: ; %bb.1: ; %cmp.false5562; SI-NEXT: s_and_b32 s4, s16, 0xffff5563; SI-NEXT: s_lshl_b32 s5, s17, 165564; SI-NEXT: s_or_b32 s4, s4, s55565; SI-NEXT: s_and_b32 s5, s18, 0xffff5566; SI-NEXT: s_lshl_b32 s6, s19, 165567; SI-NEXT: s_or_b32 s5, s5, s65568; SI-NEXT: s_and_b32 s6, s20, 0xffff5569; SI-NEXT: s_lshl_b32 s7, s21, 165570; SI-NEXT: s_or_b32 s6, s6, s75571; SI-NEXT: s_and_b32 s7, s22, 0xffff5572; SI-NEXT: s_lshl_b32 s8, s23, 165573; SI-NEXT: s_or_b32 s7, s7, s85574; SI-NEXT: s_and_b32 s8, s24, 0xffff5575; SI-NEXT: s_lshl_b32 s9, s25, 165576; SI-NEXT: s_or_b32 s8, s8, s95577; SI-NEXT: s_and_b32 s9, s26, 0xffff5578; SI-NEXT: s_lshl_b32 s10, s27, 165579; SI-NEXT: s_or_b32 s9, s9, s105580; SI-NEXT: s_cbranch_execnz .LBB43_35581; SI-NEXT: .LBB43_2: ; %cmp.true5582; SI-NEXT: s_add_i32 s16, s16, 35583; SI-NEXT: s_and_b32 s4, s16, 0xffff5584; SI-NEXT: s_lshl_b32 s5, s17, 165585; SI-NEXT: s_add_i32 s18, s18, 35586; SI-NEXT: s_or_b32 s4, s5, s45587; SI-NEXT: s_and_b32 s5, s18, 0xffff5588; SI-NEXT: s_lshl_b32 s6, s19, 165589; SI-NEXT: s_add_i32 s20, s20, 35590; SI-NEXT: s_or_b32 s5, s6, s55591; SI-NEXT: s_and_b32 s6, s20, 0xffff5592; SI-NEXT: s_lshl_b32 s7, s21, 165593; SI-NEXT: s_add_i32 s22, s22, 35594; SI-NEXT: s_or_b32 s6, s7, s65595; SI-NEXT: s_and_b32 s7, s22, 0xffff5596; SI-NEXT: s_lshl_b32 s8, s23, 165597; SI-NEXT: s_add_i32 s24, s24, 35598; SI-NEXT: s_or_b32 s7, s8, s75599; SI-NEXT: s_and_b32 s8, s24, 0xffff5600; SI-NEXT: s_lshl_b32 s9, s25, 165601; SI-NEXT: s_add_i32 s26, s26, 35602; SI-NEXT: s_or_b32 s8, s9, s85603; SI-NEXT: s_and_b32 s9, s26, 0xffff5604; SI-NEXT: s_lshl_b32 s10, s27, 165605; SI-NEXT: s_or_b32 s9, s10, s95606; SI-NEXT: s_add_i32 s4, s4, 0x300005607; SI-NEXT: s_add_i32 s5, s5, 0x300005608; SI-NEXT: s_add_i32 s6, s6, 0x300005609; SI-NEXT: s_add_i32 s7, s7, 0x300005610; SI-NEXT: s_add_i32 s8, s8, 0x300005611; SI-NEXT: s_add_i32 s9, s9, 0x300005612; SI-NEXT: .LBB43_3: ; %end5613; SI-NEXT: v_mov_b32_e32 v0, s45614; SI-NEXT: v_mov_b32_e32 v1, s55615; SI-NEXT: v_mov_b32_e32 v2, s65616; SI-NEXT: v_mov_b32_e32 v3, s75617; SI-NEXT: v_mov_b32_e32 v4, s85618; SI-NEXT: v_mov_b32_e32 v5, s95619; SI-NEXT: s_setpc_b64 s[30:31]5620; SI-NEXT: .LBB43_4:5621; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr95622; SI-NEXT: s_branch .LBB43_25623;5624; VI-LABEL: bitcast_v12i16_to_v3i64_scalar:5625; VI: ; %bb.0:5626; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5627; VI-NEXT: s_cmp_lg_u32 s22, 05628; VI-NEXT: s_cbranch_scc0 .LBB43_45629; VI-NEXT: ; %bb.1: ; %cmp.false5630; VI-NEXT: s_cbranch_execnz .LBB43_35631; VI-NEXT: .LBB43_2: ; %cmp.true5632; VI-NEXT: s_add_i32 s5, s21, 35633; VI-NEXT: s_and_b32 s4, s21, 0xffff00005634; VI-NEXT: s_and_b32 s5, s5, 0xffff5635; VI-NEXT: s_or_b32 s4, s4, s55636; VI-NEXT: s_add_i32 s5, s20, 35637; VI-NEXT: s_add_i32 s21, s4, 0x300005638; VI-NEXT: s_and_b32 s4, s20, 0xffff00005639; VI-NEXT: s_and_b32 s5, s5, 0xffff5640; VI-NEXT: s_or_b32 s4, s4, s55641; VI-NEXT: s_add_i32 s5, s19, 35642; VI-NEXT: s_add_i32 s20, s4, 0x300005643; VI-NEXT: s_and_b32 s4, s19, 0xffff00005644; VI-NEXT: s_and_b32 s5, s5, 0xffff5645; VI-NEXT: s_or_b32 s4, s4, s55646; VI-NEXT: s_add_i32 s5, s18, 35647; VI-NEXT: s_add_i32 s19, s4, 0x300005648; VI-NEXT: s_and_b32 s4, s18, 0xffff00005649; VI-NEXT: s_and_b32 s5, s5, 0xffff5650; VI-NEXT: s_or_b32 s4, s4, s55651; VI-NEXT: s_add_i32 s5, s17, 35652; VI-NEXT: s_add_i32 s18, s4, 0x300005653; VI-NEXT: s_and_b32 s4, s17, 0xffff00005654; VI-NEXT: s_and_b32 s5, s5, 0xffff5655; VI-NEXT: s_or_b32 s4, s4, s55656; VI-NEXT: s_add_i32 s5, s16, 35657; VI-NEXT: s_add_i32 s17, s4, 0x300005658; VI-NEXT: s_and_b32 s4, s16, 0xffff00005659; VI-NEXT: s_and_b32 s5, s5, 0xffff5660; VI-NEXT: s_or_b32 s4, s4, s55661; VI-NEXT: s_add_i32 s16, s4, 0x300005662; VI-NEXT: .LBB43_3: ; %end5663; VI-NEXT: v_mov_b32_e32 v0, s165664; VI-NEXT: v_mov_b32_e32 v1, s175665; VI-NEXT: v_mov_b32_e32 v2, s185666; VI-NEXT: v_mov_b32_e32 v3, s195667; VI-NEXT: v_mov_b32_e32 v4, s205668; VI-NEXT: v_mov_b32_e32 v5, s215669; VI-NEXT: s_setpc_b64 s[30:31]5670; VI-NEXT: .LBB43_4:5671; VI-NEXT: s_branch .LBB43_25672;5673; GFX9-LABEL: bitcast_v12i16_to_v3i64_scalar:5674; GFX9: ; %bb.0:5675; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5676; GFX9-NEXT: s_cmp_lg_u32 s22, 05677; GFX9-NEXT: s_cbranch_scc0 .LBB43_35678; GFX9-NEXT: ; %bb.1: ; %cmp.false5679; GFX9-NEXT: s_cbranch_execnz .LBB43_45680; GFX9-NEXT: .LBB43_2: ; %cmp.true5681; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]5682; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]5683; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]5684; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]5685; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]5686; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]5687; GFX9-NEXT: s_setpc_b64 s[30:31]5688; GFX9-NEXT: .LBB43_3:5689; GFX9-NEXT: s_branch .LBB43_25690; GFX9-NEXT: .LBB43_4:5691; GFX9-NEXT: v_mov_b32_e32 v0, s165692; GFX9-NEXT: v_mov_b32_e32 v1, s175693; GFX9-NEXT: v_mov_b32_e32 v2, s185694; GFX9-NEXT: v_mov_b32_e32 v3, s195695; GFX9-NEXT: v_mov_b32_e32 v4, s205696; GFX9-NEXT: v_mov_b32_e32 v5, s215697; GFX9-NEXT: s_setpc_b64 s[30:31]5698;5699; GFX11-LABEL: bitcast_v12i16_to_v3i64_scalar:5700; GFX11: ; %bb.0:5701; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5702; GFX11-NEXT: s_mov_b32 s5, s175703; GFX11-NEXT: s_mov_b32 s4, s165704; GFX11-NEXT: s_cmp_lg_u32 s18, 05705; GFX11-NEXT: s_mov_b32 s6, 05706; GFX11-NEXT: s_cbranch_scc0 .LBB43_35707; GFX11-NEXT: ; %bb.1: ; %Flow5708; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s65709; GFX11-NEXT: s_cbranch_vccnz .LBB43_45710; GFX11-NEXT: .LBB43_2: ; %cmp.true5711; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]5712; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]5713; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]5714; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]5715; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]5716; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]5717; GFX11-NEXT: s_setpc_b64 s[30:31]5718; GFX11-NEXT: .LBB43_3:5719; GFX11-NEXT: s_branch .LBB43_25720; GFX11-NEXT: .LBB43_4:5721; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s15722; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s35723; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s55724; GFX11-NEXT: s_setpc_b64 s[30:31]5725 %cmp = icmp eq i32 %b, 05726 br i1 %cmp, label %cmp.true, label %cmp.false5727 5728cmp.true:5729 %a1 = add <12 x i16> %a, splat (i16 3)5730 %a2 = bitcast <12 x i16> %a1 to <3 x i64>5731 br label %end5732 5733cmp.false:5734 %a3 = bitcast <12 x i16> %a to <3 x i64>5735 br label %end5736 5737end:5738 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5739 ret <3 x i64> %phi5740}5741 5742define <12 x half> @bitcast_v3i64_to_v12f16(<3 x i64> %a, i32 %b) {5743; SI-LABEL: bitcast_v3i64_to_v12f16:5744; SI: ; %bb.0:5745; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5746; SI-NEXT: v_mov_b32_e32 v13, v55747; SI-NEXT: v_mov_b32_e32 v12, v45748; SI-NEXT: v_mov_b32_e32 v15, v35749; SI-NEXT: v_mov_b32_e32 v14, v25750; SI-NEXT: v_mov_b32_e32 v17, v15751; SI-NEXT: v_mov_b32_e32 v16, v05752; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65753; SI-NEXT: ; implicit-def: $vgpr05754; SI-NEXT: ; implicit-def: $vgpr15755; SI-NEXT: ; implicit-def: $vgpr25756; SI-NEXT: ; implicit-def: $vgpr35757; SI-NEXT: ; implicit-def: $vgpr45758; SI-NEXT: ; implicit-def: $vgpr55759; SI-NEXT: ; implicit-def: $vgpr65760; SI-NEXT: ; implicit-def: $vgpr75761; SI-NEXT: ; implicit-def: $vgpr85762; SI-NEXT: ; implicit-def: $vgpr95763; SI-NEXT: ; implicit-def: $vgpr105764; SI-NEXT: ; implicit-def: $vgpr115765; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc5766; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5767; SI-NEXT: s_cbranch_execnz .LBB44_35768; SI-NEXT: ; %bb.1: ; %Flow5769; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5770; SI-NEXT: s_cbranch_execnz .LBB44_45771; SI-NEXT: .LBB44_2: ; %end5772; SI-NEXT: s_or_b64 exec, exec, s[4:5]5773; SI-NEXT: s_setpc_b64 s[30:31]5774; SI-NEXT: .LBB44_3: ; %cmp.false5775; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v135776; SI-NEXT: v_cvt_f32_f16_e32 v11, v05777; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v125778; SI-NEXT: v_cvt_f32_f16_e32 v9, v05779; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v155780; SI-NEXT: v_cvt_f32_f16_e32 v7, v05781; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v145782; SI-NEXT: v_cvt_f32_f16_e32 v5, v05783; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v175784; SI-NEXT: v_cvt_f32_f16_e32 v3, v05785; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v165786; SI-NEXT: v_cvt_f32_f16_e32 v1, v05787; SI-NEXT: v_cvt_f32_f16_e32 v10, v135788; SI-NEXT: v_cvt_f32_f16_e32 v8, v125789; SI-NEXT: v_cvt_f32_f16_e32 v6, v155790; SI-NEXT: v_cvt_f32_f16_e32 v4, v145791; SI-NEXT: v_cvt_f32_f16_e32 v2, v175792; SI-NEXT: v_cvt_f32_f16_e32 v0, v165793; SI-NEXT: ; implicit-def: $vgpr165794; SI-NEXT: ; implicit-def: $vgpr175795; SI-NEXT: ; implicit-def: $vgpr145796; SI-NEXT: ; implicit-def: $vgpr155797; SI-NEXT: ; implicit-def: $vgpr125798; SI-NEXT: ; implicit-def: $vgpr135799; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5800; SI-NEXT: s_cbranch_execz .LBB44_25801; SI-NEXT: .LBB44_4: ; %cmp.true5802; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v165803; SI-NEXT: v_addc_u32_e32 v1, vcc, 0, v17, vcc5804; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v145805; SI-NEXT: v_addc_u32_e32 v4, vcc, 0, v15, vcc5806; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v125807; SI-NEXT: v_addc_u32_e32 v8, vcc, 0, v13, vcc5808; SI-NEXT: v_lshrrev_b32_e32 v16, 16, v05809; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v15810; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v25811; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v45812; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v65813; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v85814; SI-NEXT: v_cvt_f32_f16_e32 v10, v85815; SI-NEXT: v_cvt_f32_f16_e32 v8, v65816; SI-NEXT: v_cvt_f32_f16_e32 v6, v45817; SI-NEXT: v_cvt_f32_f16_e32 v4, v25818; SI-NEXT: v_cvt_f32_f16_e32 v2, v15819; SI-NEXT: v_cvt_f32_f16_e32 v0, v05820; SI-NEXT: v_cvt_f32_f16_e32 v11, v115821; SI-NEXT: v_cvt_f32_f16_e32 v9, v95822; SI-NEXT: v_cvt_f32_f16_e32 v7, v75823; SI-NEXT: v_cvt_f32_f16_e32 v5, v55824; SI-NEXT: v_cvt_f32_f16_e32 v3, v35825; SI-NEXT: v_cvt_f32_f16_e32 v1, v165826; SI-NEXT: s_or_b64 exec, exec, s[4:5]5827; SI-NEXT: s_setpc_b64 s[30:31]5828;5829; VI-LABEL: bitcast_v3i64_to_v12f16:5830; VI: ; %bb.0:5831; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5832; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65833; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc5834; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5835; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5836; VI-NEXT: ; %bb.1: ; %cmp.true5837; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v45838; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc5839; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v25840; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc5841; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v05842; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc5843; VI-NEXT: ; %bb.2: ; %end5844; VI-NEXT: s_or_b64 exec, exec, s[4:5]5845; VI-NEXT: s_setpc_b64 s[30:31]5846;5847; GFX9-LABEL: bitcast_v3i64_to_v12f16:5848; GFX9: ; %bb.0:5849; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5850; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v65851; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc5852; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]5853; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]5854; GFX9-NEXT: ; %bb.1: ; %cmp.true5855; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 3, v45856; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc5857; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 3, v25858; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc5859; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 3, v05860; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc5861; GFX9-NEXT: ; %bb.2: ; %end5862; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]5863; GFX9-NEXT: s_setpc_b64 s[30:31]5864;5865; GFX11-LABEL: bitcast_v3i64_to_v12f16:5866; GFX11: ; %bb.0:5867; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5868; GFX11-NEXT: s_mov_b32 s0, exec_lo5869; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v65870; GFX11-NEXT: s_xor_b32 s0, exec_lo, s05871; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)5872; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s05873; GFX11-NEXT: ; %bb.1: ; %cmp.true5874; GFX11-NEXT: v_add_co_u32 v4, vcc_lo, v4, 35875; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)5876; GFX11-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v5, vcc_lo5877; GFX11-NEXT: v_add_co_u32 v2, vcc_lo, v2, 35878; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo5879; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, 35880; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)5881; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo5882; GFX11-NEXT: ; %bb.2: ; %end5883; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s05884; GFX11-NEXT: s_setpc_b64 s[30:31]5885 %cmp = icmp eq i32 %b, 05886 br i1 %cmp, label %cmp.true, label %cmp.false5887 5888cmp.true:5889 %a1 = add <3 x i64> %a, splat (i64 3)5890 %a2 = bitcast <3 x i64> %a1 to <12 x half>5891 br label %end5892 5893cmp.false:5894 %a3 = bitcast <3 x i64> %a to <12 x half>5895 br label %end5896 5897end:5898 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5899 ret <12 x half> %phi5900}5901 5902define inreg <12 x half> @bitcast_v3i64_to_v12f16_scalar(<3 x i64> inreg %a, i32 inreg %b) {5903; SI-LABEL: bitcast_v3i64_to_v12f16_scalar:5904; SI: ; %bb.0:5905; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5906; SI-NEXT: s_cmp_lg_u32 s22, 05907; SI-NEXT: s_cbranch_scc0 .LBB45_45908; SI-NEXT: ; %bb.1: ; %cmp.false5909; SI-NEXT: s_lshr_b32 s4, s21, 165910; SI-NEXT: v_cvt_f32_f16_e32 v11, s45911; SI-NEXT: s_lshr_b32 s4, s20, 165912; SI-NEXT: v_cvt_f32_f16_e32 v9, s45913; SI-NEXT: s_lshr_b32 s4, s19, 165914; SI-NEXT: v_cvt_f32_f16_e32 v7, s45915; SI-NEXT: s_lshr_b32 s4, s18, 165916; SI-NEXT: v_cvt_f32_f16_e32 v5, s45917; SI-NEXT: s_lshr_b32 s4, s17, 165918; SI-NEXT: v_cvt_f32_f16_e32 v3, s45919; SI-NEXT: s_lshr_b32 s4, s16, 165920; SI-NEXT: v_cvt_f32_f16_e32 v1, s45921; SI-NEXT: v_cvt_f32_f16_e32 v10, s215922; SI-NEXT: v_cvt_f32_f16_e32 v8, s205923; SI-NEXT: v_cvt_f32_f16_e32 v6, s195924; SI-NEXT: v_cvt_f32_f16_e32 v4, s185925; SI-NEXT: v_cvt_f32_f16_e32 v2, s175926; SI-NEXT: v_cvt_f32_f16_e32 v0, s165927; SI-NEXT: s_cbranch_execnz .LBB45_35928; SI-NEXT: .LBB45_2: ; %cmp.true5929; SI-NEXT: s_add_u32 s4, s16, 35930; SI-NEXT: s_addc_u32 s5, s17, 05931; SI-NEXT: s_lshr_b32 s6, s4, 165932; SI-NEXT: s_lshr_b32 s7, s5, 165933; SI-NEXT: s_add_u32 s8, s18, 35934; SI-NEXT: s_addc_u32 s9, s19, 05935; SI-NEXT: s_lshr_b32 s10, s8, 165936; SI-NEXT: s_lshr_b32 s11, s9, 165937; SI-NEXT: s_add_u32 s12, s20, 35938; SI-NEXT: s_addc_u32 s13, s21, 05939; SI-NEXT: s_lshr_b32 s14, s12, 165940; SI-NEXT: s_lshr_b32 s15, s13, 165941; SI-NEXT: v_cvt_f32_f16_e32 v10, s135942; SI-NEXT: v_cvt_f32_f16_e32 v8, s125943; SI-NEXT: v_cvt_f32_f16_e32 v6, s95944; SI-NEXT: v_cvt_f32_f16_e32 v4, s85945; SI-NEXT: v_cvt_f32_f16_e32 v2, s55946; SI-NEXT: v_cvt_f32_f16_e32 v0, s45947; SI-NEXT: v_cvt_f32_f16_e32 v11, s155948; SI-NEXT: v_cvt_f32_f16_e32 v9, s145949; SI-NEXT: v_cvt_f32_f16_e32 v7, s115950; SI-NEXT: v_cvt_f32_f16_e32 v5, s105951; SI-NEXT: v_cvt_f32_f16_e32 v3, s75952; SI-NEXT: v_cvt_f32_f16_e32 v1, s65953; SI-NEXT: .LBB45_3: ; %end5954; SI-NEXT: s_setpc_b64 s[30:31]5955; SI-NEXT: .LBB45_4:5956; SI-NEXT: ; implicit-def: $vgpr05957; SI-NEXT: ; implicit-def: $vgpr15958; SI-NEXT: ; implicit-def: $vgpr25959; SI-NEXT: ; implicit-def: $vgpr35960; SI-NEXT: ; implicit-def: $vgpr45961; SI-NEXT: ; implicit-def: $vgpr55962; SI-NEXT: ; implicit-def: $vgpr65963; SI-NEXT: ; implicit-def: $vgpr75964; SI-NEXT: ; implicit-def: $vgpr85965; SI-NEXT: ; implicit-def: $vgpr95966; SI-NEXT: ; implicit-def: $vgpr105967; SI-NEXT: ; implicit-def: $vgpr115968; SI-NEXT: s_branch .LBB45_25969;5970; VI-LABEL: bitcast_v3i64_to_v12f16_scalar:5971; VI: ; %bb.0:5972; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5973; VI-NEXT: s_cmp_lg_u32 s22, 05974; VI-NEXT: s_cbranch_scc0 .LBB45_45975; VI-NEXT: ; %bb.1: ; %cmp.false5976; VI-NEXT: s_cbranch_execnz .LBB45_35977; VI-NEXT: .LBB45_2: ; %cmp.true5978; VI-NEXT: s_add_u32 s20, s20, 35979; VI-NEXT: s_addc_u32 s21, s21, 05980; VI-NEXT: s_add_u32 s18, s18, 35981; VI-NEXT: s_addc_u32 s19, s19, 05982; VI-NEXT: s_add_u32 s16, s16, 35983; VI-NEXT: s_addc_u32 s17, s17, 05984; VI-NEXT: .LBB45_3: ; %end5985; VI-NEXT: v_mov_b32_e32 v0, s165986; VI-NEXT: v_mov_b32_e32 v1, s175987; VI-NEXT: v_mov_b32_e32 v2, s185988; VI-NEXT: v_mov_b32_e32 v3, s195989; VI-NEXT: v_mov_b32_e32 v4, s205990; VI-NEXT: v_mov_b32_e32 v5, s215991; VI-NEXT: s_setpc_b64 s[30:31]5992; VI-NEXT: .LBB45_4:5993; VI-NEXT: s_branch .LBB45_25994;5995; GFX9-LABEL: bitcast_v3i64_to_v12f16_scalar:5996; GFX9: ; %bb.0:5997; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5998; GFX9-NEXT: s_cmp_lg_u32 s22, 05999; GFX9-NEXT: s_cbranch_scc0 .LBB45_46000; GFX9-NEXT: ; %bb.1: ; %cmp.false6001; GFX9-NEXT: s_cbranch_execnz .LBB45_36002; GFX9-NEXT: .LBB45_2: ; %cmp.true6003; GFX9-NEXT: s_add_u32 s20, s20, 36004; GFX9-NEXT: s_addc_u32 s21, s21, 06005; GFX9-NEXT: s_add_u32 s18, s18, 36006; GFX9-NEXT: s_addc_u32 s19, s19, 06007; GFX9-NEXT: s_add_u32 s16, s16, 36008; GFX9-NEXT: s_addc_u32 s17, s17, 06009; GFX9-NEXT: .LBB45_3: ; %end6010; GFX9-NEXT: v_mov_b32_e32 v0, s166011; GFX9-NEXT: v_mov_b32_e32 v1, s176012; GFX9-NEXT: v_mov_b32_e32 v2, s186013; GFX9-NEXT: v_mov_b32_e32 v3, s196014; GFX9-NEXT: v_mov_b32_e32 v4, s206015; GFX9-NEXT: v_mov_b32_e32 v5, s216016; GFX9-NEXT: s_setpc_b64 s[30:31]6017; GFX9-NEXT: .LBB45_4:6018; GFX9-NEXT: s_branch .LBB45_26019;6020; GFX11-LABEL: bitcast_v3i64_to_v12f16_scalar:6021; GFX11: ; %bb.0:6022; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6023; GFX11-NEXT: s_cmp_lg_u32 s18, 06024; GFX11-NEXT: s_mov_b32 s4, 06025; GFX11-NEXT: s_cbranch_scc0 .LBB45_46026; GFX11-NEXT: ; %bb.1: ; %Flow6027; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s46028; GFX11-NEXT: s_cbranch_vccnz .LBB45_36029; GFX11-NEXT: .LBB45_2: ; %cmp.true6030; GFX11-NEXT: s_add_u32 s16, s16, 36031; GFX11-NEXT: s_addc_u32 s17, s17, 06032; GFX11-NEXT: s_add_u32 s2, s2, 36033; GFX11-NEXT: s_addc_u32 s3, s3, 06034; GFX11-NEXT: s_add_u32 s0, s0, 36035; GFX11-NEXT: s_addc_u32 s1, s1, 06036; GFX11-NEXT: .LBB45_3: ; %end6037; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6038; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s16039; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s36040; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s176041; GFX11-NEXT: s_setpc_b64 s[30:31]6042; GFX11-NEXT: .LBB45_4:6043; GFX11-NEXT: s_branch .LBB45_26044 %cmp = icmp eq i32 %b, 06045 br i1 %cmp, label %cmp.true, label %cmp.false6046 6047cmp.true:6048 %a1 = add <3 x i64> %a, splat (i64 3)6049 %a2 = bitcast <3 x i64> %a1 to <12 x half>6050 br label %end6051 6052cmp.false:6053 %a3 = bitcast <3 x i64> %a to <12 x half>6054 br label %end6055 6056end:6057 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6058 ret <12 x half> %phi6059}6060 6061define <3 x i64> @bitcast_v12f16_to_v3i64(<12 x half> %a, i32 %b) {6062; SI-LABEL: bitcast_v12f16_to_v3i64:6063; SI: ; %bb.0:6064; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6065; SI-NEXT: v_cvt_f16_f32_e32 v20, v16066; SI-NEXT: v_cvt_f16_f32_e32 v19, v06067; SI-NEXT: v_cvt_f16_f32_e32 v18, v36068; SI-NEXT: v_cvt_f16_f32_e32 v17, v26069; SI-NEXT: v_cvt_f16_f32_e32 v16, v56070; SI-NEXT: v_cvt_f16_f32_e32 v15, v46071; SI-NEXT: v_cvt_f16_f32_e32 v14, v76072; SI-NEXT: v_cvt_f16_f32_e32 v13, v66073; SI-NEXT: v_cvt_f16_f32_e32 v9, v96074; SI-NEXT: v_cvt_f16_f32_e32 v8, v86075; SI-NEXT: v_cvt_f16_f32_e32 v7, v116076; SI-NEXT: v_cvt_f16_f32_e32 v6, v106077; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v126078; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr56079; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc6080; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6081; SI-NEXT: s_cbranch_execnz .LBB46_36082; SI-NEXT: ; %bb.1: ; %Flow6083; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6084; SI-NEXT: s_cbranch_execnz .LBB46_46085; SI-NEXT: .LBB46_2: ; %end6086; SI-NEXT: s_or_b64 exec, exec, s[4:5]6087; SI-NEXT: s_setpc_b64 s[30:31]6088; SI-NEXT: .LBB46_3: ; %cmp.false6089; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v206090; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v186091; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v166092; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v146093; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v96094; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v76095; SI-NEXT: v_or_b32_e32 v0, v19, v06096; SI-NEXT: v_or_b32_e32 v1, v17, v16097; SI-NEXT: v_or_b32_e32 v2, v15, v26098; SI-NEXT: v_or_b32_e32 v3, v13, v36099; SI-NEXT: v_or_b32_e32 v4, v8, v46100; SI-NEXT: v_or_b32_e32 v5, v6, v56101; SI-NEXT: ; implicit-def: $vgpr206102; SI-NEXT: ; implicit-def: $vgpr196103; SI-NEXT: ; implicit-def: $vgpr186104; SI-NEXT: ; implicit-def: $vgpr176105; SI-NEXT: ; implicit-def: $vgpr166106; SI-NEXT: ; implicit-def: $vgpr156107; SI-NEXT: ; implicit-def: $vgpr146108; SI-NEXT: ; implicit-def: $vgpr136109; SI-NEXT: ; implicit-def: $vgpr96110; SI-NEXT: ; implicit-def: $vgpr86111; SI-NEXT: ; implicit-def: $vgpr76112; SI-NEXT: ; implicit-def: $vgpr66113; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6114; SI-NEXT: s_cbranch_execz .LBB46_26115; SI-NEXT: .LBB46_4: ; %cmp.true6116; SI-NEXT: v_cvt_f32_f16_e32 v0, v206117; SI-NEXT: v_cvt_f32_f16_e32 v1, v196118; SI-NEXT: v_cvt_f32_f16_e32 v2, v186119; SI-NEXT: v_cvt_f32_f16_e32 v3, v176120; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v06121; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v16122; SI-NEXT: v_cvt_f16_f32_e32 v0, v06123; SI-NEXT: v_cvt_f16_f32_e32 v1, v16124; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v26125; SI-NEXT: v_cvt_f16_f32_e32 v2, v26126; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v06127; SI-NEXT: v_or_b32_e32 v0, v1, v06128; SI-NEXT: v_cvt_f32_f16_e32 v1, v166129; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v36130; SI-NEXT: v_cvt_f16_f32_e32 v3, v36131; SI-NEXT: v_cvt_f32_f16_e32 v5, v136132; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v16133; SI-NEXT: v_cvt_f16_f32_e32 v4, v16134; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v26135; SI-NEXT: v_cvt_f32_f16_e32 v2, v156136; SI-NEXT: v_or_b32_e32 v1, v3, v16137; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46138; SI-NEXT: v_cvt_f32_f16_e32 v4, v146139; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v26140; SI-NEXT: v_cvt_f16_f32_e32 v2, v26141; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v56142; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v46143; SI-NEXT: v_cvt_f16_f32_e32 v4, v46144; SI-NEXT: v_cvt_f16_f32_e32 v5, v56145; SI-NEXT: v_cvt_f32_f16_e32 v9, v96146; SI-NEXT: v_or_b32_e32 v2, v2, v36147; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46148; SI-NEXT: v_cvt_f32_f16_e32 v4, v86149; SI-NEXT: v_cvt_f32_f16_e32 v7, v76150; SI-NEXT: v_cvt_f32_f16_e32 v6, v66151; SI-NEXT: v_or_b32_e32 v3, v5, v36152; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v96153; SI-NEXT: v_cvt_f16_f32_e32 v5, v56154; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v46155; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v76156; SI-NEXT: v_cvt_f16_f32_e32 v4, v46157; SI-NEXT: v_cvt_f16_f32_e32 v7, v76158; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v66159; SI-NEXT: v_cvt_f16_f32_e32 v6, v66160; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v56161; SI-NEXT: v_or_b32_e32 v4, v4, v56162; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v76163; SI-NEXT: v_or_b32_e32 v5, v6, v56164; SI-NEXT: s_or_b64 exec, exec, s[4:5]6165; SI-NEXT: s_setpc_b64 s[30:31]6166;6167; VI-LABEL: bitcast_v12f16_to_v3i64:6168; VI: ; %bb.0:6169; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6170; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66171; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc6172; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6173; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6174; VI-NEXT: s_cbranch_execz .LBB46_26175; VI-NEXT: ; %bb.1: ; %cmp.true6176; VI-NEXT: v_mov_b32_e32 v6, 0x2006177; VI-NEXT: v_add_f16_sdwa v7, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6178; VI-NEXT: v_add_f16_e32 v5, 0x200, v56179; VI-NEXT: v_or_b32_e32 v5, v5, v76180; VI-NEXT: v_add_f16_sdwa v7, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6181; VI-NEXT: v_add_f16_e32 v4, 0x200, v46182; VI-NEXT: v_or_b32_e32 v4, v4, v76183; VI-NEXT: v_add_f16_sdwa v7, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6184; VI-NEXT: v_add_f16_e32 v3, 0x200, v36185; VI-NEXT: v_or_b32_e32 v3, v3, v76186; VI-NEXT: v_add_f16_sdwa v7, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6187; VI-NEXT: v_add_f16_e32 v2, 0x200, v26188; VI-NEXT: v_or_b32_e32 v2, v2, v76189; VI-NEXT: v_add_f16_sdwa v7, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6190; VI-NEXT: v_add_f16_e32 v1, 0x200, v16191; VI-NEXT: v_add_f16_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6192; VI-NEXT: v_add_f16_e32 v0, 0x200, v06193; VI-NEXT: v_or_b32_e32 v1, v1, v76194; VI-NEXT: v_or_b32_e32 v0, v0, v66195; VI-NEXT: .LBB46_2: ; %end6196; VI-NEXT: s_or_b64 exec, exec, s[4:5]6197; VI-NEXT: s_setpc_b64 s[30:31]6198;6199; GFX9-LABEL: bitcast_v12f16_to_v3i64:6200; GFX9: ; %bb.0:6201; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6202; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66203; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc6204; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6205; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6206; GFX9-NEXT: ; %bb.1: ; %cmp.true6207; GFX9-NEXT: s_movk_i32 s6, 0x2006208; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]6209; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]6210; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]6211; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]6212; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]6213; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]6214; GFX9-NEXT: ; %bb.2: ; %end6215; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]6216; GFX9-NEXT: s_setpc_b64 s[30:31]6217;6218; GFX11-LABEL: bitcast_v12f16_to_v3i64:6219; GFX11: ; %bb.0:6220; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6221; GFX11-NEXT: s_mov_b32 s0, exec_lo6222; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v66223; GFX11-NEXT: s_xor_b32 s0, exec_lo, s06224; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6225; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s06226; GFX11-NEXT: ; %bb.1: ; %cmp.true6227; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]6228; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]6229; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]6230; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]6231; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]6232; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]6233; GFX11-NEXT: ; %bb.2: ; %end6234; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s06235; GFX11-NEXT: s_setpc_b64 s[30:31]6236 %cmp = icmp eq i32 %b, 06237 br i1 %cmp, label %cmp.true, label %cmp.false6238 6239cmp.true:6240 %a1 = fadd <12 x half> %a, splat (half 0xH0200)6241 %a2 = bitcast <12 x half> %a1 to <3 x i64>6242 br label %end6243 6244cmp.false:6245 %a3 = bitcast <12 x half> %a to <3 x i64>6246 br label %end6247 6248end:6249 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6250 ret <3 x i64> %phi6251}6252 6253define inreg <3 x i64> @bitcast_v12f16_to_v3i64_scalar(<12 x half> inreg %a, i32 inreg %b) {6254; SI-LABEL: bitcast_v12f16_to_v3i64_scalar:6255; SI: ; %bb.0:6256; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6257; SI-NEXT: v_cvt_f16_f32_e32 v17, s176258; SI-NEXT: v_cvt_f16_f32_e32 v16, s166259; SI-NEXT: v_cvt_f16_f32_e32 v15, s196260; SI-NEXT: v_cvt_f16_f32_e32 v14, s186261; SI-NEXT: v_cvt_f16_f32_e32 v13, s216262; SI-NEXT: v_cvt_f16_f32_e32 v12, s206263; SI-NEXT: v_cvt_f16_f32_e32 v11, s236264; SI-NEXT: v_cvt_f16_f32_e32 v10, s226265; SI-NEXT: v_cvt_f16_f32_e32 v9, s256266; SI-NEXT: v_cvt_f16_f32_e32 v8, s246267; SI-NEXT: v_cvt_f16_f32_e32 v7, s276268; SI-NEXT: v_cvt_f16_f32_e32 v6, s266269; SI-NEXT: s_cmp_lg_u32 s28, 06270; SI-NEXT: s_cbranch_scc0 .LBB47_46271; SI-NEXT: ; %bb.1: ; %cmp.false6272; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v176273; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v156274; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v136275; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v116276; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v96277; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v76278; SI-NEXT: v_or_b32_e32 v0, v16, v06279; SI-NEXT: v_or_b32_e32 v1, v14, v16280; SI-NEXT: v_or_b32_e32 v2, v12, v26281; SI-NEXT: v_or_b32_e32 v3, v10, v36282; SI-NEXT: v_or_b32_e32 v4, v8, v46283; SI-NEXT: v_or_b32_e32 v5, v6, v56284; SI-NEXT: s_cbranch_execnz .LBB47_36285; SI-NEXT: .LBB47_2: ; %cmp.true6286; SI-NEXT: v_cvt_f32_f16_e32 v0, v176287; SI-NEXT: v_cvt_f32_f16_e32 v1, v166288; SI-NEXT: v_cvt_f32_f16_e32 v2, v156289; SI-NEXT: v_cvt_f32_f16_e32 v3, v146290; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v06291; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v16292; SI-NEXT: v_cvt_f16_f32_e32 v0, v06293; SI-NEXT: v_cvt_f16_f32_e32 v1, v16294; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v26295; SI-NEXT: v_cvt_f16_f32_e32 v2, v26296; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v06297; SI-NEXT: v_or_b32_e32 v0, v1, v06298; SI-NEXT: v_cvt_f32_f16_e32 v1, v136299; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v36300; SI-NEXT: v_cvt_f16_f32_e32 v3, v36301; SI-NEXT: v_cvt_f32_f16_e32 v5, v106302; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v16303; SI-NEXT: v_cvt_f16_f32_e32 v4, v16304; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v26305; SI-NEXT: v_cvt_f32_f16_e32 v2, v126306; SI-NEXT: v_or_b32_e32 v1, v3, v16307; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46308; SI-NEXT: v_cvt_f32_f16_e32 v4, v116309; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v26310; SI-NEXT: v_cvt_f16_f32_e32 v2, v26311; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v56312; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v46313; SI-NEXT: v_cvt_f16_f32_e32 v4, v46314; SI-NEXT: v_cvt_f16_f32_e32 v5, v56315; SI-NEXT: v_cvt_f32_f16_e32 v9, v96316; SI-NEXT: v_or_b32_e32 v2, v2, v36317; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v46318; SI-NEXT: v_cvt_f32_f16_e32 v4, v86319; SI-NEXT: v_cvt_f32_f16_e32 v7, v76320; SI-NEXT: v_cvt_f32_f16_e32 v6, v66321; SI-NEXT: v_or_b32_e32 v3, v5, v36322; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v96323; SI-NEXT: v_cvt_f16_f32_e32 v5, v56324; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v46325; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v76326; SI-NEXT: v_cvt_f16_f32_e32 v4, v46327; SI-NEXT: v_cvt_f16_f32_e32 v7, v76328; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v66329; SI-NEXT: v_cvt_f16_f32_e32 v6, v66330; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v56331; SI-NEXT: v_or_b32_e32 v4, v4, v56332; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v76333; SI-NEXT: v_or_b32_e32 v5, v6, v56334; SI-NEXT: .LBB47_3: ; %end6335; SI-NEXT: s_setpc_b64 s[30:31]6336; SI-NEXT: .LBB47_4:6337; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr56338; SI-NEXT: s_branch .LBB47_26339;6340; VI-LABEL: bitcast_v12f16_to_v3i64_scalar:6341; VI: ; %bb.0:6342; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6343; VI-NEXT: s_cmp_lg_u32 s22, 06344; VI-NEXT: s_cbranch_scc0 .LBB47_36345; VI-NEXT: ; %bb.1: ; %cmp.false6346; VI-NEXT: s_cbranch_execnz .LBB47_46347; VI-NEXT: .LBB47_2: ; %cmp.true6348; VI-NEXT: s_lshr_b32 s4, s21, 166349; VI-NEXT: v_mov_b32_e32 v0, 0x2006350; VI-NEXT: v_mov_b32_e32 v1, s46351; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6352; VI-NEXT: v_add_f16_e32 v2, s21, v06353; VI-NEXT: s_lshr_b32 s4, s20, 166354; VI-NEXT: v_or_b32_e32 v5, v2, v16355; VI-NEXT: v_mov_b32_e32 v1, s46356; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6357; VI-NEXT: v_add_f16_e32 v2, s20, v06358; VI-NEXT: s_lshr_b32 s4, s19, 166359; VI-NEXT: v_or_b32_e32 v4, v2, v16360; VI-NEXT: v_mov_b32_e32 v1, s46361; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6362; VI-NEXT: v_add_f16_e32 v2, s19, v06363; VI-NEXT: s_lshr_b32 s4, s18, 166364; VI-NEXT: v_or_b32_e32 v3, v2, v16365; VI-NEXT: v_mov_b32_e32 v1, s46366; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6367; VI-NEXT: v_add_f16_e32 v2, s18, v06368; VI-NEXT: s_lshr_b32 s4, s17, 166369; VI-NEXT: v_or_b32_e32 v2, v2, v16370; VI-NEXT: v_mov_b32_e32 v1, s46371; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6372; VI-NEXT: v_add_f16_e32 v6, s17, v06373; VI-NEXT: s_lshr_b32 s4, s16, 166374; VI-NEXT: v_or_b32_e32 v1, v6, v16375; VI-NEXT: v_mov_b32_e32 v6, s46376; VI-NEXT: v_add_f16_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6377; VI-NEXT: v_add_f16_e32 v0, s16, v06378; VI-NEXT: v_or_b32_e32 v0, v0, v66379; VI-NEXT: s_setpc_b64 s[30:31]6380; VI-NEXT: .LBB47_3:6381; VI-NEXT: s_branch .LBB47_26382; VI-NEXT: .LBB47_4:6383; VI-NEXT: v_mov_b32_e32 v0, s166384; VI-NEXT: v_mov_b32_e32 v1, s176385; VI-NEXT: v_mov_b32_e32 v2, s186386; VI-NEXT: v_mov_b32_e32 v3, s196387; VI-NEXT: v_mov_b32_e32 v4, s206388; VI-NEXT: v_mov_b32_e32 v5, s216389; VI-NEXT: s_setpc_b64 s[30:31]6390;6391; GFX9-LABEL: bitcast_v12f16_to_v3i64_scalar:6392; GFX9: ; %bb.0:6393; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6394; GFX9-NEXT: s_cmp_lg_u32 s22, 06395; GFX9-NEXT: s_cbranch_scc0 .LBB47_36396; GFX9-NEXT: ; %bb.1: ; %cmp.false6397; GFX9-NEXT: s_cbranch_execnz .LBB47_46398; GFX9-NEXT: .LBB47_2: ; %cmp.true6399; GFX9-NEXT: v_mov_b32_e32 v0, 0x2006400; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]6401; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]6402; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]6403; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]6404; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]6405; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]6406; GFX9-NEXT: s_setpc_b64 s[30:31]6407; GFX9-NEXT: .LBB47_3:6408; GFX9-NEXT: s_branch .LBB47_26409; GFX9-NEXT: .LBB47_4:6410; GFX9-NEXT: v_mov_b32_e32 v0, s166411; GFX9-NEXT: v_mov_b32_e32 v1, s176412; GFX9-NEXT: v_mov_b32_e32 v2, s186413; GFX9-NEXT: v_mov_b32_e32 v3, s196414; GFX9-NEXT: v_mov_b32_e32 v4, s206415; GFX9-NEXT: v_mov_b32_e32 v5, s216416; GFX9-NEXT: s_setpc_b64 s[30:31]6417;6418; GFX11-LABEL: bitcast_v12f16_to_v3i64_scalar:6419; GFX11: ; %bb.0:6420; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6421; GFX11-NEXT: s_mov_b32 s5, s176422; GFX11-NEXT: s_mov_b32 s4, s166423; GFX11-NEXT: s_cmp_lg_u32 s18, 06424; GFX11-NEXT: s_mov_b32 s6, 06425; GFX11-NEXT: s_cbranch_scc0 .LBB47_36426; GFX11-NEXT: ; %bb.1: ; %Flow6427; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s66428; GFX11-NEXT: s_cbranch_vccnz .LBB47_46429; GFX11-NEXT: .LBB47_2: ; %cmp.true6430; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]6431; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]6432; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]6433; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]6434; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]6435; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]6436; GFX11-NEXT: s_setpc_b64 s[30:31]6437; GFX11-NEXT: .LBB47_3:6438; GFX11-NEXT: s_branch .LBB47_26439; GFX11-NEXT: .LBB47_4:6440; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s16441; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s36442; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s56443; GFX11-NEXT: s_setpc_b64 s[30:31]6444 %cmp = icmp eq i32 %b, 06445 br i1 %cmp, label %cmp.true, label %cmp.false6446 6447cmp.true:6448 %a1 = fadd <12 x half> %a, splat (half 0xH0200)6449 %a2 = bitcast <12 x half> %a1 to <3 x i64>6450 br label %end6451 6452cmp.false:6453 %a3 = bitcast <12 x half> %a to <3 x i64>6454 br label %end6455 6456end:6457 %phi = phi <3 x i64> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6458 ret <3 x i64> %phi6459}6460 6461define <12 x i16> @bitcast_v3f64_to_v12i16(<3 x double> %a, i32 %b) {6462; SI-LABEL: bitcast_v3f64_to_v12i16:6463; SI: ; %bb.0:6464; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6465; SI-NEXT: v_mov_b32_e32 v13, v56466; SI-NEXT: v_mov_b32_e32 v12, v46467; SI-NEXT: v_mov_b32_e32 v15, v36468; SI-NEXT: v_mov_b32_e32 v14, v26469; SI-NEXT: v_mov_b32_e32 v17, v16470; SI-NEXT: v_mov_b32_e32 v16, v06471; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66472; SI-NEXT: ; implicit-def: $vgpr16473; SI-NEXT: ; implicit-def: $vgpr36474; SI-NEXT: ; implicit-def: $vgpr56475; SI-NEXT: ; implicit-def: $vgpr76476; SI-NEXT: ; implicit-def: $vgpr96477; SI-NEXT: ; implicit-def: $vgpr116478; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc6479; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6480; SI-NEXT: ; %bb.1: ; %cmp.false6481; SI-NEXT: v_alignbit_b32 v9, v13, v12, 166482; SI-NEXT: v_alignbit_b32 v5, v15, v14, 166483; SI-NEXT: v_alignbit_b32 v1, v17, v16, 166484; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v136485; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v156486; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v176487; SI-NEXT: ; %bb.2: ; %Flow6488; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6489; SI-NEXT: s_cbranch_execz .LBB48_46490; SI-NEXT: ; %bb.3: ; %cmp.true6491; SI-NEXT: v_add_f64 v[16:17], v[16:17], 1.06492; SI-NEXT: v_add_f64 v[12:13], v[12:13], 1.06493; SI-NEXT: v_add_f64 v[14:15], v[14:15], 1.06494; SI-NEXT: v_alignbit_b32 v9, v13, v12, 166495; SI-NEXT: v_alignbit_b32 v5, v15, v14, 166496; SI-NEXT: v_alignbit_b32 v1, v17, v16, 166497; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v136498; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v156499; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v176500; SI-NEXT: .LBB48_4: ; %end6501; SI-NEXT: s_or_b64 exec, exec, s[4:5]6502; SI-NEXT: v_mov_b32_e32 v0, v166503; SI-NEXT: v_mov_b32_e32 v2, v176504; SI-NEXT: v_mov_b32_e32 v4, v146505; SI-NEXT: v_mov_b32_e32 v6, v156506; SI-NEXT: v_mov_b32_e32 v8, v126507; SI-NEXT: v_mov_b32_e32 v10, v136508; SI-NEXT: s_setpc_b64 s[30:31]6509;6510; VI-LABEL: bitcast_v3f64_to_v12i16:6511; VI: ; %bb.0:6512; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6513; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66514; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc6515; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6516; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6517; VI-NEXT: s_cbranch_execz .LBB48_26518; VI-NEXT: ; %bb.1: ; %cmp.true6519; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.06520; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.06521; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.06522; VI-NEXT: .LBB48_2: ; %end6523; VI-NEXT: s_or_b64 exec, exec, s[4:5]6524; VI-NEXT: s_setpc_b64 s[30:31]6525;6526; GFX9-LABEL: bitcast_v3f64_to_v12i16:6527; GFX9: ; %bb.0:6528; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6529; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66530; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc6531; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6532; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6533; GFX9-NEXT: s_cbranch_execz .LBB48_26534; GFX9-NEXT: ; %bb.1: ; %cmp.true6535; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.06536; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.06537; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.06538; GFX9-NEXT: .LBB48_2: ; %end6539; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]6540; GFX9-NEXT: s_setpc_b64 s[30:31]6541;6542; GFX11-LABEL: bitcast_v3f64_to_v12i16:6543; GFX11: ; %bb.0:6544; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6545; GFX11-NEXT: s_mov_b32 s0, exec_lo6546; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v66547; GFX11-NEXT: s_xor_b32 s0, exec_lo, s06548; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6549; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s06550; GFX11-NEXT: s_cbranch_execz .LBB48_26551; GFX11-NEXT: ; %bb.1: ; %cmp.true6552; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.06553; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.06554; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.06555; GFX11-NEXT: .LBB48_2: ; %end6556; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s06557; GFX11-NEXT: s_setpc_b64 s[30:31]6558 %cmp = icmp eq i32 %b, 06559 br i1 %cmp, label %cmp.true, label %cmp.false6560 6561cmp.true:6562 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)6563 %a2 = bitcast <3 x double> %a1 to <12 x i16>6564 br label %end6565 6566cmp.false:6567 %a3 = bitcast <3 x double> %a to <12 x i16>6568 br label %end6569 6570end:6571 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6572 ret <12 x i16> %phi6573}6574 6575define inreg <12 x i16> @bitcast_v3f64_to_v12i16_scalar(<3 x double> inreg %a, i32 inreg %b) {6576; SI-LABEL: bitcast_v3f64_to_v12i16_scalar:6577; SI: ; %bb.0:6578; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6579; SI-NEXT: s_cmp_lg_u32 s22, 06580; SI-NEXT: s_cbranch_scc0 .LBB49_36581; SI-NEXT: ; %bb.1: ; %cmp.false6582; SI-NEXT: s_lshr_b32 s14, s21, 166583; SI-NEXT: s_lshr_b32 s13, s19, 166584; SI-NEXT: s_lshr_b32 s12, s17, 166585; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 166586; SI-NEXT: s_lshr_b64 s[6:7], s[18:19], 166587; SI-NEXT: s_lshr_b64 s[8:9], s[16:17], 166588; SI-NEXT: s_cbranch_execnz .LBB49_46589; SI-NEXT: .LBB49_2: ; %cmp.true6590; SI-NEXT: v_add_f64 v[16:17], s[16:17], 1.06591; SI-NEXT: v_add_f64 v[12:13], s[20:21], 1.06592; SI-NEXT: v_add_f64 v[14:15], s[18:19], 1.06593; SI-NEXT: v_lshr_b64 v[9:10], v[12:13], 166594; SI-NEXT: v_lshr_b64 v[5:6], v[14:15], 166595; SI-NEXT: v_lshr_b64 v[1:2], v[16:17], 166596; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v136597; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v156598; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v176599; SI-NEXT: s_branch .LBB49_56600; SI-NEXT: .LBB49_3:6601; SI-NEXT: ; implicit-def: $sgpr86602; SI-NEXT: ; implicit-def: $sgpr126603; SI-NEXT: ; implicit-def: $sgpr66604; SI-NEXT: ; implicit-def: $sgpr136605; SI-NEXT: ; implicit-def: $sgpr46606; SI-NEXT: ; implicit-def: $sgpr146607; SI-NEXT: s_branch .LBB49_26608; SI-NEXT: .LBB49_4:6609; SI-NEXT: v_mov_b32_e32 v16, s166610; SI-NEXT: v_mov_b32_e32 v14, s186611; SI-NEXT: v_mov_b32_e32 v12, s206612; SI-NEXT: v_mov_b32_e32 v17, s176613; SI-NEXT: v_mov_b32_e32 v15, s196614; SI-NEXT: v_mov_b32_e32 v13, s216615; SI-NEXT: v_mov_b32_e32 v3, s126616; SI-NEXT: v_mov_b32_e32 v7, s136617; SI-NEXT: v_mov_b32_e32 v11, s146618; SI-NEXT: v_mov_b32_e32 v1, s86619; SI-NEXT: v_mov_b32_e32 v5, s66620; SI-NEXT: v_mov_b32_e32 v9, s46621; SI-NEXT: .LBB49_5: ; %end6622; SI-NEXT: v_mov_b32_e32 v0, v166623; SI-NEXT: v_mov_b32_e32 v2, v176624; SI-NEXT: v_mov_b32_e32 v4, v146625; SI-NEXT: v_mov_b32_e32 v6, v156626; SI-NEXT: v_mov_b32_e32 v8, v126627; SI-NEXT: v_mov_b32_e32 v10, v136628; SI-NEXT: s_setpc_b64 s[30:31]6629;6630; VI-LABEL: bitcast_v3f64_to_v12i16_scalar:6631; VI: ; %bb.0:6632; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6633; VI-NEXT: s_cmp_lg_u32 s22, 06634; VI-NEXT: s_cbranch_scc0 .LBB49_36635; VI-NEXT: ; %bb.1: ; %cmp.false6636; VI-NEXT: s_cbranch_execnz .LBB49_46637; VI-NEXT: .LBB49_2: ; %cmp.true6638; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.06639; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.06640; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.06641; VI-NEXT: s_setpc_b64 s[30:31]6642; VI-NEXT: .LBB49_3:6643; VI-NEXT: s_branch .LBB49_26644; VI-NEXT: .LBB49_4:6645; VI-NEXT: v_mov_b32_e32 v0, s166646; VI-NEXT: v_mov_b32_e32 v1, s176647; VI-NEXT: v_mov_b32_e32 v2, s186648; VI-NEXT: v_mov_b32_e32 v3, s196649; VI-NEXT: v_mov_b32_e32 v4, s206650; VI-NEXT: v_mov_b32_e32 v5, s216651; VI-NEXT: v_mov_b32_e32 v6, s226652; VI-NEXT: v_mov_b32_e32 v7, s236653; VI-NEXT: s_setpc_b64 s[30:31]6654;6655; GFX9-LABEL: bitcast_v3f64_to_v12i16_scalar:6656; GFX9: ; %bb.0:6657; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6658; GFX9-NEXT: s_cmp_lg_u32 s22, 06659; GFX9-NEXT: s_cbranch_scc0 .LBB49_36660; GFX9-NEXT: ; %bb.1: ; %cmp.false6661; GFX9-NEXT: s_cbranch_execnz .LBB49_46662; GFX9-NEXT: .LBB49_2: ; %cmp.true6663; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.06664; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.06665; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.06666; GFX9-NEXT: s_setpc_b64 s[30:31]6667; GFX9-NEXT: .LBB49_3:6668; GFX9-NEXT: s_branch .LBB49_26669; GFX9-NEXT: .LBB49_4:6670; GFX9-NEXT: v_mov_b32_e32 v0, s166671; GFX9-NEXT: v_mov_b32_e32 v1, s176672; GFX9-NEXT: v_mov_b32_e32 v2, s186673; GFX9-NEXT: v_mov_b32_e32 v3, s196674; GFX9-NEXT: v_mov_b32_e32 v4, s206675; GFX9-NEXT: v_mov_b32_e32 v5, s216676; GFX9-NEXT: v_mov_b32_e32 v6, s226677; GFX9-NEXT: v_mov_b32_e32 v7, s236678; GFX9-NEXT: s_setpc_b64 s[30:31]6679;6680; GFX11-LABEL: bitcast_v3f64_to_v12i16_scalar:6681; GFX11: ; %bb.0:6682; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6683; GFX11-NEXT: s_mov_b32 s5, s176684; GFX11-NEXT: s_mov_b32 s4, s166685; GFX11-NEXT: s_cmp_lg_u32 s18, 06686; GFX11-NEXT: s_mov_b32 s8, 06687; GFX11-NEXT: s_cbranch_scc0 .LBB49_36688; GFX11-NEXT: ; %bb.1: ; %Flow6689; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s86690; GFX11-NEXT: s_cbranch_vccnz .LBB49_46691; GFX11-NEXT: .LBB49_2: ; %cmp.true6692; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.06693; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.06694; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.06695; GFX11-NEXT: s_setpc_b64 s[30:31]6696; GFX11-NEXT: .LBB49_3:6697; GFX11-NEXT: s_branch .LBB49_26698; GFX11-NEXT: .LBB49_4:6699; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s16700; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s36701; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s56702; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s76703; GFX11-NEXT: s_setpc_b64 s[30:31]6704 %cmp = icmp eq i32 %b, 06705 br i1 %cmp, label %cmp.true, label %cmp.false6706 6707cmp.true:6708 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)6709 %a2 = bitcast <3 x double> %a1 to <12 x i16>6710 br label %end6711 6712cmp.false:6713 %a3 = bitcast <3 x double> %a to <12 x i16>6714 br label %end6715 6716end:6717 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6718 ret <12 x i16> %phi6719}6720 6721define <3 x double> @bitcast_v12i16_to_v3f64(<12 x i16> %a, i32 %b) {6722; SI-LABEL: bitcast_v12i16_to_v3f64:6723; SI: ; %bb.0:6724; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6725; SI-NEXT: v_mov_b32_e32 v15, v46726; SI-NEXT: v_mov_b32_e32 v14, v26727; SI-NEXT: v_mov_b32_e32 v13, v06728; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v126729; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v16730; SI-NEXT: v_lshlrev_b32_e32 v17, 16, v36731; SI-NEXT: v_lshlrev_b32_e32 v16, 16, v56732; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v76733; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v96734; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v116735; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr56736; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc6737; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6738; SI-NEXT: s_cbranch_execnz .LBB50_36739; SI-NEXT: ; %bb.1: ; %Flow6740; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6741; SI-NEXT: s_cbranch_execnz .LBB50_46742; SI-NEXT: .LBB50_2: ; %end6743; SI-NEXT: s_or_b64 exec, exec, s[4:5]6744; SI-NEXT: s_setpc_b64 s[30:31]6745; SI-NEXT: .LBB50_3: ; %cmp.false6746; SI-NEXT: v_and_b32_e32 v0, 0xffff, v136747; SI-NEXT: v_and_b32_e32 v1, 0xffff, v146748; SI-NEXT: v_and_b32_e32 v2, 0xffff, v156749; SI-NEXT: v_and_b32_e32 v3, 0xffff, v66750; SI-NEXT: v_and_b32_e32 v4, 0xffff, v86751; SI-NEXT: v_and_b32_e32 v5, 0xffff, v106752; SI-NEXT: v_or_b32_e32 v0, v0, v186753; SI-NEXT: v_or_b32_e32 v1, v1, v176754; SI-NEXT: v_or_b32_e32 v2, v2, v166755; SI-NEXT: v_or_b32_e32 v3, v3, v126756; SI-NEXT: v_or_b32_e32 v4, v4, v96757; SI-NEXT: v_or_b32_e32 v5, v5, v76758; SI-NEXT: ; implicit-def: $vgpr136759; SI-NEXT: ; implicit-def: $vgpr146760; SI-NEXT: ; implicit-def: $vgpr156761; SI-NEXT: ; implicit-def: $vgpr66762; SI-NEXT: ; implicit-def: $vgpr86763; SI-NEXT: ; implicit-def: $vgpr106764; SI-NEXT: ; implicit-def: $vgpr186765; SI-NEXT: ; implicit-def: $vgpr176766; SI-NEXT: ; implicit-def: $vgpr166767; SI-NEXT: ; implicit-def: $vgpr126768; SI-NEXT: ; implicit-def: $vgpr96769; SI-NEXT: ; implicit-def: $vgpr76770; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6771; SI-NEXT: s_cbranch_execz .LBB50_26772; SI-NEXT: .LBB50_4: ; %cmp.true6773; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v136774; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v146775; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v156776; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v66777; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v86778; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v106779; SI-NEXT: v_and_b32_e32 v0, 0xffff, v06780; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16781; SI-NEXT: v_and_b32_e32 v2, 0xffff, v26782; SI-NEXT: v_and_b32_e32 v3, 0xffff, v36783; SI-NEXT: v_and_b32_e32 v4, 0xffff, v46784; SI-NEXT: v_and_b32_e32 v5, 0xffff, v56785; SI-NEXT: v_or_b32_e32 v0, v18, v06786; SI-NEXT: s_mov_b32 s6, 0x300006787; SI-NEXT: v_or_b32_e32 v1, v17, v16788; SI-NEXT: v_or_b32_e32 v2, v16, v26789; SI-NEXT: v_or_b32_e32 v3, v12, v36790; SI-NEXT: v_or_b32_e32 v4, v9, v46791; SI-NEXT: v_or_b32_e32 v5, v7, v56792; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v06793; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v16794; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v26795; SI-NEXT: v_add_i32_e32 v3, vcc, 0x30000, v36796; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v46797; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v56798; SI-NEXT: s_or_b64 exec, exec, s[4:5]6799; SI-NEXT: s_setpc_b64 s[30:31]6800;6801; VI-LABEL: bitcast_v12i16_to_v3f64:6802; VI: ; %bb.0:6803; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6804; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66805; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc6806; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6807; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6808; VI-NEXT: s_cbranch_execz .LBB50_26809; VI-NEXT: ; %bb.1: ; %cmp.true6810; VI-NEXT: v_mov_b32_e32 v7, 36811; VI-NEXT: v_add_u16_e32 v6, 3, v56812; VI-NEXT: v_add_u16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6813; VI-NEXT: v_or_b32_e32 v5, v6, v56814; VI-NEXT: v_add_u16_e32 v6, 3, v46815; VI-NEXT: v_add_u16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6816; VI-NEXT: v_or_b32_e32 v4, v6, v46817; VI-NEXT: v_add_u16_e32 v6, 3, v36818; VI-NEXT: v_add_u16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6819; VI-NEXT: v_or_b32_e32 v3, v6, v36820; VI-NEXT: v_add_u16_e32 v6, 3, v26821; VI-NEXT: v_add_u16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6822; VI-NEXT: v_or_b32_e32 v2, v6, v26823; VI-NEXT: v_add_u16_e32 v6, 3, v16824; VI-NEXT: v_add_u16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6825; VI-NEXT: v_or_b32_e32 v1, v6, v16826; VI-NEXT: v_add_u16_e32 v6, 3, v06827; VI-NEXT: v_add_u16_sdwa v0, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6828; VI-NEXT: v_or_b32_e32 v0, v6, v06829; VI-NEXT: .LBB50_2: ; %end6830; VI-NEXT: s_or_b64 exec, exec, s[4:5]6831; VI-NEXT: s_setpc_b64 s[30:31]6832;6833; GFX9-LABEL: bitcast_v12i16_to_v3f64:6834; GFX9: ; %bb.0:6835; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6836; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v66837; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc6838; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]6839; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]6840; GFX9-NEXT: ; %bb.1: ; %cmp.true6841; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]6842; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]6843; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]6844; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]6845; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]6846; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6847; GFX9-NEXT: ; %bb.2: ; %end6848; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]6849; GFX9-NEXT: s_setpc_b64 s[30:31]6850;6851; GFX11-LABEL: bitcast_v12i16_to_v3f64:6852; GFX11: ; %bb.0:6853; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6854; GFX11-NEXT: s_mov_b32 s0, exec_lo6855; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v66856; GFX11-NEXT: s_xor_b32 s0, exec_lo, s06857; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)6858; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s06859; GFX11-NEXT: ; %bb.1: ; %cmp.true6860; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]6861; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]6862; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]6863; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]6864; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]6865; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6866; GFX11-NEXT: ; %bb.2: ; %end6867; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s06868; GFX11-NEXT: s_setpc_b64 s[30:31]6869 %cmp = icmp eq i32 %b, 06870 br i1 %cmp, label %cmp.true, label %cmp.false6871 6872cmp.true:6873 %a1 = add <12 x i16> %a, splat (i16 3)6874 %a2 = bitcast <12 x i16> %a1 to <3 x double>6875 br label %end6876 6877cmp.false:6878 %a3 = bitcast <12 x i16> %a to <3 x double>6879 br label %end6880 6881end:6882 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6883 ret <3 x double> %phi6884}6885 6886define inreg <3 x double> @bitcast_v12i16_to_v3f64_scalar(<12 x i16> inreg %a, i32 inreg %b) {6887; SI-LABEL: bitcast_v12i16_to_v3f64_scalar:6888; SI: ; %bb.0:6889; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6890; SI-NEXT: s_cmp_lg_u32 s28, 06891; SI-NEXT: s_cbranch_scc0 .LBB51_46892; SI-NEXT: ; %bb.1: ; %cmp.false6893; SI-NEXT: s_and_b32 s4, s16, 0xffff6894; SI-NEXT: s_lshl_b32 s5, s17, 166895; SI-NEXT: s_or_b32 s4, s4, s56896; SI-NEXT: s_and_b32 s5, s18, 0xffff6897; SI-NEXT: s_lshl_b32 s6, s19, 166898; SI-NEXT: s_or_b32 s5, s5, s66899; SI-NEXT: s_and_b32 s6, s20, 0xffff6900; SI-NEXT: s_lshl_b32 s7, s21, 166901; SI-NEXT: s_or_b32 s6, s6, s76902; SI-NEXT: s_and_b32 s7, s22, 0xffff6903; SI-NEXT: s_lshl_b32 s8, s23, 166904; SI-NEXT: s_or_b32 s7, s7, s86905; SI-NEXT: s_and_b32 s8, s24, 0xffff6906; SI-NEXT: s_lshl_b32 s9, s25, 166907; SI-NEXT: s_or_b32 s8, s8, s96908; SI-NEXT: s_and_b32 s9, s26, 0xffff6909; SI-NEXT: s_lshl_b32 s10, s27, 166910; SI-NEXT: s_or_b32 s9, s9, s106911; SI-NEXT: s_cbranch_execnz .LBB51_36912; SI-NEXT: .LBB51_2: ; %cmp.true6913; SI-NEXT: s_add_i32 s16, s16, 36914; SI-NEXT: s_and_b32 s4, s16, 0xffff6915; SI-NEXT: s_lshl_b32 s5, s17, 166916; SI-NEXT: s_add_i32 s18, s18, 36917; SI-NEXT: s_or_b32 s4, s5, s46918; SI-NEXT: s_and_b32 s5, s18, 0xffff6919; SI-NEXT: s_lshl_b32 s6, s19, 166920; SI-NEXT: s_add_i32 s20, s20, 36921; SI-NEXT: s_or_b32 s5, s6, s56922; SI-NEXT: s_and_b32 s6, s20, 0xffff6923; SI-NEXT: s_lshl_b32 s7, s21, 166924; SI-NEXT: s_add_i32 s22, s22, 36925; SI-NEXT: s_or_b32 s6, s7, s66926; SI-NEXT: s_and_b32 s7, s22, 0xffff6927; SI-NEXT: s_lshl_b32 s8, s23, 166928; SI-NEXT: s_add_i32 s24, s24, 36929; SI-NEXT: s_or_b32 s7, s8, s76930; SI-NEXT: s_and_b32 s8, s24, 0xffff6931; SI-NEXT: s_lshl_b32 s9, s25, 166932; SI-NEXT: s_add_i32 s26, s26, 36933; SI-NEXT: s_or_b32 s8, s9, s86934; SI-NEXT: s_and_b32 s9, s26, 0xffff6935; SI-NEXT: s_lshl_b32 s10, s27, 166936; SI-NEXT: s_or_b32 s9, s10, s96937; SI-NEXT: s_add_i32 s4, s4, 0x300006938; SI-NEXT: s_add_i32 s5, s5, 0x300006939; SI-NEXT: s_add_i32 s6, s6, 0x300006940; SI-NEXT: s_add_i32 s7, s7, 0x300006941; SI-NEXT: s_add_i32 s8, s8, 0x300006942; SI-NEXT: s_add_i32 s9, s9, 0x300006943; SI-NEXT: .LBB51_3: ; %end6944; SI-NEXT: v_mov_b32_e32 v0, s46945; SI-NEXT: v_mov_b32_e32 v1, s56946; SI-NEXT: v_mov_b32_e32 v2, s66947; SI-NEXT: v_mov_b32_e32 v3, s76948; SI-NEXT: v_mov_b32_e32 v4, s86949; SI-NEXT: v_mov_b32_e32 v5, s96950; SI-NEXT: s_setpc_b64 s[30:31]6951; SI-NEXT: .LBB51_4:6952; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr96953; SI-NEXT: s_branch .LBB51_26954;6955; VI-LABEL: bitcast_v12i16_to_v3f64_scalar:6956; VI: ; %bb.0:6957; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6958; VI-NEXT: s_cmp_lg_u32 s22, 06959; VI-NEXT: s_cbranch_scc0 .LBB51_46960; VI-NEXT: ; %bb.1: ; %cmp.false6961; VI-NEXT: s_cbranch_execnz .LBB51_36962; VI-NEXT: .LBB51_2: ; %cmp.true6963; VI-NEXT: s_add_i32 s5, s21, 36964; VI-NEXT: s_and_b32 s4, s21, 0xffff00006965; VI-NEXT: s_and_b32 s5, s5, 0xffff6966; VI-NEXT: s_or_b32 s4, s4, s56967; VI-NEXT: s_add_i32 s5, s20, 36968; VI-NEXT: s_add_i32 s21, s4, 0x300006969; VI-NEXT: s_and_b32 s4, s20, 0xffff00006970; VI-NEXT: s_and_b32 s5, s5, 0xffff6971; VI-NEXT: s_or_b32 s4, s4, s56972; VI-NEXT: s_add_i32 s5, s19, 36973; VI-NEXT: s_add_i32 s20, s4, 0x300006974; VI-NEXT: s_and_b32 s4, s19, 0xffff00006975; VI-NEXT: s_and_b32 s5, s5, 0xffff6976; VI-NEXT: s_or_b32 s4, s4, s56977; VI-NEXT: s_add_i32 s5, s18, 36978; VI-NEXT: s_add_i32 s19, s4, 0x300006979; VI-NEXT: s_and_b32 s4, s18, 0xffff00006980; VI-NEXT: s_and_b32 s5, s5, 0xffff6981; VI-NEXT: s_or_b32 s4, s4, s56982; VI-NEXT: s_add_i32 s5, s17, 36983; VI-NEXT: s_add_i32 s18, s4, 0x300006984; VI-NEXT: s_and_b32 s4, s17, 0xffff00006985; VI-NEXT: s_and_b32 s5, s5, 0xffff6986; VI-NEXT: s_or_b32 s4, s4, s56987; VI-NEXT: s_add_i32 s5, s16, 36988; VI-NEXT: s_add_i32 s17, s4, 0x300006989; VI-NEXT: s_and_b32 s4, s16, 0xffff00006990; VI-NEXT: s_and_b32 s5, s5, 0xffff6991; VI-NEXT: s_or_b32 s4, s4, s56992; VI-NEXT: s_add_i32 s16, s4, 0x300006993; VI-NEXT: .LBB51_3: ; %end6994; VI-NEXT: v_mov_b32_e32 v0, s166995; VI-NEXT: v_mov_b32_e32 v1, s176996; VI-NEXT: v_mov_b32_e32 v2, s186997; VI-NEXT: v_mov_b32_e32 v3, s196998; VI-NEXT: v_mov_b32_e32 v4, s206999; VI-NEXT: v_mov_b32_e32 v5, s217000; VI-NEXT: s_setpc_b64 s[30:31]7001; VI-NEXT: .LBB51_4:7002; VI-NEXT: s_branch .LBB51_27003;7004; GFX9-LABEL: bitcast_v12i16_to_v3f64_scalar:7005; GFX9: ; %bb.0:7006; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7007; GFX9-NEXT: s_cmp_lg_u32 s22, 07008; GFX9-NEXT: s_cbranch_scc0 .LBB51_37009; GFX9-NEXT: ; %bb.1: ; %cmp.false7010; GFX9-NEXT: s_cbranch_execnz .LBB51_47011; GFX9-NEXT: .LBB51_2: ; %cmp.true7012; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]7013; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]7014; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]7015; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]7016; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]7017; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]7018; GFX9-NEXT: s_setpc_b64 s[30:31]7019; GFX9-NEXT: .LBB51_3:7020; GFX9-NEXT: s_branch .LBB51_27021; GFX9-NEXT: .LBB51_4:7022; GFX9-NEXT: v_mov_b32_e32 v0, s167023; GFX9-NEXT: v_mov_b32_e32 v1, s177024; GFX9-NEXT: v_mov_b32_e32 v2, s187025; GFX9-NEXT: v_mov_b32_e32 v3, s197026; GFX9-NEXT: v_mov_b32_e32 v4, s207027; GFX9-NEXT: v_mov_b32_e32 v5, s217028; GFX9-NEXT: s_setpc_b64 s[30:31]7029;7030; GFX11-LABEL: bitcast_v12i16_to_v3f64_scalar:7031; GFX11: ; %bb.0:7032; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7033; GFX11-NEXT: s_mov_b32 s5, s177034; GFX11-NEXT: s_mov_b32 s4, s167035; GFX11-NEXT: s_cmp_lg_u32 s18, 07036; GFX11-NEXT: s_mov_b32 s6, 07037; GFX11-NEXT: s_cbranch_scc0 .LBB51_37038; GFX11-NEXT: ; %bb.1: ; %Flow7039; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s67040; GFX11-NEXT: s_cbranch_vccnz .LBB51_47041; GFX11-NEXT: .LBB51_2: ; %cmp.true7042; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]7043; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]7044; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]7045; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]7046; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]7047; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]7048; GFX11-NEXT: s_setpc_b64 s[30:31]7049; GFX11-NEXT: .LBB51_3:7050; GFX11-NEXT: s_branch .LBB51_27051; GFX11-NEXT: .LBB51_4:7052; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17053; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s37054; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s57055; GFX11-NEXT: s_setpc_b64 s[30:31]7056 %cmp = icmp eq i32 %b, 07057 br i1 %cmp, label %cmp.true, label %cmp.false7058 7059cmp.true:7060 %a1 = add <12 x i16> %a, splat (i16 3)7061 %a2 = bitcast <12 x i16> %a1 to <3 x double>7062 br label %end7063 7064cmp.false:7065 %a3 = bitcast <12 x i16> %a to <3 x double>7066 br label %end7067 7068end:7069 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7070 ret <3 x double> %phi7071}7072 7073define <12 x half> @bitcast_v3f64_to_v12f16(<3 x double> %a, i32 %b) {7074; SI-LABEL: bitcast_v3f64_to_v12f16:7075; SI: ; %bb.0:7076; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7077; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67078; SI-NEXT: ; implicit-def: $vgpr157079; SI-NEXT: ; implicit-def: $vgpr177080; SI-NEXT: ; implicit-def: $vgpr137081; SI-NEXT: ; implicit-def: $vgpr167082; SI-NEXT: ; implicit-def: $vgpr127083; SI-NEXT: ; implicit-def: $vgpr147084; SI-NEXT: ; implicit-def: $vgpr67085; SI-NEXT: ; implicit-def: $vgpr77086; SI-NEXT: ; implicit-def: $vgpr87087; SI-NEXT: ; implicit-def: $vgpr97088; SI-NEXT: ; implicit-def: $vgpr107089; SI-NEXT: ; implicit-def: $vgpr117090; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc7091; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7092; SI-NEXT: s_cbranch_execz .LBB52_27093; SI-NEXT: ; %bb.1: ; %cmp.false7094; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v57095; SI-NEXT: v_cvt_f32_f16_e32 v11, v67096; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v47097; SI-NEXT: v_cvt_f32_f16_e32 v9, v67098; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v37099; SI-NEXT: v_cvt_f32_f16_e32 v7, v67100; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v27101; SI-NEXT: v_cvt_f32_f16_e32 v14, v67102; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v17103; SI-NEXT: v_cvt_f32_f16_e32 v16, v67104; SI-NEXT: v_lshrrev_b32_e32 v6, 16, v07105; SI-NEXT: v_cvt_f32_f16_e32 v17, v67106; SI-NEXT: v_cvt_f32_f16_e32 v10, v57107; SI-NEXT: v_cvt_f32_f16_e32 v8, v47108; SI-NEXT: v_cvt_f32_f16_e32 v6, v37109; SI-NEXT: v_cvt_f32_f16_e32 v12, v27110; SI-NEXT: v_cvt_f32_f16_e32 v13, v17111; SI-NEXT: v_cvt_f32_f16_e32 v15, v07112; SI-NEXT: ; implicit-def: $vgpr07113; SI-NEXT: ; implicit-def: $vgpr27114; SI-NEXT: ; implicit-def: $vgpr47115; SI-NEXT: .LBB52_2: ; %Flow7116; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7117; SI-NEXT: s_cbranch_execz .LBB52_47118; SI-NEXT: ; %bb.3: ; %cmp.true7119; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.07120; SI-NEXT: v_add_f64 v[4:5], v[4:5], 1.07121; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.07122; SI-NEXT: v_cvt_f32_f16_e32 v10, v57123; SI-NEXT: v_cvt_f32_f16_e32 v8, v47124; SI-NEXT: v_cvt_f32_f16_e32 v6, v37125; SI-NEXT: v_cvt_f32_f16_e32 v12, v27126; SI-NEXT: v_cvt_f32_f16_e32 v13, v17127; SI-NEXT: v_cvt_f32_f16_e32 v15, v07128; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v57129; SI-NEXT: v_lshrrev_b32_e32 v4, 16, v47130; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v37131; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v27132; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v17133; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v07134; SI-NEXT: v_cvt_f32_f16_e32 v11, v57135; SI-NEXT: v_cvt_f32_f16_e32 v9, v47136; SI-NEXT: v_cvt_f32_f16_e32 v7, v37137; SI-NEXT: v_cvt_f32_f16_e32 v14, v27138; SI-NEXT: v_cvt_f32_f16_e32 v16, v17139; SI-NEXT: v_cvt_f32_f16_e32 v17, v07140; SI-NEXT: .LBB52_4: ; %end7141; SI-NEXT: s_or_b64 exec, exec, s[4:5]7142; SI-NEXT: v_mov_b32_e32 v0, v157143; SI-NEXT: v_mov_b32_e32 v1, v177144; SI-NEXT: v_mov_b32_e32 v2, v137145; SI-NEXT: v_mov_b32_e32 v3, v167146; SI-NEXT: v_mov_b32_e32 v4, v127147; SI-NEXT: v_mov_b32_e32 v5, v147148; SI-NEXT: s_setpc_b64 s[30:31]7149;7150; VI-LABEL: bitcast_v3f64_to_v12f16:7151; VI: ; %bb.0:7152; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7153; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67154; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc7155; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7156; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7157; VI-NEXT: s_cbranch_execz .LBB52_27158; VI-NEXT: ; %bb.1: ; %cmp.true7159; VI-NEXT: v_add_f64 v[4:5], v[4:5], 1.07160; VI-NEXT: v_add_f64 v[2:3], v[2:3], 1.07161; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.07162; VI-NEXT: .LBB52_2: ; %end7163; VI-NEXT: s_or_b64 exec, exec, s[4:5]7164; VI-NEXT: s_setpc_b64 s[30:31]7165;7166; GFX9-LABEL: bitcast_v3f64_to_v12f16:7167; GFX9: ; %bb.0:7168; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7169; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67170; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc7171; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7172; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7173; GFX9-NEXT: s_cbranch_execz .LBB52_27174; GFX9-NEXT: ; %bb.1: ; %cmp.true7175; GFX9-NEXT: v_add_f64 v[4:5], v[4:5], 1.07176; GFX9-NEXT: v_add_f64 v[2:3], v[2:3], 1.07177; GFX9-NEXT: v_add_f64 v[0:1], v[0:1], 1.07178; GFX9-NEXT: .LBB52_2: ; %end7179; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]7180; GFX9-NEXT: s_setpc_b64 s[30:31]7181;7182; GFX11-LABEL: bitcast_v3f64_to_v12f16:7183; GFX11: ; %bb.0:7184; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7185; GFX11-NEXT: s_mov_b32 s0, exec_lo7186; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v67187; GFX11-NEXT: s_xor_b32 s0, exec_lo, s07188; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)7189; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s07190; GFX11-NEXT: s_cbranch_execz .LBB52_27191; GFX11-NEXT: ; %bb.1: ; %cmp.true7192; GFX11-NEXT: v_add_f64 v[4:5], v[4:5], 1.07193; GFX11-NEXT: v_add_f64 v[2:3], v[2:3], 1.07194; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.07195; GFX11-NEXT: .LBB52_2: ; %end7196; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s07197; GFX11-NEXT: s_setpc_b64 s[30:31]7198 %cmp = icmp eq i32 %b, 07199 br i1 %cmp, label %cmp.true, label %cmp.false7200 7201cmp.true:7202 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)7203 %a2 = bitcast <3 x double> %a1 to <12 x half>7204 br label %end7205 7206cmp.false:7207 %a3 = bitcast <3 x double> %a to <12 x half>7208 br label %end7209 7210end:7211 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7212 ret <12 x half> %phi7213}7214 7215define inreg <12 x half> @bitcast_v3f64_to_v12f16_scalar(<3 x double> inreg %a, i32 inreg %b) {7216; SI-LABEL: bitcast_v3f64_to_v12f16_scalar:7217; SI: ; %bb.0:7218; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7219; SI-NEXT: s_cmp_lg_u32 s22, 07220; SI-NEXT: s_cbranch_scc0 .LBB53_47221; SI-NEXT: ; %bb.1: ; %cmp.false7222; SI-NEXT: s_lshr_b32 s4, s21, 167223; SI-NEXT: v_cvt_f32_f16_e32 v11, s47224; SI-NEXT: s_lshr_b32 s4, s20, 167225; SI-NEXT: v_cvt_f32_f16_e32 v9, s47226; SI-NEXT: s_lshr_b32 s4, s19, 167227; SI-NEXT: v_cvt_f32_f16_e32 v7, s47228; SI-NEXT: s_lshr_b32 s4, s18, 167229; SI-NEXT: v_cvt_f32_f16_e32 v5, s47230; SI-NEXT: s_lshr_b32 s4, s17, 167231; SI-NEXT: v_cvt_f32_f16_e32 v3, s47232; SI-NEXT: s_lshr_b32 s4, s16, 167233; SI-NEXT: v_cvt_f32_f16_e32 v1, s47234; SI-NEXT: v_cvt_f32_f16_e32 v10, s217235; SI-NEXT: v_cvt_f32_f16_e32 v8, s207236; SI-NEXT: v_cvt_f32_f16_e32 v6, s197237; SI-NEXT: v_cvt_f32_f16_e32 v4, s187238; SI-NEXT: v_cvt_f32_f16_e32 v2, s177239; SI-NEXT: v_cvt_f32_f16_e32 v0, s167240; SI-NEXT: s_cbranch_execnz .LBB53_37241; SI-NEXT: .LBB53_2: ; %cmp.true7242; SI-NEXT: v_add_f64 v[14:15], s[20:21], 1.07243; SI-NEXT: v_add_f64 v[16:17], s[18:19], 1.07244; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v157245; SI-NEXT: v_cvt_f32_f16_e32 v11, v17246; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v147247; SI-NEXT: v_add_f64 v[12:13], s[16:17], 1.07248; SI-NEXT: v_cvt_f32_f16_e32 v9, v17249; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v177250; SI-NEXT: v_cvt_f32_f16_e32 v7, v17251; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v167252; SI-NEXT: v_cvt_f32_f16_e32 v5, v17253; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v137254; SI-NEXT: v_cvt_f32_f16_e32 v3, v17255; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v127256; SI-NEXT: v_cvt_f32_f16_e32 v10, v157257; SI-NEXT: v_cvt_f32_f16_e32 v8, v147258; SI-NEXT: v_cvt_f32_f16_e32 v6, v177259; SI-NEXT: v_cvt_f32_f16_e32 v4, v167260; SI-NEXT: v_cvt_f32_f16_e32 v2, v137261; SI-NEXT: v_cvt_f32_f16_e32 v0, v127262; SI-NEXT: v_cvt_f32_f16_e32 v1, v17263; SI-NEXT: .LBB53_3: ; %end7264; SI-NEXT: s_setpc_b64 s[30:31]7265; SI-NEXT: .LBB53_4:7266; SI-NEXT: ; implicit-def: $vgpr07267; SI-NEXT: ; implicit-def: $vgpr17268; SI-NEXT: ; implicit-def: $vgpr27269; SI-NEXT: ; implicit-def: $vgpr37270; SI-NEXT: ; implicit-def: $vgpr47271; SI-NEXT: ; implicit-def: $vgpr57272; SI-NEXT: ; implicit-def: $vgpr67273; SI-NEXT: ; implicit-def: $vgpr77274; SI-NEXT: ; implicit-def: $vgpr87275; SI-NEXT: ; implicit-def: $vgpr97276; SI-NEXT: ; implicit-def: $vgpr107277; SI-NEXT: ; implicit-def: $vgpr117278; SI-NEXT: s_branch .LBB53_27279;7280; VI-LABEL: bitcast_v3f64_to_v12f16_scalar:7281; VI: ; %bb.0:7282; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7283; VI-NEXT: s_cmp_lg_u32 s22, 07284; VI-NEXT: s_cbranch_scc0 .LBB53_37285; VI-NEXT: ; %bb.1: ; %cmp.false7286; VI-NEXT: s_cbranch_execnz .LBB53_47287; VI-NEXT: .LBB53_2: ; %cmp.true7288; VI-NEXT: v_add_f64 v[4:5], s[20:21], 1.07289; VI-NEXT: v_add_f64 v[2:3], s[18:19], 1.07290; VI-NEXT: v_add_f64 v[0:1], s[16:17], 1.07291; VI-NEXT: s_setpc_b64 s[30:31]7292; VI-NEXT: .LBB53_3:7293; VI-NEXT: s_branch .LBB53_27294; VI-NEXT: .LBB53_4:7295; VI-NEXT: v_mov_b32_e32 v0, s167296; VI-NEXT: v_mov_b32_e32 v1, s177297; VI-NEXT: v_mov_b32_e32 v2, s187298; VI-NEXT: v_mov_b32_e32 v3, s197299; VI-NEXT: v_mov_b32_e32 v4, s207300; VI-NEXT: v_mov_b32_e32 v5, s217301; VI-NEXT: v_mov_b32_e32 v6, s227302; VI-NEXT: v_mov_b32_e32 v7, s237303; VI-NEXT: s_setpc_b64 s[30:31]7304;7305; GFX9-LABEL: bitcast_v3f64_to_v12f16_scalar:7306; GFX9: ; %bb.0:7307; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7308; GFX9-NEXT: s_cmp_lg_u32 s22, 07309; GFX9-NEXT: s_cbranch_scc0 .LBB53_37310; GFX9-NEXT: ; %bb.1: ; %cmp.false7311; GFX9-NEXT: s_cbranch_execnz .LBB53_47312; GFX9-NEXT: .LBB53_2: ; %cmp.true7313; GFX9-NEXT: v_add_f64 v[4:5], s[20:21], 1.07314; GFX9-NEXT: v_add_f64 v[2:3], s[18:19], 1.07315; GFX9-NEXT: v_add_f64 v[0:1], s[16:17], 1.07316; GFX9-NEXT: s_setpc_b64 s[30:31]7317; GFX9-NEXT: .LBB53_3:7318; GFX9-NEXT: s_branch .LBB53_27319; GFX9-NEXT: .LBB53_4:7320; GFX9-NEXT: v_mov_b32_e32 v0, s167321; GFX9-NEXT: v_mov_b32_e32 v1, s177322; GFX9-NEXT: v_mov_b32_e32 v2, s187323; GFX9-NEXT: v_mov_b32_e32 v3, s197324; GFX9-NEXT: v_mov_b32_e32 v4, s207325; GFX9-NEXT: v_mov_b32_e32 v5, s217326; GFX9-NEXT: v_mov_b32_e32 v6, s227327; GFX9-NEXT: v_mov_b32_e32 v7, s237328; GFX9-NEXT: s_setpc_b64 s[30:31]7329;7330; GFX11-LABEL: bitcast_v3f64_to_v12f16_scalar:7331; GFX11: ; %bb.0:7332; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7333; GFX11-NEXT: s_mov_b32 s5, s177334; GFX11-NEXT: s_mov_b32 s4, s167335; GFX11-NEXT: s_cmp_lg_u32 s18, 07336; GFX11-NEXT: s_mov_b32 s8, 07337; GFX11-NEXT: s_cbranch_scc0 .LBB53_37338; GFX11-NEXT: ; %bb.1: ; %Flow7339; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s87340; GFX11-NEXT: s_cbranch_vccnz .LBB53_47341; GFX11-NEXT: .LBB53_2: ; %cmp.true7342; GFX11-NEXT: v_add_f64 v[4:5], s[4:5], 1.07343; GFX11-NEXT: v_add_f64 v[2:3], s[2:3], 1.07344; GFX11-NEXT: v_add_f64 v[0:1], s[0:1], 1.07345; GFX11-NEXT: s_setpc_b64 s[30:31]7346; GFX11-NEXT: .LBB53_3:7347; GFX11-NEXT: s_branch .LBB53_27348; GFX11-NEXT: .LBB53_4:7349; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17350; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s37351; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s57352; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s77353; GFX11-NEXT: s_setpc_b64 s[30:31]7354 %cmp = icmp eq i32 %b, 07355 br i1 %cmp, label %cmp.true, label %cmp.false7356 7357cmp.true:7358 %a1 = fadd <3 x double> %a, splat (double 1.000000e+00)7359 %a2 = bitcast <3 x double> %a1 to <12 x half>7360 br label %end7361 7362cmp.false:7363 %a3 = bitcast <3 x double> %a to <12 x half>7364 br label %end7365 7366end:7367 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7368 ret <12 x half> %phi7369}7370 7371define <3 x double> @bitcast_v12f16_to_v3f64(<12 x half> %a, i32 %b) {7372; SI-LABEL: bitcast_v12f16_to_v3f64:7373; SI: ; %bb.0:7374; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7375; SI-NEXT: v_cvt_f16_f32_e32 v20, v17376; SI-NEXT: v_cvt_f16_f32_e32 v19, v07377; SI-NEXT: v_cvt_f16_f32_e32 v18, v37378; SI-NEXT: v_cvt_f16_f32_e32 v17, v27379; SI-NEXT: v_cvt_f16_f32_e32 v16, v57380; SI-NEXT: v_cvt_f16_f32_e32 v15, v47381; SI-NEXT: v_cvt_f16_f32_e32 v14, v77382; SI-NEXT: v_cvt_f16_f32_e32 v13, v67383; SI-NEXT: v_cvt_f16_f32_e32 v9, v97384; SI-NEXT: v_cvt_f16_f32_e32 v8, v87385; SI-NEXT: v_cvt_f16_f32_e32 v7, v117386; SI-NEXT: v_cvt_f16_f32_e32 v6, v107387; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v127388; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr57389; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc7390; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7391; SI-NEXT: s_cbranch_execnz .LBB54_37392; SI-NEXT: ; %bb.1: ; %Flow7393; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7394; SI-NEXT: s_cbranch_execnz .LBB54_47395; SI-NEXT: .LBB54_2: ; %end7396; SI-NEXT: s_or_b64 exec, exec, s[4:5]7397; SI-NEXT: s_setpc_b64 s[30:31]7398; SI-NEXT: .LBB54_3: ; %cmp.false7399; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v207400; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v187401; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v167402; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v147403; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v97404; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v77405; SI-NEXT: v_or_b32_e32 v0, v19, v07406; SI-NEXT: v_or_b32_e32 v1, v17, v17407; SI-NEXT: v_or_b32_e32 v2, v15, v27408; SI-NEXT: v_or_b32_e32 v3, v13, v37409; SI-NEXT: v_or_b32_e32 v4, v8, v47410; SI-NEXT: v_or_b32_e32 v5, v6, v57411; SI-NEXT: ; implicit-def: $vgpr207412; SI-NEXT: ; implicit-def: $vgpr197413; SI-NEXT: ; implicit-def: $vgpr187414; SI-NEXT: ; implicit-def: $vgpr177415; SI-NEXT: ; implicit-def: $vgpr167416; SI-NEXT: ; implicit-def: $vgpr157417; SI-NEXT: ; implicit-def: $vgpr147418; SI-NEXT: ; implicit-def: $vgpr137419; SI-NEXT: ; implicit-def: $vgpr97420; SI-NEXT: ; implicit-def: $vgpr87421; SI-NEXT: ; implicit-def: $vgpr77422; SI-NEXT: ; implicit-def: $vgpr67423; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7424; SI-NEXT: s_cbranch_execz .LBB54_27425; SI-NEXT: .LBB54_4: ; %cmp.true7426; SI-NEXT: v_cvt_f32_f16_e32 v0, v207427; SI-NEXT: v_cvt_f32_f16_e32 v1, v197428; SI-NEXT: v_cvt_f32_f16_e32 v2, v187429; SI-NEXT: v_cvt_f32_f16_e32 v3, v177430; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v07431; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17432; SI-NEXT: v_cvt_f16_f32_e32 v0, v07433; SI-NEXT: v_cvt_f16_f32_e32 v1, v17434; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27435; SI-NEXT: v_cvt_f16_f32_e32 v2, v27436; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v07437; SI-NEXT: v_or_b32_e32 v0, v1, v07438; SI-NEXT: v_cvt_f32_f16_e32 v1, v167439; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37440; SI-NEXT: v_cvt_f16_f32_e32 v3, v37441; SI-NEXT: v_cvt_f32_f16_e32 v5, v137442; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17443; SI-NEXT: v_cvt_f16_f32_e32 v4, v17444; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27445; SI-NEXT: v_cvt_f32_f16_e32 v2, v157446; SI-NEXT: v_or_b32_e32 v1, v3, v17447; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47448; SI-NEXT: v_cvt_f32_f16_e32 v4, v147449; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27450; SI-NEXT: v_cvt_f16_f32_e32 v2, v27451; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57452; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47453; SI-NEXT: v_cvt_f16_f32_e32 v4, v47454; SI-NEXT: v_cvt_f16_f32_e32 v5, v57455; SI-NEXT: v_cvt_f32_f16_e32 v9, v97456; SI-NEXT: v_or_b32_e32 v2, v2, v37457; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47458; SI-NEXT: v_cvt_f32_f16_e32 v4, v87459; SI-NEXT: v_cvt_f32_f16_e32 v7, v77460; SI-NEXT: v_cvt_f32_f16_e32 v6, v67461; SI-NEXT: v_or_b32_e32 v3, v5, v37462; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v97463; SI-NEXT: v_cvt_f16_f32_e32 v5, v57464; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47465; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77466; SI-NEXT: v_cvt_f16_f32_e32 v4, v47467; SI-NEXT: v_cvt_f16_f32_e32 v7, v77468; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67469; SI-NEXT: v_cvt_f16_f32_e32 v6, v67470; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v57471; SI-NEXT: v_or_b32_e32 v4, v4, v57472; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v77473; SI-NEXT: v_or_b32_e32 v5, v6, v57474; SI-NEXT: s_or_b64 exec, exec, s[4:5]7475; SI-NEXT: s_setpc_b64 s[30:31]7476;7477; VI-LABEL: bitcast_v12f16_to_v3f64:7478; VI: ; %bb.0:7479; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7480; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67481; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc7482; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7483; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7484; VI-NEXT: s_cbranch_execz .LBB54_27485; VI-NEXT: ; %bb.1: ; %cmp.true7486; VI-NEXT: v_mov_b32_e32 v6, 0x2007487; VI-NEXT: v_add_f16_sdwa v7, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7488; VI-NEXT: v_add_f16_e32 v5, 0x200, v57489; VI-NEXT: v_or_b32_e32 v5, v5, v77490; VI-NEXT: v_add_f16_sdwa v7, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7491; VI-NEXT: v_add_f16_e32 v4, 0x200, v47492; VI-NEXT: v_or_b32_e32 v4, v4, v77493; VI-NEXT: v_add_f16_sdwa v7, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7494; VI-NEXT: v_add_f16_e32 v3, 0x200, v37495; VI-NEXT: v_or_b32_e32 v3, v3, v77496; VI-NEXT: v_add_f16_sdwa v7, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7497; VI-NEXT: v_add_f16_e32 v2, 0x200, v27498; VI-NEXT: v_or_b32_e32 v2, v2, v77499; VI-NEXT: v_add_f16_sdwa v7, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7500; VI-NEXT: v_add_f16_e32 v1, 0x200, v17501; VI-NEXT: v_add_f16_sdwa v6, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7502; VI-NEXT: v_add_f16_e32 v0, 0x200, v07503; VI-NEXT: v_or_b32_e32 v1, v1, v77504; VI-NEXT: v_or_b32_e32 v0, v0, v67505; VI-NEXT: .LBB54_2: ; %end7506; VI-NEXT: s_or_b64 exec, exec, s[4:5]7507; VI-NEXT: s_setpc_b64 s[30:31]7508;7509; GFX9-LABEL: bitcast_v12f16_to_v3f64:7510; GFX9: ; %bb.0:7511; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7512; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67513; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc7514; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7515; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7516; GFX9-NEXT: ; %bb.1: ; %cmp.true7517; GFX9-NEXT: s_movk_i32 s6, 0x2007518; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]7519; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]7520; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]7521; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]7522; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]7523; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]7524; GFX9-NEXT: ; %bb.2: ; %end7525; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]7526; GFX9-NEXT: s_setpc_b64 s[30:31]7527;7528; GFX11-LABEL: bitcast_v12f16_to_v3f64:7529; GFX11: ; %bb.0:7530; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7531; GFX11-NEXT: s_mov_b32 s0, exec_lo7532; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v67533; GFX11-NEXT: s_xor_b32 s0, exec_lo, s07534; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)7535; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s07536; GFX11-NEXT: ; %bb.1: ; %cmp.true7537; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]7538; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]7539; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]7540; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]7541; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]7542; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]7543; GFX11-NEXT: ; %bb.2: ; %end7544; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s07545; GFX11-NEXT: s_setpc_b64 s[30:31]7546 %cmp = icmp eq i32 %b, 07547 br i1 %cmp, label %cmp.true, label %cmp.false7548 7549cmp.true:7550 %a1 = fadd <12 x half> %a, splat (half 0xH0200)7551 %a2 = bitcast <12 x half> %a1 to <3 x double>7552 br label %end7553 7554cmp.false:7555 %a3 = bitcast <12 x half> %a to <3 x double>7556 br label %end7557 7558end:7559 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7560 ret <3 x double> %phi7561}7562 7563define inreg <3 x double> @bitcast_v12f16_to_v3f64_scalar(<12 x half> inreg %a, i32 inreg %b) {7564; SI-LABEL: bitcast_v12f16_to_v3f64_scalar:7565; SI: ; %bb.0:7566; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7567; SI-NEXT: v_cvt_f16_f32_e32 v17, s177568; SI-NEXT: v_cvt_f16_f32_e32 v16, s167569; SI-NEXT: v_cvt_f16_f32_e32 v15, s197570; SI-NEXT: v_cvt_f16_f32_e32 v14, s187571; SI-NEXT: v_cvt_f16_f32_e32 v13, s217572; SI-NEXT: v_cvt_f16_f32_e32 v12, s207573; SI-NEXT: v_cvt_f16_f32_e32 v11, s237574; SI-NEXT: v_cvt_f16_f32_e32 v10, s227575; SI-NEXT: v_cvt_f16_f32_e32 v9, s257576; SI-NEXT: v_cvt_f16_f32_e32 v8, s247577; SI-NEXT: v_cvt_f16_f32_e32 v7, s277578; SI-NEXT: v_cvt_f16_f32_e32 v6, s267579; SI-NEXT: s_cmp_lg_u32 s28, 07580; SI-NEXT: s_cbranch_scc0 .LBB55_47581; SI-NEXT: ; %bb.1: ; %cmp.false7582; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v177583; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v157584; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v137585; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v117586; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v97587; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v77588; SI-NEXT: v_or_b32_e32 v0, v16, v07589; SI-NEXT: v_or_b32_e32 v1, v14, v17590; SI-NEXT: v_or_b32_e32 v2, v12, v27591; SI-NEXT: v_or_b32_e32 v3, v10, v37592; SI-NEXT: v_or_b32_e32 v4, v8, v47593; SI-NEXT: v_or_b32_e32 v5, v6, v57594; SI-NEXT: s_cbranch_execnz .LBB55_37595; SI-NEXT: .LBB55_2: ; %cmp.true7596; SI-NEXT: v_cvt_f32_f16_e32 v0, v177597; SI-NEXT: v_cvt_f32_f16_e32 v1, v167598; SI-NEXT: v_cvt_f32_f16_e32 v2, v157599; SI-NEXT: v_cvt_f32_f16_e32 v3, v147600; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v07601; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17602; SI-NEXT: v_cvt_f16_f32_e32 v0, v07603; SI-NEXT: v_cvt_f16_f32_e32 v1, v17604; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27605; SI-NEXT: v_cvt_f16_f32_e32 v2, v27606; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v07607; SI-NEXT: v_or_b32_e32 v0, v1, v07608; SI-NEXT: v_cvt_f32_f16_e32 v1, v137609; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v37610; SI-NEXT: v_cvt_f16_f32_e32 v3, v37611; SI-NEXT: v_cvt_f32_f16_e32 v5, v107612; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v17613; SI-NEXT: v_cvt_f16_f32_e32 v4, v17614; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v27615; SI-NEXT: v_cvt_f32_f16_e32 v2, v127616; SI-NEXT: v_or_b32_e32 v1, v3, v17617; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47618; SI-NEXT: v_cvt_f32_f16_e32 v4, v117619; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v27620; SI-NEXT: v_cvt_f16_f32_e32 v2, v27621; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v57622; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47623; SI-NEXT: v_cvt_f16_f32_e32 v4, v47624; SI-NEXT: v_cvt_f16_f32_e32 v5, v57625; SI-NEXT: v_cvt_f32_f16_e32 v9, v97626; SI-NEXT: v_or_b32_e32 v2, v2, v37627; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v47628; SI-NEXT: v_cvt_f32_f16_e32 v4, v87629; SI-NEXT: v_cvt_f32_f16_e32 v7, v77630; SI-NEXT: v_cvt_f32_f16_e32 v6, v67631; SI-NEXT: v_or_b32_e32 v3, v5, v37632; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v97633; SI-NEXT: v_cvt_f16_f32_e32 v5, v57634; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v47635; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v77636; SI-NEXT: v_cvt_f16_f32_e32 v4, v47637; SI-NEXT: v_cvt_f16_f32_e32 v7, v77638; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v67639; SI-NEXT: v_cvt_f16_f32_e32 v6, v67640; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v57641; SI-NEXT: v_or_b32_e32 v4, v4, v57642; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v77643; SI-NEXT: v_or_b32_e32 v5, v6, v57644; SI-NEXT: .LBB55_3: ; %end7645; SI-NEXT: s_setpc_b64 s[30:31]7646; SI-NEXT: .LBB55_4:7647; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr57648; SI-NEXT: s_branch .LBB55_27649;7650; VI-LABEL: bitcast_v12f16_to_v3f64_scalar:7651; VI: ; %bb.0:7652; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7653; VI-NEXT: s_cmp_lg_u32 s22, 07654; VI-NEXT: s_cbranch_scc0 .LBB55_37655; VI-NEXT: ; %bb.1: ; %cmp.false7656; VI-NEXT: s_cbranch_execnz .LBB55_47657; VI-NEXT: .LBB55_2: ; %cmp.true7658; VI-NEXT: s_lshr_b32 s4, s21, 167659; VI-NEXT: v_mov_b32_e32 v0, 0x2007660; VI-NEXT: v_mov_b32_e32 v1, s47661; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7662; VI-NEXT: v_add_f16_e32 v2, s21, v07663; VI-NEXT: s_lshr_b32 s4, s20, 167664; VI-NEXT: v_or_b32_e32 v5, v2, v17665; VI-NEXT: v_mov_b32_e32 v1, s47666; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7667; VI-NEXT: v_add_f16_e32 v2, s20, v07668; VI-NEXT: s_lshr_b32 s4, s19, 167669; VI-NEXT: v_or_b32_e32 v4, v2, v17670; VI-NEXT: v_mov_b32_e32 v1, s47671; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7672; VI-NEXT: v_add_f16_e32 v2, s19, v07673; VI-NEXT: s_lshr_b32 s4, s18, 167674; VI-NEXT: v_or_b32_e32 v3, v2, v17675; VI-NEXT: v_mov_b32_e32 v1, s47676; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7677; VI-NEXT: v_add_f16_e32 v2, s18, v07678; VI-NEXT: s_lshr_b32 s4, s17, 167679; VI-NEXT: v_or_b32_e32 v2, v2, v17680; VI-NEXT: v_mov_b32_e32 v1, s47681; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7682; VI-NEXT: v_add_f16_e32 v6, s17, v07683; VI-NEXT: s_lshr_b32 s4, s16, 167684; VI-NEXT: v_or_b32_e32 v1, v6, v17685; VI-NEXT: v_mov_b32_e32 v6, s47686; VI-NEXT: v_add_f16_sdwa v6, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7687; VI-NEXT: v_add_f16_e32 v0, s16, v07688; VI-NEXT: v_or_b32_e32 v0, v0, v67689; VI-NEXT: s_setpc_b64 s[30:31]7690; VI-NEXT: .LBB55_3:7691; VI-NEXT: s_branch .LBB55_27692; VI-NEXT: .LBB55_4:7693; VI-NEXT: v_mov_b32_e32 v0, s167694; VI-NEXT: v_mov_b32_e32 v1, s177695; VI-NEXT: v_mov_b32_e32 v2, s187696; VI-NEXT: v_mov_b32_e32 v3, s197697; VI-NEXT: v_mov_b32_e32 v4, s207698; VI-NEXT: v_mov_b32_e32 v5, s217699; VI-NEXT: s_setpc_b64 s[30:31]7700;7701; GFX9-LABEL: bitcast_v12f16_to_v3f64_scalar:7702; GFX9: ; %bb.0:7703; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7704; GFX9-NEXT: s_cmp_lg_u32 s22, 07705; GFX9-NEXT: s_cbranch_scc0 .LBB55_37706; GFX9-NEXT: ; %bb.1: ; %cmp.false7707; GFX9-NEXT: s_cbranch_execnz .LBB55_47708; GFX9-NEXT: .LBB55_2: ; %cmp.true7709; GFX9-NEXT: v_mov_b32_e32 v0, 0x2007710; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]7711; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]7712; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]7713; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]7714; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]7715; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]7716; GFX9-NEXT: s_setpc_b64 s[30:31]7717; GFX9-NEXT: .LBB55_3:7718; GFX9-NEXT: s_branch .LBB55_27719; GFX9-NEXT: .LBB55_4:7720; GFX9-NEXT: v_mov_b32_e32 v0, s167721; GFX9-NEXT: v_mov_b32_e32 v1, s177722; GFX9-NEXT: v_mov_b32_e32 v2, s187723; GFX9-NEXT: v_mov_b32_e32 v3, s197724; GFX9-NEXT: v_mov_b32_e32 v4, s207725; GFX9-NEXT: v_mov_b32_e32 v5, s217726; GFX9-NEXT: s_setpc_b64 s[30:31]7727;7728; GFX11-LABEL: bitcast_v12f16_to_v3f64_scalar:7729; GFX11: ; %bb.0:7730; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7731; GFX11-NEXT: s_mov_b32 s5, s177732; GFX11-NEXT: s_mov_b32 s4, s167733; GFX11-NEXT: s_cmp_lg_u32 s18, 07734; GFX11-NEXT: s_mov_b32 s6, 07735; GFX11-NEXT: s_cbranch_scc0 .LBB55_37736; GFX11-NEXT: ; %bb.1: ; %Flow7737; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s67738; GFX11-NEXT: s_cbranch_vccnz .LBB55_47739; GFX11-NEXT: .LBB55_2: ; %cmp.true7740; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]7741; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]7742; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]7743; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]7744; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]7745; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]7746; GFX11-NEXT: s_setpc_b64 s[30:31]7747; GFX11-NEXT: .LBB55_3:7748; GFX11-NEXT: s_branch .LBB55_27749; GFX11-NEXT: .LBB55_4:7750; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s17751; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s37752; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s57753; GFX11-NEXT: s_setpc_b64 s[30:31]7754 %cmp = icmp eq i32 %b, 07755 br i1 %cmp, label %cmp.true, label %cmp.false7756 7757cmp.true:7758 %a1 = fadd <12 x half> %a, splat (half 0xH0200)7759 %a2 = bitcast <12 x half> %a1 to <3 x double>7760 br label %end7761 7762cmp.false:7763 %a3 = bitcast <12 x half> %a to <3 x double>7764 br label %end7765 7766end:7767 %phi = phi <3 x double> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7768 ret <3 x double> %phi7769}7770 7771define <12 x half> @bitcast_v12i16_to_v12f16(<12 x i16> %a, i32 %b) {7772; SI-LABEL: bitcast_v12i16_to_v12f16:7773; SI: ; %bb.0:7774; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7775; SI-NEXT: v_mov_b32_e32 v23, v117776; SI-NEXT: v_mov_b32_e32 v22, v107777; SI-NEXT: v_mov_b32_e32 v21, v97778; SI-NEXT: v_mov_b32_e32 v20, v87779; SI-NEXT: v_mov_b32_e32 v19, v77780; SI-NEXT: v_mov_b32_e32 v18, v67781; SI-NEXT: v_mov_b32_e32 v17, v57782; SI-NEXT: v_mov_b32_e32 v16, v47783; SI-NEXT: v_mov_b32_e32 v15, v37784; SI-NEXT: v_mov_b32_e32 v14, v27785; SI-NEXT: v_mov_b32_e32 v13, v17786; SI-NEXT: v_mov_b32_e32 v24, v07787; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v127788; SI-NEXT: ; implicit-def: $vgpr07789; SI-NEXT: ; implicit-def: $vgpr17790; SI-NEXT: ; implicit-def: $vgpr27791; SI-NEXT: ; implicit-def: $vgpr37792; SI-NEXT: ; implicit-def: $vgpr47793; SI-NEXT: ; implicit-def: $vgpr57794; SI-NEXT: ; implicit-def: $vgpr67795; SI-NEXT: ; implicit-def: $vgpr77796; SI-NEXT: ; implicit-def: $vgpr87797; SI-NEXT: ; implicit-def: $vgpr97798; SI-NEXT: ; implicit-def: $vgpr107799; SI-NEXT: ; implicit-def: $vgpr117800; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc7801; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7802; SI-NEXT: s_cbranch_execnz .LBB56_37803; SI-NEXT: ; %bb.1: ; %Flow7804; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7805; SI-NEXT: s_cbranch_execnz .LBB56_47806; SI-NEXT: .LBB56_2: ; %end7807; SI-NEXT: s_or_b64 exec, exec, s[4:5]7808; SI-NEXT: s_setpc_b64 s[30:31]7809; SI-NEXT: .LBB56_3: ; %cmp.false7810; SI-NEXT: v_cvt_f32_f16_e32 v0, v247811; SI-NEXT: v_cvt_f32_f16_e32 v1, v137812; SI-NEXT: v_cvt_f32_f16_e32 v2, v147813; SI-NEXT: v_cvt_f32_f16_e32 v3, v157814; SI-NEXT: v_cvt_f32_f16_e32 v4, v167815; SI-NEXT: v_cvt_f32_f16_e32 v5, v177816; SI-NEXT: v_cvt_f32_f16_e32 v6, v187817; SI-NEXT: v_cvt_f32_f16_e32 v7, v197818; SI-NEXT: v_cvt_f32_f16_e32 v8, v207819; SI-NEXT: v_cvt_f32_f16_e32 v9, v217820; SI-NEXT: v_cvt_f32_f16_e32 v10, v227821; SI-NEXT: v_cvt_f32_f16_e32 v11, v237822; SI-NEXT: ; implicit-def: $vgpr247823; SI-NEXT: ; implicit-def: $vgpr137824; SI-NEXT: ; implicit-def: $vgpr147825; SI-NEXT: ; implicit-def: $vgpr157826; SI-NEXT: ; implicit-def: $vgpr167827; SI-NEXT: ; implicit-def: $vgpr177828; SI-NEXT: ; implicit-def: $vgpr187829; SI-NEXT: ; implicit-def: $vgpr197830; SI-NEXT: ; implicit-def: $vgpr207831; SI-NEXT: ; implicit-def: $vgpr217832; SI-NEXT: ; implicit-def: $vgpr227833; SI-NEXT: ; implicit-def: $vgpr237834; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7835; SI-NEXT: s_cbranch_execz .LBB56_27836; SI-NEXT: .LBB56_4: ; %cmp.true7837; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v237838; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v227839; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v217840; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v207841; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v197842; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v187843; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v177844; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v167845; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v157846; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v147847; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v137848; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v247849; SI-NEXT: v_cvt_f32_f16_e32 v0, v07850; SI-NEXT: v_cvt_f32_f16_e32 v1, v17851; SI-NEXT: v_cvt_f32_f16_e32 v2, v27852; SI-NEXT: v_cvt_f32_f16_e32 v3, v37853; SI-NEXT: v_cvt_f32_f16_e32 v4, v47854; SI-NEXT: v_cvt_f32_f16_e32 v5, v57855; SI-NEXT: v_cvt_f32_f16_e32 v6, v67856; SI-NEXT: v_cvt_f32_f16_e32 v7, v77857; SI-NEXT: v_cvt_f32_f16_e32 v8, v87858; SI-NEXT: v_cvt_f32_f16_e32 v9, v97859; SI-NEXT: v_cvt_f32_f16_e32 v10, v107860; SI-NEXT: v_cvt_f32_f16_e32 v11, v117861; SI-NEXT: s_or_b64 exec, exec, s[4:5]7862; SI-NEXT: s_setpc_b64 s[30:31]7863;7864; VI-LABEL: bitcast_v12i16_to_v12f16:7865; VI: ; %bb.0:7866; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7867; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67868; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc7869; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7870; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7871; VI-NEXT: s_cbranch_execz .LBB56_27872; VI-NEXT: ; %bb.1: ; %cmp.true7873; VI-NEXT: v_mov_b32_e32 v6, 37874; VI-NEXT: v_add_u16_sdwa v7, v0, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7875; VI-NEXT: v_add_u16_sdwa v8, v1, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7876; VI-NEXT: v_add_u16_sdwa v9, v2, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7877; VI-NEXT: v_add_u16_sdwa v10, v3, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7878; VI-NEXT: v_add_u16_sdwa v11, v4, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7879; VI-NEXT: v_add_u16_sdwa v6, v5, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7880; VI-NEXT: v_add_u16_e32 v5, 3, v57881; VI-NEXT: v_add_u16_e32 v4, 3, v47882; VI-NEXT: v_add_u16_e32 v3, 3, v37883; VI-NEXT: v_add_u16_e32 v2, 3, v27884; VI-NEXT: v_add_u16_e32 v1, 3, v17885; VI-NEXT: v_add_u16_e32 v0, 3, v07886; VI-NEXT: v_or_b32_e32 v5, v5, v67887; VI-NEXT: v_or_b32_e32 v4, v4, v117888; VI-NEXT: v_or_b32_e32 v3, v3, v107889; VI-NEXT: v_or_b32_e32 v2, v2, v97890; VI-NEXT: v_or_b32_e32 v1, v1, v87891; VI-NEXT: v_or_b32_e32 v0, v0, v77892; VI-NEXT: .LBB56_2: ; %end7893; VI-NEXT: s_or_b64 exec, exec, s[4:5]7894; VI-NEXT: s_setpc_b64 s[30:31]7895;7896; GFX9-LABEL: bitcast_v12i16_to_v12f16:7897; GFX9: ; %bb.0:7898; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7899; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v67900; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc7901; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]7902; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]7903; GFX9-NEXT: ; %bb.1: ; %cmp.true7904; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]7905; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]7906; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]7907; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]7908; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]7909; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]7910; GFX9-NEXT: ; %bb.2: ; %end7911; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]7912; GFX9-NEXT: s_setpc_b64 s[30:31]7913;7914; GFX11-LABEL: bitcast_v12i16_to_v12f16:7915; GFX11: ; %bb.0:7916; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7917; GFX11-NEXT: s_mov_b32 s0, exec_lo7918; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v67919; GFX11-NEXT: s_xor_b32 s0, exec_lo, s07920; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)7921; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s07922; GFX11-NEXT: ; %bb.1: ; %cmp.true7923; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]7924; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]7925; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]7926; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]7927; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]7928; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]7929; GFX11-NEXT: ; %bb.2: ; %end7930; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s07931; GFX11-NEXT: s_setpc_b64 s[30:31]7932 %cmp = icmp eq i32 %b, 07933 br i1 %cmp, label %cmp.true, label %cmp.false7934 7935cmp.true:7936 %a1 = add <12 x i16> %a, splat (i16 3)7937 %a2 = bitcast <12 x i16> %a1 to <12 x half>7938 br label %end7939 7940cmp.false:7941 %a3 = bitcast <12 x i16> %a to <12 x half>7942 br label %end7943 7944end:7945 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7946 ret <12 x half> %phi7947}7948 7949define inreg <12 x half> @bitcast_v12i16_to_v12f16_scalar(<12 x i16> inreg %a, i32 inreg %b) {7950; SI-LABEL: bitcast_v12i16_to_v12f16_scalar:7951; SI: ; %bb.0:7952; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7953; SI-NEXT: s_cmp_lg_u32 s28, 07954; SI-NEXT: s_cbranch_scc0 .LBB57_47955; SI-NEXT: ; %bb.1: ; %cmp.false7956; SI-NEXT: v_cvt_f32_f16_e32 v0, s167957; SI-NEXT: v_cvt_f32_f16_e32 v1, s177958; SI-NEXT: v_cvt_f32_f16_e32 v2, s187959; SI-NEXT: v_cvt_f32_f16_e32 v3, s197960; SI-NEXT: v_cvt_f32_f16_e32 v4, s207961; SI-NEXT: v_cvt_f32_f16_e32 v5, s217962; SI-NEXT: v_cvt_f32_f16_e32 v6, s227963; SI-NEXT: v_cvt_f32_f16_e32 v7, s237964; SI-NEXT: v_cvt_f32_f16_e32 v8, s247965; SI-NEXT: v_cvt_f32_f16_e32 v9, s257966; SI-NEXT: v_cvt_f32_f16_e32 v10, s267967; SI-NEXT: v_cvt_f32_f16_e32 v11, s277968; SI-NEXT: s_cbranch_execnz .LBB57_37969; SI-NEXT: .LBB57_2: ; %cmp.true7970; SI-NEXT: s_add_i32 s27, s27, 37971; SI-NEXT: s_add_i32 s26, s26, 37972; SI-NEXT: s_add_i32 s25, s25, 37973; SI-NEXT: s_add_i32 s24, s24, 37974; SI-NEXT: s_add_i32 s23, s23, 37975; SI-NEXT: s_add_i32 s22, s22, 37976; SI-NEXT: s_add_i32 s21, s21, 37977; SI-NEXT: s_add_i32 s20, s20, 37978; SI-NEXT: s_add_i32 s19, s19, 37979; SI-NEXT: s_add_i32 s18, s18, 37980; SI-NEXT: s_add_i32 s17, s17, 37981; SI-NEXT: s_add_i32 s16, s16, 37982; SI-NEXT: v_cvt_f32_f16_e32 v0, s167983; SI-NEXT: v_cvt_f32_f16_e32 v1, s177984; SI-NEXT: v_cvt_f32_f16_e32 v2, s187985; SI-NEXT: v_cvt_f32_f16_e32 v3, s197986; SI-NEXT: v_cvt_f32_f16_e32 v4, s207987; SI-NEXT: v_cvt_f32_f16_e32 v5, s217988; SI-NEXT: v_cvt_f32_f16_e32 v6, s227989; SI-NEXT: v_cvt_f32_f16_e32 v7, s237990; SI-NEXT: v_cvt_f32_f16_e32 v8, s247991; SI-NEXT: v_cvt_f32_f16_e32 v9, s257992; SI-NEXT: v_cvt_f32_f16_e32 v10, s267993; SI-NEXT: v_cvt_f32_f16_e32 v11, s277994; SI-NEXT: .LBB57_3: ; %end7995; SI-NEXT: s_setpc_b64 s[30:31]7996; SI-NEXT: .LBB57_4:7997; SI-NEXT: ; implicit-def: $vgpr07998; SI-NEXT: ; implicit-def: $vgpr17999; SI-NEXT: ; implicit-def: $vgpr28000; SI-NEXT: ; implicit-def: $vgpr38001; SI-NEXT: ; implicit-def: $vgpr48002; SI-NEXT: ; implicit-def: $vgpr58003; SI-NEXT: ; implicit-def: $vgpr68004; SI-NEXT: ; implicit-def: $vgpr78005; SI-NEXT: ; implicit-def: $vgpr88006; SI-NEXT: ; implicit-def: $vgpr98007; SI-NEXT: ; implicit-def: $vgpr108008; SI-NEXT: ; implicit-def: $vgpr118009; SI-NEXT: s_branch .LBB57_28010;8011; VI-LABEL: bitcast_v12i16_to_v12f16_scalar:8012; VI: ; %bb.0:8013; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8014; VI-NEXT: s_cmp_lg_u32 s22, 08015; VI-NEXT: s_cbranch_scc0 .LBB57_48016; VI-NEXT: ; %bb.1: ; %cmp.false8017; VI-NEXT: s_cbranch_execnz .LBB57_38018; VI-NEXT: .LBB57_2: ; %cmp.true8019; VI-NEXT: s_add_i32 s5, s16, 38020; VI-NEXT: s_add_i32 s7, s17, 38021; VI-NEXT: s_add_i32 s9, s18, 38022; VI-NEXT: s_add_i32 s11, s19, 38023; VI-NEXT: s_add_i32 s13, s20, 38024; VI-NEXT: s_add_i32 s15, s21, 38025; VI-NEXT: s_and_b32 s4, s16, 0xffff00008026; VI-NEXT: s_and_b32 s6, s17, 0xffff00008027; VI-NEXT: s_and_b32 s8, s18, 0xffff00008028; VI-NEXT: s_and_b32 s10, s19, 0xffff00008029; VI-NEXT: s_and_b32 s12, s20, 0xffff00008030; VI-NEXT: s_and_b32 s14, s21, 0xffff00008031; VI-NEXT: s_and_b32 s15, s15, 0xffff8032; VI-NEXT: s_and_b32 s13, s13, 0xffff8033; VI-NEXT: s_and_b32 s11, s11, 0xffff8034; VI-NEXT: s_and_b32 s9, s9, 0xffff8035; VI-NEXT: s_and_b32 s7, s7, 0xffff8036; VI-NEXT: s_and_b32 s5, s5, 0xffff8037; VI-NEXT: s_or_b32 s14, s14, s158038; VI-NEXT: s_or_b32 s12, s12, s138039; VI-NEXT: s_or_b32 s10, s10, s118040; VI-NEXT: s_or_b32 s8, s8, s98041; VI-NEXT: s_or_b32 s6, s6, s78042; VI-NEXT: s_or_b32 s4, s4, s58043; VI-NEXT: s_add_i32 s21, s14, 0x300008044; VI-NEXT: s_add_i32 s20, s12, 0x300008045; VI-NEXT: s_add_i32 s19, s10, 0x300008046; VI-NEXT: s_add_i32 s18, s8, 0x300008047; VI-NEXT: s_add_i32 s17, s6, 0x300008048; VI-NEXT: s_add_i32 s16, s4, 0x300008049; VI-NEXT: .LBB57_3: ; %end8050; VI-NEXT: v_mov_b32_e32 v0, s168051; VI-NEXT: v_mov_b32_e32 v1, s178052; VI-NEXT: v_mov_b32_e32 v2, s188053; VI-NEXT: v_mov_b32_e32 v3, s198054; VI-NEXT: v_mov_b32_e32 v4, s208055; VI-NEXT: v_mov_b32_e32 v5, s218056; VI-NEXT: s_setpc_b64 s[30:31]8057; VI-NEXT: .LBB57_4:8058; VI-NEXT: s_branch .LBB57_28059;8060; GFX9-LABEL: bitcast_v12i16_to_v12f16_scalar:8061; GFX9: ; %bb.0:8062; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8063; GFX9-NEXT: s_cmp_lg_u32 s22, 08064; GFX9-NEXT: s_cbranch_scc0 .LBB57_38065; GFX9-NEXT: ; %bb.1: ; %cmp.false8066; GFX9-NEXT: s_cbranch_execnz .LBB57_48067; GFX9-NEXT: .LBB57_2: ; %cmp.true8068; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]8069; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]8070; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]8071; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]8072; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]8073; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]8074; GFX9-NEXT: s_setpc_b64 s[30:31]8075; GFX9-NEXT: .LBB57_3:8076; GFX9-NEXT: s_branch .LBB57_28077; GFX9-NEXT: .LBB57_4:8078; GFX9-NEXT: v_mov_b32_e32 v0, s168079; GFX9-NEXT: v_mov_b32_e32 v1, s178080; GFX9-NEXT: v_mov_b32_e32 v2, s188081; GFX9-NEXT: v_mov_b32_e32 v3, s198082; GFX9-NEXT: v_mov_b32_e32 v4, s208083; GFX9-NEXT: v_mov_b32_e32 v5, s218084; GFX9-NEXT: v_mov_b32_e32 v6, s228085; GFX9-NEXT: v_mov_b32_e32 v7, s238086; GFX9-NEXT: s_setpc_b64 s[30:31]8087;8088; GFX11-LABEL: bitcast_v12i16_to_v12f16_scalar:8089; GFX11: ; %bb.0:8090; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8091; GFX11-NEXT: s_mov_b32 s5, s178092; GFX11-NEXT: s_mov_b32 s4, s168093; GFX11-NEXT: s_cmp_lg_u32 s18, 08094; GFX11-NEXT: s_mov_b32 s8, 08095; GFX11-NEXT: s_cbranch_scc0 .LBB57_38096; GFX11-NEXT: ; %bb.1: ; %Flow8097; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s88098; GFX11-NEXT: s_cbranch_vccnz .LBB57_48099; GFX11-NEXT: .LBB57_2: ; %cmp.true8100; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]8101; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]8102; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]8103; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]8104; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]8105; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]8106; GFX11-NEXT: s_setpc_b64 s[30:31]8107; GFX11-NEXT: .LBB57_3:8108; GFX11-NEXT: s_branch .LBB57_28109; GFX11-NEXT: .LBB57_4:8110; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18111; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s38112; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s58113; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s78114; GFX11-NEXT: s_setpc_b64 s[30:31]8115 %cmp = icmp eq i32 %b, 08116 br i1 %cmp, label %cmp.true, label %cmp.false8117 8118cmp.true:8119 %a1 = add <12 x i16> %a, splat (i16 3)8120 %a2 = bitcast <12 x i16> %a1 to <12 x half>8121 br label %end8122 8123cmp.false:8124 %a3 = bitcast <12 x i16> %a to <12 x half>8125 br label %end8126 8127end:8128 %phi = phi <12 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8129 ret <12 x half> %phi8130}8131 8132define <12 x i16> @bitcast_v12f16_to_v12i16(<12 x half> %a, i32 %b) {8133; SI-LABEL: bitcast_v12f16_to_v12i16:8134; SI: ; %bb.0:8135; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8136; SI-NEXT: v_cvt_f16_f32_e32 v0, v08137; SI-NEXT: v_cvt_f16_f32_e32 v1, v18138; SI-NEXT: v_cvt_f16_f32_e32 v2, v28139; SI-NEXT: v_cvt_f16_f32_e32 v3, v38140; SI-NEXT: v_cvt_f16_f32_e32 v4, v48141; SI-NEXT: v_cvt_f16_f32_e32 v5, v58142; SI-NEXT: v_cvt_f16_f32_e32 v6, v68143; SI-NEXT: v_cvt_f16_f32_e32 v7, v78144; SI-NEXT: v_cvt_f16_f32_e32 v8, v88145; SI-NEXT: v_cvt_f16_f32_e32 v9, v98146; SI-NEXT: v_cvt_f16_f32_e32 v10, v108147; SI-NEXT: v_cvt_f16_f32_e32 v11, v118148; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v128149; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc8150; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8151; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8152; SI-NEXT: s_cbranch_execz .LBB58_28153; SI-NEXT: ; %bb.1: ; %cmp.true8154; SI-NEXT: v_cvt_f32_f16_e32 v11, v118155; SI-NEXT: v_cvt_f32_f16_e32 v10, v108156; SI-NEXT: v_cvt_f32_f16_e32 v7, v78157; SI-NEXT: v_cvt_f32_f16_e32 v6, v68158; SI-NEXT: v_cvt_f32_f16_e32 v3, v38159; SI-NEXT: v_cvt_f32_f16_e32 v1, v18160; SI-NEXT: v_cvt_f32_f16_e32 v5, v58161; SI-NEXT: v_cvt_f32_f16_e32 v9, v98162; SI-NEXT: v_cvt_f32_f16_e32 v2, v28163; SI-NEXT: v_cvt_f32_f16_e32 v0, v08164; SI-NEXT: v_cvt_f32_f16_e32 v4, v48165; SI-NEXT: v_cvt_f32_f16_e32 v8, v88166; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v118167; SI-NEXT: v_cvt_f16_f32_e32 v11, v118168; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v108169; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v78170; SI-NEXT: v_cvt_f16_f32_e32 v10, v108171; SI-NEXT: v_cvt_f16_f32_e32 v7, v78172; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v68173; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v38174; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v18175; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v58176; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v98177; SI-NEXT: v_cvt_f16_f32_e32 v6, v68178; SI-NEXT: v_cvt_f16_f32_e32 v3, v38179; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v28180; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v08181; SI-NEXT: v_cvt_f16_f32_e32 v1, v18182; SI-NEXT: v_cvt_f16_f32_e32 v5, v58183; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v48184; SI-NEXT: v_cvt_f16_f32_e32 v9, v98185; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v88186; SI-NEXT: v_cvt_f16_f32_e32 v2, v28187; SI-NEXT: v_cvt_f16_f32_e32 v0, v08188; SI-NEXT: v_cvt_f16_f32_e32 v4, v48189; SI-NEXT: v_cvt_f16_f32_e32 v8, v88190; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v118191; SI-NEXT: v_or_b32_e32 v10, v10, v128192; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v78193; SI-NEXT: v_or_b32_e32 v6, v6, v128194; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v38195; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18196; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v58197; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v98198; SI-NEXT: v_or_b32_e32 v2, v2, v128199; SI-NEXT: v_or_b32_e32 v0, v0, v18200; SI-NEXT: v_or_b32_e32 v4, v4, v58201; SI-NEXT: v_or_b32_e32 v8, v8, v98202; SI-NEXT: v_alignbit_b32 v1, v2, v1, 168203; SI-NEXT: v_alignbit_b32 v5, v6, v5, 168204; SI-NEXT: v_alignbit_b32 v9, v10, v9, 168205; SI-NEXT: .LBB58_2: ; %end8206; SI-NEXT: s_or_b64 exec, exec, s[4:5]8207; SI-NEXT: s_setpc_b64 s[30:31]8208;8209; VI-LABEL: bitcast_v12f16_to_v12i16:8210; VI: ; %bb.0:8211; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8212; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v68213; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc8214; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8215; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8216; VI-NEXT: s_cbranch_execz .LBB58_28217; VI-NEXT: ; %bb.1: ; %cmp.true8218; VI-NEXT: v_mov_b32_e32 v7, 0x2008219; VI-NEXT: v_add_f16_e32 v6, 0x200, v08220; VI-NEXT: v_add_f16_sdwa v0, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8221; VI-NEXT: v_add_f16_e32 v8, 0x200, v18222; VI-NEXT: v_add_f16_sdwa v1, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8223; VI-NEXT: v_add_f16_e32 v9, 0x200, v28224; VI-NEXT: v_add_f16_sdwa v2, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8225; VI-NEXT: v_add_f16_e32 v10, 0x200, v38226; VI-NEXT: v_add_f16_sdwa v3, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8227; VI-NEXT: v_add_f16_e32 v11, 0x200, v48228; VI-NEXT: v_add_f16_sdwa v4, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8229; VI-NEXT: v_add_f16_e32 v12, 0x200, v58230; VI-NEXT: v_add_f16_sdwa v5, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD8231; VI-NEXT: v_or_b32_e32 v5, v12, v58232; VI-NEXT: v_or_b32_e32 v4, v11, v48233; VI-NEXT: v_or_b32_e32 v3, v10, v38234; VI-NEXT: v_or_b32_e32 v2, v9, v28235; VI-NEXT: v_or_b32_e32 v1, v8, v18236; VI-NEXT: v_or_b32_e32 v0, v6, v08237; VI-NEXT: .LBB58_2: ; %end8238; VI-NEXT: s_or_b64 exec, exec, s[4:5]8239; VI-NEXT: s_setpc_b64 s[30:31]8240;8241; GFX9-LABEL: bitcast_v12f16_to_v12i16:8242; GFX9: ; %bb.0:8243; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8244; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v68245; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc8246; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]8247; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]8248; GFX9-NEXT: ; %bb.1: ; %cmp.true8249; GFX9-NEXT: s_movk_i32 s6, 0x2008250; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]8251; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]8252; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]8253; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]8254; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]8255; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]8256; GFX9-NEXT: ; %bb.2: ; %end8257; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]8258; GFX9-NEXT: s_setpc_b64 s[30:31]8259;8260; GFX11-LABEL: bitcast_v12f16_to_v12i16:8261; GFX11: ; %bb.0:8262; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8263; GFX11-NEXT: s_mov_b32 s0, exec_lo8264; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v68265; GFX11-NEXT: s_xor_b32 s0, exec_lo, s08266; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)8267; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s08268; GFX11-NEXT: ; %bb.1: ; %cmp.true8269; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]8270; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]8271; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]8272; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]8273; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]8274; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]8275; GFX11-NEXT: ; %bb.2: ; %end8276; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s08277; GFX11-NEXT: s_setpc_b64 s[30:31]8278 %cmp = icmp eq i32 %b, 08279 br i1 %cmp, label %cmp.true, label %cmp.false8280 8281cmp.true:8282 %a1 = fadd <12 x half> %a, splat (half 0xH0200)8283 %a2 = bitcast <12 x half> %a1 to <12 x i16>8284 br label %end8285 8286cmp.false:8287 %a3 = bitcast <12 x half> %a to <12 x i16>8288 br label %end8289 8290end:8291 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8292 ret <12 x i16> %phi8293}8294 8295define inreg <12 x i16> @bitcast_v12f16_to_v12i16_scalar(<12 x half> inreg %a, i32 inreg %b) {8296; SI-LABEL: bitcast_v12f16_to_v12i16_scalar:8297; SI: ; %bb.0:8298; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8299; SI-NEXT: v_cvt_f16_f32_e32 v0, s168300; SI-NEXT: v_cvt_f16_f32_e32 v14, s178301; SI-NEXT: v_cvt_f16_f32_e32 v2, s188302; SI-NEXT: v_cvt_f16_f32_e32 v3, s198303; SI-NEXT: v_cvt_f16_f32_e32 v4, s208304; SI-NEXT: v_cvt_f16_f32_e32 v15, s218305; SI-NEXT: v_cvt_f16_f32_e32 v6, s228306; SI-NEXT: v_cvt_f16_f32_e32 v7, s238307; SI-NEXT: v_cvt_f16_f32_e32 v8, s248308; SI-NEXT: v_cvt_f16_f32_e32 v12, s258309; SI-NEXT: v_cvt_f16_f32_e32 v10, s268310; SI-NEXT: v_cvt_f16_f32_e32 v11, s278311; SI-NEXT: s_cmp_lg_u32 s28, 08312; SI-NEXT: s_cbranch_scc0 .LBB59_48313; SI-NEXT: ; %bb.1: ; %cmp.false8314; SI-NEXT: s_cbranch_execnz .LBB59_38315; SI-NEXT: .LBB59_2: ; %cmp.true8316; SI-NEXT: v_cvt_f32_f16_e32 v11, v118317; SI-NEXT: v_cvt_f32_f16_e32 v10, v108318; SI-NEXT: v_cvt_f32_f16_e32 v7, v78319; SI-NEXT: v_cvt_f32_f16_e32 v6, v68320; SI-NEXT: v_cvt_f32_f16_e32 v3, v38321; SI-NEXT: v_cvt_f32_f16_e32 v1, v148322; SI-NEXT: v_cvt_f32_f16_e32 v2, v28323; SI-NEXT: v_cvt_f32_f16_e32 v5, v158324; SI-NEXT: v_cvt_f32_f16_e32 v9, v128325; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v118326; SI-NEXT: v_cvt_f16_f32_e32 v11, v118327; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v108328; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v78329; SI-NEXT: v_cvt_f32_f16_e32 v0, v08330; SI-NEXT: v_cvt_f32_f16_e32 v4, v48331; SI-NEXT: v_cvt_f32_f16_e32 v8, v88332; SI-NEXT: v_cvt_f16_f32_e32 v10, v108333; SI-NEXT: v_cvt_f16_f32_e32 v7, v78334; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v68335; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v38336; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v18337; SI-NEXT: v_cvt_f16_f32_e32 v6, v68338; SI-NEXT: v_cvt_f16_f32_e32 v3, v38339; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v28340; SI-NEXT: v_cvt_f16_f32_e32 v1, v18341; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v58342; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v98343; SI-NEXT: v_cvt_f16_f32_e32 v2, v28344; SI-NEXT: v_cvt_f16_f32_e32 v5, v58345; SI-NEXT: v_cvt_f16_f32_e32 v9, v98346; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v118347; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v08348; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v48349; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v88350; SI-NEXT: v_or_b32_e32 v10, v10, v128351; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v78352; SI-NEXT: v_cvt_f16_f32_e32 v0, v08353; SI-NEXT: v_cvt_f16_f32_e32 v4, v48354; SI-NEXT: v_cvt_f16_f32_e32 v8, v88355; SI-NEXT: v_or_b32_e32 v6, v6, v128356; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v38357; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v18358; SI-NEXT: v_or_b32_e32 v2, v2, v128359; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v58360; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v98361; SI-NEXT: v_lshr_b64 v[14:15], v[1:2], 168362; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 168363; SI-NEXT: v_lshr_b64 v[12:13], v[9:10], 168364; SI-NEXT: v_or_b32_e32 v0, v0, v18365; SI-NEXT: v_or_b32_e32 v4, v4, v58366; SI-NEXT: v_or_b32_e32 v8, v8, v98367; SI-NEXT: .LBB59_3: ; %end8368; SI-NEXT: v_mov_b32_e32 v1, v148369; SI-NEXT: v_mov_b32_e32 v5, v158370; SI-NEXT: v_mov_b32_e32 v9, v128371; SI-NEXT: s_setpc_b64 s[30:31]8372; SI-NEXT: .LBB59_4:8373; SI-NEXT: s_branch .LBB59_28374;8375; VI-LABEL: bitcast_v12f16_to_v12i16_scalar:8376; VI: ; %bb.0:8377; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8378; VI-NEXT: s_cmp_lg_u32 s22, 08379; VI-NEXT: s_cbranch_scc0 .LBB59_38380; VI-NEXT: ; %bb.1: ; %cmp.false8381; VI-NEXT: s_cbranch_execnz .LBB59_48382; VI-NEXT: .LBB59_2: ; %cmp.true8383; VI-NEXT: s_lshr_b32 s4, s16, 168384; VI-NEXT: v_mov_b32_e32 v1, s48385; VI-NEXT: s_lshr_b32 s4, s17, 168386; VI-NEXT: v_mov_b32_e32 v2, s48387; VI-NEXT: s_lshr_b32 s4, s18, 168388; VI-NEXT: v_mov_b32_e32 v3, s48389; VI-NEXT: s_lshr_b32 s4, s19, 168390; VI-NEXT: v_mov_b32_e32 v4, s48391; VI-NEXT: s_lshr_b32 s4, s20, 168392; VI-NEXT: v_mov_b32_e32 v5, s48393; VI-NEXT: s_lshr_b32 s4, s21, 168394; VI-NEXT: v_mov_b32_e32 v0, 0x2008395; VI-NEXT: v_mov_b32_e32 v12, s48396; VI-NEXT: v_add_f16_e32 v6, s16, v08397; VI-NEXT: v_add_f16_sdwa v7, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8398; VI-NEXT: v_add_f16_e32 v1, s17, v08399; VI-NEXT: v_add_f16_sdwa v8, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8400; VI-NEXT: v_add_f16_e32 v2, s18, v08401; VI-NEXT: v_add_f16_sdwa v9, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8402; VI-NEXT: v_add_f16_e32 v3, s19, v08403; VI-NEXT: v_add_f16_sdwa v10, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8404; VI-NEXT: v_add_f16_e32 v4, s20, v08405; VI-NEXT: v_add_f16_sdwa v11, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8406; VI-NEXT: v_add_f16_e32 v5, s21, v08407; VI-NEXT: v_add_f16_sdwa v0, v12, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8408; VI-NEXT: v_or_b32_e32 v5, v5, v08409; VI-NEXT: v_or_b32_e32 v4, v4, v118410; VI-NEXT: v_or_b32_e32 v3, v3, v108411; VI-NEXT: v_or_b32_e32 v2, v2, v98412; VI-NEXT: v_or_b32_e32 v1, v1, v88413; VI-NEXT: v_or_b32_e32 v0, v6, v78414; VI-NEXT: s_setpc_b64 s[30:31]8415; VI-NEXT: .LBB59_3:8416; VI-NEXT: s_branch .LBB59_28417; VI-NEXT: .LBB59_4:8418; VI-NEXT: v_mov_b32_e32 v0, s168419; VI-NEXT: v_mov_b32_e32 v1, s178420; VI-NEXT: v_mov_b32_e32 v2, s188421; VI-NEXT: v_mov_b32_e32 v3, s198422; VI-NEXT: v_mov_b32_e32 v4, s208423; VI-NEXT: v_mov_b32_e32 v5, s218424; VI-NEXT: v_mov_b32_e32 v6, s228425; VI-NEXT: v_mov_b32_e32 v7, s238426; VI-NEXT: s_setpc_b64 s[30:31]8427;8428; GFX9-LABEL: bitcast_v12f16_to_v12i16_scalar:8429; GFX9: ; %bb.0:8430; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8431; GFX9-NEXT: s_cmp_lg_u32 s22, 08432; GFX9-NEXT: s_cbranch_scc0 .LBB59_38433; GFX9-NEXT: ; %bb.1: ; %cmp.false8434; GFX9-NEXT: s_cbranch_execnz .LBB59_48435; GFX9-NEXT: .LBB59_2: ; %cmp.true8436; GFX9-NEXT: v_mov_b32_e32 v0, 0x2008437; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]8438; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]8439; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]8440; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]8441; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]8442; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]8443; GFX9-NEXT: s_setpc_b64 s[30:31]8444; GFX9-NEXT: .LBB59_3:8445; GFX9-NEXT: s_branch .LBB59_28446; GFX9-NEXT: .LBB59_4:8447; GFX9-NEXT: v_mov_b32_e32 v0, s168448; GFX9-NEXT: v_mov_b32_e32 v1, s178449; GFX9-NEXT: v_mov_b32_e32 v2, s188450; GFX9-NEXT: v_mov_b32_e32 v3, s198451; GFX9-NEXT: v_mov_b32_e32 v4, s208452; GFX9-NEXT: v_mov_b32_e32 v5, s218453; GFX9-NEXT: v_mov_b32_e32 v6, s228454; GFX9-NEXT: v_mov_b32_e32 v7, s238455; GFX9-NEXT: s_setpc_b64 s[30:31]8456;8457; GFX11-LABEL: bitcast_v12f16_to_v12i16_scalar:8458; GFX11: ; %bb.0:8459; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8460; GFX11-NEXT: s_mov_b32 s5, s178461; GFX11-NEXT: s_mov_b32 s4, s168462; GFX11-NEXT: s_cmp_lg_u32 s18, 08463; GFX11-NEXT: s_mov_b32 s8, 08464; GFX11-NEXT: s_cbranch_scc0 .LBB59_38465; GFX11-NEXT: ; %bb.1: ; %Flow8466; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s88467; GFX11-NEXT: s_cbranch_vccnz .LBB59_48468; GFX11-NEXT: .LBB59_2: ; %cmp.true8469; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]8470; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]8471; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]8472; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]8473; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]8474; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]8475; GFX11-NEXT: s_setpc_b64 s[30:31]8476; GFX11-NEXT: .LBB59_3:8477; GFX11-NEXT: s_branch .LBB59_28478; GFX11-NEXT: .LBB59_4:8479; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s18480; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s38481; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s58482; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s78483; GFX11-NEXT: s_setpc_b64 s[30:31]8484 %cmp = icmp eq i32 %b, 08485 br i1 %cmp, label %cmp.true, label %cmp.false8486 8487cmp.true:8488 %a1 = fadd <12 x half> %a, splat (half 0xH0200)8489 %a2 = bitcast <12 x half> %a1 to <12 x i16>8490 br label %end8491 8492cmp.false:8493 %a3 = bitcast <12 x half> %a to <12 x i16>8494 br label %end8495 8496end:8497 %phi = phi <12 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8498 ret <12 x i16> %phi8499}8500;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:8501; GFX11-FAKE16: {{.*}}8502; GFX11-TRUE16: {{.*}}8503