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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <7 x float> @bitcast_v7i32_to_v7f32(<7 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v7i32_to_v7f32:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v714; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT: ; %bb.1: ; %cmp.true18; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v619; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v520; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v421; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v322; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v223; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v124; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v025; SI-NEXT: ; %bb.2: ; %end26; SI-NEXT: s_or_b64 exec, exec, s[4:5]27; SI-NEXT: s_setpc_b64 s[30:31]28;29; VI-LABEL: bitcast_v7i32_to_v7f32:30; VI: ; %bb.0:31; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v733; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc34; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]35; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]36; VI-NEXT: ; %bb.1: ; %cmp.true37; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v638; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v539; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v440; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v341; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v242; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v143; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v044; VI-NEXT: ; %bb.2: ; %end45; VI-NEXT: s_or_b64 exec, exec, s[4:5]46; VI-NEXT: s_setpc_b64 s[30:31]47;48; GFX9-LABEL: bitcast_v7i32_to_v7f32:49; GFX9: ; %bb.0:50; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v752; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc53; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]54; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]55; GFX9-NEXT: ; %bb.1: ; %cmp.true56; GFX9-NEXT: v_add_u32_e32 v6, 3, v657; GFX9-NEXT: v_add_u32_e32 v5, 3, v558; GFX9-NEXT: v_add_u32_e32 v4, 3, v459; GFX9-NEXT: v_add_u32_e32 v3, 3, v360; GFX9-NEXT: v_add_u32_e32 v2, 3, v261; GFX9-NEXT: v_add_u32_e32 v1, 3, v162; GFX9-NEXT: v_add_u32_e32 v0, 3, v063; GFX9-NEXT: ; %bb.2: ; %end64; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]65; GFX9-NEXT: s_setpc_b64 s[30:31]66;67; GFX11-LABEL: bitcast_v7i32_to_v7f32:68; GFX11: ; %bb.0:69; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)70; GFX11-NEXT: s_mov_b32 s0, exec_lo71; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v772; GFX11-NEXT: s_xor_b32 s0, exec_lo, s073; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)74; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s075; GFX11-NEXT: s_cbranch_execz .LBB0_276; GFX11-NEXT: ; %bb.1: ; %cmp.true77; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v678; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v579; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v480; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v381; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v282; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v183; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v084; GFX11-NEXT: .LBB0_2: ; %end85; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s086; GFX11-NEXT: s_setpc_b64 s[30:31]87 %cmp = icmp eq i32 %b, 088 br i1 %cmp, label %cmp.true, label %cmp.false89 90cmp.true:91 %a1 = add <7 x i32> %a, splat (i32 3)92 %a2 = bitcast <7 x i32> %a1 to <7 x float>93 br label %end94 95cmp.false:96 %a3 = bitcast <7 x i32> %a to <7 x float>97 br label %end98 99end:100 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]101 ret <7 x float> %phi102}103 104define inreg <7 x float> @bitcast_v7i32_to_v7f32_scalar(<7 x i32> inreg %a, i32 inreg %b) {105; SI-LABEL: bitcast_v7i32_to_v7f32_scalar:106; SI: ; %bb.0:107; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; SI-NEXT: s_cmp_lg_u32 s23, 0109; SI-NEXT: s_cbranch_scc0 .LBB1_4110; SI-NEXT: ; %bb.1: ; %cmp.false111; SI-NEXT: s_cbranch_execnz .LBB1_3112; SI-NEXT: .LBB1_2: ; %cmp.true113; SI-NEXT: s_add_i32 s22, s22, 3114; SI-NEXT: s_add_i32 s21, s21, 3115; SI-NEXT: s_add_i32 s20, s20, 3116; SI-NEXT: s_add_i32 s19, s19, 3117; SI-NEXT: s_add_i32 s18, s18, 3118; SI-NEXT: s_add_i32 s17, s17, 3119; SI-NEXT: s_add_i32 s16, s16, 3120; SI-NEXT: .LBB1_3: ; %end121; SI-NEXT: v_mov_b32_e32 v0, s16122; SI-NEXT: v_mov_b32_e32 v1, s17123; SI-NEXT: v_mov_b32_e32 v2, s18124; SI-NEXT: v_mov_b32_e32 v3, s19125; SI-NEXT: v_mov_b32_e32 v4, s20126; SI-NEXT: v_mov_b32_e32 v5, s21127; SI-NEXT: v_mov_b32_e32 v6, s22128; SI-NEXT: s_setpc_b64 s[30:31]129; SI-NEXT: .LBB1_4:130; SI-NEXT: s_branch .LBB1_2131;132; VI-LABEL: bitcast_v7i32_to_v7f32_scalar:133; VI: ; %bb.0:134; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)135; VI-NEXT: s_cmp_lg_u32 s23, 0136; VI-NEXT: s_cbranch_scc0 .LBB1_4137; VI-NEXT: ; %bb.1: ; %cmp.false138; VI-NEXT: s_cbranch_execnz .LBB1_3139; VI-NEXT: .LBB1_2: ; %cmp.true140; VI-NEXT: s_add_i32 s22, s22, 3141; VI-NEXT: s_add_i32 s21, s21, 3142; VI-NEXT: s_add_i32 s20, s20, 3143; VI-NEXT: s_add_i32 s19, s19, 3144; VI-NEXT: s_add_i32 s18, s18, 3145; VI-NEXT: s_add_i32 s17, s17, 3146; VI-NEXT: s_add_i32 s16, s16, 3147; VI-NEXT: .LBB1_3: ; %end148; VI-NEXT: v_mov_b32_e32 v0, s16149; VI-NEXT: v_mov_b32_e32 v1, s17150; VI-NEXT: v_mov_b32_e32 v2, s18151; VI-NEXT: v_mov_b32_e32 v3, s19152; VI-NEXT: v_mov_b32_e32 v4, s20153; VI-NEXT: v_mov_b32_e32 v5, s21154; VI-NEXT: v_mov_b32_e32 v6, s22155; VI-NEXT: s_setpc_b64 s[30:31]156; VI-NEXT: .LBB1_4:157; VI-NEXT: s_branch .LBB1_2158;159; GFX9-LABEL: bitcast_v7i32_to_v7f32_scalar:160; GFX9: ; %bb.0:161; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)162; GFX9-NEXT: s_cmp_lg_u32 s23, 0163; GFX9-NEXT: s_cbranch_scc0 .LBB1_4164; GFX9-NEXT: ; %bb.1: ; %cmp.false165; GFX9-NEXT: s_cbranch_execnz .LBB1_3166; GFX9-NEXT: .LBB1_2: ; %cmp.true167; GFX9-NEXT: s_add_i32 s22, s22, 3168; GFX9-NEXT: s_add_i32 s21, s21, 3169; GFX9-NEXT: s_add_i32 s20, s20, 3170; GFX9-NEXT: s_add_i32 s19, s19, 3171; GFX9-NEXT: s_add_i32 s18, s18, 3172; GFX9-NEXT: s_add_i32 s17, s17, 3173; GFX9-NEXT: s_add_i32 s16, s16, 3174; GFX9-NEXT: .LBB1_3: ; %end175; GFX9-NEXT: v_mov_b32_e32 v0, s16176; GFX9-NEXT: v_mov_b32_e32 v1, s17177; GFX9-NEXT: v_mov_b32_e32 v2, s18178; GFX9-NEXT: v_mov_b32_e32 v3, s19179; GFX9-NEXT: v_mov_b32_e32 v4, s20180; GFX9-NEXT: v_mov_b32_e32 v5, s21181; GFX9-NEXT: v_mov_b32_e32 v6, s22182; GFX9-NEXT: s_setpc_b64 s[30:31]183; GFX9-NEXT: .LBB1_4:184; GFX9-NEXT: s_branch .LBB1_2185;186; GFX11-LABEL: bitcast_v7i32_to_v7f32_scalar:187; GFX11: ; %bb.0:188; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)189; GFX11-NEXT: s_cmp_lg_u32 s19, 0190; GFX11-NEXT: s_mov_b32 s4, 0191; GFX11-NEXT: s_cbranch_scc0 .LBB1_4192; GFX11-NEXT: ; %bb.1: ; %Flow193; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4194; GFX11-NEXT: s_cbranch_vccnz .LBB1_3195; GFX11-NEXT: .LBB1_2: ; %cmp.true196; GFX11-NEXT: s_add_i32 s18, s18, 3197; GFX11-NEXT: s_add_i32 s17, s17, 3198; GFX11-NEXT: s_add_i32 s16, s16, 3199; GFX11-NEXT: s_add_i32 s3, s3, 3200; GFX11-NEXT: s_add_i32 s2, s2, 3201; GFX11-NEXT: s_add_i32 s1, s1, 3202; GFX11-NEXT: s_add_i32 s0, s0, 3203; GFX11-NEXT: .LBB1_3: ; %end204; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)205; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1206; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3207; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17208; GFX11-NEXT: v_mov_b32_e32 v6, s18209; GFX11-NEXT: s_setpc_b64 s[30:31]210; GFX11-NEXT: .LBB1_4:211; GFX11-NEXT: s_branch .LBB1_2212 %cmp = icmp eq i32 %b, 0213 br i1 %cmp, label %cmp.true, label %cmp.false214 215cmp.true:216 %a1 = add <7 x i32> %a, splat (i32 3)217 %a2 = bitcast <7 x i32> %a1 to <7 x float>218 br label %end219 220cmp.false:221 %a3 = bitcast <7 x i32> %a to <7 x float>222 br label %end223 224end:225 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]226 ret <7 x float> %phi227}228 229define <7 x i32> @bitcast_v7f32_to_v7i32(<7 x float> %a, i32 %b) {230; SI-LABEL: bitcast_v7f32_to_v7i32:231; SI: ; %bb.0:232; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)233; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7234; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc235; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]236; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]237; SI-NEXT: ; %bb.1: ; %cmp.true238; SI-NEXT: v_add_f32_e32 v6, 1.0, v6239; SI-NEXT: v_add_f32_e32 v5, 1.0, v5240; SI-NEXT: v_add_f32_e32 v4, 1.0, v4241; SI-NEXT: v_add_f32_e32 v3, 1.0, v3242; SI-NEXT: v_add_f32_e32 v2, 1.0, v2243; SI-NEXT: v_add_f32_e32 v1, 1.0, v1244; SI-NEXT: v_add_f32_e32 v0, 1.0, v0245; SI-NEXT: ; %bb.2: ; %end246; SI-NEXT: s_or_b64 exec, exec, s[4:5]247; SI-NEXT: s_setpc_b64 s[30:31]248;249; VI-LABEL: bitcast_v7f32_to_v7i32:250; VI: ; %bb.0:251; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)252; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7253; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc254; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]255; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]256; VI-NEXT: ; %bb.1: ; %cmp.true257; VI-NEXT: v_add_f32_e32 v6, 1.0, v6258; VI-NEXT: v_add_f32_e32 v5, 1.0, v5259; VI-NEXT: v_add_f32_e32 v4, 1.0, v4260; VI-NEXT: v_add_f32_e32 v3, 1.0, v3261; VI-NEXT: v_add_f32_e32 v2, 1.0, v2262; VI-NEXT: v_add_f32_e32 v1, 1.0, v1263; VI-NEXT: v_add_f32_e32 v0, 1.0, v0264; VI-NEXT: ; %bb.2: ; %end265; VI-NEXT: s_or_b64 exec, exec, s[4:5]266; VI-NEXT: s_setpc_b64 s[30:31]267;268; GFX9-LABEL: bitcast_v7f32_to_v7i32:269; GFX9: ; %bb.0:270; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)271; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7272; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc273; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]274; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]275; GFX9-NEXT: ; %bb.1: ; %cmp.true276; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6277; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5278; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4279; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3280; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2281; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1282; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0283; GFX9-NEXT: ; %bb.2: ; %end284; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]285; GFX9-NEXT: s_setpc_b64 s[30:31]286;287; GFX11-LABEL: bitcast_v7f32_to_v7i32:288; GFX11: ; %bb.0:289; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)290; GFX11-NEXT: s_mov_b32 s0, exec_lo291; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7292; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0293; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)294; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0295; GFX11-NEXT: ; %bb.1: ; %cmp.true296; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5297; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3298; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1299; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0300; GFX11-NEXT: ; %bb.2: ; %end301; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0302; GFX11-NEXT: s_setpc_b64 s[30:31]303 %cmp = icmp eq i32 %b, 0304 br i1 %cmp, label %cmp.true, label %cmp.false305 306cmp.true:307 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)308 %a2 = bitcast <7 x float> %a1 to <7 x i32>309 br label %end310 311cmp.false:312 %a3 = bitcast <7 x float> %a to <7 x i32>313 br label %end314 315end:316 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]317 ret <7 x i32> %phi318}319 320define inreg <7 x i32> @bitcast_v7f32_to_v7i32_scalar(<7 x float> inreg %a, i32 inreg %b) {321; SI-LABEL: bitcast_v7f32_to_v7i32_scalar:322; SI: ; %bb.0:323; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)324; SI-NEXT: s_cmp_lg_u32 s23, 0325; SI-NEXT: s_cbranch_scc0 .LBB3_3326; SI-NEXT: ; %bb.1: ; %cmp.false327; SI-NEXT: s_cbranch_execnz .LBB3_4328; SI-NEXT: .LBB3_2: ; %cmp.true329; SI-NEXT: v_add_f32_e64 v6, s22, 1.0330; SI-NEXT: v_add_f32_e64 v5, s21, 1.0331; SI-NEXT: v_add_f32_e64 v4, s20, 1.0332; SI-NEXT: v_add_f32_e64 v3, s19, 1.0333; SI-NEXT: v_add_f32_e64 v2, s18, 1.0334; SI-NEXT: v_add_f32_e64 v1, s17, 1.0335; SI-NEXT: v_add_f32_e64 v0, s16, 1.0336; SI-NEXT: s_setpc_b64 s[30:31]337; SI-NEXT: .LBB3_3:338; SI-NEXT: s_branch .LBB3_2339; SI-NEXT: .LBB3_4:340; SI-NEXT: v_mov_b32_e32 v0, s16341; SI-NEXT: v_mov_b32_e32 v1, s17342; SI-NEXT: v_mov_b32_e32 v2, s18343; SI-NEXT: v_mov_b32_e32 v3, s19344; SI-NEXT: v_mov_b32_e32 v4, s20345; SI-NEXT: v_mov_b32_e32 v5, s21346; SI-NEXT: v_mov_b32_e32 v6, s22347; SI-NEXT: s_setpc_b64 s[30:31]348;349; VI-LABEL: bitcast_v7f32_to_v7i32_scalar:350; VI: ; %bb.0:351; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)352; VI-NEXT: s_cmp_lg_u32 s23, 0353; VI-NEXT: s_cbranch_scc0 .LBB3_3354; VI-NEXT: ; %bb.1: ; %cmp.false355; VI-NEXT: s_cbranch_execnz .LBB3_4356; VI-NEXT: .LBB3_2: ; %cmp.true357; VI-NEXT: v_add_f32_e64 v6, s22, 1.0358; VI-NEXT: v_add_f32_e64 v5, s21, 1.0359; VI-NEXT: v_add_f32_e64 v4, s20, 1.0360; VI-NEXT: v_add_f32_e64 v3, s19, 1.0361; VI-NEXT: v_add_f32_e64 v2, s18, 1.0362; VI-NEXT: v_add_f32_e64 v1, s17, 1.0363; VI-NEXT: v_add_f32_e64 v0, s16, 1.0364; VI-NEXT: s_setpc_b64 s[30:31]365; VI-NEXT: .LBB3_3:366; VI-NEXT: s_branch .LBB3_2367; VI-NEXT: .LBB3_4:368; VI-NEXT: v_mov_b32_e32 v0, s16369; VI-NEXT: v_mov_b32_e32 v1, s17370; VI-NEXT: v_mov_b32_e32 v2, s18371; VI-NEXT: v_mov_b32_e32 v3, s19372; VI-NEXT: v_mov_b32_e32 v4, s20373; VI-NEXT: v_mov_b32_e32 v5, s21374; VI-NEXT: v_mov_b32_e32 v6, s22375; VI-NEXT: s_setpc_b64 s[30:31]376;377; GFX9-LABEL: bitcast_v7f32_to_v7i32_scalar:378; GFX9: ; %bb.0:379; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)380; GFX9-NEXT: s_cmp_lg_u32 s23, 0381; GFX9-NEXT: s_cbranch_scc0 .LBB3_3382; GFX9-NEXT: ; %bb.1: ; %cmp.false383; GFX9-NEXT: s_cbranch_execnz .LBB3_4384; GFX9-NEXT: .LBB3_2: ; %cmp.true385; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0386; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0387; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0388; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0389; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0390; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0391; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0392; GFX9-NEXT: s_setpc_b64 s[30:31]393; GFX9-NEXT: .LBB3_3:394; GFX9-NEXT: s_branch .LBB3_2395; GFX9-NEXT: .LBB3_4:396; GFX9-NEXT: v_mov_b32_e32 v0, s16397; GFX9-NEXT: v_mov_b32_e32 v1, s17398; GFX9-NEXT: v_mov_b32_e32 v2, s18399; GFX9-NEXT: v_mov_b32_e32 v3, s19400; GFX9-NEXT: v_mov_b32_e32 v4, s20401; GFX9-NEXT: v_mov_b32_e32 v5, s21402; GFX9-NEXT: v_mov_b32_e32 v6, s22403; GFX9-NEXT: s_setpc_b64 s[30:31]404;405; GFX11-LABEL: bitcast_v7f32_to_v7i32_scalar:406; GFX11: ; %bb.0:407; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)408; GFX11-NEXT: s_mov_b32 s6, s18409; GFX11-NEXT: s_mov_b32 s5, s17410; GFX11-NEXT: s_mov_b32 s4, s16411; GFX11-NEXT: s_cmp_lg_u32 s19, 0412; GFX11-NEXT: s_mov_b32 s7, 0413; GFX11-NEXT: s_cbranch_scc0 .LBB3_3414; GFX11-NEXT: ; %bb.1: ; %Flow415; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s7416; GFX11-NEXT: s_cbranch_vccnz .LBB3_4417; GFX11-NEXT: .LBB3_2: ; %cmp.true418; GFX11-NEXT: v_add_f32_e64 v6, s6, 1.0419; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.0420; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.0421; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.0422; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.0423; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.0424; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0425; GFX11-NEXT: s_setpc_b64 s[30:31]426; GFX11-NEXT: .LBB3_3:427; GFX11-NEXT: s_branch .LBB3_2428; GFX11-NEXT: .LBB3_4:429; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1430; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3431; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5432; GFX11-NEXT: v_mov_b32_e32 v6, s6433; GFX11-NEXT: s_setpc_b64 s[30:31]434 %cmp = icmp eq i32 %b, 0435 br i1 %cmp, label %cmp.true, label %cmp.false436 437cmp.true:438 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)439 %a2 = bitcast <7 x float> %a1 to <7 x i32>440 br label %end441 442cmp.false:443 %a3 = bitcast <7 x float> %a to <7 x i32>444 br label %end445 446end:447 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]448 ret <7 x i32> %phi449}450 451define <14 x i16> @bitcast_v7i32_to_v14i16(<7 x i32> %a, i32 %b) {452; SI-LABEL: bitcast_v7i32_to_v14i16:453; SI: ; %bb.0:454; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)455; SI-NEXT: v_mov_b32_e32 v12, v6456; SI-NEXT: v_mov_b32_e32 v10, v5457; SI-NEXT: v_mov_b32_e32 v8, v4458; SI-NEXT: v_mov_b32_e32 v6, v3459; SI-NEXT: v_mov_b32_e32 v4, v2460; SI-NEXT: v_mov_b32_e32 v2, v1461; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7462; SI-NEXT: ; implicit-def: $vgpr1463; SI-NEXT: ; implicit-def: $vgpr3464; SI-NEXT: ; implicit-def: $vgpr5465; SI-NEXT: ; implicit-def: $vgpr7466; SI-NEXT: ; implicit-def: $vgpr9467; SI-NEXT: ; implicit-def: $vgpr11468; SI-NEXT: ; implicit-def: $vgpr13469; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc470; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]471; SI-NEXT: s_cbranch_execnz .LBB4_3472; SI-NEXT: ; %bb.1: ; %Flow473; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]474; SI-NEXT: s_cbranch_execnz .LBB4_4475; SI-NEXT: .LBB4_2: ; %end476; SI-NEXT: s_or_b64 exec, exec, s[4:5]477; SI-NEXT: s_setpc_b64 s[30:31]478; SI-NEXT: .LBB4_3: ; %cmp.false479; SI-NEXT: v_alignbit_b32 v13, v0, v12, 16480; SI-NEXT: v_alignbit_b32 v9, v10, v8, 16481; SI-NEXT: v_alignbit_b32 v5, v6, v4, 16482; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16483; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10484; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6485; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2486; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]487; SI-NEXT: s_cbranch_execz .LBB4_2488; SI-NEXT: .LBB4_4: ; %cmp.true489; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12490; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2491; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0492; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6493; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4494; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10495; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8496; SI-NEXT: v_alignbit_b32 v9, v10, v8, 16497; SI-NEXT: v_alignbit_b32 v5, v6, v4, 16498; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16499; SI-NEXT: v_alignbit_b32 v13, v0, v12, 16500; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10501; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6502; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2503; SI-NEXT: s_or_b64 exec, exec, s[4:5]504; SI-NEXT: s_setpc_b64 s[30:31]505;506; VI-LABEL: bitcast_v7i32_to_v14i16:507; VI: ; %bb.0:508; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)509; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7510; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc511; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]512; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]513; VI-NEXT: ; %bb.1: ; %cmp.true514; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6515; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5516; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4517; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3518; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2519; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1520; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0521; VI-NEXT: ; %bb.2: ; %end522; VI-NEXT: s_or_b64 exec, exec, s[4:5]523; VI-NEXT: s_setpc_b64 s[30:31]524;525; GFX9-LABEL: bitcast_v7i32_to_v14i16:526; GFX9: ; %bb.0:527; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)528; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7529; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc530; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]531; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]532; GFX9-NEXT: ; %bb.1: ; %cmp.true533; GFX9-NEXT: v_add_u32_e32 v6, 3, v6534; GFX9-NEXT: v_add_u32_e32 v5, 3, v5535; GFX9-NEXT: v_add_u32_e32 v4, 3, v4536; GFX9-NEXT: v_add_u32_e32 v3, 3, v3537; GFX9-NEXT: v_add_u32_e32 v2, 3, v2538; GFX9-NEXT: v_add_u32_e32 v1, 3, v1539; GFX9-NEXT: v_add_u32_e32 v0, 3, v0540; GFX9-NEXT: ; %bb.2: ; %end541; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]542; GFX9-NEXT: s_setpc_b64 s[30:31]543;544; GFX11-LABEL: bitcast_v7i32_to_v14i16:545; GFX11: ; %bb.0:546; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)547; GFX11-NEXT: s_mov_b32 s0, exec_lo548; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7549; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0550; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)551; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0552; GFX11-NEXT: s_cbranch_execz .LBB4_2553; GFX11-NEXT: ; %bb.1: ; %cmp.true554; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6555; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5556; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4557; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3558; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2559; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1560; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0561; GFX11-NEXT: .LBB4_2: ; %end562; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0563; GFX11-NEXT: s_setpc_b64 s[30:31]564 %cmp = icmp eq i32 %b, 0565 br i1 %cmp, label %cmp.true, label %cmp.false566 567cmp.true:568 %a1 = add <7 x i32> %a, splat (i32 3)569 %a2 = bitcast <7 x i32> %a1 to <14 x i16>570 br label %end571 572cmp.false:573 %a3 = bitcast <7 x i32> %a to <14 x i16>574 br label %end575 576end:577 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]578 ret <14 x i16> %phi579}580 581define inreg <14 x i16> @bitcast_v7i32_to_v14i16_scalar(<7 x i32> inreg %a, i32 inreg %b) {582; SI-LABEL: bitcast_v7i32_to_v14i16_scalar:583; SI: ; %bb.0:584; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)585; SI-NEXT: s_cmp_lg_u32 s23, 0586; SI-NEXT: s_cbranch_scc0 .LBB5_4587; SI-NEXT: ; %bb.1: ; %cmp.false588; SI-NEXT: s_lshr_b32 s23, s17, 16589; SI-NEXT: s_lshr_b32 s14, s21, 16590; SI-NEXT: s_lshr_b32 s15, s19, 16591; SI-NEXT: s_lshr_b64 s[6:7], s[22:23], 16592; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 16593; SI-NEXT: s_lshr_b64 s[8:9], s[18:19], 16594; SI-NEXT: s_lshr_b64 s[10:11], s[16:17], 16595; SI-NEXT: s_cbranch_execnz .LBB5_3596; SI-NEXT: .LBB5_2: ; %cmp.true597; SI-NEXT: s_add_i32 s17, s17, 3598; SI-NEXT: s_add_i32 s22, s22, 3599; SI-NEXT: s_add_i32 s16, s16, 3600; SI-NEXT: s_add_i32 s19, s19, 3601; SI-NEXT: s_add_i32 s18, s18, 3602; SI-NEXT: s_add_i32 s21, s21, 3603; SI-NEXT: s_add_i32 s20, s20, 3604; SI-NEXT: s_lshr_b32 s23, s17, 16605; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 16606; SI-NEXT: s_lshr_b64 s[8:9], s[18:19], 16607; SI-NEXT: s_lshr_b64 s[10:11], s[16:17], 16608; SI-NEXT: s_lshr_b32 s14, s21, 16609; SI-NEXT: s_lshr_b32 s15, s19, 16610; SI-NEXT: s_lshr_b64 s[6:7], s[22:23], 16611; SI-NEXT: .LBB5_3: ; %end612; SI-NEXT: v_mov_b32_e32 v0, s16613; SI-NEXT: v_mov_b32_e32 v1, s10614; SI-NEXT: v_mov_b32_e32 v2, s17615; SI-NEXT: v_mov_b32_e32 v3, s23616; SI-NEXT: v_mov_b32_e32 v4, s18617; SI-NEXT: v_mov_b32_e32 v5, s8618; SI-NEXT: v_mov_b32_e32 v6, s19619; SI-NEXT: v_mov_b32_e32 v7, s15620; SI-NEXT: v_mov_b32_e32 v8, s20621; SI-NEXT: v_mov_b32_e32 v9, s4622; SI-NEXT: v_mov_b32_e32 v10, s21623; SI-NEXT: v_mov_b32_e32 v11, s14624; SI-NEXT: v_mov_b32_e32 v12, s22625; SI-NEXT: v_mov_b32_e32 v13, s6626; SI-NEXT: s_setpc_b64 s[30:31]627; SI-NEXT: .LBB5_4:628; SI-NEXT: ; implicit-def: $sgpr10629; SI-NEXT: ; implicit-def: $sgpr23630; SI-NEXT: ; implicit-def: $sgpr8631; SI-NEXT: ; implicit-def: $sgpr15632; SI-NEXT: ; implicit-def: $sgpr4633; SI-NEXT: ; implicit-def: $sgpr14634; SI-NEXT: ; implicit-def: $sgpr6635; SI-NEXT: s_branch .LBB5_2636;637; VI-LABEL: bitcast_v7i32_to_v14i16_scalar:638; VI: ; %bb.0:639; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)640; VI-NEXT: s_cmp_lg_u32 s23, 0641; VI-NEXT: s_cbranch_scc0 .LBB5_4642; VI-NEXT: ; %bb.1: ; %cmp.false643; VI-NEXT: s_cbranch_execnz .LBB5_3644; VI-NEXT: .LBB5_2: ; %cmp.true645; VI-NEXT: s_add_i32 s22, s22, 3646; VI-NEXT: s_add_i32 s21, s21, 3647; VI-NEXT: s_add_i32 s20, s20, 3648; VI-NEXT: s_add_i32 s19, s19, 3649; VI-NEXT: s_add_i32 s18, s18, 3650; VI-NEXT: s_add_i32 s17, s17, 3651; VI-NEXT: s_add_i32 s16, s16, 3652; VI-NEXT: .LBB5_3: ; %end653; VI-NEXT: v_mov_b32_e32 v0, s16654; VI-NEXT: v_mov_b32_e32 v1, s17655; VI-NEXT: v_mov_b32_e32 v2, s18656; VI-NEXT: v_mov_b32_e32 v3, s19657; VI-NEXT: v_mov_b32_e32 v4, s20658; VI-NEXT: v_mov_b32_e32 v5, s21659; VI-NEXT: v_mov_b32_e32 v6, s22660; VI-NEXT: s_setpc_b64 s[30:31]661; VI-NEXT: .LBB5_4:662; VI-NEXT: s_branch .LBB5_2663;664; GFX9-LABEL: bitcast_v7i32_to_v14i16_scalar:665; GFX9: ; %bb.0:666; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; GFX9-NEXT: s_cmp_lg_u32 s23, 0668; GFX9-NEXT: s_cbranch_scc0 .LBB5_4669; GFX9-NEXT: ; %bb.1: ; %cmp.false670; GFX9-NEXT: s_cbranch_execnz .LBB5_3671; GFX9-NEXT: .LBB5_2: ; %cmp.true672; GFX9-NEXT: s_add_i32 s22, s22, 3673; GFX9-NEXT: s_add_i32 s21, s21, 3674; GFX9-NEXT: s_add_i32 s20, s20, 3675; GFX9-NEXT: s_add_i32 s19, s19, 3676; GFX9-NEXT: s_add_i32 s18, s18, 3677; GFX9-NEXT: s_add_i32 s17, s17, 3678; GFX9-NEXT: s_add_i32 s16, s16, 3679; GFX9-NEXT: .LBB5_3: ; %end680; GFX9-NEXT: v_mov_b32_e32 v0, s16681; GFX9-NEXT: v_mov_b32_e32 v1, s17682; GFX9-NEXT: v_mov_b32_e32 v2, s18683; GFX9-NEXT: v_mov_b32_e32 v3, s19684; GFX9-NEXT: v_mov_b32_e32 v4, s20685; GFX9-NEXT: v_mov_b32_e32 v5, s21686; GFX9-NEXT: v_mov_b32_e32 v6, s22687; GFX9-NEXT: s_setpc_b64 s[30:31]688; GFX9-NEXT: .LBB5_4:689; GFX9-NEXT: s_branch .LBB5_2690;691; GFX11-LABEL: bitcast_v7i32_to_v14i16_scalar:692; GFX11: ; %bb.0:693; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)694; GFX11-NEXT: s_cmp_lg_u32 s19, 0695; GFX11-NEXT: s_mov_b32 s4, 0696; GFX11-NEXT: s_cbranch_scc0 .LBB5_4697; GFX11-NEXT: ; %bb.1: ; %Flow698; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4699; GFX11-NEXT: s_cbranch_vccnz .LBB5_3700; GFX11-NEXT: .LBB5_2: ; %cmp.true701; GFX11-NEXT: s_add_i32 s18, s18, 3702; GFX11-NEXT: s_add_i32 s17, s17, 3703; GFX11-NEXT: s_add_i32 s16, s16, 3704; GFX11-NEXT: s_add_i32 s3, s3, 3705; GFX11-NEXT: s_add_i32 s2, s2, 3706; GFX11-NEXT: s_add_i32 s1, s1, 3707; GFX11-NEXT: s_add_i32 s0, s0, 3708; GFX11-NEXT: .LBB5_3: ; %end709; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)710; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1711; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3712; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17713; GFX11-NEXT: v_mov_b32_e32 v6, s18714; GFX11-NEXT: s_setpc_b64 s[30:31]715; GFX11-NEXT: .LBB5_4:716; GFX11-NEXT: s_branch .LBB5_2717 %cmp = icmp eq i32 %b, 0718 br i1 %cmp, label %cmp.true, label %cmp.false719 720cmp.true:721 %a1 = add <7 x i32> %a, splat (i32 3)722 %a2 = bitcast <7 x i32> %a1 to <14 x i16>723 br label %end724 725cmp.false:726 %a3 = bitcast <7 x i32> %a to <14 x i16>727 br label %end728 729end:730 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]731 ret <14 x i16> %phi732}733 734define <7 x i32> @bitcast_v14i16_to_v7i32(<14 x i16> %a, i32 %b) {735; SI-LABEL: bitcast_v14i16_to_v7i32:736; SI: ; %bb.0:737; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)738; SI-NEXT: v_mov_b32_e32 v18, v6739; SI-NEXT: v_mov_b32_e32 v17, v4740; SI-NEXT: v_mov_b32_e32 v16, v2741; SI-NEXT: v_mov_b32_e32 v15, v0742; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v14743; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v1744; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v3745; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v5746; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v7747; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v9748; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v11749; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v13750; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6751; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc752; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]753; SI-NEXT: s_cbranch_execnz .LBB6_3754; SI-NEXT: ; %bb.1: ; %Flow755; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]756; SI-NEXT: s_cbranch_execnz .LBB6_4757; SI-NEXT: .LBB6_2: ; %end758; SI-NEXT: s_or_b64 exec, exec, s[4:5]759; SI-NEXT: s_setpc_b64 s[30:31]760; SI-NEXT: .LBB6_3: ; %cmp.false761; SI-NEXT: v_and_b32_e32 v0, 0xffff, v15762; SI-NEXT: v_and_b32_e32 v1, 0xffff, v16763; SI-NEXT: v_and_b32_e32 v2, 0xffff, v17764; SI-NEXT: v_and_b32_e32 v3, 0xffff, v18765; SI-NEXT: v_and_b32_e32 v4, 0xffff, v8766; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10767; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12768; SI-NEXT: v_or_b32_e32 v0, v0, v22769; SI-NEXT: v_or_b32_e32 v1, v1, v21770; SI-NEXT: v_or_b32_e32 v2, v2, v20771; SI-NEXT: v_or_b32_e32 v3, v3, v19772; SI-NEXT: v_or_b32_e32 v4, v4, v14773; SI-NEXT: v_or_b32_e32 v5, v5, v9774; SI-NEXT: v_or_b32_e32 v6, v6, v7775; SI-NEXT: ; implicit-def: $vgpr15776; SI-NEXT: ; implicit-def: $vgpr16777; SI-NEXT: ; implicit-def: $vgpr17778; SI-NEXT: ; implicit-def: $vgpr18779; SI-NEXT: ; implicit-def: $vgpr8780; SI-NEXT: ; implicit-def: $vgpr10781; SI-NEXT: ; implicit-def: $vgpr12782; SI-NEXT: ; implicit-def: $vgpr22783; SI-NEXT: ; implicit-def: $vgpr21784; SI-NEXT: ; implicit-def: $vgpr20785; SI-NEXT: ; implicit-def: $vgpr19786; SI-NEXT: ; implicit-def: $vgpr14787; SI-NEXT: ; implicit-def: $vgpr9788; SI-NEXT: ; implicit-def: $vgpr7789; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]790; SI-NEXT: s_cbranch_execz .LBB6_2791; SI-NEXT: .LBB6_4: ; %cmp.true792; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v15793; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v16794; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v17795; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v18796; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v8797; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10798; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v12799; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0800; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1801; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2802; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3803; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4804; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5805; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6806; SI-NEXT: v_or_b32_e32 v0, v22, v0807; SI-NEXT: s_mov_b32 s6, 0x30000808; SI-NEXT: v_or_b32_e32 v1, v21, v1809; SI-NEXT: v_or_b32_e32 v2, v20, v2810; SI-NEXT: v_or_b32_e32 v3, v19, v3811; SI-NEXT: v_or_b32_e32 v4, v14, v4812; SI-NEXT: v_or_b32_e32 v5, v9, v5813; SI-NEXT: v_or_b32_e32 v6, v7, v6814; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0815; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1816; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2817; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3818; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v4819; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v5820; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6821; SI-NEXT: s_or_b64 exec, exec, s[4:5]822; SI-NEXT: s_setpc_b64 s[30:31]823;824; VI-LABEL: bitcast_v14i16_to_v7i32:825; VI: ; %bb.0:826; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)827; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7828; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc829; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]830; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]831; VI-NEXT: s_cbranch_execz .LBB6_2832; VI-NEXT: ; %bb.1: ; %cmp.true833; VI-NEXT: v_mov_b32_e32 v8, 3834; VI-NEXT: v_add_u16_e32 v7, 3, v6835; VI-NEXT: v_add_u16_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD836; VI-NEXT: v_or_b32_e32 v6, v7, v6837; VI-NEXT: v_add_u16_e32 v7, 3, v5838; VI-NEXT: v_add_u16_sdwa v5, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD839; VI-NEXT: v_or_b32_e32 v5, v7, v5840; VI-NEXT: v_add_u16_e32 v7, 3, v4841; VI-NEXT: v_add_u16_sdwa v4, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD842; VI-NEXT: v_or_b32_e32 v4, v7, v4843; VI-NEXT: v_add_u16_e32 v7, 3, v3844; VI-NEXT: v_add_u16_sdwa v3, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD845; VI-NEXT: v_or_b32_e32 v3, v7, v3846; VI-NEXT: v_add_u16_e32 v7, 3, v2847; VI-NEXT: v_add_u16_sdwa v2, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD848; VI-NEXT: v_or_b32_e32 v2, v7, v2849; VI-NEXT: v_add_u16_e32 v7, 3, v1850; VI-NEXT: v_add_u16_sdwa v1, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD851; VI-NEXT: v_or_b32_e32 v1, v7, v1852; VI-NEXT: v_add_u16_e32 v7, 3, v0853; VI-NEXT: v_add_u16_sdwa v0, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD854; VI-NEXT: v_or_b32_e32 v0, v7, v0855; VI-NEXT: .LBB6_2: ; %end856; VI-NEXT: s_or_b64 exec, exec, s[4:5]857; VI-NEXT: s_setpc_b64 s[30:31]858;859; GFX9-LABEL: bitcast_v14i16_to_v7i32:860; GFX9: ; %bb.0:861; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)862; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7863; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc864; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]865; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]866; GFX9-NEXT: ; %bb.1: ; %cmp.true867; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]868; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]869; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]870; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]871; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]872; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]873; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]874; GFX9-NEXT: ; %bb.2: ; %end875; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]876; GFX9-NEXT: s_setpc_b64 s[30:31]877;878; GFX11-LABEL: bitcast_v14i16_to_v7i32:879; GFX11: ; %bb.0:880; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)881; GFX11-NEXT: s_mov_b32 s0, exec_lo882; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v7883; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0884; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)885; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0886; GFX11-NEXT: s_cbranch_execz .LBB6_2887; GFX11-NEXT: ; %bb.1: ; %cmp.true888; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]889; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]890; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]891; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]892; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]893; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]894; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]895; GFX11-NEXT: .LBB6_2: ; %end896; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0897; GFX11-NEXT: s_setpc_b64 s[30:31]898 %cmp = icmp eq i32 %b, 0899 br i1 %cmp, label %cmp.true, label %cmp.false900 901cmp.true:902 %a1 = add <14 x i16> %a, splat (i16 3)903 %a2 = bitcast <14 x i16> %a1 to <7 x i32>904 br label %end905 906cmp.false:907 %a3 = bitcast <14 x i16> %a to <7 x i32>908 br label %end909 910end:911 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]912 ret <7 x i32> %phi913}914 915define inreg <7 x i32> @bitcast_v14i16_to_v7i32_scalar(<14 x i16> inreg %a, i32 inreg %b) {916; SI-LABEL: bitcast_v14i16_to_v7i32_scalar:917; SI: ; %bb.0:918; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)919; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0920; SI-NEXT: s_and_b64 s[4:5], vcc, exec921; SI-NEXT: s_cbranch_scc0 .LBB7_4922; SI-NEXT: ; %bb.1: ; %cmp.false923; SI-NEXT: s_and_b32 s4, s16, 0xffff924; SI-NEXT: s_lshl_b32 s5, s17, 16925; SI-NEXT: s_or_b32 s4, s4, s5926; SI-NEXT: s_and_b32 s5, s18, 0xffff927; SI-NEXT: s_lshl_b32 s6, s19, 16928; SI-NEXT: s_or_b32 s5, s5, s6929; SI-NEXT: s_and_b32 s6, s20, 0xffff930; SI-NEXT: s_lshl_b32 s7, s21, 16931; SI-NEXT: s_or_b32 s6, s6, s7932; SI-NEXT: s_and_b32 s7, s22, 0xffff933; SI-NEXT: s_lshl_b32 s8, s23, 16934; SI-NEXT: s_or_b32 s7, s7, s8935; SI-NEXT: s_and_b32 s8, s24, 0xffff936; SI-NEXT: s_lshl_b32 s9, s25, 16937; SI-NEXT: s_or_b32 s8, s8, s9938; SI-NEXT: s_and_b32 s9, s26, 0xffff939; SI-NEXT: s_lshl_b32 s10, s27, 16940; SI-NEXT: s_or_b32 s9, s9, s10941; SI-NEXT: s_and_b32 s10, s28, 0xffff942; SI-NEXT: s_lshl_b32 s11, s29, 16943; SI-NEXT: s_or_b32 s10, s10, s11944; SI-NEXT: s_cbranch_execnz .LBB7_3945; SI-NEXT: .LBB7_2: ; %cmp.true946; SI-NEXT: s_add_i32 s16, s16, 3947; SI-NEXT: s_and_b32 s4, s16, 0xffff948; SI-NEXT: s_lshl_b32 s5, s17, 16949; SI-NEXT: s_add_i32 s18, s18, 3950; SI-NEXT: s_or_b32 s4, s5, s4951; SI-NEXT: s_and_b32 s5, s18, 0xffff952; SI-NEXT: s_lshl_b32 s6, s19, 16953; SI-NEXT: s_add_i32 s20, s20, 3954; SI-NEXT: s_or_b32 s5, s6, s5955; SI-NEXT: s_and_b32 s6, s20, 0xffff956; SI-NEXT: s_lshl_b32 s7, s21, 16957; SI-NEXT: s_add_i32 s22, s22, 3958; SI-NEXT: s_or_b32 s6, s7, s6959; SI-NEXT: s_and_b32 s7, s22, 0xffff960; SI-NEXT: s_lshl_b32 s8, s23, 16961; SI-NEXT: s_add_i32 s24, s24, 3962; SI-NEXT: s_or_b32 s7, s8, s7963; SI-NEXT: s_and_b32 s8, s24, 0xffff964; SI-NEXT: s_lshl_b32 s9, s25, 16965; SI-NEXT: s_add_i32 s26, s26, 3966; SI-NEXT: s_or_b32 s8, s9, s8967; SI-NEXT: s_and_b32 s9, s26, 0xffff968; SI-NEXT: s_lshl_b32 s10, s27, 16969; SI-NEXT: s_add_i32 s28, s28, 3970; SI-NEXT: s_or_b32 s9, s10, s9971; SI-NEXT: s_and_b32 s10, s28, 0xffff972; SI-NEXT: s_lshl_b32 s11, s29, 16973; SI-NEXT: s_or_b32 s10, s11, s10974; SI-NEXT: s_add_i32 s4, s4, 0x30000975; SI-NEXT: s_add_i32 s5, s5, 0x30000976; SI-NEXT: s_add_i32 s6, s6, 0x30000977; SI-NEXT: s_add_i32 s7, s7, 0x30000978; SI-NEXT: s_add_i32 s8, s8, 0x30000979; SI-NEXT: s_add_i32 s9, s9, 0x30000980; SI-NEXT: s_add_i32 s10, s10, 0x30000981; SI-NEXT: .LBB7_3: ; %end982; SI-NEXT: v_mov_b32_e32 v0, s4983; SI-NEXT: v_mov_b32_e32 v1, s5984; SI-NEXT: v_mov_b32_e32 v2, s6985; SI-NEXT: v_mov_b32_e32 v3, s7986; SI-NEXT: v_mov_b32_e32 v4, s8987; SI-NEXT: v_mov_b32_e32 v5, s9988; SI-NEXT: v_mov_b32_e32 v6, s10989; SI-NEXT: s_setpc_b64 s[30:31]990; SI-NEXT: .LBB7_4:991; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10992; SI-NEXT: s_branch .LBB7_2993;994; VI-LABEL: bitcast_v14i16_to_v7i32_scalar:995; VI: ; %bb.0:996; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)997; VI-NEXT: s_cmp_lg_u32 s23, 0998; VI-NEXT: s_cbranch_scc0 .LBB7_4999; VI-NEXT: ; %bb.1: ; %cmp.false1000; VI-NEXT: s_cbranch_execnz .LBB7_31001; VI-NEXT: .LBB7_2: ; %cmp.true1002; VI-NEXT: s_add_i32 s5, s22, 31003; VI-NEXT: s_and_b32 s4, s22, 0xffff00001004; VI-NEXT: s_and_b32 s5, s5, 0xffff1005; VI-NEXT: s_or_b32 s4, s4, s51006; VI-NEXT: s_add_i32 s5, s21, 31007; VI-NEXT: s_add_i32 s22, s4, 0x300001008; VI-NEXT: s_and_b32 s4, s21, 0xffff00001009; VI-NEXT: s_and_b32 s5, s5, 0xffff1010; VI-NEXT: s_or_b32 s4, s4, s51011; VI-NEXT: s_add_i32 s5, s20, 31012; VI-NEXT: s_add_i32 s21, s4, 0x300001013; VI-NEXT: s_and_b32 s4, s20, 0xffff00001014; VI-NEXT: s_and_b32 s5, s5, 0xffff1015; VI-NEXT: s_or_b32 s4, s4, s51016; VI-NEXT: s_add_i32 s5, s19, 31017; VI-NEXT: s_add_i32 s20, s4, 0x300001018; VI-NEXT: s_and_b32 s4, s19, 0xffff00001019; VI-NEXT: s_and_b32 s5, s5, 0xffff1020; VI-NEXT: s_or_b32 s4, s4, s51021; VI-NEXT: s_add_i32 s5, s18, 31022; VI-NEXT: s_add_i32 s19, s4, 0x300001023; VI-NEXT: s_and_b32 s4, s18, 0xffff00001024; VI-NEXT: s_and_b32 s5, s5, 0xffff1025; VI-NEXT: s_or_b32 s4, s4, s51026; VI-NEXT: s_add_i32 s5, s17, 31027; VI-NEXT: s_add_i32 s18, s4, 0x300001028; VI-NEXT: s_and_b32 s4, s17, 0xffff00001029; VI-NEXT: s_and_b32 s5, s5, 0xffff1030; VI-NEXT: s_or_b32 s4, s4, s51031; VI-NEXT: s_add_i32 s5, s16, 31032; VI-NEXT: s_add_i32 s17, s4, 0x300001033; VI-NEXT: s_and_b32 s4, s16, 0xffff00001034; VI-NEXT: s_and_b32 s5, s5, 0xffff1035; VI-NEXT: s_or_b32 s4, s4, s51036; VI-NEXT: s_add_i32 s16, s4, 0x300001037; VI-NEXT: .LBB7_3: ; %end1038; VI-NEXT: v_mov_b32_e32 v0, s161039; VI-NEXT: v_mov_b32_e32 v1, s171040; VI-NEXT: v_mov_b32_e32 v2, s181041; VI-NEXT: v_mov_b32_e32 v3, s191042; VI-NEXT: v_mov_b32_e32 v4, s201043; VI-NEXT: v_mov_b32_e32 v5, s211044; VI-NEXT: v_mov_b32_e32 v6, s221045; VI-NEXT: s_setpc_b64 s[30:31]1046; VI-NEXT: .LBB7_4:1047; VI-NEXT: s_branch .LBB7_21048;1049; GFX9-LABEL: bitcast_v14i16_to_v7i32_scalar:1050; GFX9: ; %bb.0:1051; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1052; GFX9-NEXT: s_cmp_lg_u32 s23, 01053; GFX9-NEXT: s_cbranch_scc0 .LBB7_31054; GFX9-NEXT: ; %bb.1: ; %cmp.false1055; GFX9-NEXT: s_cbranch_execnz .LBB7_41056; GFX9-NEXT: .LBB7_2: ; %cmp.true1057; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]1058; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]1059; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]1060; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]1061; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]1062; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]1063; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1064; GFX9-NEXT: s_setpc_b64 s[30:31]1065; GFX9-NEXT: .LBB7_3:1066; GFX9-NEXT: s_branch .LBB7_21067; GFX9-NEXT: .LBB7_4:1068; GFX9-NEXT: v_mov_b32_e32 v0, s161069; GFX9-NEXT: v_mov_b32_e32 v1, s171070; GFX9-NEXT: v_mov_b32_e32 v2, s181071; GFX9-NEXT: v_mov_b32_e32 v3, s191072; GFX9-NEXT: v_mov_b32_e32 v4, s201073; GFX9-NEXT: v_mov_b32_e32 v5, s211074; GFX9-NEXT: v_mov_b32_e32 v6, s221075; GFX9-NEXT: s_setpc_b64 s[30:31]1076;1077; GFX11-LABEL: bitcast_v14i16_to_v7i32_scalar:1078; GFX11: ; %bb.0:1079; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1080; GFX11-NEXT: s_mov_b32 s6, s181081; GFX11-NEXT: s_mov_b32 s5, s171082; GFX11-NEXT: s_mov_b32 s4, s161083; GFX11-NEXT: s_cmp_lg_u32 s19, 01084; GFX11-NEXT: s_mov_b32 s7, 01085; GFX11-NEXT: s_cbranch_scc0 .LBB7_31086; GFX11-NEXT: ; %bb.1: ; %Flow1087; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s71088; GFX11-NEXT: s_cbranch_vccnz .LBB7_41089; GFX11-NEXT: .LBB7_2: ; %cmp.true1090; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]1091; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]1092; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]1093; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]1094; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]1095; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]1096; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]1097; GFX11-NEXT: s_setpc_b64 s[30:31]1098; GFX11-NEXT: .LBB7_3:1099; GFX11-NEXT: s_branch .LBB7_21100; GFX11-NEXT: .LBB7_4:1101; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11102; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31103; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s51104; GFX11-NEXT: v_mov_b32_e32 v6, s61105; GFX11-NEXT: s_setpc_b64 s[30:31]1106 %cmp = icmp eq i32 %b, 01107 br i1 %cmp, label %cmp.true, label %cmp.false1108 1109cmp.true:1110 %a1 = add <14 x i16> %a, splat (i16 3)1111 %a2 = bitcast <14 x i16> %a1 to <7 x i32>1112 br label %end1113 1114cmp.false:1115 %a3 = bitcast <14 x i16> %a to <7 x i32>1116 br label %end1117 1118end:1119 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1120 ret <7 x i32> %phi1121}1122 1123define <14 x half> @bitcast_v7i32_to_v14f16(<7 x i32> %a, i32 %b) {1124; SI-LABEL: bitcast_v7i32_to_v14f16:1125; SI: ; %bb.0:1126; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1127; SI-NEXT: v_mov_b32_e32 v20, v61128; SI-NEXT: v_mov_b32_e32 v19, v51129; SI-NEXT: v_mov_b32_e32 v18, v41130; SI-NEXT: v_mov_b32_e32 v17, v31131; SI-NEXT: v_mov_b32_e32 v16, v21132; SI-NEXT: v_mov_b32_e32 v15, v11133; SI-NEXT: v_mov_b32_e32 v14, v01134; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71135; SI-NEXT: ; implicit-def: $vgpr01136; SI-NEXT: ; implicit-def: $vgpr11137; SI-NEXT: ; implicit-def: $vgpr21138; SI-NEXT: ; implicit-def: $vgpr31139; SI-NEXT: ; implicit-def: $vgpr41140; SI-NEXT: ; implicit-def: $vgpr51141; SI-NEXT: ; implicit-def: $vgpr61142; SI-NEXT: ; implicit-def: $vgpr71143; SI-NEXT: ; implicit-def: $vgpr81144; SI-NEXT: ; implicit-def: $vgpr91145; SI-NEXT: ; implicit-def: $vgpr101146; SI-NEXT: ; implicit-def: $vgpr111147; SI-NEXT: ; implicit-def: $vgpr121148; SI-NEXT: ; implicit-def: $vgpr131149; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1150; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1151; SI-NEXT: s_cbranch_execnz .LBB8_31152; SI-NEXT: ; %bb.1: ; %Flow1153; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1154; SI-NEXT: s_cbranch_execnz .LBB8_41155; SI-NEXT: .LBB8_2: ; %end1156; SI-NEXT: s_or_b64 exec, exec, s[4:5]1157; SI-NEXT: s_setpc_b64 s[30:31]1158; SI-NEXT: .LBB8_3: ; %cmp.false1159; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v201160; SI-NEXT: v_cvt_f32_f16_e32 v13, v01161; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v191162; SI-NEXT: v_cvt_f32_f16_e32 v11, v01163; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v181164; SI-NEXT: v_cvt_f32_f16_e32 v9, v01165; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v171166; SI-NEXT: v_cvt_f32_f16_e32 v7, v01167; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v161168; SI-NEXT: v_cvt_f32_f16_e32 v5, v01169; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v151170; SI-NEXT: v_cvt_f32_f16_e32 v3, v01171; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v141172; SI-NEXT: v_cvt_f32_f16_e32 v1, v01173; SI-NEXT: v_cvt_f32_f16_e32 v12, v201174; SI-NEXT: v_cvt_f32_f16_e32 v10, v191175; SI-NEXT: v_cvt_f32_f16_e32 v8, v181176; SI-NEXT: v_cvt_f32_f16_e32 v6, v171177; SI-NEXT: v_cvt_f32_f16_e32 v4, v161178; SI-NEXT: v_cvt_f32_f16_e32 v2, v151179; SI-NEXT: v_cvt_f32_f16_e32 v0, v141180; SI-NEXT: ; implicit-def: $vgpr141181; SI-NEXT: ; implicit-def: $vgpr151182; SI-NEXT: ; implicit-def: $vgpr161183; SI-NEXT: ; implicit-def: $vgpr171184; SI-NEXT: ; implicit-def: $vgpr181185; SI-NEXT: ; implicit-def: $vgpr191186; SI-NEXT: ; implicit-def: $vgpr201187; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1188; SI-NEXT: s_cbranch_execz .LBB8_21189; SI-NEXT: .LBB8_4: ; %cmp.true1190; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v141191; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v151192; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v161193; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v171194; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v181195; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v191196; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v201197; SI-NEXT: v_cvt_f32_f16_e32 v12, v131198; SI-NEXT: v_cvt_f32_f16_e32 v10, v111199; SI-NEXT: v_cvt_f32_f16_e32 v8, v91200; SI-NEXT: v_cvt_f32_f16_e32 v6, v71201; SI-NEXT: v_cvt_f32_f16_e32 v4, v51202; SI-NEXT: v_cvt_f32_f16_e32 v2, v31203; SI-NEXT: v_cvt_f32_f16_e32 v0, v11204; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v131205; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v111206; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v91207; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v71208; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v51209; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v31210; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11211; SI-NEXT: v_cvt_f32_f16_e32 v13, v131212; SI-NEXT: v_cvt_f32_f16_e32 v11, v111213; SI-NEXT: v_cvt_f32_f16_e32 v9, v91214; SI-NEXT: v_cvt_f32_f16_e32 v7, v71215; SI-NEXT: v_cvt_f32_f16_e32 v5, v51216; SI-NEXT: v_cvt_f32_f16_e32 v3, v31217; SI-NEXT: v_cvt_f32_f16_e32 v1, v11218; SI-NEXT: s_or_b64 exec, exec, s[4:5]1219; SI-NEXT: s_setpc_b64 s[30:31]1220;1221; VI-LABEL: bitcast_v7i32_to_v14f16:1222; VI: ; %bb.0:1223; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1224; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71225; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1226; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1227; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1228; VI-NEXT: ; %bb.1: ; %cmp.true1229; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v61230; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51231; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41232; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31233; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21234; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11235; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01236; VI-NEXT: ; %bb.2: ; %end1237; VI-NEXT: s_or_b64 exec, exec, s[4:5]1238; VI-NEXT: s_setpc_b64 s[30:31]1239;1240; GFX9-LABEL: bitcast_v7i32_to_v14f16:1241; GFX9: ; %bb.0:1242; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1243; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71244; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1245; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1246; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1247; GFX9-NEXT: ; %bb.1: ; %cmp.true1248; GFX9-NEXT: v_add_u32_e32 v6, 3, v61249; GFX9-NEXT: v_add_u32_e32 v5, 3, v51250; GFX9-NEXT: v_add_u32_e32 v4, 3, v41251; GFX9-NEXT: v_add_u32_e32 v3, 3, v31252; GFX9-NEXT: v_add_u32_e32 v2, 3, v21253; GFX9-NEXT: v_add_u32_e32 v1, 3, v11254; GFX9-NEXT: v_add_u32_e32 v0, 3, v01255; GFX9-NEXT: ; %bb.2: ; %end1256; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1257; GFX9-NEXT: s_setpc_b64 s[30:31]1258;1259; GFX11-LABEL: bitcast_v7i32_to_v14f16:1260; GFX11: ; %bb.0:1261; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1262; GFX11-NEXT: s_mov_b32 s0, exec_lo1263; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v71264; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01265; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1266; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01267; GFX11-NEXT: s_cbranch_execz .LBB8_21268; GFX11-NEXT: ; %bb.1: ; %cmp.true1269; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v61270; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51271; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41272; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31273; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21274; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11275; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01276; GFX11-NEXT: .LBB8_2: ; %end1277; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01278; GFX11-NEXT: s_setpc_b64 s[30:31]1279 %cmp = icmp eq i32 %b, 01280 br i1 %cmp, label %cmp.true, label %cmp.false1281 1282cmp.true:1283 %a1 = add <7 x i32> %a, splat (i32 3)1284 %a2 = bitcast <7 x i32> %a1 to <14 x half>1285 br label %end1286 1287cmp.false:1288 %a3 = bitcast <7 x i32> %a to <14 x half>1289 br label %end1290 1291end:1292 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1293 ret <14 x half> %phi1294}1295 1296define inreg <14 x half> @bitcast_v7i32_to_v14f16_scalar(<7 x i32> inreg %a, i32 inreg %b) {1297; SI-LABEL: bitcast_v7i32_to_v14f16_scalar:1298; SI: ; %bb.0:1299; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1300; SI-NEXT: s_cmp_lg_u32 s23, 01301; SI-NEXT: s_cbranch_scc0 .LBB9_41302; SI-NEXT: ; %bb.1: ; %cmp.false1303; SI-NEXT: s_lshr_b32 s4, s22, 161304; SI-NEXT: v_cvt_f32_f16_e32 v13, s41305; SI-NEXT: s_lshr_b32 s4, s21, 161306; SI-NEXT: v_cvt_f32_f16_e32 v11, s41307; SI-NEXT: s_lshr_b32 s4, s20, 161308; SI-NEXT: v_cvt_f32_f16_e32 v9, s41309; SI-NEXT: s_lshr_b32 s4, s19, 161310; SI-NEXT: v_cvt_f32_f16_e32 v7, s41311; SI-NEXT: s_lshr_b32 s4, s18, 161312; SI-NEXT: v_cvt_f32_f16_e32 v5, s41313; SI-NEXT: s_lshr_b32 s4, s17, 161314; SI-NEXT: v_cvt_f32_f16_e32 v3, s41315; SI-NEXT: s_lshr_b32 s4, s16, 161316; SI-NEXT: v_cvt_f32_f16_e32 v1, s41317; SI-NEXT: v_cvt_f32_f16_e32 v12, s221318; SI-NEXT: v_cvt_f32_f16_e32 v10, s211319; SI-NEXT: v_cvt_f32_f16_e32 v8, s201320; SI-NEXT: v_cvt_f32_f16_e32 v6, s191321; SI-NEXT: v_cvt_f32_f16_e32 v4, s181322; SI-NEXT: v_cvt_f32_f16_e32 v2, s171323; SI-NEXT: v_cvt_f32_f16_e32 v0, s161324; SI-NEXT: s_cbranch_execnz .LBB9_31325; SI-NEXT: .LBB9_2: ; %cmp.true1326; SI-NEXT: s_add_i32 s22, s22, 31327; SI-NEXT: s_add_i32 s21, s21, 31328; SI-NEXT: s_lshr_b32 s4, s22, 161329; SI-NEXT: s_add_i32 s20, s20, 31330; SI-NEXT: v_cvt_f32_f16_e32 v13, s41331; SI-NEXT: s_lshr_b32 s4, s21, 161332; SI-NEXT: s_add_i32 s19, s19, 31333; SI-NEXT: v_cvt_f32_f16_e32 v11, s41334; SI-NEXT: s_lshr_b32 s4, s20, 161335; SI-NEXT: s_add_i32 s18, s18, 31336; SI-NEXT: v_cvt_f32_f16_e32 v9, s41337; SI-NEXT: s_lshr_b32 s4, s19, 161338; SI-NEXT: s_add_i32 s17, s17, 31339; SI-NEXT: v_cvt_f32_f16_e32 v7, s41340; SI-NEXT: s_lshr_b32 s4, s18, 161341; SI-NEXT: s_add_i32 s16, s16, 31342; SI-NEXT: v_cvt_f32_f16_e32 v5, s41343; SI-NEXT: s_lshr_b32 s4, s17, 161344; SI-NEXT: v_cvt_f32_f16_e32 v3, s41345; SI-NEXT: s_lshr_b32 s4, s16, 161346; SI-NEXT: v_cvt_f32_f16_e32 v12, s221347; SI-NEXT: v_cvt_f32_f16_e32 v10, s211348; SI-NEXT: v_cvt_f32_f16_e32 v8, s201349; SI-NEXT: v_cvt_f32_f16_e32 v6, s191350; SI-NEXT: v_cvt_f32_f16_e32 v4, s181351; SI-NEXT: v_cvt_f32_f16_e32 v2, s171352; SI-NEXT: v_cvt_f32_f16_e32 v0, s161353; SI-NEXT: v_cvt_f32_f16_e32 v1, s41354; SI-NEXT: .LBB9_3: ; %end1355; SI-NEXT: s_setpc_b64 s[30:31]1356; SI-NEXT: .LBB9_4:1357; SI-NEXT: ; implicit-def: $vgpr01358; SI-NEXT: ; implicit-def: $vgpr11359; SI-NEXT: ; implicit-def: $vgpr21360; SI-NEXT: ; implicit-def: $vgpr31361; SI-NEXT: ; implicit-def: $vgpr41362; SI-NEXT: ; implicit-def: $vgpr51363; SI-NEXT: ; implicit-def: $vgpr61364; SI-NEXT: ; implicit-def: $vgpr71365; SI-NEXT: ; implicit-def: $vgpr81366; SI-NEXT: ; implicit-def: $vgpr91367; SI-NEXT: ; implicit-def: $vgpr101368; SI-NEXT: ; implicit-def: $vgpr111369; SI-NEXT: ; implicit-def: $vgpr121370; SI-NEXT: ; implicit-def: $vgpr131371; SI-NEXT: s_branch .LBB9_21372;1373; VI-LABEL: bitcast_v7i32_to_v14f16_scalar:1374; VI: ; %bb.0:1375; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1376; VI-NEXT: s_cmp_lg_u32 s23, 01377; VI-NEXT: s_cbranch_scc0 .LBB9_41378; VI-NEXT: ; %bb.1: ; %cmp.false1379; VI-NEXT: s_cbranch_execnz .LBB9_31380; VI-NEXT: .LBB9_2: ; %cmp.true1381; VI-NEXT: s_add_i32 s22, s22, 31382; VI-NEXT: s_add_i32 s21, s21, 31383; VI-NEXT: s_add_i32 s20, s20, 31384; VI-NEXT: s_add_i32 s19, s19, 31385; VI-NEXT: s_add_i32 s18, s18, 31386; VI-NEXT: s_add_i32 s17, s17, 31387; VI-NEXT: s_add_i32 s16, s16, 31388; VI-NEXT: .LBB9_3: ; %end1389; VI-NEXT: v_mov_b32_e32 v0, s161390; VI-NEXT: v_mov_b32_e32 v1, s171391; VI-NEXT: v_mov_b32_e32 v2, s181392; VI-NEXT: v_mov_b32_e32 v3, s191393; VI-NEXT: v_mov_b32_e32 v4, s201394; VI-NEXT: v_mov_b32_e32 v5, s211395; VI-NEXT: v_mov_b32_e32 v6, s221396; VI-NEXT: s_setpc_b64 s[30:31]1397; VI-NEXT: .LBB9_4:1398; VI-NEXT: s_branch .LBB9_21399;1400; GFX9-LABEL: bitcast_v7i32_to_v14f16_scalar:1401; GFX9: ; %bb.0:1402; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1403; GFX9-NEXT: s_cmp_lg_u32 s23, 01404; GFX9-NEXT: s_cbranch_scc0 .LBB9_41405; GFX9-NEXT: ; %bb.1: ; %cmp.false1406; GFX9-NEXT: s_cbranch_execnz .LBB9_31407; GFX9-NEXT: .LBB9_2: ; %cmp.true1408; GFX9-NEXT: s_add_i32 s22, s22, 31409; GFX9-NEXT: s_add_i32 s21, s21, 31410; GFX9-NEXT: s_add_i32 s20, s20, 31411; GFX9-NEXT: s_add_i32 s19, s19, 31412; GFX9-NEXT: s_add_i32 s18, s18, 31413; GFX9-NEXT: s_add_i32 s17, s17, 31414; GFX9-NEXT: s_add_i32 s16, s16, 31415; GFX9-NEXT: .LBB9_3: ; %end1416; GFX9-NEXT: v_mov_b32_e32 v0, s161417; GFX9-NEXT: v_mov_b32_e32 v1, s171418; GFX9-NEXT: v_mov_b32_e32 v2, s181419; GFX9-NEXT: v_mov_b32_e32 v3, s191420; GFX9-NEXT: v_mov_b32_e32 v4, s201421; GFX9-NEXT: v_mov_b32_e32 v5, s211422; GFX9-NEXT: v_mov_b32_e32 v6, s221423; GFX9-NEXT: s_setpc_b64 s[30:31]1424; GFX9-NEXT: .LBB9_4:1425; GFX9-NEXT: s_branch .LBB9_21426;1427; GFX11-LABEL: bitcast_v7i32_to_v14f16_scalar:1428; GFX11: ; %bb.0:1429; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1430; GFX11-NEXT: s_cmp_lg_u32 s19, 01431; GFX11-NEXT: s_mov_b32 s4, 01432; GFX11-NEXT: s_cbranch_scc0 .LBB9_41433; GFX11-NEXT: ; %bb.1: ; %Flow1434; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41435; GFX11-NEXT: s_cbranch_vccnz .LBB9_31436; GFX11-NEXT: .LBB9_2: ; %cmp.true1437; GFX11-NEXT: s_add_i32 s18, s18, 31438; GFX11-NEXT: s_add_i32 s17, s17, 31439; GFX11-NEXT: s_add_i32 s16, s16, 31440; GFX11-NEXT: s_add_i32 s3, s3, 31441; GFX11-NEXT: s_add_i32 s2, s2, 31442; GFX11-NEXT: s_add_i32 s1, s1, 31443; GFX11-NEXT: s_add_i32 s0, s0, 31444; GFX11-NEXT: .LBB9_3: ; %end1445; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1446; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11447; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31448; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171449; GFX11-NEXT: v_mov_b32_e32 v6, s181450; GFX11-NEXT: s_setpc_b64 s[30:31]1451; GFX11-NEXT: .LBB9_4:1452; GFX11-NEXT: s_branch .LBB9_21453 %cmp = icmp eq i32 %b, 01454 br i1 %cmp, label %cmp.true, label %cmp.false1455 1456cmp.true:1457 %a1 = add <7 x i32> %a, splat (i32 3)1458 %a2 = bitcast <7 x i32> %a1 to <14 x half>1459 br label %end1460 1461cmp.false:1462 %a3 = bitcast <7 x i32> %a to <14 x half>1463 br label %end1464 1465end:1466 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1467 ret <14 x half> %phi1468}1469 1470define <7 x i32> @bitcast_v14f16_to_v7i32(<14 x half> %a, i32 %b) {1471; SI-LABEL: bitcast_v14f16_to_v7i32:1472; SI: ; %bb.0:1473; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1474; SI-NEXT: v_cvt_f16_f32_e32 v24, v11475; SI-NEXT: v_cvt_f16_f32_e32 v23, v01476; SI-NEXT: v_cvt_f16_f32_e32 v22, v31477; SI-NEXT: v_cvt_f16_f32_e32 v21, v21478; SI-NEXT: v_cvt_f16_f32_e32 v20, v51479; SI-NEXT: v_cvt_f16_f32_e32 v19, v41480; SI-NEXT: v_cvt_f16_f32_e32 v18, v71481; SI-NEXT: v_cvt_f16_f32_e32 v17, v61482; SI-NEXT: v_cvt_f16_f32_e32 v16, v91483; SI-NEXT: v_cvt_f16_f32_e32 v15, v81484; SI-NEXT: v_cvt_f16_f32_e32 v11, v111485; SI-NEXT: v_cvt_f16_f32_e32 v9, v101486; SI-NEXT: v_cvt_f16_f32_e32 v8, v131487; SI-NEXT: v_cvt_f16_f32_e32 v7, v121488; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v141489; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr61490; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1491; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1492; SI-NEXT: s_cbranch_execnz .LBB10_31493; SI-NEXT: ; %bb.1: ; %Flow1494; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1495; SI-NEXT: s_cbranch_execnz .LBB10_41496; SI-NEXT: .LBB10_2: ; %end1497; SI-NEXT: s_or_b64 exec, exec, s[4:5]1498; SI-NEXT: s_setpc_b64 s[30:31]1499; SI-NEXT: .LBB10_3: ; %cmp.false1500; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v241501; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v221502; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v201503; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v181504; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v161505; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v111506; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v81507; SI-NEXT: v_or_b32_e32 v0, v23, v01508; SI-NEXT: v_or_b32_e32 v1, v21, v11509; SI-NEXT: v_or_b32_e32 v2, v19, v21510; SI-NEXT: v_or_b32_e32 v3, v17, v31511; SI-NEXT: v_or_b32_e32 v4, v15, v41512; SI-NEXT: v_or_b32_e32 v5, v9, v51513; SI-NEXT: v_or_b32_e32 v6, v7, v61514; SI-NEXT: ; implicit-def: $vgpr241515; SI-NEXT: ; implicit-def: $vgpr231516; SI-NEXT: ; implicit-def: $vgpr221517; SI-NEXT: ; implicit-def: $vgpr211518; SI-NEXT: ; implicit-def: $vgpr201519; SI-NEXT: ; implicit-def: $vgpr191520; SI-NEXT: ; implicit-def: $vgpr181521; SI-NEXT: ; implicit-def: $vgpr171522; SI-NEXT: ; implicit-def: $vgpr161523; SI-NEXT: ; implicit-def: $vgpr151524; SI-NEXT: ; implicit-def: $vgpr111525; SI-NEXT: ; implicit-def: $vgpr91526; SI-NEXT: ; implicit-def: $vgpr81527; SI-NEXT: ; implicit-def: $vgpr71528; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1529; SI-NEXT: s_cbranch_execz .LBB10_21530; SI-NEXT: .LBB10_4: ; %cmp.true1531; SI-NEXT: v_cvt_f32_f16_e32 v0, v241532; SI-NEXT: v_cvt_f32_f16_e32 v1, v231533; SI-NEXT: v_cvt_f32_f16_e32 v2, v221534; SI-NEXT: v_cvt_f32_f16_e32 v3, v211535; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01536; SI-NEXT: v_cvt_f16_f32_e32 v0, v01537; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11538; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21539; SI-NEXT: v_cvt_f16_f32_e32 v1, v11540; SI-NEXT: v_cvt_f16_f32_e32 v2, v21541; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v31542; SI-NEXT: v_cvt_f16_f32_e32 v3, v31543; SI-NEXT: v_cvt_f32_f16_e32 v4, v201544; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01545; SI-NEXT: v_or_b32_e32 v0, v1, v01546; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21547; SI-NEXT: v_or_b32_e32 v1, v3, v11548; SI-NEXT: v_cvt_f32_f16_e32 v2, v191549; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v41550; SI-NEXT: v_cvt_f32_f16_e32 v4, v181551; SI-NEXT: v_cvt_f16_f32_e32 v3, v31552; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21553; SI-NEXT: v_cvt_f16_f32_e32 v2, v21554; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41555; SI-NEXT: v_cvt_f16_f32_e32 v4, v41556; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31557; SI-NEXT: v_cvt_f32_f16_e32 v5, v171558; SI-NEXT: v_or_b32_e32 v2, v2, v31559; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41560; SI-NEXT: v_cvt_f32_f16_e32 v4, v161561; SI-NEXT: v_cvt_f32_f16_e32 v6, v151562; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v51563; SI-NEXT: v_cvt_f16_f32_e32 v5, v51564; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41565; SI-NEXT: v_cvt_f16_f32_e32 v4, v41566; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61567; SI-NEXT: v_cvt_f16_f32_e32 v6, v61568; SI-NEXT: v_or_b32_e32 v3, v5, v31569; SI-NEXT: v_cvt_f32_f16_e32 v5, v111570; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v41571; SI-NEXT: v_or_b32_e32 v4, v6, v41572; SI-NEXT: v_cvt_f32_f16_e32 v6, v91573; SI-NEXT: v_cvt_f32_f16_e32 v8, v81574; SI-NEXT: v_cvt_f32_f16_e32 v7, v71575; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v51576; SI-NEXT: v_cvt_f16_f32_e32 v5, v51577; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61578; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v81579; SI-NEXT: v_cvt_f16_f32_e32 v6, v61580; SI-NEXT: v_cvt_f16_f32_e32 v8, v81581; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v71582; SI-NEXT: v_cvt_f16_f32_e32 v7, v71583; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v51584; SI-NEXT: v_or_b32_e32 v5, v6, v51585; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v81586; SI-NEXT: v_or_b32_e32 v6, v7, v61587; SI-NEXT: s_or_b64 exec, exec, s[4:5]1588; SI-NEXT: s_setpc_b64 s[30:31]1589;1590; VI-LABEL: bitcast_v14f16_to_v7i32:1591; VI: ; %bb.0:1592; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1593; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71594; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1595; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1596; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1597; VI-NEXT: s_cbranch_execz .LBB10_21598; VI-NEXT: ; %bb.1: ; %cmp.true1599; VI-NEXT: v_mov_b32_e32 v7, 0x2001600; VI-NEXT: v_add_f16_sdwa v8, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1601; VI-NEXT: v_add_f16_e32 v6, 0x200, v61602; VI-NEXT: v_or_b32_e32 v6, v6, v81603; VI-NEXT: v_add_f16_sdwa v8, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1604; VI-NEXT: v_add_f16_e32 v5, 0x200, v51605; VI-NEXT: v_or_b32_e32 v5, v5, v81606; VI-NEXT: v_add_f16_sdwa v8, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1607; VI-NEXT: v_add_f16_e32 v4, 0x200, v41608; VI-NEXT: v_or_b32_e32 v4, v4, v81609; VI-NEXT: v_add_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1610; VI-NEXT: v_add_f16_e32 v3, 0x200, v31611; VI-NEXT: v_or_b32_e32 v3, v3, v81612; VI-NEXT: v_add_f16_sdwa v8, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1613; VI-NEXT: v_add_f16_e32 v2, 0x200, v21614; VI-NEXT: v_or_b32_e32 v2, v2, v81615; VI-NEXT: v_add_f16_sdwa v8, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1616; VI-NEXT: v_add_f16_e32 v1, 0x200, v11617; VI-NEXT: v_add_f16_sdwa v7, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1618; VI-NEXT: v_add_f16_e32 v0, 0x200, v01619; VI-NEXT: v_or_b32_e32 v1, v1, v81620; VI-NEXT: v_or_b32_e32 v0, v0, v71621; VI-NEXT: .LBB10_2: ; %end1622; VI-NEXT: s_or_b64 exec, exec, s[4:5]1623; VI-NEXT: s_setpc_b64 s[30:31]1624;1625; GFX9-LABEL: bitcast_v14f16_to_v7i32:1626; GFX9: ; %bb.0:1627; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1628; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71629; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1630; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1631; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1632; GFX9-NEXT: ; %bb.1: ; %cmp.true1633; GFX9-NEXT: s_movk_i32 s6, 0x2001634; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]1635; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]1636; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]1637; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]1638; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]1639; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]1640; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]1641; GFX9-NEXT: ; %bb.2: ; %end1642; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1643; GFX9-NEXT: s_setpc_b64 s[30:31]1644;1645; GFX11-LABEL: bitcast_v14f16_to_v7i32:1646; GFX11: ; %bb.0:1647; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1648; GFX11-NEXT: s_mov_b32 s0, exec_lo1649; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v71650; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01651; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1652; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01653; GFX11-NEXT: s_cbranch_execz .LBB10_21654; GFX11-NEXT: ; %bb.1: ; %cmp.true1655; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]1656; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]1657; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]1658; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]1659; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]1660; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]1661; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]1662; GFX11-NEXT: .LBB10_2: ; %end1663; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01664; GFX11-NEXT: s_setpc_b64 s[30:31]1665 %cmp = icmp eq i32 %b, 01666 br i1 %cmp, label %cmp.true, label %cmp.false1667 1668cmp.true:1669 %a1 = fadd <14 x half> %a, splat (half 0xH0200)1670 %a2 = bitcast <14 x half> %a1 to <7 x i32>1671 br label %end1672 1673cmp.false:1674 %a3 = bitcast <14 x half> %a to <7 x i32>1675 br label %end1676 1677end:1678 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1679 ret <7 x i32> %phi1680}1681 1682define inreg <7 x i32> @bitcast_v14f16_to_v7i32_scalar(<14 x half> inreg %a, i32 inreg %b) {1683; SI-LABEL: bitcast_v14f16_to_v7i32_scalar:1684; SI: ; %bb.0:1685; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1686; SI-NEXT: v_cvt_f16_f32_e32 v20, s171687; SI-NEXT: v_cvt_f16_f32_e32 v19, s161688; SI-NEXT: v_cvt_f16_f32_e32 v18, s191689; SI-NEXT: v_cvt_f16_f32_e32 v17, s181690; SI-NEXT: v_cvt_f16_f32_e32 v16, s211691; SI-NEXT: v_cvt_f16_f32_e32 v15, s201692; SI-NEXT: v_cvt_f16_f32_e32 v14, s231693; SI-NEXT: v_cvt_f16_f32_e32 v13, s221694; SI-NEXT: v_cvt_f16_f32_e32 v12, s251695; SI-NEXT: v_cvt_f16_f32_e32 v11, s241696; SI-NEXT: v_cvt_f16_f32_e32 v10, s271697; SI-NEXT: v_cvt_f16_f32_e32 v9, s261698; SI-NEXT: v_cvt_f16_f32_e32 v8, s291699; SI-NEXT: v_cvt_f16_f32_e32 v7, s281700; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v01701; SI-NEXT: s_and_b64 s[4:5], vcc, exec1702; SI-NEXT: s_cbranch_scc0 .LBB11_41703; SI-NEXT: ; %bb.1: ; %cmp.false1704; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v201705; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v181706; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v161707; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v141708; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v121709; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v101710; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v81711; SI-NEXT: v_or_b32_e32 v0, v19, v01712; SI-NEXT: v_or_b32_e32 v1, v17, v11713; SI-NEXT: v_or_b32_e32 v2, v15, v21714; SI-NEXT: v_or_b32_e32 v3, v13, v31715; SI-NEXT: v_or_b32_e32 v4, v11, v41716; SI-NEXT: v_or_b32_e32 v5, v9, v51717; SI-NEXT: v_or_b32_e32 v6, v7, v61718; SI-NEXT: s_cbranch_execnz .LBB11_31719; SI-NEXT: .LBB11_2: ; %cmp.true1720; SI-NEXT: v_cvt_f32_f16_e32 v0, v201721; SI-NEXT: v_cvt_f32_f16_e32 v1, v191722; SI-NEXT: v_cvt_f32_f16_e32 v2, v181723; SI-NEXT: v_cvt_f32_f16_e32 v3, v171724; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01725; SI-NEXT: v_cvt_f16_f32_e32 v0, v01726; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11727; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21728; SI-NEXT: v_cvt_f16_f32_e32 v1, v11729; SI-NEXT: v_cvt_f16_f32_e32 v2, v21730; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v31731; SI-NEXT: v_cvt_f16_f32_e32 v3, v31732; SI-NEXT: v_cvt_f32_f16_e32 v4, v161733; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01734; SI-NEXT: v_or_b32_e32 v0, v1, v01735; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v21736; SI-NEXT: v_or_b32_e32 v1, v3, v11737; SI-NEXT: v_cvt_f32_f16_e32 v2, v151738; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v41739; SI-NEXT: v_cvt_f32_f16_e32 v4, v141740; SI-NEXT: v_cvt_f16_f32_e32 v3, v31741; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21742; SI-NEXT: v_cvt_f16_f32_e32 v2, v21743; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41744; SI-NEXT: v_cvt_f16_f32_e32 v4, v41745; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v31746; SI-NEXT: v_cvt_f32_f16_e32 v5, v131747; SI-NEXT: v_or_b32_e32 v2, v2, v31748; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41749; SI-NEXT: v_cvt_f32_f16_e32 v4, v121750; SI-NEXT: v_cvt_f32_f16_e32 v6, v111751; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v51752; SI-NEXT: v_cvt_f16_f32_e32 v5, v51753; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41754; SI-NEXT: v_cvt_f16_f32_e32 v4, v41755; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61756; SI-NEXT: v_cvt_f16_f32_e32 v6, v61757; SI-NEXT: v_or_b32_e32 v3, v5, v31758; SI-NEXT: v_cvt_f32_f16_e32 v5, v101759; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v41760; SI-NEXT: v_or_b32_e32 v4, v6, v41761; SI-NEXT: v_cvt_f32_f16_e32 v6, v91762; SI-NEXT: v_cvt_f32_f16_e32 v8, v81763; SI-NEXT: v_cvt_f32_f16_e32 v7, v71764; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v51765; SI-NEXT: v_cvt_f16_f32_e32 v5, v51766; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61767; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v81768; SI-NEXT: v_cvt_f16_f32_e32 v6, v61769; SI-NEXT: v_cvt_f16_f32_e32 v8, v81770; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v71771; SI-NEXT: v_cvt_f16_f32_e32 v7, v71772; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v51773; SI-NEXT: v_or_b32_e32 v5, v6, v51774; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v81775; SI-NEXT: v_or_b32_e32 v6, v7, v61776; SI-NEXT: .LBB11_3: ; %end1777; SI-NEXT: s_setpc_b64 s[30:31]1778; SI-NEXT: .LBB11_4:1779; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr61780; SI-NEXT: s_branch .LBB11_21781;1782; VI-LABEL: bitcast_v14f16_to_v7i32_scalar:1783; VI: ; %bb.0:1784; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1785; VI-NEXT: s_cmp_lg_u32 s23, 01786; VI-NEXT: s_cbranch_scc0 .LBB11_31787; VI-NEXT: ; %bb.1: ; %cmp.false1788; VI-NEXT: s_cbranch_execnz .LBB11_41789; VI-NEXT: .LBB11_2: ; %cmp.true1790; VI-NEXT: s_lshr_b32 s4, s22, 161791; VI-NEXT: v_mov_b32_e32 v0, 0x2001792; VI-NEXT: v_mov_b32_e32 v1, s41793; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1794; VI-NEXT: v_add_f16_e32 v2, s22, v01795; VI-NEXT: s_lshr_b32 s4, s21, 161796; VI-NEXT: v_or_b32_e32 v6, v2, v11797; VI-NEXT: v_mov_b32_e32 v1, s41798; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1799; VI-NEXT: v_add_f16_e32 v2, s21, v01800; VI-NEXT: s_lshr_b32 s4, s20, 161801; VI-NEXT: v_or_b32_e32 v5, v2, v11802; VI-NEXT: v_mov_b32_e32 v1, s41803; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1804; VI-NEXT: v_add_f16_e32 v2, s20, v01805; VI-NEXT: s_lshr_b32 s4, s19, 161806; VI-NEXT: v_or_b32_e32 v4, v2, v11807; VI-NEXT: v_mov_b32_e32 v1, s41808; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1809; VI-NEXT: v_add_f16_e32 v2, s19, v01810; VI-NEXT: s_lshr_b32 s4, s18, 161811; VI-NEXT: v_or_b32_e32 v3, v2, v11812; VI-NEXT: v_mov_b32_e32 v1, s41813; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1814; VI-NEXT: v_add_f16_e32 v2, s18, v01815; VI-NEXT: s_lshr_b32 s4, s17, 161816; VI-NEXT: v_or_b32_e32 v2, v2, v11817; VI-NEXT: v_mov_b32_e32 v1, s41818; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1819; VI-NEXT: v_add_f16_e32 v7, s17, v01820; VI-NEXT: s_lshr_b32 s4, s16, 161821; VI-NEXT: v_or_b32_e32 v1, v7, v11822; VI-NEXT: v_mov_b32_e32 v7, s41823; VI-NEXT: v_add_f16_sdwa v7, v7, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD1824; VI-NEXT: v_add_f16_e32 v0, s16, v01825; VI-NEXT: v_or_b32_e32 v0, v0, v71826; VI-NEXT: s_setpc_b64 s[30:31]1827; VI-NEXT: .LBB11_3:1828; VI-NEXT: s_branch .LBB11_21829; VI-NEXT: .LBB11_4:1830; VI-NEXT: v_mov_b32_e32 v0, s161831; VI-NEXT: v_mov_b32_e32 v1, s171832; VI-NEXT: v_mov_b32_e32 v2, s181833; VI-NEXT: v_mov_b32_e32 v3, s191834; VI-NEXT: v_mov_b32_e32 v4, s201835; VI-NEXT: v_mov_b32_e32 v5, s211836; VI-NEXT: v_mov_b32_e32 v6, s221837; VI-NEXT: s_setpc_b64 s[30:31]1838;1839; GFX9-LABEL: bitcast_v14f16_to_v7i32_scalar:1840; GFX9: ; %bb.0:1841; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1842; GFX9-NEXT: s_cmp_lg_u32 s23, 01843; GFX9-NEXT: s_cbranch_scc0 .LBB11_31844; GFX9-NEXT: ; %bb.1: ; %cmp.false1845; GFX9-NEXT: s_cbranch_execnz .LBB11_41846; GFX9-NEXT: .LBB11_2: ; %cmp.true1847; GFX9-NEXT: v_mov_b32_e32 v0, 0x2001848; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]1849; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]1850; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]1851; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]1852; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]1853; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]1854; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]1855; GFX9-NEXT: s_setpc_b64 s[30:31]1856; GFX9-NEXT: .LBB11_3:1857; GFX9-NEXT: s_branch .LBB11_21858; GFX9-NEXT: .LBB11_4:1859; GFX9-NEXT: v_mov_b32_e32 v0, s161860; GFX9-NEXT: v_mov_b32_e32 v1, s171861; GFX9-NEXT: v_mov_b32_e32 v2, s181862; GFX9-NEXT: v_mov_b32_e32 v3, s191863; GFX9-NEXT: v_mov_b32_e32 v4, s201864; GFX9-NEXT: v_mov_b32_e32 v5, s211865; GFX9-NEXT: v_mov_b32_e32 v6, s221866; GFX9-NEXT: s_setpc_b64 s[30:31]1867;1868; GFX11-LABEL: bitcast_v14f16_to_v7i32_scalar:1869; GFX11: ; %bb.0:1870; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1871; GFX11-NEXT: s_mov_b32 s6, s181872; GFX11-NEXT: s_mov_b32 s5, s171873; GFX11-NEXT: s_mov_b32 s4, s161874; GFX11-NEXT: s_cmp_lg_u32 s19, 01875; GFX11-NEXT: s_mov_b32 s7, 01876; GFX11-NEXT: s_cbranch_scc0 .LBB11_31877; GFX11-NEXT: ; %bb.1: ; %Flow1878; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s71879; GFX11-NEXT: s_cbranch_vccnz .LBB11_41880; GFX11-NEXT: .LBB11_2: ; %cmp.true1881; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]1882; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]1883; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]1884; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]1885; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]1886; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]1887; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]1888; GFX11-NEXT: s_setpc_b64 s[30:31]1889; GFX11-NEXT: .LBB11_3:1890; GFX11-NEXT: s_branch .LBB11_21891; GFX11-NEXT: .LBB11_4:1892; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11893; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31894; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s51895; GFX11-NEXT: v_mov_b32_e32 v6, s61896; GFX11-NEXT: s_setpc_b64 s[30:31]1897 %cmp = icmp eq i32 %b, 01898 br i1 %cmp, label %cmp.true, label %cmp.false1899 1900cmp.true:1901 %a1 = fadd <14 x half> %a, splat (half 0xH0200)1902 %a2 = bitcast <14 x half> %a1 to <7 x i32>1903 br label %end1904 1905cmp.false:1906 %a3 = bitcast <14 x half> %a to <7 x i32>1907 br label %end1908 1909end:1910 %phi = phi <7 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1911 ret <7 x i32> %phi1912}1913 1914define <14 x i16> @bitcast_v7f32_to_v14i16(<7 x float> %a, i32 %b) {1915; SI-LABEL: bitcast_v7f32_to_v14i16:1916; SI: ; %bb.0:1917; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1918; SI-NEXT: v_mov_b32_e32 v12, v61919; SI-NEXT: v_mov_b32_e32 v10, v51920; SI-NEXT: v_mov_b32_e32 v8, v41921; SI-NEXT: v_mov_b32_e32 v6, v31922; SI-NEXT: v_mov_b32_e32 v4, v21923; SI-NEXT: v_mov_b32_e32 v2, v11924; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71925; SI-NEXT: ; implicit-def: $vgpr11926; SI-NEXT: ; implicit-def: $vgpr31927; SI-NEXT: ; implicit-def: $vgpr51928; SI-NEXT: ; implicit-def: $vgpr71929; SI-NEXT: ; implicit-def: $vgpr91930; SI-NEXT: ; implicit-def: $vgpr111931; SI-NEXT: ; implicit-def: $vgpr131932; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1933; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1934; SI-NEXT: s_cbranch_execnz .LBB12_31935; SI-NEXT: ; %bb.1: ; %Flow1936; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1937; SI-NEXT: s_cbranch_execnz .LBB12_41938; SI-NEXT: .LBB12_2: ; %end1939; SI-NEXT: s_or_b64 exec, exec, s[4:5]1940; SI-NEXT: s_setpc_b64 s[30:31]1941; SI-NEXT: .LBB12_3: ; %cmp.false1942; SI-NEXT: v_alignbit_b32 v13, v0, v12, 161943; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161944; SI-NEXT: v_alignbit_b32 v5, v6, v4, 161945; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161946; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101947; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v61948; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21949; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1950; SI-NEXT: s_cbranch_execz .LBB12_21951; SI-NEXT: .LBB12_4: ; %cmp.true1952; SI-NEXT: v_add_f32_e32 v12, 1.0, v121953; SI-NEXT: v_add_f32_e32 v2, 1.0, v21954; SI-NEXT: v_add_f32_e32 v0, 1.0, v01955; SI-NEXT: v_add_f32_e32 v6, 1.0, v61956; SI-NEXT: v_add_f32_e32 v4, 1.0, v41957; SI-NEXT: v_add_f32_e32 v10, 1.0, v101958; SI-NEXT: v_add_f32_e32 v8, 1.0, v81959; SI-NEXT: v_alignbit_b32 v9, v10, v8, 161960; SI-NEXT: v_alignbit_b32 v5, v6, v4, 161961; SI-NEXT: v_alignbit_b32 v1, v2, v0, 161962; SI-NEXT: v_alignbit_b32 v13, v0, v12, 161963; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v101964; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v61965; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v21966; SI-NEXT: s_or_b64 exec, exec, s[4:5]1967; SI-NEXT: s_setpc_b64 s[30:31]1968;1969; VI-LABEL: bitcast_v7f32_to_v14i16:1970; VI: ; %bb.0:1971; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1972; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71973; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1974; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1975; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1976; VI-NEXT: ; %bb.1: ; %cmp.true1977; VI-NEXT: v_add_f32_e32 v6, 1.0, v61978; VI-NEXT: v_add_f32_e32 v5, 1.0, v51979; VI-NEXT: v_add_f32_e32 v4, 1.0, v41980; VI-NEXT: v_add_f32_e32 v3, 1.0, v31981; VI-NEXT: v_add_f32_e32 v2, 1.0, v21982; VI-NEXT: v_add_f32_e32 v1, 1.0, v11983; VI-NEXT: v_add_f32_e32 v0, 1.0, v01984; VI-NEXT: ; %bb.2: ; %end1985; VI-NEXT: s_or_b64 exec, exec, s[4:5]1986; VI-NEXT: s_setpc_b64 s[30:31]1987;1988; GFX9-LABEL: bitcast_v7f32_to_v14i16:1989; GFX9: ; %bb.0:1990; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1991; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v71992; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1993; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1994; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1995; GFX9-NEXT: ; %bb.1: ; %cmp.true1996; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v61997; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v51998; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v41999; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v32000; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v22001; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v12002; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v02003; GFX9-NEXT: ; %bb.2: ; %end2004; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2005; GFX9-NEXT: s_setpc_b64 s[30:31]2006;2007; GFX11-LABEL: bitcast_v7f32_to_v14i16:2008; GFX11: ; %bb.0:2009; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2010; GFX11-NEXT: s_mov_b32 s0, exec_lo2011; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v72012; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02013; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2014; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02015; GFX11-NEXT: ; %bb.1: ; %cmp.true2016; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v52017; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v32018; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v12019; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v02020; GFX11-NEXT: ; %bb.2: ; %end2021; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02022; GFX11-NEXT: s_setpc_b64 s[30:31]2023 %cmp = icmp eq i32 %b, 02024 br i1 %cmp, label %cmp.true, label %cmp.false2025 2026cmp.true:2027 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)2028 %a2 = bitcast <7 x float> %a1 to <14 x i16>2029 br label %end2030 2031cmp.false:2032 %a3 = bitcast <7 x float> %a to <14 x i16>2033 br label %end2034 2035end:2036 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2037 ret <14 x i16> %phi2038}2039 2040define inreg <14 x i16> @bitcast_v7f32_to_v14i16_scalar(<7 x float> inreg %a, i32 inreg %b) {2041; SI-LABEL: bitcast_v7f32_to_v14i16_scalar:2042; SI: ; %bb.0:2043; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2044; SI-NEXT: s_cmp_lg_u32 s23, 02045; SI-NEXT: s_cbranch_scc0 .LBB13_32046; SI-NEXT: ; %bb.1: ; %cmp.false2047; SI-NEXT: s_lshr_b32 s23, s21, 162048; SI-NEXT: s_lshr_b32 s15, s19, 162049; SI-NEXT: s_lshr_b32 s14, s17, 162050; SI-NEXT: s_lshr_b64 s[6:7], s[22:23], 162051; SI-NEXT: s_lshr_b64 s[4:5], s[20:21], 162052; SI-NEXT: s_lshr_b64 s[8:9], s[18:19], 162053; SI-NEXT: s_lshr_b64 s[10:11], s[16:17], 162054; SI-NEXT: s_cbranch_execnz .LBB13_42055; SI-NEXT: .LBB13_2: ; %cmp.true2056; SI-NEXT: v_add_f32_e64 v12, s22, 1.02057; SI-NEXT: v_add_f32_e64 v20, s17, 1.02058; SI-NEXT: v_add_f32_e64 v19, s16, 1.02059; SI-NEXT: v_add_f32_e64 v18, s19, 1.02060; SI-NEXT: v_add_f32_e64 v17, s18, 1.02061; SI-NEXT: v_add_f32_e64 v16, s21, 1.02062; SI-NEXT: v_add_f32_e64 v15, s20, 1.02063; SI-NEXT: v_lshr_b64 v[9:10], v[15:16], 162064; SI-NEXT: v_lshr_b64 v[5:6], v[17:18], 162065; SI-NEXT: v_lshr_b64 v[1:2], v[19:20], 162066; SI-NEXT: v_lshr_b64 v[13:14], v[12:13], 162067; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v162068; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v182069; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v202070; SI-NEXT: s_branch .LBB13_52071; SI-NEXT: .LBB13_3:2072; SI-NEXT: ; implicit-def: $sgpr102073; SI-NEXT: ; implicit-def: $sgpr142074; SI-NEXT: ; implicit-def: $sgpr82075; SI-NEXT: ; implicit-def: $sgpr152076; SI-NEXT: ; implicit-def: $sgpr42077; SI-NEXT: ; implicit-def: $sgpr232078; SI-NEXT: ; implicit-def: $sgpr62079; SI-NEXT: s_branch .LBB13_22080; SI-NEXT: .LBB13_4:2081; SI-NEXT: v_mov_b32_e32 v19, s162082; SI-NEXT: v_mov_b32_e32 v20, s172083; SI-NEXT: v_mov_b32_e32 v17, s182084; SI-NEXT: v_mov_b32_e32 v18, s192085; SI-NEXT: v_mov_b32_e32 v15, s202086; SI-NEXT: v_mov_b32_e32 v16, s212087; SI-NEXT: v_mov_b32_e32 v12, s222088; SI-NEXT: v_mov_b32_e32 v3, s142089; SI-NEXT: v_mov_b32_e32 v7, s152090; SI-NEXT: v_mov_b32_e32 v11, s232091; SI-NEXT: v_mov_b32_e32 v13, s62092; SI-NEXT: v_mov_b32_e32 v1, s102093; SI-NEXT: v_mov_b32_e32 v5, s82094; SI-NEXT: v_mov_b32_e32 v9, s42095; SI-NEXT: .LBB13_5: ; %end2096; SI-NEXT: v_mov_b32_e32 v0, v192097; SI-NEXT: v_mov_b32_e32 v2, v202098; SI-NEXT: v_mov_b32_e32 v4, v172099; SI-NEXT: v_mov_b32_e32 v6, v182100; SI-NEXT: v_mov_b32_e32 v8, v152101; SI-NEXT: v_mov_b32_e32 v10, v162102; SI-NEXT: s_setpc_b64 s[30:31]2103;2104; VI-LABEL: bitcast_v7f32_to_v14i16_scalar:2105; VI: ; %bb.0:2106; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2107; VI-NEXT: s_cmp_lg_u32 s23, 02108; VI-NEXT: s_cbranch_scc0 .LBB13_32109; VI-NEXT: ; %bb.1: ; %cmp.false2110; VI-NEXT: s_cbranch_execnz .LBB13_42111; VI-NEXT: .LBB13_2: ; %cmp.true2112; VI-NEXT: v_add_f32_e64 v6, s22, 1.02113; VI-NEXT: v_add_f32_e64 v5, s21, 1.02114; VI-NEXT: v_add_f32_e64 v4, s20, 1.02115; VI-NEXT: v_add_f32_e64 v3, s19, 1.02116; VI-NEXT: v_add_f32_e64 v2, s18, 1.02117; VI-NEXT: v_add_f32_e64 v1, s17, 1.02118; VI-NEXT: v_add_f32_e64 v0, s16, 1.02119; VI-NEXT: s_setpc_b64 s[30:31]2120; VI-NEXT: .LBB13_3:2121; VI-NEXT: s_branch .LBB13_22122; VI-NEXT: .LBB13_4:2123; VI-NEXT: v_mov_b32_e32 v0, s162124; VI-NEXT: v_mov_b32_e32 v1, s172125; VI-NEXT: v_mov_b32_e32 v2, s182126; VI-NEXT: v_mov_b32_e32 v3, s192127; VI-NEXT: v_mov_b32_e32 v4, s202128; VI-NEXT: v_mov_b32_e32 v5, s212129; VI-NEXT: v_mov_b32_e32 v6, s222130; VI-NEXT: v_mov_b32_e32 v7, s232131; VI-NEXT: s_setpc_b64 s[30:31]2132;2133; GFX9-LABEL: bitcast_v7f32_to_v14i16_scalar:2134; GFX9: ; %bb.0:2135; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2136; GFX9-NEXT: s_cmp_lg_u32 s23, 02137; GFX9-NEXT: s_cbranch_scc0 .LBB13_32138; GFX9-NEXT: ; %bb.1: ; %cmp.false2139; GFX9-NEXT: s_cbranch_execnz .LBB13_42140; GFX9-NEXT: .LBB13_2: ; %cmp.true2141; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.02142; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.02143; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.02144; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.02145; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.02146; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.02147; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.02148; GFX9-NEXT: s_setpc_b64 s[30:31]2149; GFX9-NEXT: .LBB13_3:2150; GFX9-NEXT: s_branch .LBB13_22151; GFX9-NEXT: .LBB13_4:2152; GFX9-NEXT: v_mov_b32_e32 v0, s162153; GFX9-NEXT: v_mov_b32_e32 v1, s172154; GFX9-NEXT: v_mov_b32_e32 v2, s182155; GFX9-NEXT: v_mov_b32_e32 v3, s192156; GFX9-NEXT: v_mov_b32_e32 v4, s202157; GFX9-NEXT: v_mov_b32_e32 v5, s212158; GFX9-NEXT: v_mov_b32_e32 v6, s222159; GFX9-NEXT: v_mov_b32_e32 v7, s232160; GFX9-NEXT: s_setpc_b64 s[30:31]2161;2162; GFX11-LABEL: bitcast_v7f32_to_v14i16_scalar:2163; GFX11: ; %bb.0:2164; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2165; GFX11-NEXT: s_mov_b32 s6, s182166; GFX11-NEXT: s_mov_b32 s5, s172167; GFX11-NEXT: s_mov_b32 s4, s162168; GFX11-NEXT: s_cmp_lg_u32 s19, 02169; GFX11-NEXT: s_mov_b32 s8, 02170; GFX11-NEXT: s_cbranch_scc0 .LBB13_32171; GFX11-NEXT: ; %bb.1: ; %Flow2172; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s82173; GFX11-NEXT: s_cbranch_vccnz .LBB13_42174; GFX11-NEXT: .LBB13_2: ; %cmp.true2175; GFX11-NEXT: v_add_f32_e64 v6, s6, 1.02176; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.02177; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.02178; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.02179; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.02180; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.02181; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.02182; GFX11-NEXT: s_setpc_b64 s[30:31]2183; GFX11-NEXT: .LBB13_3:2184; GFX11-NEXT: s_branch .LBB13_22185; GFX11-NEXT: .LBB13_4:2186; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12187; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32188; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52189; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s72190; GFX11-NEXT: s_setpc_b64 s[30:31]2191 %cmp = icmp eq i32 %b, 02192 br i1 %cmp, label %cmp.true, label %cmp.false2193 2194cmp.true:2195 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)2196 %a2 = bitcast <7 x float> %a1 to <14 x i16>2197 br label %end2198 2199cmp.false:2200 %a3 = bitcast <7 x float> %a to <14 x i16>2201 br label %end2202 2203end:2204 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2205 ret <14 x i16> %phi2206}2207 2208define <7 x float> @bitcast_v14i16_to_v7f32(<14 x i16> %a, i32 %b) {2209; SI-LABEL: bitcast_v14i16_to_v7f32:2210; SI: ; %bb.0:2211; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2212; SI-NEXT: v_mov_b32_e32 v18, v62213; SI-NEXT: v_mov_b32_e32 v17, v42214; SI-NEXT: v_mov_b32_e32 v16, v22215; SI-NEXT: v_mov_b32_e32 v15, v02216; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142217; SI-NEXT: v_lshlrev_b32_e32 v22, 16, v12218; SI-NEXT: v_lshlrev_b32_e32 v21, 16, v32219; SI-NEXT: v_lshlrev_b32_e32 v20, 16, v52220; SI-NEXT: v_lshlrev_b32_e32 v19, 16, v72221; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v92222; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v112223; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v132224; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr62225; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2226; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2227; SI-NEXT: s_cbranch_execnz .LBB14_32228; SI-NEXT: ; %bb.1: ; %Flow2229; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2230; SI-NEXT: s_cbranch_execnz .LBB14_42231; SI-NEXT: .LBB14_2: ; %end2232; SI-NEXT: s_or_b64 exec, exec, s[4:5]2233; SI-NEXT: s_setpc_b64 s[30:31]2234; SI-NEXT: .LBB14_3: ; %cmp.false2235; SI-NEXT: v_and_b32_e32 v0, 0xffff, v152236; SI-NEXT: v_and_b32_e32 v1, 0xffff, v162237; SI-NEXT: v_and_b32_e32 v2, 0xffff, v172238; SI-NEXT: v_and_b32_e32 v3, 0xffff, v182239; SI-NEXT: v_and_b32_e32 v4, 0xffff, v82240; SI-NEXT: v_and_b32_e32 v5, 0xffff, v102241; SI-NEXT: v_and_b32_e32 v6, 0xffff, v122242; SI-NEXT: v_or_b32_e32 v0, v0, v222243; SI-NEXT: v_or_b32_e32 v1, v1, v212244; SI-NEXT: v_or_b32_e32 v2, v2, v202245; SI-NEXT: v_or_b32_e32 v3, v3, v192246; SI-NEXT: v_or_b32_e32 v4, v4, v142247; SI-NEXT: v_or_b32_e32 v5, v5, v92248; SI-NEXT: v_or_b32_e32 v6, v6, v72249; SI-NEXT: ; implicit-def: $vgpr152250; SI-NEXT: ; implicit-def: $vgpr162251; SI-NEXT: ; implicit-def: $vgpr172252; SI-NEXT: ; implicit-def: $vgpr182253; SI-NEXT: ; implicit-def: $vgpr82254; SI-NEXT: ; implicit-def: $vgpr102255; SI-NEXT: ; implicit-def: $vgpr122256; SI-NEXT: ; implicit-def: $vgpr222257; SI-NEXT: ; implicit-def: $vgpr212258; SI-NEXT: ; implicit-def: $vgpr202259; SI-NEXT: ; implicit-def: $vgpr192260; SI-NEXT: ; implicit-def: $vgpr142261; SI-NEXT: ; implicit-def: $vgpr92262; SI-NEXT: ; implicit-def: $vgpr72263; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2264; SI-NEXT: s_cbranch_execz .LBB14_22265; SI-NEXT: .LBB14_4: ; %cmp.true2266; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v152267; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v162268; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v172269; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v182270; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v82271; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v102272; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v122273; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02274; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12275; SI-NEXT: v_and_b32_e32 v2, 0xffff, v22276; SI-NEXT: v_and_b32_e32 v3, 0xffff, v32277; SI-NEXT: v_and_b32_e32 v4, 0xffff, v42278; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52279; SI-NEXT: v_and_b32_e32 v6, 0xffff, v62280; SI-NEXT: v_or_b32_e32 v0, v22, v02281; SI-NEXT: s_mov_b32 s6, 0x300002282; SI-NEXT: v_or_b32_e32 v1, v21, v12283; SI-NEXT: v_or_b32_e32 v2, v20, v22284; SI-NEXT: v_or_b32_e32 v3, v19, v32285; SI-NEXT: v_or_b32_e32 v4, v14, v42286; SI-NEXT: v_or_b32_e32 v5, v9, v52287; SI-NEXT: v_or_b32_e32 v6, v7, v62288; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v02289; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v12290; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v22291; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v32292; SI-NEXT: v_add_i32_e32 v4, vcc, 0x30000, v42293; SI-NEXT: v_add_i32_e32 v5, vcc, 0x30000, v52294; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v62295; SI-NEXT: s_or_b64 exec, exec, s[4:5]2296; SI-NEXT: s_setpc_b64 s[30:31]2297;2298; VI-LABEL: bitcast_v14i16_to_v7f32:2299; VI: ; %bb.0:2300; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2301; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v72302; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2303; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2304; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2305; VI-NEXT: s_cbranch_execz .LBB14_22306; VI-NEXT: ; %bb.1: ; %cmp.true2307; VI-NEXT: v_mov_b32_e32 v8, 32308; VI-NEXT: v_add_u16_e32 v7, 3, v62309; VI-NEXT: v_add_u16_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2310; VI-NEXT: v_or_b32_e32 v6, v7, v62311; VI-NEXT: v_add_u16_e32 v7, 3, v52312; VI-NEXT: v_add_u16_sdwa v5, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2313; VI-NEXT: v_or_b32_e32 v5, v7, v52314; VI-NEXT: v_add_u16_e32 v7, 3, v42315; VI-NEXT: v_add_u16_sdwa v4, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2316; VI-NEXT: v_or_b32_e32 v4, v7, v42317; VI-NEXT: v_add_u16_e32 v7, 3, v32318; VI-NEXT: v_add_u16_sdwa v3, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2319; VI-NEXT: v_or_b32_e32 v3, v7, v32320; VI-NEXT: v_add_u16_e32 v7, 3, v22321; VI-NEXT: v_add_u16_sdwa v2, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2322; VI-NEXT: v_or_b32_e32 v2, v7, v22323; VI-NEXT: v_add_u16_e32 v7, 3, v12324; VI-NEXT: v_add_u16_sdwa v1, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2325; VI-NEXT: v_or_b32_e32 v1, v7, v12326; VI-NEXT: v_add_u16_e32 v7, 3, v02327; VI-NEXT: v_add_u16_sdwa v0, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2328; VI-NEXT: v_or_b32_e32 v0, v7, v02329; VI-NEXT: .LBB14_2: ; %end2330; VI-NEXT: s_or_b64 exec, exec, s[4:5]2331; VI-NEXT: s_setpc_b64 s[30:31]2332;2333; GFX9-LABEL: bitcast_v14i16_to_v7f32:2334; GFX9: ; %bb.0:2335; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2336; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v72337; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2338; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2339; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2340; GFX9-NEXT: ; %bb.1: ; %cmp.true2341; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2342; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2343; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2344; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2345; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2346; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2347; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2348; GFX9-NEXT: ; %bb.2: ; %end2349; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2350; GFX9-NEXT: s_setpc_b64 s[30:31]2351;2352; GFX11-LABEL: bitcast_v14i16_to_v7f32:2353; GFX11: ; %bb.0:2354; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2355; GFX11-NEXT: s_mov_b32 s0, exec_lo2356; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v72357; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02358; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2359; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02360; GFX11-NEXT: s_cbranch_execz .LBB14_22361; GFX11-NEXT: ; %bb.1: ; %cmp.true2362; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2363; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2364; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2365; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2366; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2367; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2368; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2369; GFX11-NEXT: .LBB14_2: ; %end2370; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02371; GFX11-NEXT: s_setpc_b64 s[30:31]2372 %cmp = icmp eq i32 %b, 02373 br i1 %cmp, label %cmp.true, label %cmp.false2374 2375cmp.true:2376 %a1 = add <14 x i16> %a, splat (i16 3)2377 %a2 = bitcast <14 x i16> %a1 to <7 x float>2378 br label %end2379 2380cmp.false:2381 %a3 = bitcast <14 x i16> %a to <7 x float>2382 br label %end2383 2384end:2385 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2386 ret <7 x float> %phi2387}2388 2389define inreg <7 x float> @bitcast_v14i16_to_v7f32_scalar(<14 x i16> inreg %a, i32 inreg %b) {2390; SI-LABEL: bitcast_v14i16_to_v7f32_scalar:2391; SI: ; %bb.0:2392; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2393; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v02394; SI-NEXT: s_and_b64 s[4:5], vcc, exec2395; SI-NEXT: s_cbranch_scc0 .LBB15_42396; SI-NEXT: ; %bb.1: ; %cmp.false2397; SI-NEXT: s_and_b32 s4, s16, 0xffff2398; SI-NEXT: s_lshl_b32 s5, s17, 162399; SI-NEXT: s_or_b32 s4, s4, s52400; SI-NEXT: s_and_b32 s5, s18, 0xffff2401; SI-NEXT: s_lshl_b32 s6, s19, 162402; SI-NEXT: s_or_b32 s5, s5, s62403; SI-NEXT: s_and_b32 s6, s20, 0xffff2404; SI-NEXT: s_lshl_b32 s7, s21, 162405; SI-NEXT: s_or_b32 s6, s6, s72406; SI-NEXT: s_and_b32 s7, s22, 0xffff2407; SI-NEXT: s_lshl_b32 s8, s23, 162408; SI-NEXT: s_or_b32 s7, s7, s82409; SI-NEXT: s_and_b32 s8, s24, 0xffff2410; SI-NEXT: s_lshl_b32 s9, s25, 162411; SI-NEXT: s_or_b32 s8, s8, s92412; SI-NEXT: s_and_b32 s9, s26, 0xffff2413; SI-NEXT: s_lshl_b32 s10, s27, 162414; SI-NEXT: s_or_b32 s9, s9, s102415; SI-NEXT: s_and_b32 s10, s28, 0xffff2416; SI-NEXT: s_lshl_b32 s11, s29, 162417; SI-NEXT: s_or_b32 s10, s10, s112418; SI-NEXT: s_cbranch_execnz .LBB15_32419; SI-NEXT: .LBB15_2: ; %cmp.true2420; SI-NEXT: s_add_i32 s16, s16, 32421; SI-NEXT: s_and_b32 s4, s16, 0xffff2422; SI-NEXT: s_lshl_b32 s5, s17, 162423; SI-NEXT: s_add_i32 s18, s18, 32424; SI-NEXT: s_or_b32 s4, s5, s42425; SI-NEXT: s_and_b32 s5, s18, 0xffff2426; SI-NEXT: s_lshl_b32 s6, s19, 162427; SI-NEXT: s_add_i32 s20, s20, 32428; SI-NEXT: s_or_b32 s5, s6, s52429; SI-NEXT: s_and_b32 s6, s20, 0xffff2430; SI-NEXT: s_lshl_b32 s7, s21, 162431; SI-NEXT: s_add_i32 s22, s22, 32432; SI-NEXT: s_or_b32 s6, s7, s62433; SI-NEXT: s_and_b32 s7, s22, 0xffff2434; SI-NEXT: s_lshl_b32 s8, s23, 162435; SI-NEXT: s_add_i32 s24, s24, 32436; SI-NEXT: s_or_b32 s7, s8, s72437; SI-NEXT: s_and_b32 s8, s24, 0xffff2438; SI-NEXT: s_lshl_b32 s9, s25, 162439; SI-NEXT: s_add_i32 s26, s26, 32440; SI-NEXT: s_or_b32 s8, s9, s82441; SI-NEXT: s_and_b32 s9, s26, 0xffff2442; SI-NEXT: s_lshl_b32 s10, s27, 162443; SI-NEXT: s_add_i32 s28, s28, 32444; SI-NEXT: s_or_b32 s9, s10, s92445; SI-NEXT: s_and_b32 s10, s28, 0xffff2446; SI-NEXT: s_lshl_b32 s11, s29, 162447; SI-NEXT: s_or_b32 s10, s11, s102448; SI-NEXT: s_add_i32 s4, s4, 0x300002449; SI-NEXT: s_add_i32 s5, s5, 0x300002450; SI-NEXT: s_add_i32 s6, s6, 0x300002451; SI-NEXT: s_add_i32 s7, s7, 0x300002452; SI-NEXT: s_add_i32 s8, s8, 0x300002453; SI-NEXT: s_add_i32 s9, s9, 0x300002454; SI-NEXT: s_add_i32 s10, s10, 0x300002455; SI-NEXT: .LBB15_3: ; %end2456; SI-NEXT: v_mov_b32_e32 v0, s42457; SI-NEXT: v_mov_b32_e32 v1, s52458; SI-NEXT: v_mov_b32_e32 v2, s62459; SI-NEXT: v_mov_b32_e32 v3, s72460; SI-NEXT: v_mov_b32_e32 v4, s82461; SI-NEXT: v_mov_b32_e32 v5, s92462; SI-NEXT: v_mov_b32_e32 v6, s102463; SI-NEXT: s_setpc_b64 s[30:31]2464; SI-NEXT: .LBB15_4:2465; SI-NEXT: ; implicit-def: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr102466; SI-NEXT: s_branch .LBB15_22467;2468; VI-LABEL: bitcast_v14i16_to_v7f32_scalar:2469; VI: ; %bb.0:2470; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2471; VI-NEXT: s_cmp_lg_u32 s23, 02472; VI-NEXT: s_cbranch_scc0 .LBB15_42473; VI-NEXT: ; %bb.1: ; %cmp.false2474; VI-NEXT: s_cbranch_execnz .LBB15_32475; VI-NEXT: .LBB15_2: ; %cmp.true2476; VI-NEXT: s_add_i32 s5, s22, 32477; VI-NEXT: s_and_b32 s4, s22, 0xffff00002478; VI-NEXT: s_and_b32 s5, s5, 0xffff2479; VI-NEXT: s_or_b32 s4, s4, s52480; VI-NEXT: s_add_i32 s5, s21, 32481; VI-NEXT: s_add_i32 s22, s4, 0x300002482; VI-NEXT: s_and_b32 s4, s21, 0xffff00002483; VI-NEXT: s_and_b32 s5, s5, 0xffff2484; VI-NEXT: s_or_b32 s4, s4, s52485; VI-NEXT: s_add_i32 s5, s20, 32486; VI-NEXT: s_add_i32 s21, s4, 0x300002487; VI-NEXT: s_and_b32 s4, s20, 0xffff00002488; VI-NEXT: s_and_b32 s5, s5, 0xffff2489; VI-NEXT: s_or_b32 s4, s4, s52490; VI-NEXT: s_add_i32 s5, s19, 32491; VI-NEXT: s_add_i32 s20, s4, 0x300002492; VI-NEXT: s_and_b32 s4, s19, 0xffff00002493; VI-NEXT: s_and_b32 s5, s5, 0xffff2494; VI-NEXT: s_or_b32 s4, s4, s52495; VI-NEXT: s_add_i32 s5, s18, 32496; VI-NEXT: s_add_i32 s19, s4, 0x300002497; VI-NEXT: s_and_b32 s4, s18, 0xffff00002498; VI-NEXT: s_and_b32 s5, s5, 0xffff2499; VI-NEXT: s_or_b32 s4, s4, s52500; VI-NEXT: s_add_i32 s5, s17, 32501; VI-NEXT: s_add_i32 s18, s4, 0x300002502; VI-NEXT: s_and_b32 s4, s17, 0xffff00002503; VI-NEXT: s_and_b32 s5, s5, 0xffff2504; VI-NEXT: s_or_b32 s4, s4, s52505; VI-NEXT: s_add_i32 s5, s16, 32506; VI-NEXT: s_add_i32 s17, s4, 0x300002507; VI-NEXT: s_and_b32 s4, s16, 0xffff00002508; VI-NEXT: s_and_b32 s5, s5, 0xffff2509; VI-NEXT: s_or_b32 s4, s4, s52510; VI-NEXT: s_add_i32 s16, s4, 0x300002511; VI-NEXT: .LBB15_3: ; %end2512; VI-NEXT: v_mov_b32_e32 v0, s162513; VI-NEXT: v_mov_b32_e32 v1, s172514; VI-NEXT: v_mov_b32_e32 v2, s182515; VI-NEXT: v_mov_b32_e32 v3, s192516; VI-NEXT: v_mov_b32_e32 v4, s202517; VI-NEXT: v_mov_b32_e32 v5, s212518; VI-NEXT: v_mov_b32_e32 v6, s222519; VI-NEXT: s_setpc_b64 s[30:31]2520; VI-NEXT: .LBB15_4:2521; VI-NEXT: s_branch .LBB15_22522;2523; GFX9-LABEL: bitcast_v14i16_to_v7f32_scalar:2524; GFX9: ; %bb.0:2525; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2526; GFX9-NEXT: s_cmp_lg_u32 s23, 02527; GFX9-NEXT: s_cbranch_scc0 .LBB15_32528; GFX9-NEXT: ; %bb.1: ; %cmp.false2529; GFX9-NEXT: s_cbranch_execnz .LBB15_42530; GFX9-NEXT: .LBB15_2: ; %cmp.true2531; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]2532; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]2533; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]2534; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]2535; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]2536; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]2537; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]2538; GFX9-NEXT: s_setpc_b64 s[30:31]2539; GFX9-NEXT: .LBB15_3:2540; GFX9-NEXT: s_branch .LBB15_22541; GFX9-NEXT: .LBB15_4:2542; GFX9-NEXT: v_mov_b32_e32 v0, s162543; GFX9-NEXT: v_mov_b32_e32 v1, s172544; GFX9-NEXT: v_mov_b32_e32 v2, s182545; GFX9-NEXT: v_mov_b32_e32 v3, s192546; GFX9-NEXT: v_mov_b32_e32 v4, s202547; GFX9-NEXT: v_mov_b32_e32 v5, s212548; GFX9-NEXT: v_mov_b32_e32 v6, s222549; GFX9-NEXT: s_setpc_b64 s[30:31]2550;2551; GFX11-LABEL: bitcast_v14i16_to_v7f32_scalar:2552; GFX11: ; %bb.0:2553; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2554; GFX11-NEXT: s_mov_b32 s6, s182555; GFX11-NEXT: s_mov_b32 s5, s172556; GFX11-NEXT: s_mov_b32 s4, s162557; GFX11-NEXT: s_cmp_lg_u32 s19, 02558; GFX11-NEXT: s_mov_b32 s7, 02559; GFX11-NEXT: s_cbranch_scc0 .LBB15_32560; GFX11-NEXT: ; %bb.1: ; %Flow2561; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s72562; GFX11-NEXT: s_cbranch_vccnz .LBB15_42563; GFX11-NEXT: .LBB15_2: ; %cmp.true2564; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]2565; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]2566; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]2567; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]2568; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]2569; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]2570; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]2571; GFX11-NEXT: s_setpc_b64 s[30:31]2572; GFX11-NEXT: .LBB15_3:2573; GFX11-NEXT: s_branch .LBB15_22574; GFX11-NEXT: .LBB15_4:2575; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12576; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32577; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52578; GFX11-NEXT: v_mov_b32_e32 v6, s62579; GFX11-NEXT: s_setpc_b64 s[30:31]2580 %cmp = icmp eq i32 %b, 02581 br i1 %cmp, label %cmp.true, label %cmp.false2582 2583cmp.true:2584 %a1 = add <14 x i16> %a, splat (i16 3)2585 %a2 = bitcast <14 x i16> %a1 to <7 x float>2586 br label %end2587 2588cmp.false:2589 %a3 = bitcast <14 x i16> %a to <7 x float>2590 br label %end2591 2592end:2593 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2594 ret <7 x float> %phi2595}2596 2597define <14 x half> @bitcast_v7f32_to_v14f16(<7 x float> %a, i32 %b) {2598; SI-LABEL: bitcast_v7f32_to_v14f16:2599; SI: ; %bb.0:2600; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2601; SI-NEXT: v_mov_b32_e32 v20, v62602; SI-NEXT: v_mov_b32_e32 v19, v52603; SI-NEXT: v_mov_b32_e32 v18, v42604; SI-NEXT: v_mov_b32_e32 v17, v32605; SI-NEXT: v_mov_b32_e32 v16, v22606; SI-NEXT: v_mov_b32_e32 v15, v12607; SI-NEXT: v_mov_b32_e32 v14, v02608; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v72609; SI-NEXT: ; implicit-def: $vgpr02610; SI-NEXT: ; implicit-def: $vgpr12611; SI-NEXT: ; implicit-def: $vgpr22612; SI-NEXT: ; implicit-def: $vgpr32613; SI-NEXT: ; implicit-def: $vgpr42614; SI-NEXT: ; implicit-def: $vgpr52615; SI-NEXT: ; implicit-def: $vgpr62616; SI-NEXT: ; implicit-def: $vgpr72617; SI-NEXT: ; implicit-def: $vgpr82618; SI-NEXT: ; implicit-def: $vgpr92619; SI-NEXT: ; implicit-def: $vgpr102620; SI-NEXT: ; implicit-def: $vgpr112621; SI-NEXT: ; implicit-def: $vgpr122622; SI-NEXT: ; implicit-def: $vgpr132623; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2624; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2625; SI-NEXT: s_cbranch_execnz .LBB16_32626; SI-NEXT: ; %bb.1: ; %Flow2627; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2628; SI-NEXT: s_cbranch_execnz .LBB16_42629; SI-NEXT: .LBB16_2: ; %end2630; SI-NEXT: s_or_b64 exec, exec, s[4:5]2631; SI-NEXT: s_setpc_b64 s[30:31]2632; SI-NEXT: .LBB16_3: ; %cmp.false2633; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v202634; SI-NEXT: v_cvt_f32_f16_e32 v13, v02635; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v192636; SI-NEXT: v_cvt_f32_f16_e32 v11, v02637; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v182638; SI-NEXT: v_cvt_f32_f16_e32 v9, v02639; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v172640; SI-NEXT: v_cvt_f32_f16_e32 v7, v02641; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v162642; SI-NEXT: v_cvt_f32_f16_e32 v5, v02643; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v152644; SI-NEXT: v_cvt_f32_f16_e32 v3, v02645; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v142646; SI-NEXT: v_cvt_f32_f16_e32 v1, v02647; SI-NEXT: v_cvt_f32_f16_e32 v12, v202648; SI-NEXT: v_cvt_f32_f16_e32 v10, v192649; SI-NEXT: v_cvt_f32_f16_e32 v8, v182650; SI-NEXT: v_cvt_f32_f16_e32 v6, v172651; SI-NEXT: v_cvt_f32_f16_e32 v4, v162652; SI-NEXT: v_cvt_f32_f16_e32 v2, v152653; SI-NEXT: v_cvt_f32_f16_e32 v0, v142654; SI-NEXT: ; implicit-def: $vgpr142655; SI-NEXT: ; implicit-def: $vgpr152656; SI-NEXT: ; implicit-def: $vgpr162657; SI-NEXT: ; implicit-def: $vgpr172658; SI-NEXT: ; implicit-def: $vgpr182659; SI-NEXT: ; implicit-def: $vgpr192660; SI-NEXT: ; implicit-def: $vgpr202661; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2662; SI-NEXT: s_cbranch_execz .LBB16_22663; SI-NEXT: .LBB16_4: ; %cmp.true2664; SI-NEXT: v_add_f32_e32 v1, 1.0, v142665; SI-NEXT: v_add_f32_e32 v3, 1.0, v152666; SI-NEXT: v_add_f32_e32 v5, 1.0, v162667; SI-NEXT: v_add_f32_e32 v7, 1.0, v172668; SI-NEXT: v_add_f32_e32 v9, 1.0, v182669; SI-NEXT: v_add_f32_e32 v11, 1.0, v192670; SI-NEXT: v_add_f32_e32 v13, 1.0, v202671; SI-NEXT: v_cvt_f32_f16_e32 v12, v132672; SI-NEXT: v_cvt_f32_f16_e32 v10, v112673; SI-NEXT: v_cvt_f32_f16_e32 v8, v92674; SI-NEXT: v_cvt_f32_f16_e32 v6, v72675; SI-NEXT: v_cvt_f32_f16_e32 v4, v52676; SI-NEXT: v_cvt_f32_f16_e32 v2, v32677; SI-NEXT: v_cvt_f32_f16_e32 v0, v12678; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v132679; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v112680; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v92681; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v72682; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v52683; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v32684; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12685; SI-NEXT: v_cvt_f32_f16_e32 v13, v132686; SI-NEXT: v_cvt_f32_f16_e32 v11, v112687; SI-NEXT: v_cvt_f32_f16_e32 v9, v92688; SI-NEXT: v_cvt_f32_f16_e32 v7, v72689; SI-NEXT: v_cvt_f32_f16_e32 v5, v52690; SI-NEXT: v_cvt_f32_f16_e32 v3, v32691; SI-NEXT: v_cvt_f32_f16_e32 v1, v12692; SI-NEXT: s_or_b64 exec, exec, s[4:5]2693; SI-NEXT: s_setpc_b64 s[30:31]2694;2695; VI-LABEL: bitcast_v7f32_to_v14f16:2696; VI: ; %bb.0:2697; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2698; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v72699; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2700; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2701; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2702; VI-NEXT: ; %bb.1: ; %cmp.true2703; VI-NEXT: v_add_f32_e32 v6, 1.0, v62704; VI-NEXT: v_add_f32_e32 v5, 1.0, v52705; VI-NEXT: v_add_f32_e32 v4, 1.0, v42706; VI-NEXT: v_add_f32_e32 v3, 1.0, v32707; VI-NEXT: v_add_f32_e32 v2, 1.0, v22708; VI-NEXT: v_add_f32_e32 v1, 1.0, v12709; VI-NEXT: v_add_f32_e32 v0, 1.0, v02710; VI-NEXT: ; %bb.2: ; %end2711; VI-NEXT: s_or_b64 exec, exec, s[4:5]2712; VI-NEXT: s_setpc_b64 s[30:31]2713;2714; GFX9-LABEL: bitcast_v7f32_to_v14f16:2715; GFX9: ; %bb.0:2716; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2717; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v72718; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2719; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2720; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2721; GFX9-NEXT: ; %bb.1: ; %cmp.true2722; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v62723; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v52724; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v42725; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v32726; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v22727; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v12728; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v02729; GFX9-NEXT: ; %bb.2: ; %end2730; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2731; GFX9-NEXT: s_setpc_b64 s[30:31]2732;2733; GFX11-LABEL: bitcast_v7f32_to_v14f16:2734; GFX11: ; %bb.0:2735; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2736; GFX11-NEXT: s_mov_b32 s0, exec_lo2737; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v72738; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02739; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2740; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02741; GFX11-NEXT: ; %bb.1: ; %cmp.true2742; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v52743; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v32744; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v12745; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v02746; GFX11-NEXT: ; %bb.2: ; %end2747; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02748; GFX11-NEXT: s_setpc_b64 s[30:31]2749 %cmp = icmp eq i32 %b, 02750 br i1 %cmp, label %cmp.true, label %cmp.false2751 2752cmp.true:2753 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)2754 %a2 = bitcast <7 x float> %a1 to <14 x half>2755 br label %end2756 2757cmp.false:2758 %a3 = bitcast <7 x float> %a to <14 x half>2759 br label %end2760 2761end:2762 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2763 ret <14 x half> %phi2764}2765 2766define inreg <14 x half> @bitcast_v7f32_to_v14f16_scalar(<7 x float> inreg %a, i32 inreg %b) {2767; SI-LABEL: bitcast_v7f32_to_v14f16_scalar:2768; SI: ; %bb.0:2769; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2770; SI-NEXT: s_cmp_lg_u32 s23, 02771; SI-NEXT: s_cbranch_scc0 .LBB17_42772; SI-NEXT: ; %bb.1: ; %cmp.false2773; SI-NEXT: s_lshr_b32 s4, s22, 162774; SI-NEXT: v_cvt_f32_f16_e32 v13, s42775; SI-NEXT: s_lshr_b32 s4, s21, 162776; SI-NEXT: v_cvt_f32_f16_e32 v11, s42777; SI-NEXT: s_lshr_b32 s4, s20, 162778; SI-NEXT: v_cvt_f32_f16_e32 v9, s42779; SI-NEXT: s_lshr_b32 s4, s19, 162780; SI-NEXT: v_cvt_f32_f16_e32 v7, s42781; SI-NEXT: s_lshr_b32 s4, s18, 162782; SI-NEXT: v_cvt_f32_f16_e32 v5, s42783; SI-NEXT: s_lshr_b32 s4, s17, 162784; SI-NEXT: v_cvt_f32_f16_e32 v3, s42785; SI-NEXT: s_lshr_b32 s4, s16, 162786; SI-NEXT: v_cvt_f32_f16_e32 v1, s42787; SI-NEXT: v_cvt_f32_f16_e32 v12, s222788; SI-NEXT: v_cvt_f32_f16_e32 v10, s212789; SI-NEXT: v_cvt_f32_f16_e32 v8, s202790; SI-NEXT: v_cvt_f32_f16_e32 v6, s192791; SI-NEXT: v_cvt_f32_f16_e32 v4, s182792; SI-NEXT: v_cvt_f32_f16_e32 v2, s172793; SI-NEXT: v_cvt_f32_f16_e32 v0, s162794; SI-NEXT: s_cbranch_execnz .LBB17_32795; SI-NEXT: .LBB17_2: ; %cmp.true2796; SI-NEXT: v_add_f32_e64 v1, s16, 1.02797; SI-NEXT: v_add_f32_e64 v3, s17, 1.02798; SI-NEXT: v_add_f32_e64 v5, s18, 1.02799; SI-NEXT: v_add_f32_e64 v7, s19, 1.02800; SI-NEXT: v_add_f32_e64 v9, s20, 1.02801; SI-NEXT: v_add_f32_e64 v11, s21, 1.02802; SI-NEXT: v_add_f32_e64 v13, s22, 1.02803; SI-NEXT: v_cvt_f32_f16_e32 v12, v132804; SI-NEXT: v_cvt_f32_f16_e32 v10, v112805; SI-NEXT: v_cvt_f32_f16_e32 v8, v92806; SI-NEXT: v_cvt_f32_f16_e32 v6, v72807; SI-NEXT: v_cvt_f32_f16_e32 v4, v52808; SI-NEXT: v_cvt_f32_f16_e32 v2, v32809; SI-NEXT: v_cvt_f32_f16_e32 v0, v12810; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v132811; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v112812; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v92813; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v72814; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v52815; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v32816; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v12817; SI-NEXT: v_cvt_f32_f16_e32 v13, v132818; SI-NEXT: v_cvt_f32_f16_e32 v11, v112819; SI-NEXT: v_cvt_f32_f16_e32 v9, v92820; SI-NEXT: v_cvt_f32_f16_e32 v7, v72821; SI-NEXT: v_cvt_f32_f16_e32 v5, v52822; SI-NEXT: v_cvt_f32_f16_e32 v3, v32823; SI-NEXT: v_cvt_f32_f16_e32 v1, v12824; SI-NEXT: .LBB17_3: ; %end2825; SI-NEXT: s_setpc_b64 s[30:31]2826; SI-NEXT: .LBB17_4:2827; SI-NEXT: ; implicit-def: $vgpr02828; SI-NEXT: ; implicit-def: $vgpr12829; SI-NEXT: ; implicit-def: $vgpr22830; SI-NEXT: ; implicit-def: $vgpr32831; SI-NEXT: ; implicit-def: $vgpr42832; SI-NEXT: ; implicit-def: $vgpr52833; SI-NEXT: ; implicit-def: $vgpr62834; SI-NEXT: ; implicit-def: $vgpr72835; SI-NEXT: ; implicit-def: $vgpr82836; SI-NEXT: ; implicit-def: $vgpr92837; SI-NEXT: ; implicit-def: $vgpr102838; SI-NEXT: ; implicit-def: $vgpr112839; SI-NEXT: ; implicit-def: $vgpr122840; SI-NEXT: ; implicit-def: $vgpr132841; SI-NEXT: s_branch .LBB17_22842;2843; VI-LABEL: bitcast_v7f32_to_v14f16_scalar:2844; VI: ; %bb.0:2845; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2846; VI-NEXT: s_cmp_lg_u32 s23, 02847; VI-NEXT: s_cbranch_scc0 .LBB17_32848; VI-NEXT: ; %bb.1: ; %cmp.false2849; VI-NEXT: s_cbranch_execnz .LBB17_42850; VI-NEXT: .LBB17_2: ; %cmp.true2851; VI-NEXT: v_add_f32_e64 v6, s22, 1.02852; VI-NEXT: v_add_f32_e64 v5, s21, 1.02853; VI-NEXT: v_add_f32_e64 v4, s20, 1.02854; VI-NEXT: v_add_f32_e64 v3, s19, 1.02855; VI-NEXT: v_add_f32_e64 v2, s18, 1.02856; VI-NEXT: v_add_f32_e64 v1, s17, 1.02857; VI-NEXT: v_add_f32_e64 v0, s16, 1.02858; VI-NEXT: s_setpc_b64 s[30:31]2859; VI-NEXT: .LBB17_3:2860; VI-NEXT: s_branch .LBB17_22861; VI-NEXT: .LBB17_4:2862; VI-NEXT: v_mov_b32_e32 v0, s162863; VI-NEXT: v_mov_b32_e32 v1, s172864; VI-NEXT: v_mov_b32_e32 v2, s182865; VI-NEXT: v_mov_b32_e32 v3, s192866; VI-NEXT: v_mov_b32_e32 v4, s202867; VI-NEXT: v_mov_b32_e32 v5, s212868; VI-NEXT: v_mov_b32_e32 v6, s222869; VI-NEXT: v_mov_b32_e32 v7, s232870; VI-NEXT: s_setpc_b64 s[30:31]2871;2872; GFX9-LABEL: bitcast_v7f32_to_v14f16_scalar:2873; GFX9: ; %bb.0:2874; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2875; GFX9-NEXT: s_cmp_lg_u32 s23, 02876; GFX9-NEXT: s_cbranch_scc0 .LBB17_32877; GFX9-NEXT: ; %bb.1: ; %cmp.false2878; GFX9-NEXT: s_cbranch_execnz .LBB17_42879; GFX9-NEXT: .LBB17_2: ; %cmp.true2880; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.02881; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.02882; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.02883; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.02884; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.02885; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.02886; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.02887; GFX9-NEXT: s_setpc_b64 s[30:31]2888; GFX9-NEXT: .LBB17_3:2889; GFX9-NEXT: s_branch .LBB17_22890; GFX9-NEXT: .LBB17_4:2891; GFX9-NEXT: v_mov_b32_e32 v0, s162892; GFX9-NEXT: v_mov_b32_e32 v1, s172893; GFX9-NEXT: v_mov_b32_e32 v2, s182894; GFX9-NEXT: v_mov_b32_e32 v3, s192895; GFX9-NEXT: v_mov_b32_e32 v4, s202896; GFX9-NEXT: v_mov_b32_e32 v5, s212897; GFX9-NEXT: v_mov_b32_e32 v6, s222898; GFX9-NEXT: v_mov_b32_e32 v7, s232899; GFX9-NEXT: s_setpc_b64 s[30:31]2900;2901; GFX11-LABEL: bitcast_v7f32_to_v14f16_scalar:2902; GFX11: ; %bb.0:2903; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2904; GFX11-NEXT: s_mov_b32 s6, s182905; GFX11-NEXT: s_mov_b32 s5, s172906; GFX11-NEXT: s_mov_b32 s4, s162907; GFX11-NEXT: s_cmp_lg_u32 s19, 02908; GFX11-NEXT: s_mov_b32 s8, 02909; GFX11-NEXT: s_cbranch_scc0 .LBB17_32910; GFX11-NEXT: ; %bb.1: ; %Flow2911; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s82912; GFX11-NEXT: s_cbranch_vccnz .LBB17_42913; GFX11-NEXT: .LBB17_2: ; %cmp.true2914; GFX11-NEXT: v_add_f32_e64 v6, s6, 1.02915; GFX11-NEXT: v_add_f32_e64 v5, s5, 1.02916; GFX11-NEXT: v_add_f32_e64 v4, s4, 1.02917; GFX11-NEXT: v_add_f32_e64 v3, s3, 1.02918; GFX11-NEXT: v_add_f32_e64 v2, s2, 1.02919; GFX11-NEXT: v_add_f32_e64 v1, s1, 1.02920; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.02921; GFX11-NEXT: s_setpc_b64 s[30:31]2922; GFX11-NEXT: .LBB17_3:2923; GFX11-NEXT: s_branch .LBB17_22924; GFX11-NEXT: .LBB17_4:2925; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s12926; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s32927; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s52928; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s72929; GFX11-NEXT: s_setpc_b64 s[30:31]2930 %cmp = icmp eq i32 %b, 02931 br i1 %cmp, label %cmp.true, label %cmp.false2932 2933cmp.true:2934 %a1 = fadd <7 x float> %a, splat (float 1.000000e+00)2935 %a2 = bitcast <7 x float> %a1 to <14 x half>2936 br label %end2937 2938cmp.false:2939 %a3 = bitcast <7 x float> %a to <14 x half>2940 br label %end2941 2942end:2943 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2944 ret <14 x half> %phi2945}2946 2947define <7 x float> @bitcast_v14f16_to_v7f32(<14 x half> %a, i32 %b) {2948; SI-LABEL: bitcast_v14f16_to_v7f32:2949; SI: ; %bb.0:2950; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2951; SI-NEXT: v_cvt_f16_f32_e32 v24, v12952; SI-NEXT: v_cvt_f16_f32_e32 v23, v02953; SI-NEXT: v_cvt_f16_f32_e32 v22, v32954; SI-NEXT: v_cvt_f16_f32_e32 v21, v22955; SI-NEXT: v_cvt_f16_f32_e32 v20, v52956; SI-NEXT: v_cvt_f16_f32_e32 v19, v42957; SI-NEXT: v_cvt_f16_f32_e32 v18, v72958; SI-NEXT: v_cvt_f16_f32_e32 v17, v62959; SI-NEXT: v_cvt_f16_f32_e32 v16, v92960; SI-NEXT: v_cvt_f16_f32_e32 v15, v82961; SI-NEXT: v_cvt_f16_f32_e32 v11, v112962; SI-NEXT: v_cvt_f16_f32_e32 v9, v102963; SI-NEXT: v_cvt_f16_f32_e32 v8, v132964; SI-NEXT: v_cvt_f16_f32_e32 v7, v122965; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v142966; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr62967; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2968; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2969; SI-NEXT: s_cbranch_execnz .LBB18_32970; SI-NEXT: ; %bb.1: ; %Flow2971; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2972; SI-NEXT: s_cbranch_execnz .LBB18_42973; SI-NEXT: .LBB18_2: ; %end2974; SI-NEXT: s_or_b64 exec, exec, s[4:5]2975; SI-NEXT: s_setpc_b64 s[30:31]2976; SI-NEXT: .LBB18_3: ; %cmp.false2977; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v242978; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v222979; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v202980; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v182981; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v162982; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v112983; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v82984; SI-NEXT: v_or_b32_e32 v0, v23, v02985; SI-NEXT: v_or_b32_e32 v1, v21, v12986; SI-NEXT: v_or_b32_e32 v2, v19, v22987; SI-NEXT: v_or_b32_e32 v3, v17, v32988; SI-NEXT: v_or_b32_e32 v4, v15, v42989; SI-NEXT: v_or_b32_e32 v5, v9, v52990; SI-NEXT: v_or_b32_e32 v6, v7, v62991; SI-NEXT: ; implicit-def: $vgpr242992; SI-NEXT: ; implicit-def: $vgpr232993; SI-NEXT: ; implicit-def: $vgpr222994; SI-NEXT: ; implicit-def: $vgpr212995; SI-NEXT: ; implicit-def: $vgpr202996; SI-NEXT: ; implicit-def: $vgpr192997; SI-NEXT: ; implicit-def: $vgpr182998; SI-NEXT: ; implicit-def: $vgpr172999; SI-NEXT: ; implicit-def: $vgpr163000; SI-NEXT: ; implicit-def: $vgpr153001; SI-NEXT: ; implicit-def: $vgpr113002; SI-NEXT: ; implicit-def: $vgpr93003; SI-NEXT: ; implicit-def: $vgpr83004; SI-NEXT: ; implicit-def: $vgpr73005; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3006; SI-NEXT: s_cbranch_execz .LBB18_23007; SI-NEXT: .LBB18_4: ; %cmp.true3008; SI-NEXT: v_cvt_f32_f16_e32 v0, v243009; SI-NEXT: v_cvt_f32_f16_e32 v1, v233010; SI-NEXT: v_cvt_f32_f16_e32 v2, v223011; SI-NEXT: v_cvt_f32_f16_e32 v3, v213012; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03013; SI-NEXT: v_cvt_f16_f32_e32 v0, v03014; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13015; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23016; SI-NEXT: v_cvt_f16_f32_e32 v1, v13017; SI-NEXT: v_cvt_f16_f32_e32 v2, v23018; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33019; SI-NEXT: v_cvt_f16_f32_e32 v3, v33020; SI-NEXT: v_cvt_f32_f16_e32 v4, v203021; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03022; SI-NEXT: v_or_b32_e32 v0, v1, v03023; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23024; SI-NEXT: v_or_b32_e32 v1, v3, v13025; SI-NEXT: v_cvt_f32_f16_e32 v2, v193026; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v43027; SI-NEXT: v_cvt_f32_f16_e32 v4, v183028; SI-NEXT: v_cvt_f16_f32_e32 v3, v33029; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23030; SI-NEXT: v_cvt_f16_f32_e32 v2, v23031; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43032; SI-NEXT: v_cvt_f16_f32_e32 v4, v43033; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33034; SI-NEXT: v_cvt_f32_f16_e32 v5, v173035; SI-NEXT: v_or_b32_e32 v2, v2, v33036; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43037; SI-NEXT: v_cvt_f32_f16_e32 v4, v163038; SI-NEXT: v_cvt_f32_f16_e32 v6, v153039; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53040; SI-NEXT: v_cvt_f16_f32_e32 v5, v53041; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43042; SI-NEXT: v_cvt_f16_f32_e32 v4, v43043; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63044; SI-NEXT: v_cvt_f16_f32_e32 v6, v63045; SI-NEXT: v_or_b32_e32 v3, v5, v33046; SI-NEXT: v_cvt_f32_f16_e32 v5, v113047; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v43048; SI-NEXT: v_or_b32_e32 v4, v6, v43049; SI-NEXT: v_cvt_f32_f16_e32 v6, v93050; SI-NEXT: v_cvt_f32_f16_e32 v8, v83051; SI-NEXT: v_cvt_f32_f16_e32 v7, v73052; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53053; SI-NEXT: v_cvt_f16_f32_e32 v5, v53054; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63055; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83056; SI-NEXT: v_cvt_f16_f32_e32 v6, v63057; SI-NEXT: v_cvt_f16_f32_e32 v8, v83058; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73059; SI-NEXT: v_cvt_f16_f32_e32 v7, v73060; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53061; SI-NEXT: v_or_b32_e32 v5, v6, v53062; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v83063; SI-NEXT: v_or_b32_e32 v6, v7, v63064; SI-NEXT: s_or_b64 exec, exec, s[4:5]3065; SI-NEXT: s_setpc_b64 s[30:31]3066;3067; VI-LABEL: bitcast_v14f16_to_v7f32:3068; VI: ; %bb.0:3069; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3070; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73071; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3072; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3073; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3074; VI-NEXT: s_cbranch_execz .LBB18_23075; VI-NEXT: ; %bb.1: ; %cmp.true3076; VI-NEXT: v_mov_b32_e32 v7, 0x2003077; VI-NEXT: v_add_f16_sdwa v8, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3078; VI-NEXT: v_add_f16_e32 v6, 0x200, v63079; VI-NEXT: v_or_b32_e32 v6, v6, v83080; VI-NEXT: v_add_f16_sdwa v8, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3081; VI-NEXT: v_add_f16_e32 v5, 0x200, v53082; VI-NEXT: v_or_b32_e32 v5, v5, v83083; VI-NEXT: v_add_f16_sdwa v8, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3084; VI-NEXT: v_add_f16_e32 v4, 0x200, v43085; VI-NEXT: v_or_b32_e32 v4, v4, v83086; VI-NEXT: v_add_f16_sdwa v8, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3087; VI-NEXT: v_add_f16_e32 v3, 0x200, v33088; VI-NEXT: v_or_b32_e32 v3, v3, v83089; VI-NEXT: v_add_f16_sdwa v8, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3090; VI-NEXT: v_add_f16_e32 v2, 0x200, v23091; VI-NEXT: v_or_b32_e32 v2, v2, v83092; VI-NEXT: v_add_f16_sdwa v8, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3093; VI-NEXT: v_add_f16_e32 v1, 0x200, v13094; VI-NEXT: v_add_f16_sdwa v7, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3095; VI-NEXT: v_add_f16_e32 v0, 0x200, v03096; VI-NEXT: v_or_b32_e32 v1, v1, v83097; VI-NEXT: v_or_b32_e32 v0, v0, v73098; VI-NEXT: .LBB18_2: ; %end3099; VI-NEXT: s_or_b64 exec, exec, s[4:5]3100; VI-NEXT: s_setpc_b64 s[30:31]3101;3102; GFX9-LABEL: bitcast_v14f16_to_v7f32:3103; GFX9: ; %bb.0:3104; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3105; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73106; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3107; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3108; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3109; GFX9-NEXT: ; %bb.1: ; %cmp.true3110; GFX9-NEXT: s_movk_i32 s6, 0x2003111; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]3112; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]3113; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]3114; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]3115; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]3116; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]3117; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3118; GFX9-NEXT: ; %bb.2: ; %end3119; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3120; GFX9-NEXT: s_setpc_b64 s[30:31]3121;3122; GFX11-LABEL: bitcast_v14f16_to_v7f32:3123; GFX11: ; %bb.0:3124; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3125; GFX11-NEXT: s_mov_b32 s0, exec_lo3126; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v73127; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03128; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3129; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03130; GFX11-NEXT: s_cbranch_execz .LBB18_23131; GFX11-NEXT: ; %bb.1: ; %cmp.true3132; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]3133; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]3134; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]3135; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]3136; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]3137; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]3138; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3139; GFX11-NEXT: .LBB18_2: ; %end3140; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03141; GFX11-NEXT: s_setpc_b64 s[30:31]3142 %cmp = icmp eq i32 %b, 03143 br i1 %cmp, label %cmp.true, label %cmp.false3144 3145cmp.true:3146 %a1 = fadd <14 x half> %a, splat (half 0xH0200)3147 %a2 = bitcast <14 x half> %a1 to <7 x float>3148 br label %end3149 3150cmp.false:3151 %a3 = bitcast <14 x half> %a to <7 x float>3152 br label %end3153 3154end:3155 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3156 ret <7 x float> %phi3157}3158 3159define inreg <7 x float> @bitcast_v14f16_to_v7f32_scalar(<14 x half> inreg %a, i32 inreg %b) {3160; SI-LABEL: bitcast_v14f16_to_v7f32_scalar:3161; SI: ; %bb.0:3162; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3163; SI-NEXT: v_cvt_f16_f32_e32 v20, s173164; SI-NEXT: v_cvt_f16_f32_e32 v19, s163165; SI-NEXT: v_cvt_f16_f32_e32 v18, s193166; SI-NEXT: v_cvt_f16_f32_e32 v17, s183167; SI-NEXT: v_cvt_f16_f32_e32 v16, s213168; SI-NEXT: v_cvt_f16_f32_e32 v15, s203169; SI-NEXT: v_cvt_f16_f32_e32 v14, s233170; SI-NEXT: v_cvt_f16_f32_e32 v13, s223171; SI-NEXT: v_cvt_f16_f32_e32 v12, s253172; SI-NEXT: v_cvt_f16_f32_e32 v11, s243173; SI-NEXT: v_cvt_f16_f32_e32 v10, s273174; SI-NEXT: v_cvt_f16_f32_e32 v9, s263175; SI-NEXT: v_cvt_f16_f32_e32 v8, s293176; SI-NEXT: v_cvt_f16_f32_e32 v7, s283177; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03178; SI-NEXT: s_and_b64 s[4:5], vcc, exec3179; SI-NEXT: s_cbranch_scc0 .LBB19_43180; SI-NEXT: ; %bb.1: ; %cmp.false3181; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v203182; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v183183; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v163184; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v143185; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v123186; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v103187; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v83188; SI-NEXT: v_or_b32_e32 v0, v19, v03189; SI-NEXT: v_or_b32_e32 v1, v17, v13190; SI-NEXT: v_or_b32_e32 v2, v15, v23191; SI-NEXT: v_or_b32_e32 v3, v13, v33192; SI-NEXT: v_or_b32_e32 v4, v11, v43193; SI-NEXT: v_or_b32_e32 v5, v9, v53194; SI-NEXT: v_or_b32_e32 v6, v7, v63195; SI-NEXT: s_cbranch_execnz .LBB19_33196; SI-NEXT: .LBB19_2: ; %cmp.true3197; SI-NEXT: v_cvt_f32_f16_e32 v0, v203198; SI-NEXT: v_cvt_f32_f16_e32 v1, v193199; SI-NEXT: v_cvt_f32_f16_e32 v2, v183200; SI-NEXT: v_cvt_f32_f16_e32 v3, v173201; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03202; SI-NEXT: v_cvt_f16_f32_e32 v0, v03203; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13204; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23205; SI-NEXT: v_cvt_f16_f32_e32 v1, v13206; SI-NEXT: v_cvt_f16_f32_e32 v2, v23207; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33208; SI-NEXT: v_cvt_f16_f32_e32 v3, v33209; SI-NEXT: v_cvt_f32_f16_e32 v4, v163210; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03211; SI-NEXT: v_or_b32_e32 v0, v1, v03212; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v23213; SI-NEXT: v_or_b32_e32 v1, v3, v13214; SI-NEXT: v_cvt_f32_f16_e32 v2, v153215; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v43216; SI-NEXT: v_cvt_f32_f16_e32 v4, v143217; SI-NEXT: v_cvt_f16_f32_e32 v3, v33218; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23219; SI-NEXT: v_cvt_f16_f32_e32 v2, v23220; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43221; SI-NEXT: v_cvt_f16_f32_e32 v4, v43222; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v33223; SI-NEXT: v_cvt_f32_f16_e32 v5, v133224; SI-NEXT: v_or_b32_e32 v2, v2, v33225; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43226; SI-NEXT: v_cvt_f32_f16_e32 v4, v123227; SI-NEXT: v_cvt_f32_f16_e32 v6, v113228; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53229; SI-NEXT: v_cvt_f16_f32_e32 v5, v53230; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43231; SI-NEXT: v_cvt_f16_f32_e32 v4, v43232; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63233; SI-NEXT: v_cvt_f16_f32_e32 v6, v63234; SI-NEXT: v_or_b32_e32 v3, v5, v33235; SI-NEXT: v_cvt_f32_f16_e32 v5, v103236; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v43237; SI-NEXT: v_or_b32_e32 v4, v6, v43238; SI-NEXT: v_cvt_f32_f16_e32 v6, v93239; SI-NEXT: v_cvt_f32_f16_e32 v8, v83240; SI-NEXT: v_cvt_f32_f16_e32 v7, v73241; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53242; SI-NEXT: v_cvt_f16_f32_e32 v5, v53243; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63244; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83245; SI-NEXT: v_cvt_f16_f32_e32 v6, v63246; SI-NEXT: v_cvt_f16_f32_e32 v8, v83247; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73248; SI-NEXT: v_cvt_f16_f32_e32 v7, v73249; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53250; SI-NEXT: v_or_b32_e32 v5, v6, v53251; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v83252; SI-NEXT: v_or_b32_e32 v6, v7, v63253; SI-NEXT: .LBB19_3: ; %end3254; SI-NEXT: s_setpc_b64 s[30:31]3255; SI-NEXT: .LBB19_4:3256; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr63257; SI-NEXT: s_branch .LBB19_23258;3259; VI-LABEL: bitcast_v14f16_to_v7f32_scalar:3260; VI: ; %bb.0:3261; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3262; VI-NEXT: s_cmp_lg_u32 s23, 03263; VI-NEXT: s_cbranch_scc0 .LBB19_33264; VI-NEXT: ; %bb.1: ; %cmp.false3265; VI-NEXT: s_cbranch_execnz .LBB19_43266; VI-NEXT: .LBB19_2: ; %cmp.true3267; VI-NEXT: s_lshr_b32 s4, s22, 163268; VI-NEXT: v_mov_b32_e32 v0, 0x2003269; VI-NEXT: v_mov_b32_e32 v1, s43270; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3271; VI-NEXT: v_add_f16_e32 v2, s22, v03272; VI-NEXT: s_lshr_b32 s4, s21, 163273; VI-NEXT: v_or_b32_e32 v6, v2, v13274; VI-NEXT: v_mov_b32_e32 v1, s43275; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3276; VI-NEXT: v_add_f16_e32 v2, s21, v03277; VI-NEXT: s_lshr_b32 s4, s20, 163278; VI-NEXT: v_or_b32_e32 v5, v2, v13279; VI-NEXT: v_mov_b32_e32 v1, s43280; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3281; VI-NEXT: v_add_f16_e32 v2, s20, v03282; VI-NEXT: s_lshr_b32 s4, s19, 163283; VI-NEXT: v_or_b32_e32 v4, v2, v13284; VI-NEXT: v_mov_b32_e32 v1, s43285; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3286; VI-NEXT: v_add_f16_e32 v2, s19, v03287; VI-NEXT: s_lshr_b32 s4, s18, 163288; VI-NEXT: v_or_b32_e32 v3, v2, v13289; VI-NEXT: v_mov_b32_e32 v1, s43290; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3291; VI-NEXT: v_add_f16_e32 v2, s18, v03292; VI-NEXT: s_lshr_b32 s4, s17, 163293; VI-NEXT: v_or_b32_e32 v2, v2, v13294; VI-NEXT: v_mov_b32_e32 v1, s43295; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3296; VI-NEXT: v_add_f16_e32 v7, s17, v03297; VI-NEXT: s_lshr_b32 s4, s16, 163298; VI-NEXT: v_or_b32_e32 v1, v7, v13299; VI-NEXT: v_mov_b32_e32 v7, s43300; VI-NEXT: v_add_f16_sdwa v7, v7, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3301; VI-NEXT: v_add_f16_e32 v0, s16, v03302; VI-NEXT: v_or_b32_e32 v0, v0, v73303; VI-NEXT: s_setpc_b64 s[30:31]3304; VI-NEXT: .LBB19_3:3305; VI-NEXT: s_branch .LBB19_23306; VI-NEXT: .LBB19_4:3307; VI-NEXT: v_mov_b32_e32 v0, s163308; VI-NEXT: v_mov_b32_e32 v1, s173309; VI-NEXT: v_mov_b32_e32 v2, s183310; VI-NEXT: v_mov_b32_e32 v3, s193311; VI-NEXT: v_mov_b32_e32 v4, s203312; VI-NEXT: v_mov_b32_e32 v5, s213313; VI-NEXT: v_mov_b32_e32 v6, s223314; VI-NEXT: s_setpc_b64 s[30:31]3315;3316; GFX9-LABEL: bitcast_v14f16_to_v7f32_scalar:3317; GFX9: ; %bb.0:3318; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3319; GFX9-NEXT: s_cmp_lg_u32 s23, 03320; GFX9-NEXT: s_cbranch_scc0 .LBB19_33321; GFX9-NEXT: ; %bb.1: ; %cmp.false3322; GFX9-NEXT: s_cbranch_execnz .LBB19_43323; GFX9-NEXT: .LBB19_2: ; %cmp.true3324; GFX9-NEXT: v_mov_b32_e32 v0, 0x2003325; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]3326; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]3327; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]3328; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]3329; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]3330; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]3331; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]3332; GFX9-NEXT: s_setpc_b64 s[30:31]3333; GFX9-NEXT: .LBB19_3:3334; GFX9-NEXT: s_branch .LBB19_23335; GFX9-NEXT: .LBB19_4:3336; GFX9-NEXT: v_mov_b32_e32 v0, s163337; GFX9-NEXT: v_mov_b32_e32 v1, s173338; GFX9-NEXT: v_mov_b32_e32 v2, s183339; GFX9-NEXT: v_mov_b32_e32 v3, s193340; GFX9-NEXT: v_mov_b32_e32 v4, s203341; GFX9-NEXT: v_mov_b32_e32 v5, s213342; GFX9-NEXT: v_mov_b32_e32 v6, s223343; GFX9-NEXT: s_setpc_b64 s[30:31]3344;3345; GFX11-LABEL: bitcast_v14f16_to_v7f32_scalar:3346; GFX11: ; %bb.0:3347; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3348; GFX11-NEXT: s_mov_b32 s6, s183349; GFX11-NEXT: s_mov_b32 s5, s173350; GFX11-NEXT: s_mov_b32 s4, s163351; GFX11-NEXT: s_cmp_lg_u32 s19, 03352; GFX11-NEXT: s_mov_b32 s7, 03353; GFX11-NEXT: s_cbranch_scc0 .LBB19_33354; GFX11-NEXT: ; %bb.1: ; %Flow3355; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s73356; GFX11-NEXT: s_cbranch_vccnz .LBB19_43357; GFX11-NEXT: .LBB19_2: ; %cmp.true3358; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]3359; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]3360; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]3361; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]3362; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]3363; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]3364; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]3365; GFX11-NEXT: s_setpc_b64 s[30:31]3366; GFX11-NEXT: .LBB19_3:3367; GFX11-NEXT: s_branch .LBB19_23368; GFX11-NEXT: .LBB19_4:3369; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13370; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33371; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53372; GFX11-NEXT: v_mov_b32_e32 v6, s63373; GFX11-NEXT: s_setpc_b64 s[30:31]3374 %cmp = icmp eq i32 %b, 03375 br i1 %cmp, label %cmp.true, label %cmp.false3376 3377cmp.true:3378 %a1 = fadd <14 x half> %a, splat (half 0xH0200)3379 %a2 = bitcast <14 x half> %a1 to <7 x float>3380 br label %end3381 3382cmp.false:3383 %a3 = bitcast <14 x half> %a to <7 x float>3384 br label %end3385 3386end:3387 %phi = phi <7 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3388 ret <7 x float> %phi3389}3390 3391define <14 x half> @bitcast_v14i16_to_v14f16(<14 x i16> %a, i32 %b) {3392; SI-LABEL: bitcast_v14i16_to_v14f16:3393; SI: ; %bb.0:3394; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3395; SI-NEXT: v_mov_b32_e32 v27, v133396; SI-NEXT: v_mov_b32_e32 v26, v123397; SI-NEXT: v_mov_b32_e32 v25, v113398; SI-NEXT: v_mov_b32_e32 v24, v103399; SI-NEXT: v_mov_b32_e32 v23, v93400; SI-NEXT: v_mov_b32_e32 v22, v83401; SI-NEXT: v_mov_b32_e32 v21, v73402; SI-NEXT: v_mov_b32_e32 v20, v63403; SI-NEXT: v_mov_b32_e32 v19, v53404; SI-NEXT: v_mov_b32_e32 v18, v43405; SI-NEXT: v_mov_b32_e32 v17, v33406; SI-NEXT: v_mov_b32_e32 v16, v23407; SI-NEXT: v_mov_b32_e32 v15, v13408; SI-NEXT: v_mov_b32_e32 v28, v03409; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143410; SI-NEXT: ; implicit-def: $vgpr03411; SI-NEXT: ; implicit-def: $vgpr13412; SI-NEXT: ; implicit-def: $vgpr23413; SI-NEXT: ; implicit-def: $vgpr33414; SI-NEXT: ; implicit-def: $vgpr43415; SI-NEXT: ; implicit-def: $vgpr53416; SI-NEXT: ; implicit-def: $vgpr63417; SI-NEXT: ; implicit-def: $vgpr73418; SI-NEXT: ; implicit-def: $vgpr83419; SI-NEXT: ; implicit-def: $vgpr93420; SI-NEXT: ; implicit-def: $vgpr103421; SI-NEXT: ; implicit-def: $vgpr113422; SI-NEXT: ; implicit-def: $vgpr123423; SI-NEXT: ; implicit-def: $vgpr133424; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3425; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3426; SI-NEXT: s_cbranch_execnz .LBB20_33427; SI-NEXT: ; %bb.1: ; %Flow3428; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3429; SI-NEXT: s_cbranch_execnz .LBB20_43430; SI-NEXT: .LBB20_2: ; %end3431; SI-NEXT: s_or_b64 exec, exec, s[4:5]3432; SI-NEXT: s_setpc_b64 s[30:31]3433; SI-NEXT: .LBB20_3: ; %cmp.false3434; SI-NEXT: v_cvt_f32_f16_e32 v0, v283435; SI-NEXT: v_cvt_f32_f16_e32 v1, v153436; SI-NEXT: v_cvt_f32_f16_e32 v2, v163437; SI-NEXT: v_cvt_f32_f16_e32 v3, v173438; SI-NEXT: v_cvt_f32_f16_e32 v4, v183439; SI-NEXT: v_cvt_f32_f16_e32 v5, v193440; SI-NEXT: v_cvt_f32_f16_e32 v6, v203441; SI-NEXT: v_cvt_f32_f16_e32 v7, v213442; SI-NEXT: v_cvt_f32_f16_e32 v8, v223443; SI-NEXT: v_cvt_f32_f16_e32 v9, v233444; SI-NEXT: v_cvt_f32_f16_e32 v10, v243445; SI-NEXT: v_cvt_f32_f16_e32 v11, v253446; SI-NEXT: v_cvt_f32_f16_e32 v12, v263447; SI-NEXT: v_cvt_f32_f16_e32 v13, v273448; SI-NEXT: ; implicit-def: $vgpr283449; SI-NEXT: ; implicit-def: $vgpr153450; SI-NEXT: ; implicit-def: $vgpr163451; SI-NEXT: ; implicit-def: $vgpr173452; SI-NEXT: ; implicit-def: $vgpr183453; SI-NEXT: ; implicit-def: $vgpr193454; SI-NEXT: ; implicit-def: $vgpr203455; SI-NEXT: ; implicit-def: $vgpr213456; SI-NEXT: ; implicit-def: $vgpr223457; SI-NEXT: ; implicit-def: $vgpr233458; SI-NEXT: ; implicit-def: $vgpr243459; SI-NEXT: ; implicit-def: $vgpr253460; SI-NEXT: ; implicit-def: $vgpr263461; SI-NEXT: ; implicit-def: $vgpr273462; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3463; SI-NEXT: s_cbranch_execz .LBB20_23464; SI-NEXT: .LBB20_4: ; %cmp.true3465; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v273466; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v263467; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v253468; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v243469; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v233470; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v223471; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v213472; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v203473; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v193474; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v183475; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v173476; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v163477; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v153478; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v283479; SI-NEXT: v_cvt_f32_f16_e32 v0, v03480; SI-NEXT: v_cvt_f32_f16_e32 v1, v13481; SI-NEXT: v_cvt_f32_f16_e32 v2, v23482; SI-NEXT: v_cvt_f32_f16_e32 v3, v33483; SI-NEXT: v_cvt_f32_f16_e32 v4, v43484; SI-NEXT: v_cvt_f32_f16_e32 v5, v53485; SI-NEXT: v_cvt_f32_f16_e32 v6, v63486; SI-NEXT: v_cvt_f32_f16_e32 v7, v73487; SI-NEXT: v_cvt_f32_f16_e32 v8, v83488; SI-NEXT: v_cvt_f32_f16_e32 v9, v93489; SI-NEXT: v_cvt_f32_f16_e32 v10, v103490; SI-NEXT: v_cvt_f32_f16_e32 v11, v113491; SI-NEXT: v_cvt_f32_f16_e32 v12, v123492; SI-NEXT: v_cvt_f32_f16_e32 v13, v133493; SI-NEXT: s_or_b64 exec, exec, s[4:5]3494; SI-NEXT: s_setpc_b64 s[30:31]3495;3496; VI-LABEL: bitcast_v14i16_to_v14f16:3497; VI: ; %bb.0:3498; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3499; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73500; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3501; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3502; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3503; VI-NEXT: s_cbranch_execz .LBB20_23504; VI-NEXT: ; %bb.1: ; %cmp.true3505; VI-NEXT: v_mov_b32_e32 v7, 33506; VI-NEXT: v_add_u16_sdwa v8, v0, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3507; VI-NEXT: v_add_u16_sdwa v9, v1, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3508; VI-NEXT: v_add_u16_sdwa v10, v2, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3509; VI-NEXT: v_add_u16_sdwa v11, v3, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3510; VI-NEXT: v_add_u16_sdwa v12, v4, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3511; VI-NEXT: v_add_u16_sdwa v13, v5, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3512; VI-NEXT: v_add_u16_sdwa v7, v6, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3513; VI-NEXT: v_add_u16_e32 v6, 3, v63514; VI-NEXT: v_add_u16_e32 v5, 3, v53515; VI-NEXT: v_add_u16_e32 v4, 3, v43516; VI-NEXT: v_add_u16_e32 v3, 3, v33517; VI-NEXT: v_add_u16_e32 v2, 3, v23518; VI-NEXT: v_add_u16_e32 v1, 3, v13519; VI-NEXT: v_add_u16_e32 v0, 3, v03520; VI-NEXT: v_or_b32_e32 v6, v6, v73521; VI-NEXT: v_or_b32_e32 v5, v5, v133522; VI-NEXT: v_or_b32_e32 v4, v4, v123523; VI-NEXT: v_or_b32_e32 v3, v3, v113524; VI-NEXT: v_or_b32_e32 v2, v2, v103525; VI-NEXT: v_or_b32_e32 v1, v1, v93526; VI-NEXT: v_or_b32_e32 v0, v0, v83527; VI-NEXT: .LBB20_2: ; %end3528; VI-NEXT: s_or_b64 exec, exec, s[4:5]3529; VI-NEXT: s_setpc_b64 s[30:31]3530;3531; GFX9-LABEL: bitcast_v14i16_to_v14f16:3532; GFX9: ; %bb.0:3533; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3534; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73535; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3536; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3537; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3538; GFX9-NEXT: ; %bb.1: ; %cmp.true3539; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]3540; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3541; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3542; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3543; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3544; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3545; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3546; GFX9-NEXT: ; %bb.2: ; %end3547; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3548; GFX9-NEXT: s_setpc_b64 s[30:31]3549;3550; GFX11-LABEL: bitcast_v14i16_to_v14f16:3551; GFX11: ; %bb.0:3552; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3553; GFX11-NEXT: s_mov_b32 s0, exec_lo3554; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v73555; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03556; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3557; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03558; GFX11-NEXT: s_cbranch_execz .LBB20_23559; GFX11-NEXT: ; %bb.1: ; %cmp.true3560; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]3561; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]3562; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]3563; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]3564; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]3565; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]3566; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]3567; GFX11-NEXT: .LBB20_2: ; %end3568; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03569; GFX11-NEXT: s_setpc_b64 s[30:31]3570 %cmp = icmp eq i32 %b, 03571 br i1 %cmp, label %cmp.true, label %cmp.false3572 3573cmp.true:3574 %a1 = add <14 x i16> %a, splat (i16 3)3575 %a2 = bitcast <14 x i16> %a1 to <14 x half>3576 br label %end3577 3578cmp.false:3579 %a3 = bitcast <14 x i16> %a to <14 x half>3580 br label %end3581 3582end:3583 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3584 ret <14 x half> %phi3585}3586 3587define inreg <14 x half> @bitcast_v14i16_to_v14f16_scalar(<14 x i16> inreg %a, i32 inreg %b) {3588; SI-LABEL: bitcast_v14i16_to_v14f16_scalar:3589; SI: ; %bb.0:3590; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3591; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03592; SI-NEXT: s_and_b64 s[4:5], vcc, exec3593; SI-NEXT: s_cbranch_scc0 .LBB21_43594; SI-NEXT: ; %bb.1: ; %cmp.false3595; SI-NEXT: v_cvt_f32_f16_e32 v0, s163596; SI-NEXT: v_cvt_f32_f16_e32 v1, s173597; SI-NEXT: v_cvt_f32_f16_e32 v2, s183598; SI-NEXT: v_cvt_f32_f16_e32 v3, s193599; SI-NEXT: v_cvt_f32_f16_e32 v4, s203600; SI-NEXT: v_cvt_f32_f16_e32 v5, s213601; SI-NEXT: v_cvt_f32_f16_e32 v6, s223602; SI-NEXT: v_cvt_f32_f16_e32 v7, s233603; SI-NEXT: v_cvt_f32_f16_e32 v8, s243604; SI-NEXT: v_cvt_f32_f16_e32 v9, s253605; SI-NEXT: v_cvt_f32_f16_e32 v10, s263606; SI-NEXT: v_cvt_f32_f16_e32 v11, s273607; SI-NEXT: v_cvt_f32_f16_e32 v12, s283608; SI-NEXT: v_cvt_f32_f16_e32 v13, s293609; SI-NEXT: s_cbranch_execnz .LBB21_33610; SI-NEXT: .LBB21_2: ; %cmp.true3611; SI-NEXT: s_add_i32 s29, s29, 33612; SI-NEXT: s_add_i32 s28, s28, 33613; SI-NEXT: s_add_i32 s27, s27, 33614; SI-NEXT: s_add_i32 s26, s26, 33615; SI-NEXT: s_add_i32 s25, s25, 33616; SI-NEXT: s_add_i32 s24, s24, 33617; SI-NEXT: s_add_i32 s23, s23, 33618; SI-NEXT: s_add_i32 s22, s22, 33619; SI-NEXT: s_add_i32 s21, s21, 33620; SI-NEXT: s_add_i32 s20, s20, 33621; SI-NEXT: s_add_i32 s19, s19, 33622; SI-NEXT: s_add_i32 s18, s18, 33623; SI-NEXT: s_add_i32 s17, s17, 33624; SI-NEXT: s_add_i32 s16, s16, 33625; SI-NEXT: v_cvt_f32_f16_e32 v0, s163626; SI-NEXT: v_cvt_f32_f16_e32 v1, s173627; SI-NEXT: v_cvt_f32_f16_e32 v2, s183628; SI-NEXT: v_cvt_f32_f16_e32 v3, s193629; SI-NEXT: v_cvt_f32_f16_e32 v4, s203630; SI-NEXT: v_cvt_f32_f16_e32 v5, s213631; SI-NEXT: v_cvt_f32_f16_e32 v6, s223632; SI-NEXT: v_cvt_f32_f16_e32 v7, s233633; SI-NEXT: v_cvt_f32_f16_e32 v8, s243634; SI-NEXT: v_cvt_f32_f16_e32 v9, s253635; SI-NEXT: v_cvt_f32_f16_e32 v10, s263636; SI-NEXT: v_cvt_f32_f16_e32 v11, s273637; SI-NEXT: v_cvt_f32_f16_e32 v12, s283638; SI-NEXT: v_cvt_f32_f16_e32 v13, s293639; SI-NEXT: .LBB21_3: ; %end3640; SI-NEXT: s_setpc_b64 s[30:31]3641; SI-NEXT: .LBB21_4:3642; SI-NEXT: ; implicit-def: $vgpr03643; SI-NEXT: ; implicit-def: $vgpr13644; SI-NEXT: ; implicit-def: $vgpr23645; SI-NEXT: ; implicit-def: $vgpr33646; SI-NEXT: ; implicit-def: $vgpr43647; SI-NEXT: ; implicit-def: $vgpr53648; SI-NEXT: ; implicit-def: $vgpr63649; SI-NEXT: ; implicit-def: $vgpr73650; SI-NEXT: ; implicit-def: $vgpr83651; SI-NEXT: ; implicit-def: $vgpr93652; SI-NEXT: ; implicit-def: $vgpr103653; SI-NEXT: ; implicit-def: $vgpr113654; SI-NEXT: ; implicit-def: $vgpr123655; SI-NEXT: ; implicit-def: $vgpr133656; SI-NEXT: s_branch .LBB21_23657;3658; VI-LABEL: bitcast_v14i16_to_v14f16_scalar:3659; VI: ; %bb.0:3660; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3661; VI-NEXT: s_cmp_lg_u32 s23, 03662; VI-NEXT: s_cbranch_scc0 .LBB21_43663; VI-NEXT: ; %bb.1: ; %cmp.false3664; VI-NEXT: s_cbranch_execnz .LBB21_33665; VI-NEXT: .LBB21_2: ; %cmp.true3666; VI-NEXT: s_add_i32 s5, s16, 33667; VI-NEXT: s_and_b32 s6, s17, 0xffff00003668; VI-NEXT: s_add_i32 s7, s17, 33669; VI-NEXT: s_add_i32 s9, s18, 33670; VI-NEXT: s_add_i32 s11, s19, 33671; VI-NEXT: s_add_i32 s13, s20, 33672; VI-NEXT: s_add_i32 s15, s21, 33673; VI-NEXT: s_add_i32 s17, s22, 33674; VI-NEXT: s_and_b32 s4, s16, 0xffff00003675; VI-NEXT: s_and_b32 s8, s18, 0xffff00003676; VI-NEXT: s_and_b32 s10, s19, 0xffff00003677; VI-NEXT: s_and_b32 s12, s20, 0xffff00003678; VI-NEXT: s_and_b32 s14, s21, 0xffff00003679; VI-NEXT: s_and_b32 s16, s22, 0xffff00003680; VI-NEXT: s_and_b32 s17, s17, 0xffff3681; VI-NEXT: s_and_b32 s15, s15, 0xffff3682; VI-NEXT: s_and_b32 s13, s13, 0xffff3683; VI-NEXT: s_and_b32 s11, s11, 0xffff3684; VI-NEXT: s_and_b32 s9, s9, 0xffff3685; VI-NEXT: s_and_b32 s7, s7, 0xffff3686; VI-NEXT: s_and_b32 s5, s5, 0xffff3687; VI-NEXT: s_or_b32 s16, s16, s173688; VI-NEXT: s_or_b32 s14, s14, s153689; VI-NEXT: s_or_b32 s12, s12, s133690; VI-NEXT: s_or_b32 s10, s10, s113691; VI-NEXT: s_or_b32 s8, s8, s93692; VI-NEXT: s_or_b32 s6, s6, s73693; VI-NEXT: s_or_b32 s4, s4, s53694; VI-NEXT: s_add_i32 s22, s16, 0x300003695; VI-NEXT: s_add_i32 s21, s14, 0x300003696; VI-NEXT: s_add_i32 s20, s12, 0x300003697; VI-NEXT: s_add_i32 s19, s10, 0x300003698; VI-NEXT: s_add_i32 s18, s8, 0x300003699; VI-NEXT: s_add_i32 s17, s6, 0x300003700; VI-NEXT: s_add_i32 s16, s4, 0x300003701; VI-NEXT: .LBB21_3: ; %end3702; VI-NEXT: v_mov_b32_e32 v0, s163703; VI-NEXT: v_mov_b32_e32 v1, s173704; VI-NEXT: v_mov_b32_e32 v2, s183705; VI-NEXT: v_mov_b32_e32 v3, s193706; VI-NEXT: v_mov_b32_e32 v4, s203707; VI-NEXT: v_mov_b32_e32 v5, s213708; VI-NEXT: v_mov_b32_e32 v6, s223709; VI-NEXT: s_setpc_b64 s[30:31]3710; VI-NEXT: .LBB21_4:3711; VI-NEXT: s_branch .LBB21_23712;3713; GFX9-LABEL: bitcast_v14i16_to_v14f16_scalar:3714; GFX9: ; %bb.0:3715; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3716; GFX9-NEXT: s_cmp_lg_u32 s23, 03717; GFX9-NEXT: s_cbranch_scc0 .LBB21_33718; GFX9-NEXT: ; %bb.1: ; %cmp.false3719; GFX9-NEXT: s_cbranch_execnz .LBB21_43720; GFX9-NEXT: .LBB21_2: ; %cmp.true3721; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]3722; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]3723; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]3724; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]3725; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]3726; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]3727; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]3728; GFX9-NEXT: s_setpc_b64 s[30:31]3729; GFX9-NEXT: .LBB21_3:3730; GFX9-NEXT: s_branch .LBB21_23731; GFX9-NEXT: .LBB21_4:3732; GFX9-NEXT: v_mov_b32_e32 v0, s163733; GFX9-NEXT: v_mov_b32_e32 v1, s173734; GFX9-NEXT: v_mov_b32_e32 v2, s183735; GFX9-NEXT: v_mov_b32_e32 v3, s193736; GFX9-NEXT: v_mov_b32_e32 v4, s203737; GFX9-NEXT: v_mov_b32_e32 v5, s213738; GFX9-NEXT: v_mov_b32_e32 v6, s223739; GFX9-NEXT: v_mov_b32_e32 v7, s233740; GFX9-NEXT: s_setpc_b64 s[30:31]3741;3742; GFX11-LABEL: bitcast_v14i16_to_v14f16_scalar:3743; GFX11: ; %bb.0:3744; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3745; GFX11-NEXT: s_mov_b32 s6, s183746; GFX11-NEXT: s_mov_b32 s5, s173747; GFX11-NEXT: s_mov_b32 s4, s163748; GFX11-NEXT: s_cmp_lg_u32 s19, 03749; GFX11-NEXT: s_mov_b32 s8, 03750; GFX11-NEXT: s_cbranch_scc0 .LBB21_33751; GFX11-NEXT: ; %bb.1: ; %Flow3752; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s83753; GFX11-NEXT: s_cbranch_vccnz .LBB21_43754; GFX11-NEXT: .LBB21_2: ; %cmp.true3755; GFX11-NEXT: v_pk_add_u16 v6, s6, 3 op_sel_hi:[1,0]3756; GFX11-NEXT: v_pk_add_u16 v5, s5, 3 op_sel_hi:[1,0]3757; GFX11-NEXT: v_pk_add_u16 v4, s4, 3 op_sel_hi:[1,0]3758; GFX11-NEXT: v_pk_add_u16 v3, s3, 3 op_sel_hi:[1,0]3759; GFX11-NEXT: v_pk_add_u16 v2, s2, 3 op_sel_hi:[1,0]3760; GFX11-NEXT: v_pk_add_u16 v1, s1, 3 op_sel_hi:[1,0]3761; GFX11-NEXT: v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]3762; GFX11-NEXT: s_setpc_b64 s[30:31]3763; GFX11-NEXT: .LBB21_3:3764; GFX11-NEXT: s_branch .LBB21_23765; GFX11-NEXT: .LBB21_4:3766; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s13767; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s33768; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s53769; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s73770; GFX11-NEXT: s_setpc_b64 s[30:31]3771 %cmp = icmp eq i32 %b, 03772 br i1 %cmp, label %cmp.true, label %cmp.false3773 3774cmp.true:3775 %a1 = add <14 x i16> %a, splat (i16 3)3776 %a2 = bitcast <14 x i16> %a1 to <14 x half>3777 br label %end3778 3779cmp.false:3780 %a3 = bitcast <14 x i16> %a to <14 x half>3781 br label %end3782 3783end:3784 %phi = phi <14 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3785 ret <14 x half> %phi3786}3787 3788define <14 x i16> @bitcast_v14f16_to_v14i16(<14 x half> %a, i32 %b) {3789; SI-LABEL: bitcast_v14f16_to_v14i16:3790; SI: ; %bb.0:3791; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3792; SI-NEXT: v_cvt_f16_f32_e32 v0, v03793; SI-NEXT: v_cvt_f16_f32_e32 v1, v13794; SI-NEXT: v_cvt_f16_f32_e32 v2, v23795; SI-NEXT: v_cvt_f16_f32_e32 v3, v33796; SI-NEXT: v_cvt_f16_f32_e32 v4, v43797; SI-NEXT: v_cvt_f16_f32_e32 v5, v53798; SI-NEXT: v_cvt_f16_f32_e32 v6, v63799; SI-NEXT: v_cvt_f16_f32_e32 v7, v73800; SI-NEXT: v_cvt_f16_f32_e32 v8, v83801; SI-NEXT: v_cvt_f16_f32_e32 v9, v93802; SI-NEXT: v_cvt_f16_f32_e32 v10, v103803; SI-NEXT: v_cvt_f16_f32_e32 v11, v113804; SI-NEXT: v_cvt_f16_f32_e32 v12, v123805; SI-NEXT: v_cvt_f16_f32_e32 v13, v133806; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v143807; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3808; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3809; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3810; SI-NEXT: s_cbranch_execz .LBB22_23811; SI-NEXT: ; %bb.1: ; %cmp.true3812; SI-NEXT: v_cvt_f32_f16_e32 v13, v133813; SI-NEXT: v_cvt_f32_f16_e32 v12, v123814; SI-NEXT: v_cvt_f32_f16_e32 v11, v113815; SI-NEXT: v_cvt_f32_f16_e32 v10, v103816; SI-NEXT: v_cvt_f32_f16_e32 v7, v73817; SI-NEXT: v_cvt_f32_f16_e32 v6, v63818; SI-NEXT: v_cvt_f32_f16_e32 v3, v33819; SI-NEXT: v_cvt_f32_f16_e32 v1, v13820; SI-NEXT: v_cvt_f32_f16_e32 v5, v53821; SI-NEXT: v_cvt_f32_f16_e32 v9, v93822; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v133823; SI-NEXT: v_cvt_f32_f16_e32 v2, v23824; SI-NEXT: v_cvt_f32_f16_e32 v0, v03825; SI-NEXT: v_cvt_f32_f16_e32 v4, v43826; SI-NEXT: v_cvt_f32_f16_e32 v8, v83827; SI-NEXT: v_cvt_f16_f32_e32 v13, v133828; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v123829; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v113830; SI-NEXT: v_cvt_f16_f32_e32 v12, v123831; SI-NEXT: v_cvt_f16_f32_e32 v11, v113832; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103833; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73834; SI-NEXT: v_cvt_f16_f32_e32 v10, v103835; SI-NEXT: v_cvt_f16_f32_e32 v7, v73836; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63837; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33838; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13839; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53840; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93841; SI-NEXT: v_cvt_f16_f32_e32 v6, v63842; SI-NEXT: v_cvt_f16_f32_e32 v3, v33843; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23844; SI-NEXT: v_cvt_f16_f32_e32 v1, v13845; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03846; SI-NEXT: v_cvt_f16_f32_e32 v5, v53847; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43848; SI-NEXT: v_cvt_f16_f32_e32 v9, v93849; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83850; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v133851; SI-NEXT: v_cvt_f16_f32_e32 v2, v23852; SI-NEXT: v_cvt_f16_f32_e32 v0, v03853; SI-NEXT: v_cvt_f16_f32_e32 v4, v43854; SI-NEXT: v_cvt_f16_f32_e32 v8, v83855; SI-NEXT: v_or_b32_e32 v12, v12, v143856; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v113857; SI-NEXT: v_or_b32_e32 v10, v10, v143858; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v73859; SI-NEXT: v_or_b32_e32 v6, v6, v143860; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v33861; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v13862; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53863; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v93864; SI-NEXT: v_or_b32_e32 v2, v2, v143865; SI-NEXT: v_or_b32_e32 v0, v0, v13866; SI-NEXT: v_or_b32_e32 v4, v4, v53867; SI-NEXT: v_or_b32_e32 v8, v8, v93868; SI-NEXT: v_alignbit_b32 v1, v2, v1, 163869; SI-NEXT: v_alignbit_b32 v5, v6, v5, 163870; SI-NEXT: v_alignbit_b32 v9, v10, v9, 163871; SI-NEXT: .LBB22_2: ; %end3872; SI-NEXT: s_or_b64 exec, exec, s[4:5]3873; SI-NEXT: s_setpc_b64 s[30:31]3874;3875; VI-LABEL: bitcast_v14f16_to_v14i16:3876; VI: ; %bb.0:3877; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3878; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73879; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3880; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3881; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3882; VI-NEXT: s_cbranch_execz .LBB22_23883; VI-NEXT: ; %bb.1: ; %cmp.true3884; VI-NEXT: v_mov_b32_e32 v8, 0x2003885; VI-NEXT: v_add_f16_e32 v7, 0x200, v03886; VI-NEXT: v_add_f16_sdwa v0, v0, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3887; VI-NEXT: v_add_f16_e32 v9, 0x200, v13888; VI-NEXT: v_add_f16_sdwa v1, v1, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3889; VI-NEXT: v_add_f16_e32 v10, 0x200, v23890; VI-NEXT: v_add_f16_sdwa v2, v2, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3891; VI-NEXT: v_add_f16_e32 v11, 0x200, v33892; VI-NEXT: v_add_f16_sdwa v3, v3, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3893; VI-NEXT: v_add_f16_e32 v12, 0x200, v43894; VI-NEXT: v_add_f16_sdwa v4, v4, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3895; VI-NEXT: v_add_f16_e32 v13, 0x200, v53896; VI-NEXT: v_add_f16_sdwa v5, v5, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3897; VI-NEXT: v_add_f16_e32 v14, 0x200, v63898; VI-NEXT: v_add_f16_sdwa v6, v6, v8 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3899; VI-NEXT: v_or_b32_e32 v6, v14, v63900; VI-NEXT: v_or_b32_e32 v5, v13, v53901; VI-NEXT: v_or_b32_e32 v4, v12, v43902; VI-NEXT: v_or_b32_e32 v3, v11, v33903; VI-NEXT: v_or_b32_e32 v2, v10, v23904; VI-NEXT: v_or_b32_e32 v1, v9, v13905; VI-NEXT: v_or_b32_e32 v0, v7, v03906; VI-NEXT: .LBB22_2: ; %end3907; VI-NEXT: s_or_b64 exec, exec, s[4:5]3908; VI-NEXT: s_setpc_b64 s[30:31]3909;3910; GFX9-LABEL: bitcast_v14f16_to_v14i16:3911; GFX9: ; %bb.0:3912; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3913; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v73914; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3915; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3916; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3917; GFX9-NEXT: ; %bb.1: ; %cmp.true3918; GFX9-NEXT: s_movk_i32 s6, 0x2003919; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]3920; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]3921; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]3922; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]3923; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]3924; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]3925; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3926; GFX9-NEXT: ; %bb.2: ; %end3927; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3928; GFX9-NEXT: s_setpc_b64 s[30:31]3929;3930; GFX11-LABEL: bitcast_v14f16_to_v14i16:3931; GFX11: ; %bb.0:3932; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3933; GFX11-NEXT: s_mov_b32 s0, exec_lo3934; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v73935; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03936; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3937; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03938; GFX11-NEXT: s_cbranch_execz .LBB22_23939; GFX11-NEXT: ; %bb.1: ; %cmp.true3940; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]3941; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]3942; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]3943; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]3944; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]3945; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]3946; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3947; GFX11-NEXT: .LBB22_2: ; %end3948; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03949; GFX11-NEXT: s_setpc_b64 s[30:31]3950 %cmp = icmp eq i32 %b, 03951 br i1 %cmp, label %cmp.true, label %cmp.false3952 3953cmp.true:3954 %a1 = fadd <14 x half> %a, splat (half 0xH0200)3955 %a2 = bitcast <14 x half> %a1 to <14 x i16>3956 br label %end3957 3958cmp.false:3959 %a3 = bitcast <14 x half> %a to <14 x i16>3960 br label %end3961 3962end:3963 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3964 ret <14 x i16> %phi3965}3966 3967define inreg <14 x i16> @bitcast_v14f16_to_v14i16_scalar(<14 x half> inreg %a, i32 inreg %b) {3968; SI-LABEL: bitcast_v14f16_to_v14i16_scalar:3969; SI: ; %bb.0:3970; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3971; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v03972; SI-NEXT: v_cvt_f16_f32_e32 v0, s163973; SI-NEXT: v_cvt_f16_f32_e32 v14, s173974; SI-NEXT: v_cvt_f16_f32_e32 v2, s183975; SI-NEXT: v_cvt_f16_f32_e32 v3, s193976; SI-NEXT: v_cvt_f16_f32_e32 v4, s203977; SI-NEXT: v_cvt_f16_f32_e32 v15, s213978; SI-NEXT: v_cvt_f16_f32_e32 v6, s223979; SI-NEXT: v_cvt_f16_f32_e32 v7, s233980; SI-NEXT: v_cvt_f16_f32_e32 v8, s243981; SI-NEXT: v_cvt_f16_f32_e32 v16, s253982; SI-NEXT: v_cvt_f16_f32_e32 v10, s263983; SI-NEXT: v_cvt_f16_f32_e32 v11, s273984; SI-NEXT: v_cvt_f16_f32_e32 v12, s283985; SI-NEXT: v_cvt_f16_f32_e32 v13, s293986; SI-NEXT: s_and_b64 s[4:5], vcc, exec3987; SI-NEXT: s_cbranch_scc0 .LBB23_43988; SI-NEXT: ; %bb.1: ; %cmp.false3989; SI-NEXT: s_cbranch_execnz .LBB23_33990; SI-NEXT: .LBB23_2: ; %cmp.true3991; SI-NEXT: v_cvt_f32_f16_e32 v13, v133992; SI-NEXT: v_cvt_f32_f16_e32 v12, v123993; SI-NEXT: v_cvt_f32_f16_e32 v11, v113994; SI-NEXT: v_cvt_f32_f16_e32 v10, v103995; SI-NEXT: v_cvt_f32_f16_e32 v7, v73996; SI-NEXT: v_cvt_f32_f16_e32 v6, v63997; SI-NEXT: v_cvt_f32_f16_e32 v3, v33998; SI-NEXT: v_cvt_f32_f16_e32 v1, v143999; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v134000; SI-NEXT: v_cvt_f32_f16_e32 v2, v24001; SI-NEXT: v_cvt_f32_f16_e32 v5, v154002; SI-NEXT: v_cvt_f16_f32_e32 v13, v134003; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v124004; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v114005; SI-NEXT: v_cvt_f32_f16_e32 v9, v164006; SI-NEXT: v_cvt_f16_f32_e32 v12, v124007; SI-NEXT: v_cvt_f16_f32_e32 v11, v114008; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v104009; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v74010; SI-NEXT: v_cvt_f16_f32_e32 v10, v104011; SI-NEXT: v_cvt_f16_f32_e32 v7, v74012; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v64013; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v34014; SI-NEXT: v_cvt_f32_f16_e32 v0, v04015; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14016; SI-NEXT: v_cvt_f32_f16_e32 v4, v44017; SI-NEXT: v_cvt_f32_f16_e32 v8, v84018; SI-NEXT: v_cvt_f16_f32_e32 v6, v64019; SI-NEXT: v_cvt_f16_f32_e32 v3, v34020; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24021; SI-NEXT: v_cvt_f16_f32_e32 v1, v14022; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v54023; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v134024; SI-NEXT: v_cvt_f16_f32_e32 v2, v24025; SI-NEXT: v_cvt_f16_f32_e32 v5, v54026; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v94027; SI-NEXT: v_or_b32_e32 v12, v12, v144028; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v114029; SI-NEXT: v_cvt_f16_f32_e32 v9, v94030; SI-NEXT: v_or_b32_e32 v10, v10, v144031; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v74032; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v04033; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44034; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v84035; SI-NEXT: v_or_b32_e32 v6, v6, v144036; SI-NEXT: v_lshlrev_b32_e32 v14, 16, v34037; SI-NEXT: v_cvt_f16_f32_e32 v0, v04038; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14039; SI-NEXT: v_cvt_f16_f32_e32 v4, v44040; SI-NEXT: v_cvt_f16_f32_e32 v8, v84041; SI-NEXT: v_or_b32_e32 v2, v2, v144042; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54043; SI-NEXT: v_lshr_b64 v[14:15], v[1:2], 164044; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v94045; SI-NEXT: v_lshr_b64 v[15:16], v[5:6], 164046; SI-NEXT: v_lshr_b64 v[16:17], v[9:10], 164047; SI-NEXT: v_or_b32_e32 v0, v0, v14048; SI-NEXT: v_or_b32_e32 v4, v4, v54049; SI-NEXT: v_or_b32_e32 v8, v8, v94050; SI-NEXT: .LBB23_3: ; %end4051; SI-NEXT: v_mov_b32_e32 v1, v144052; SI-NEXT: v_mov_b32_e32 v5, v154053; SI-NEXT: v_mov_b32_e32 v9, v164054; SI-NEXT: s_setpc_b64 s[30:31]4055; SI-NEXT: .LBB23_4:4056; SI-NEXT: s_branch .LBB23_24057;4058; VI-LABEL: bitcast_v14f16_to_v14i16_scalar:4059; VI: ; %bb.0:4060; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4061; VI-NEXT: s_cmp_lg_u32 s23, 04062; VI-NEXT: s_cbranch_scc0 .LBB23_34063; VI-NEXT: ; %bb.1: ; %cmp.false4064; VI-NEXT: s_cbranch_execnz .LBB23_44065; VI-NEXT: .LBB23_2: ; %cmp.true4066; VI-NEXT: s_lshr_b32 s4, s16, 164067; VI-NEXT: v_mov_b32_e32 v1, s44068; VI-NEXT: s_lshr_b32 s4, s17, 164069; VI-NEXT: v_mov_b32_e32 v2, s44070; VI-NEXT: s_lshr_b32 s4, s18, 164071; VI-NEXT: v_mov_b32_e32 v3, s44072; VI-NEXT: s_lshr_b32 s4, s19, 164073; VI-NEXT: v_mov_b32_e32 v4, s44074; VI-NEXT: s_lshr_b32 s4, s20, 164075; VI-NEXT: v_mov_b32_e32 v5, s44076; VI-NEXT: s_lshr_b32 s4, s21, 164077; VI-NEXT: v_mov_b32_e32 v6, s44078; VI-NEXT: s_lshr_b32 s4, s22, 164079; VI-NEXT: v_mov_b32_e32 v0, 0x2004080; VI-NEXT: v_mov_b32_e32 v14, s44081; VI-NEXT: v_add_f16_e32 v7, s16, v04082; VI-NEXT: v_add_f16_sdwa v8, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4083; VI-NEXT: v_add_f16_e32 v1, s17, v04084; VI-NEXT: v_add_f16_sdwa v9, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4085; VI-NEXT: v_add_f16_e32 v2, s18, v04086; VI-NEXT: v_add_f16_sdwa v10, v3, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4087; VI-NEXT: v_add_f16_e32 v3, s19, v04088; VI-NEXT: v_add_f16_sdwa v11, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4089; VI-NEXT: v_add_f16_e32 v4, s20, v04090; VI-NEXT: v_add_f16_sdwa v12, v5, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4091; VI-NEXT: v_add_f16_e32 v5, s21, v04092; VI-NEXT: v_add_f16_sdwa v13, v6, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4093; VI-NEXT: v_add_f16_e32 v6, s22, v04094; VI-NEXT: v_add_f16_sdwa v0, v14, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4095; VI-NEXT: v_or_b32_e32 v6, v6, v04096; VI-NEXT: v_or_b32_e32 v5, v5, v134097; VI-NEXT: v_or_b32_e32 v4, v4, v124098; VI-NEXT: v_or_b32_e32 v3, v3, v114099; VI-NEXT: v_or_b32_e32 v2, v2, v104100; VI-NEXT: v_or_b32_e32 v1, v1, v94101; VI-NEXT: v_or_b32_e32 v0, v7, v84102; VI-NEXT: s_setpc_b64 s[30:31]4103; VI-NEXT: .LBB23_3:4104; VI-NEXT: s_branch .LBB23_24105; VI-NEXT: .LBB23_4:4106; VI-NEXT: v_mov_b32_e32 v0, s164107; VI-NEXT: v_mov_b32_e32 v1, s174108; VI-NEXT: v_mov_b32_e32 v2, s184109; VI-NEXT: v_mov_b32_e32 v3, s194110; VI-NEXT: v_mov_b32_e32 v4, s204111; VI-NEXT: v_mov_b32_e32 v5, s214112; VI-NEXT: v_mov_b32_e32 v6, s224113; VI-NEXT: v_mov_b32_e32 v7, s234114; VI-NEXT: s_setpc_b64 s[30:31]4115;4116; GFX9-LABEL: bitcast_v14f16_to_v14i16_scalar:4117; GFX9: ; %bb.0:4118; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4119; GFX9-NEXT: s_cmp_lg_u32 s23, 04120; GFX9-NEXT: s_cbranch_scc0 .LBB23_34121; GFX9-NEXT: ; %bb.1: ; %cmp.false4122; GFX9-NEXT: s_cbranch_execnz .LBB23_44123; GFX9-NEXT: .LBB23_2: ; %cmp.true4124; GFX9-NEXT: v_mov_b32_e32 v0, 0x2004125; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]4126; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]4127; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]4128; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]4129; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]4130; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4131; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4132; GFX9-NEXT: s_setpc_b64 s[30:31]4133; GFX9-NEXT: .LBB23_3:4134; GFX9-NEXT: s_branch .LBB23_24135; GFX9-NEXT: .LBB23_4:4136; GFX9-NEXT: v_mov_b32_e32 v0, s164137; GFX9-NEXT: v_mov_b32_e32 v1, s174138; GFX9-NEXT: v_mov_b32_e32 v2, s184139; GFX9-NEXT: v_mov_b32_e32 v3, s194140; GFX9-NEXT: v_mov_b32_e32 v4, s204141; GFX9-NEXT: v_mov_b32_e32 v5, s214142; GFX9-NEXT: v_mov_b32_e32 v6, s224143; GFX9-NEXT: v_mov_b32_e32 v7, s234144; GFX9-NEXT: s_setpc_b64 s[30:31]4145;4146; GFX11-LABEL: bitcast_v14f16_to_v14i16_scalar:4147; GFX11: ; %bb.0:4148; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4149; GFX11-NEXT: s_mov_b32 s6, s184150; GFX11-NEXT: s_mov_b32 s5, s174151; GFX11-NEXT: s_mov_b32 s4, s164152; GFX11-NEXT: s_cmp_lg_u32 s19, 04153; GFX11-NEXT: s_mov_b32 s8, 04154; GFX11-NEXT: s_cbranch_scc0 .LBB23_34155; GFX11-NEXT: ; %bb.1: ; %Flow4156; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s84157; GFX11-NEXT: s_cbranch_vccnz .LBB23_44158; GFX11-NEXT: .LBB23_2: ; %cmp.true4159; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s6 op_sel_hi:[0,1]4160; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s5 op_sel_hi:[0,1]4161; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s4 op_sel_hi:[0,1]4162; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s3 op_sel_hi:[0,1]4163; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s2 op_sel_hi:[0,1]4164; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s1 op_sel_hi:[0,1]4165; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]4166; GFX11-NEXT: s_setpc_b64 s[30:31]4167; GFX11-NEXT: .LBB23_3:4168; GFX11-NEXT: s_branch .LBB23_24169; GFX11-NEXT: .LBB23_4:4170; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s14171; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s34172; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s54173; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s74174; GFX11-NEXT: s_setpc_b64 s[30:31]4175 %cmp = icmp eq i32 %b, 04176 br i1 %cmp, label %cmp.true, label %cmp.false4177 4178cmp.true:4179 %a1 = fadd <14 x half> %a, splat (half 0xH0200)4180 %a2 = bitcast <14 x half> %a1 to <14 x i16>4181 br label %end4182 4183cmp.false:4184 %a3 = bitcast <14 x half> %a to <14 x i16>4185 br label %end4186 4187end:4188 %phi = phi <14 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4189 ret <14 x i16> %phi4190}4191;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:4192; GFX11-FAKE16: {{.*}}4193; GFX11-TRUE16: {{.*}}4194