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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define <9 x float> @bitcast_v9i32_to_v9f32(<9 x i32> %a, i32 %b) {10; SI-LABEL: bitcast_v9i32_to_v9f32:11; SI: ; %bb.0:12; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v914; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT: ; %bb.1: ; %cmp.true18; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v819; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v720; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v621; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v522; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v423; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v324; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v225; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v126; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v027; SI-NEXT: ; %bb.2: ; %end28; SI-NEXT: s_or_b64 exec, exec, s[4:5]29; SI-NEXT: s_setpc_b64 s[30:31]30;31; VI-LABEL: bitcast_v9i32_to_v9f32:32; VI: ; %bb.0:33; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)34; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v935; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc36; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]37; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]38; VI-NEXT: ; %bb.1: ; %cmp.true39; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v840; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v741; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v642; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v543; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v444; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v345; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v246; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v147; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v048; VI-NEXT: ; %bb.2: ; %end49; VI-NEXT: s_or_b64 exec, exec, s[4:5]50; VI-NEXT: s_setpc_b64 s[30:31]51;52; GFX9-LABEL: bitcast_v9i32_to_v9f32:53; GFX9: ; %bb.0:54; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)55; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v956; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc57; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]58; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]59; GFX9-NEXT: ; %bb.1: ; %cmp.true60; GFX9-NEXT: v_add_u32_e32 v8, 3, v861; GFX9-NEXT: v_add_u32_e32 v7, 3, v762; GFX9-NEXT: v_add_u32_e32 v6, 3, v663; GFX9-NEXT: v_add_u32_e32 v5, 3, v564; GFX9-NEXT: v_add_u32_e32 v4, 3, v465; GFX9-NEXT: v_add_u32_e32 v3, 3, v366; GFX9-NEXT: v_add_u32_e32 v2, 3, v267; GFX9-NEXT: v_add_u32_e32 v1, 3, v168; GFX9-NEXT: v_add_u32_e32 v0, 3, v069; GFX9-NEXT: ; %bb.2: ; %end70; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]71; GFX9-NEXT: s_setpc_b64 s[30:31]72;73; GFX11-LABEL: bitcast_v9i32_to_v9f32:74; GFX11: ; %bb.0:75; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; GFX11-NEXT: s_mov_b32 s0, exec_lo77; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v978; GFX11-NEXT: s_xor_b32 s0, exec_lo, s079; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)80; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s081; GFX11-NEXT: s_cbranch_execz .LBB0_282; GFX11-NEXT: ; %bb.1: ; %cmp.true83; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v884; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v785; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v686; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v587; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v488; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v389; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v290; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v191; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v092; GFX11-NEXT: .LBB0_2: ; %end93; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s094; GFX11-NEXT: s_setpc_b64 s[30:31]95 %cmp = icmp eq i32 %b, 096 br i1 %cmp, label %cmp.true, label %cmp.false97 98cmp.true:99 %a1 = add <9 x i32> %a, splat (i32 3)100 %a2 = bitcast <9 x i32> %a1 to <9 x float>101 br label %end102 103cmp.false:104 %a3 = bitcast <9 x i32> %a to <9 x float>105 br label %end106 107end:108 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]109 ret <9 x float> %phi110}111 112define inreg <9 x float> @bitcast_v9i32_to_v9f32_scalar(<9 x i32> inreg %a, i32 inreg %b) {113; SI-LABEL: bitcast_v9i32_to_v9f32_scalar:114; SI: ; %bb.0:115; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)116; SI-NEXT: s_cmp_lg_u32 s25, 0117; SI-NEXT: s_cbranch_scc0 .LBB1_4118; SI-NEXT: ; %bb.1: ; %cmp.false119; SI-NEXT: s_cbranch_execnz .LBB1_3120; SI-NEXT: .LBB1_2: ; %cmp.true121; SI-NEXT: s_add_i32 s24, s24, 3122; SI-NEXT: s_add_i32 s23, s23, 3123; SI-NEXT: s_add_i32 s22, s22, 3124; SI-NEXT: s_add_i32 s21, s21, 3125; SI-NEXT: s_add_i32 s20, s20, 3126; SI-NEXT: s_add_i32 s19, s19, 3127; SI-NEXT: s_add_i32 s18, s18, 3128; SI-NEXT: s_add_i32 s17, s17, 3129; SI-NEXT: s_add_i32 s16, s16, 3130; SI-NEXT: .LBB1_3: ; %end131; SI-NEXT: v_mov_b32_e32 v0, s16132; SI-NEXT: v_mov_b32_e32 v1, s17133; SI-NEXT: v_mov_b32_e32 v2, s18134; SI-NEXT: v_mov_b32_e32 v3, s19135; SI-NEXT: v_mov_b32_e32 v4, s20136; SI-NEXT: v_mov_b32_e32 v5, s21137; SI-NEXT: v_mov_b32_e32 v6, s22138; SI-NEXT: v_mov_b32_e32 v7, s23139; SI-NEXT: v_mov_b32_e32 v8, s24140; SI-NEXT: s_setpc_b64 s[30:31]141; SI-NEXT: .LBB1_4:142; SI-NEXT: s_branch .LBB1_2143;144; VI-LABEL: bitcast_v9i32_to_v9f32_scalar:145; VI: ; %bb.0:146; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)147; VI-NEXT: s_cmp_lg_u32 s25, 0148; VI-NEXT: s_cbranch_scc0 .LBB1_4149; VI-NEXT: ; %bb.1: ; %cmp.false150; VI-NEXT: s_cbranch_execnz .LBB1_3151; VI-NEXT: .LBB1_2: ; %cmp.true152; VI-NEXT: s_add_i32 s24, s24, 3153; VI-NEXT: s_add_i32 s23, s23, 3154; VI-NEXT: s_add_i32 s22, s22, 3155; VI-NEXT: s_add_i32 s21, s21, 3156; VI-NEXT: s_add_i32 s20, s20, 3157; VI-NEXT: s_add_i32 s19, s19, 3158; VI-NEXT: s_add_i32 s18, s18, 3159; VI-NEXT: s_add_i32 s17, s17, 3160; VI-NEXT: s_add_i32 s16, s16, 3161; VI-NEXT: .LBB1_3: ; %end162; VI-NEXT: v_mov_b32_e32 v0, s16163; VI-NEXT: v_mov_b32_e32 v1, s17164; VI-NEXT: v_mov_b32_e32 v2, s18165; VI-NEXT: v_mov_b32_e32 v3, s19166; VI-NEXT: v_mov_b32_e32 v4, s20167; VI-NEXT: v_mov_b32_e32 v5, s21168; VI-NEXT: v_mov_b32_e32 v6, s22169; VI-NEXT: v_mov_b32_e32 v7, s23170; VI-NEXT: v_mov_b32_e32 v8, s24171; VI-NEXT: s_setpc_b64 s[30:31]172; VI-NEXT: .LBB1_4:173; VI-NEXT: s_branch .LBB1_2174;175; GFX9-LABEL: bitcast_v9i32_to_v9f32_scalar:176; GFX9: ; %bb.0:177; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)178; GFX9-NEXT: s_cmp_lg_u32 s25, 0179; GFX9-NEXT: s_cbranch_scc0 .LBB1_4180; GFX9-NEXT: ; %bb.1: ; %cmp.false181; GFX9-NEXT: s_cbranch_execnz .LBB1_3182; GFX9-NEXT: .LBB1_2: ; %cmp.true183; GFX9-NEXT: s_add_i32 s24, s24, 3184; GFX9-NEXT: s_add_i32 s23, s23, 3185; GFX9-NEXT: s_add_i32 s22, s22, 3186; GFX9-NEXT: s_add_i32 s21, s21, 3187; GFX9-NEXT: s_add_i32 s20, s20, 3188; GFX9-NEXT: s_add_i32 s19, s19, 3189; GFX9-NEXT: s_add_i32 s18, s18, 3190; GFX9-NEXT: s_add_i32 s17, s17, 3191; GFX9-NEXT: s_add_i32 s16, s16, 3192; GFX9-NEXT: .LBB1_3: ; %end193; GFX9-NEXT: v_mov_b32_e32 v0, s16194; GFX9-NEXT: v_mov_b32_e32 v1, s17195; GFX9-NEXT: v_mov_b32_e32 v2, s18196; GFX9-NEXT: v_mov_b32_e32 v3, s19197; GFX9-NEXT: v_mov_b32_e32 v4, s20198; GFX9-NEXT: v_mov_b32_e32 v5, s21199; GFX9-NEXT: v_mov_b32_e32 v6, s22200; GFX9-NEXT: v_mov_b32_e32 v7, s23201; GFX9-NEXT: v_mov_b32_e32 v8, s24202; GFX9-NEXT: s_setpc_b64 s[30:31]203; GFX9-NEXT: .LBB1_4:204; GFX9-NEXT: s_branch .LBB1_2205;206; GFX11-LABEL: bitcast_v9i32_to_v9f32_scalar:207; GFX11: ; %bb.0:208; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)209; GFX11-NEXT: s_cmp_lg_u32 s21, 0210; GFX11-NEXT: s_mov_b32 s4, 0211; GFX11-NEXT: s_cbranch_scc0 .LBB1_4212; GFX11-NEXT: ; %bb.1: ; %Flow213; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4214; GFX11-NEXT: s_cbranch_vccnz .LBB1_3215; GFX11-NEXT: .LBB1_2: ; %cmp.true216; GFX11-NEXT: s_add_i32 s20, s20, 3217; GFX11-NEXT: s_add_i32 s19, s19, 3218; GFX11-NEXT: s_add_i32 s18, s18, 3219; GFX11-NEXT: s_add_i32 s17, s17, 3220; GFX11-NEXT: s_add_i32 s16, s16, 3221; GFX11-NEXT: s_add_i32 s3, s3, 3222; GFX11-NEXT: s_add_i32 s2, s2, 3223; GFX11-NEXT: s_add_i32 s1, s1, 3224; GFX11-NEXT: s_add_i32 s0, s0, 3225; GFX11-NEXT: .LBB1_3: ; %end226; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)227; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1228; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3229; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17230; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19231; GFX11-NEXT: v_mov_b32_e32 v8, s20232; GFX11-NEXT: s_setpc_b64 s[30:31]233; GFX11-NEXT: .LBB1_4:234; GFX11-NEXT: s_branch .LBB1_2235 %cmp = icmp eq i32 %b, 0236 br i1 %cmp, label %cmp.true, label %cmp.false237 238cmp.true:239 %a1 = add <9 x i32> %a, splat (i32 3)240 %a2 = bitcast <9 x i32> %a1 to <9 x float>241 br label %end242 243cmp.false:244 %a3 = bitcast <9 x i32> %a to <9 x float>245 br label %end246 247end:248 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]249 ret <9 x float> %phi250}251 252define <9 x i32> @bitcast_v9f32_to_v9i32(<9 x float> %a, i32 %b) {253; SI-LABEL: bitcast_v9f32_to_v9i32:254; SI: ; %bb.0:255; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)256; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9257; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc258; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]259; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]260; SI-NEXT: ; %bb.1: ; %cmp.true261; SI-NEXT: v_add_f32_e32 v8, 1.0, v8262; SI-NEXT: v_add_f32_e32 v7, 1.0, v7263; SI-NEXT: v_add_f32_e32 v6, 1.0, v6264; SI-NEXT: v_add_f32_e32 v5, 1.0, v5265; SI-NEXT: v_add_f32_e32 v4, 1.0, v4266; SI-NEXT: v_add_f32_e32 v3, 1.0, v3267; SI-NEXT: v_add_f32_e32 v2, 1.0, v2268; SI-NEXT: v_add_f32_e32 v1, 1.0, v1269; SI-NEXT: v_add_f32_e32 v0, 1.0, v0270; SI-NEXT: ; %bb.2: ; %end271; SI-NEXT: s_or_b64 exec, exec, s[4:5]272; SI-NEXT: s_setpc_b64 s[30:31]273;274; VI-LABEL: bitcast_v9f32_to_v9i32:275; VI: ; %bb.0:276; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)277; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9278; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc279; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]280; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]281; VI-NEXT: ; %bb.1: ; %cmp.true282; VI-NEXT: v_add_f32_e32 v8, 1.0, v8283; VI-NEXT: v_add_f32_e32 v7, 1.0, v7284; VI-NEXT: v_add_f32_e32 v6, 1.0, v6285; VI-NEXT: v_add_f32_e32 v5, 1.0, v5286; VI-NEXT: v_add_f32_e32 v4, 1.0, v4287; VI-NEXT: v_add_f32_e32 v3, 1.0, v3288; VI-NEXT: v_add_f32_e32 v2, 1.0, v2289; VI-NEXT: v_add_f32_e32 v1, 1.0, v1290; VI-NEXT: v_add_f32_e32 v0, 1.0, v0291; VI-NEXT: ; %bb.2: ; %end292; VI-NEXT: s_or_b64 exec, exec, s[4:5]293; VI-NEXT: s_setpc_b64 s[30:31]294;295; GFX9-LABEL: bitcast_v9f32_to_v9i32:296; GFX9: ; %bb.0:297; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)298; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9299; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc300; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]301; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]302; GFX9-NEXT: ; %bb.1: ; %cmp.true303; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v8304; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v7305; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v6306; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v5307; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v4308; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v3309; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v2310; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v1311; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v0312; GFX9-NEXT: ; %bb.2: ; %end313; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]314; GFX9-NEXT: s_setpc_b64 s[30:31]315;316; GFX11-LABEL: bitcast_v9f32_to_v9i32:317; GFX11: ; %bb.0:318; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)319; GFX11-NEXT: s_mov_b32 s0, exec_lo320; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9321; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0322; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)323; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0324; GFX11-NEXT: ; %bb.1: ; %cmp.true325; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v7326; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v5327; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v3328; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v1329; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0330; GFX11-NEXT: ; %bb.2: ; %end331; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0332; GFX11-NEXT: s_setpc_b64 s[30:31]333 %cmp = icmp eq i32 %b, 0334 br i1 %cmp, label %cmp.true, label %cmp.false335 336cmp.true:337 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)338 %a2 = bitcast <9 x float> %a1 to <9 x i32>339 br label %end340 341cmp.false:342 %a3 = bitcast <9 x float> %a to <9 x i32>343 br label %end344 345end:346 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]347 ret <9 x i32> %phi348}349 350define inreg <9 x i32> @bitcast_v9f32_to_v9i32_scalar(<9 x float> inreg %a, i32 inreg %b) {351; SI-LABEL: bitcast_v9f32_to_v9i32_scalar:352; SI: ; %bb.0:353; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; SI-NEXT: s_cmp_lg_u32 s25, 0355; SI-NEXT: s_cbranch_scc0 .LBB3_3356; SI-NEXT: ; %bb.1: ; %cmp.false357; SI-NEXT: s_cbranch_execnz .LBB3_4358; SI-NEXT: .LBB3_2: ; %cmp.true359; SI-NEXT: v_add_f32_e64 v8, s24, 1.0360; SI-NEXT: v_add_f32_e64 v7, s23, 1.0361; SI-NEXT: v_add_f32_e64 v6, s22, 1.0362; SI-NEXT: v_add_f32_e64 v5, s21, 1.0363; SI-NEXT: v_add_f32_e64 v4, s20, 1.0364; SI-NEXT: v_add_f32_e64 v3, s19, 1.0365; SI-NEXT: v_add_f32_e64 v2, s18, 1.0366; SI-NEXT: v_add_f32_e64 v1, s17, 1.0367; SI-NEXT: v_add_f32_e64 v0, s16, 1.0368; SI-NEXT: s_setpc_b64 s[30:31]369; SI-NEXT: .LBB3_3:370; SI-NEXT: s_branch .LBB3_2371; SI-NEXT: .LBB3_4:372; SI-NEXT: v_mov_b32_e32 v0, s16373; SI-NEXT: v_mov_b32_e32 v1, s17374; SI-NEXT: v_mov_b32_e32 v2, s18375; SI-NEXT: v_mov_b32_e32 v3, s19376; SI-NEXT: v_mov_b32_e32 v4, s20377; SI-NEXT: v_mov_b32_e32 v5, s21378; SI-NEXT: v_mov_b32_e32 v6, s22379; SI-NEXT: v_mov_b32_e32 v7, s23380; SI-NEXT: v_mov_b32_e32 v8, s24381; SI-NEXT: s_setpc_b64 s[30:31]382;383; VI-LABEL: bitcast_v9f32_to_v9i32_scalar:384; VI: ; %bb.0:385; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)386; VI-NEXT: s_cmp_lg_u32 s25, 0387; VI-NEXT: s_cbranch_scc0 .LBB3_3388; VI-NEXT: ; %bb.1: ; %cmp.false389; VI-NEXT: s_cbranch_execnz .LBB3_4390; VI-NEXT: .LBB3_2: ; %cmp.true391; VI-NEXT: v_add_f32_e64 v8, s24, 1.0392; VI-NEXT: v_add_f32_e64 v7, s23, 1.0393; VI-NEXT: v_add_f32_e64 v6, s22, 1.0394; VI-NEXT: v_add_f32_e64 v5, s21, 1.0395; VI-NEXT: v_add_f32_e64 v4, s20, 1.0396; VI-NEXT: v_add_f32_e64 v3, s19, 1.0397; VI-NEXT: v_add_f32_e64 v2, s18, 1.0398; VI-NEXT: v_add_f32_e64 v1, s17, 1.0399; VI-NEXT: v_add_f32_e64 v0, s16, 1.0400; VI-NEXT: s_setpc_b64 s[30:31]401; VI-NEXT: .LBB3_3:402; VI-NEXT: s_branch .LBB3_2403; VI-NEXT: .LBB3_4:404; VI-NEXT: v_mov_b32_e32 v0, s16405; VI-NEXT: v_mov_b32_e32 v1, s17406; VI-NEXT: v_mov_b32_e32 v2, s18407; VI-NEXT: v_mov_b32_e32 v3, s19408; VI-NEXT: v_mov_b32_e32 v4, s20409; VI-NEXT: v_mov_b32_e32 v5, s21410; VI-NEXT: v_mov_b32_e32 v6, s22411; VI-NEXT: v_mov_b32_e32 v7, s23412; VI-NEXT: v_mov_b32_e32 v8, s24413; VI-NEXT: s_setpc_b64 s[30:31]414;415; GFX9-LABEL: bitcast_v9f32_to_v9i32_scalar:416; GFX9: ; %bb.0:417; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)418; GFX9-NEXT: s_cmp_lg_u32 s25, 0419; GFX9-NEXT: s_cbranch_scc0 .LBB3_3420; GFX9-NEXT: ; %bb.1: ; %cmp.false421; GFX9-NEXT: s_cbranch_execnz .LBB3_4422; GFX9-NEXT: .LBB3_2: ; %cmp.true423; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.0424; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.0425; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.0426; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.0427; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.0428; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.0429; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.0430; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.0431; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.0432; GFX9-NEXT: s_setpc_b64 s[30:31]433; GFX9-NEXT: .LBB3_3:434; GFX9-NEXT: s_branch .LBB3_2435; GFX9-NEXT: .LBB3_4:436; GFX9-NEXT: v_mov_b32_e32 v0, s16437; GFX9-NEXT: v_mov_b32_e32 v1, s17438; GFX9-NEXT: v_mov_b32_e32 v2, s18439; GFX9-NEXT: v_mov_b32_e32 v3, s19440; GFX9-NEXT: v_mov_b32_e32 v4, s20441; GFX9-NEXT: v_mov_b32_e32 v5, s21442; GFX9-NEXT: v_mov_b32_e32 v6, s22443; GFX9-NEXT: v_mov_b32_e32 v7, s23444; GFX9-NEXT: v_mov_b32_e32 v8, s24445; GFX9-NEXT: s_setpc_b64 s[30:31]446;447; GFX11-LABEL: bitcast_v9f32_to_v9i32_scalar:448; GFX11: ; %bb.0:449; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)450; GFX11-NEXT: s_mov_b32 s15, s3451; GFX11-NEXT: s_mov_b32 s14, s2452; GFX11-NEXT: s_mov_b32 s13, s1453; GFX11-NEXT: s_mov_b32 s12, s0454; GFX11-NEXT: s_cmp_lg_u32 s21, 0455; GFX11-NEXT: s_mov_b32 s0, 0456; GFX11-NEXT: s_cbranch_scc0 .LBB3_3457; GFX11-NEXT: ; %bb.1: ; %Flow458; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s0459; GFX11-NEXT: s_cbranch_vccnz .LBB3_4460; GFX11-NEXT: .LBB3_2: ; %cmp.true461; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.0462; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.0463; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.0464; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.0465; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.0466; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.0467; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.0468; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.0469; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.0470; GFX11-NEXT: s_setpc_b64 s[30:31]471; GFX11-NEXT: .LBB3_3:472; GFX11-NEXT: s_branch .LBB3_2473; GFX11-NEXT: .LBB3_4:474; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s13475; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s15476; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17477; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19478; GFX11-NEXT: v_mov_b32_e32 v8, s20479; GFX11-NEXT: s_setpc_b64 s[30:31]480 %cmp = icmp eq i32 %b, 0481 br i1 %cmp, label %cmp.true, label %cmp.false482 483cmp.true:484 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)485 %a2 = bitcast <9 x float> %a1 to <9 x i32>486 br label %end487 488cmp.false:489 %a3 = bitcast <9 x float> %a to <9 x i32>490 br label %end491 492end:493 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]494 ret <9 x i32> %phi495}496 497define <18 x i16> @bitcast_v9i32_to_v18i16(<9 x i32> %a, i32 %b) {498; SI-LABEL: bitcast_v9i32_to_v18i16:499; SI: ; %bb.0:500; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)501; SI-NEXT: v_mov_b32_e32 v16, v8502; SI-NEXT: v_mov_b32_e32 v14, v7503; SI-NEXT: v_mov_b32_e32 v12, v6504; SI-NEXT: v_mov_b32_e32 v10, v5505; SI-NEXT: v_mov_b32_e32 v8, v4506; SI-NEXT: v_mov_b32_e32 v6, v3507; SI-NEXT: v_mov_b32_e32 v4, v2508; SI-NEXT: v_mov_b32_e32 v2, v1509; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9510; SI-NEXT: ; implicit-def: $vgpr1511; SI-NEXT: ; implicit-def: $vgpr3512; SI-NEXT: ; implicit-def: $vgpr5513; SI-NEXT: ; implicit-def: $vgpr7514; SI-NEXT: ; implicit-def: $vgpr9515; SI-NEXT: ; implicit-def: $vgpr11516; SI-NEXT: ; implicit-def: $vgpr13517; SI-NEXT: ; implicit-def: $vgpr15518; SI-NEXT: ; implicit-def: $vgpr17519; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc520; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]521; SI-NEXT: s_cbranch_execnz .LBB4_3522; SI-NEXT: ; %bb.1: ; %Flow523; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]524; SI-NEXT: s_cbranch_execnz .LBB4_4525; SI-NEXT: .LBB4_2: ; %end526; SI-NEXT: s_or_b64 exec, exec, s[4:5]527; SI-NEXT: s_setpc_b64 s[30:31]528; SI-NEXT: .LBB4_3: ; %cmp.false529; SI-NEXT: v_alignbit_b32 v17, v0, v16, 16530; SI-NEXT: v_alignbit_b32 v13, v14, v12, 16531; SI-NEXT: v_alignbit_b32 v9, v10, v8, 16532; SI-NEXT: v_alignbit_b32 v5, v6, v4, 16533; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16534; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14535; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10536; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6537; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2538; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]539; SI-NEXT: s_cbranch_execz .LBB4_2540; SI-NEXT: .LBB4_4: ; %cmp.true541; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v16542; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v2543; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v0544; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v6545; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v4546; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v10547; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v8548; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v14549; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v12550; SI-NEXT: v_alignbit_b32 v13, v14, v12, 16551; SI-NEXT: v_alignbit_b32 v9, v10, v8, 16552; SI-NEXT: v_alignbit_b32 v5, v6, v4, 16553; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16554; SI-NEXT: v_alignbit_b32 v17, v0, v16, 16555; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v14556; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v10557; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v6558; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2559; SI-NEXT: s_or_b64 exec, exec, s[4:5]560; SI-NEXT: s_setpc_b64 s[30:31]561;562; VI-LABEL: bitcast_v9i32_to_v18i16:563; VI: ; %bb.0:564; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)565; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9566; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc567; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]568; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]569; VI-NEXT: ; %bb.1: ; %cmp.true570; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v8571; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v7572; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v6573; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v5574; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v4575; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v3576; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v2577; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v1578; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v0579; VI-NEXT: ; %bb.2: ; %end580; VI-NEXT: s_or_b64 exec, exec, s[4:5]581; VI-NEXT: s_setpc_b64 s[30:31]582;583; GFX9-LABEL: bitcast_v9i32_to_v18i16:584; GFX9: ; %bb.0:585; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)586; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9587; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc588; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]589; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]590; GFX9-NEXT: ; %bb.1: ; %cmp.true591; GFX9-NEXT: v_add_u32_e32 v8, 3, v8592; GFX9-NEXT: v_add_u32_e32 v7, 3, v7593; GFX9-NEXT: v_add_u32_e32 v6, 3, v6594; GFX9-NEXT: v_add_u32_e32 v5, 3, v5595; GFX9-NEXT: v_add_u32_e32 v4, 3, v4596; GFX9-NEXT: v_add_u32_e32 v3, 3, v3597; GFX9-NEXT: v_add_u32_e32 v2, 3, v2598; GFX9-NEXT: v_add_u32_e32 v1, 3, v1599; GFX9-NEXT: v_add_u32_e32 v0, 3, v0600; GFX9-NEXT: ; %bb.2: ; %end601; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]602; GFX9-NEXT: s_setpc_b64 s[30:31]603;604; GFX11-LABEL: bitcast_v9i32_to_v18i16:605; GFX11: ; %bb.0:606; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)607; GFX11-NEXT: s_mov_b32 s0, exec_lo608; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9609; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0610; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)611; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0612; GFX11-NEXT: s_cbranch_execz .LBB4_2613; GFX11-NEXT: ; %bb.1: ; %cmp.true614; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v8615; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v7616; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v6617; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v5618; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v4619; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v3620; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v2621; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v1622; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v0623; GFX11-NEXT: .LBB4_2: ; %end624; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s0625; GFX11-NEXT: s_setpc_b64 s[30:31]626 %cmp = icmp eq i32 %b, 0627 br i1 %cmp, label %cmp.true, label %cmp.false628 629cmp.true:630 %a1 = add <9 x i32> %a, splat (i32 3)631 %a2 = bitcast <9 x i32> %a1 to <18 x i16>632 br label %end633 634cmp.false:635 %a3 = bitcast <9 x i32> %a to <18 x i16>636 br label %end637 638end:639 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]640 ret <18 x i16> %phi641}642 643define inreg <18 x i16> @bitcast_v9i32_to_v18i16_scalar(<9 x i32> inreg %a, i32 inreg %b) {644; SI-LABEL: bitcast_v9i32_to_v18i16_scalar:645; SI: ; %bb.0:646; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)647; SI-NEXT: s_cmp_lg_u32 s25, 0648; SI-NEXT: s_cbranch_scc0 .LBB5_4649; SI-NEXT: ; %bb.1: ; %cmp.false650; SI-NEXT: s_lshr_b32 s25, s23, 16651; SI-NEXT: s_lshr_b32 s26, s21, 16652; SI-NEXT: s_lshr_b32 s27, s19, 16653; SI-NEXT: s_lshr_b32 s28, s17, 16654; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 16655; SI-NEXT: s_lshr_b64 s[4:5], s[22:23], 16656; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], 16657; SI-NEXT: s_lshr_b64 s[10:11], s[18:19], 16658; SI-NEXT: s_lshr_b64 s[12:13], s[16:17], 16659; SI-NEXT: s_cbranch_execnz .LBB5_3660; SI-NEXT: .LBB5_2: ; %cmp.true661; SI-NEXT: s_add_i32 s23, s23, 3662; SI-NEXT: s_add_i32 s24, s24, 3663; SI-NEXT: s_add_i32 s17, s17, 3664; SI-NEXT: s_add_i32 s16, s16, 3665; SI-NEXT: s_add_i32 s19, s19, 3666; SI-NEXT: s_add_i32 s18, s18, 3667; SI-NEXT: s_add_i32 s21, s21, 3668; SI-NEXT: s_add_i32 s20, s20, 3669; SI-NEXT: s_add_i32 s22, s22, 3670; SI-NEXT: s_lshr_b32 s25, s23, 16671; SI-NEXT: s_lshr_b64 s[4:5], s[22:23], 16672; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], 16673; SI-NEXT: s_lshr_b64 s[10:11], s[18:19], 16674; SI-NEXT: s_lshr_b64 s[12:13], s[16:17], 16675; SI-NEXT: s_lshr_b32 s26, s21, 16676; SI-NEXT: s_lshr_b32 s27, s19, 16677; SI-NEXT: s_lshr_b32 s28, s17, 16678; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 16679; SI-NEXT: .LBB5_3: ; %end680; SI-NEXT: v_mov_b32_e32 v0, s16681; SI-NEXT: v_mov_b32_e32 v1, s12682; SI-NEXT: v_mov_b32_e32 v2, s17683; SI-NEXT: v_mov_b32_e32 v3, s28684; SI-NEXT: v_mov_b32_e32 v4, s18685; SI-NEXT: v_mov_b32_e32 v5, s10686; SI-NEXT: v_mov_b32_e32 v6, s19687; SI-NEXT: v_mov_b32_e32 v7, s27688; SI-NEXT: v_mov_b32_e32 v8, s20689; SI-NEXT: v_mov_b32_e32 v9, s6690; SI-NEXT: v_mov_b32_e32 v10, s21691; SI-NEXT: v_mov_b32_e32 v11, s26692; SI-NEXT: v_mov_b32_e32 v12, s22693; SI-NEXT: v_mov_b32_e32 v13, s4694; SI-NEXT: v_mov_b32_e32 v14, s23695; SI-NEXT: v_mov_b32_e32 v15, s25696; SI-NEXT: v_mov_b32_e32 v16, s24697; SI-NEXT: v_mov_b32_e32 v17, s8698; SI-NEXT: s_setpc_b64 s[30:31]699; SI-NEXT: .LBB5_4:700; SI-NEXT: ; implicit-def: $sgpr12701; SI-NEXT: ; implicit-def: $sgpr28702; SI-NEXT: ; implicit-def: $sgpr10703; SI-NEXT: ; implicit-def: $sgpr27704; SI-NEXT: ; implicit-def: $sgpr6705; SI-NEXT: ; implicit-def: $sgpr26706; SI-NEXT: ; implicit-def: $sgpr4707; SI-NEXT: ; implicit-def: $sgpr25708; SI-NEXT: ; implicit-def: $sgpr8709; SI-NEXT: s_branch .LBB5_2710;711; VI-LABEL: bitcast_v9i32_to_v18i16_scalar:712; VI: ; %bb.0:713; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)714; VI-NEXT: s_cmp_lg_u32 s25, 0715; VI-NEXT: s_cbranch_scc0 .LBB5_4716; VI-NEXT: ; %bb.1: ; %cmp.false717; VI-NEXT: s_cbranch_execnz .LBB5_3718; VI-NEXT: .LBB5_2: ; %cmp.true719; VI-NEXT: s_add_i32 s24, s24, 3720; VI-NEXT: s_add_i32 s23, s23, 3721; VI-NEXT: s_add_i32 s22, s22, 3722; VI-NEXT: s_add_i32 s21, s21, 3723; VI-NEXT: s_add_i32 s20, s20, 3724; VI-NEXT: s_add_i32 s19, s19, 3725; VI-NEXT: s_add_i32 s18, s18, 3726; VI-NEXT: s_add_i32 s17, s17, 3727; VI-NEXT: s_add_i32 s16, s16, 3728; VI-NEXT: .LBB5_3: ; %end729; VI-NEXT: v_mov_b32_e32 v0, s16730; VI-NEXT: v_mov_b32_e32 v1, s17731; VI-NEXT: v_mov_b32_e32 v2, s18732; VI-NEXT: v_mov_b32_e32 v3, s19733; VI-NEXT: v_mov_b32_e32 v4, s20734; VI-NEXT: v_mov_b32_e32 v5, s21735; VI-NEXT: v_mov_b32_e32 v6, s22736; VI-NEXT: v_mov_b32_e32 v7, s23737; VI-NEXT: v_mov_b32_e32 v8, s24738; VI-NEXT: s_setpc_b64 s[30:31]739; VI-NEXT: .LBB5_4:740; VI-NEXT: s_branch .LBB5_2741;742; GFX9-LABEL: bitcast_v9i32_to_v18i16_scalar:743; GFX9: ; %bb.0:744; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)745; GFX9-NEXT: s_cmp_lg_u32 s25, 0746; GFX9-NEXT: s_cbranch_scc0 .LBB5_4747; GFX9-NEXT: ; %bb.1: ; %cmp.false748; GFX9-NEXT: s_cbranch_execnz .LBB5_3749; GFX9-NEXT: .LBB5_2: ; %cmp.true750; GFX9-NEXT: s_add_i32 s24, s24, 3751; GFX9-NEXT: s_add_i32 s23, s23, 3752; GFX9-NEXT: s_add_i32 s22, s22, 3753; GFX9-NEXT: s_add_i32 s21, s21, 3754; GFX9-NEXT: s_add_i32 s20, s20, 3755; GFX9-NEXT: s_add_i32 s19, s19, 3756; GFX9-NEXT: s_add_i32 s18, s18, 3757; GFX9-NEXT: s_add_i32 s17, s17, 3758; GFX9-NEXT: s_add_i32 s16, s16, 3759; GFX9-NEXT: .LBB5_3: ; %end760; GFX9-NEXT: v_mov_b32_e32 v0, s16761; GFX9-NEXT: v_mov_b32_e32 v1, s17762; GFX9-NEXT: v_mov_b32_e32 v2, s18763; GFX9-NEXT: v_mov_b32_e32 v3, s19764; GFX9-NEXT: v_mov_b32_e32 v4, s20765; GFX9-NEXT: v_mov_b32_e32 v5, s21766; GFX9-NEXT: v_mov_b32_e32 v6, s22767; GFX9-NEXT: v_mov_b32_e32 v7, s23768; GFX9-NEXT: v_mov_b32_e32 v8, s24769; GFX9-NEXT: s_setpc_b64 s[30:31]770; GFX9-NEXT: .LBB5_4:771; GFX9-NEXT: s_branch .LBB5_2772;773; GFX11-LABEL: bitcast_v9i32_to_v18i16_scalar:774; GFX11: ; %bb.0:775; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)776; GFX11-NEXT: s_cmp_lg_u32 s21, 0777; GFX11-NEXT: s_mov_b32 s4, 0778; GFX11-NEXT: s_cbranch_scc0 .LBB5_4779; GFX11-NEXT: ; %bb.1: ; %Flow780; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s4781; GFX11-NEXT: s_cbranch_vccnz .LBB5_3782; GFX11-NEXT: .LBB5_2: ; %cmp.true783; GFX11-NEXT: s_add_i32 s20, s20, 3784; GFX11-NEXT: s_add_i32 s19, s19, 3785; GFX11-NEXT: s_add_i32 s18, s18, 3786; GFX11-NEXT: s_add_i32 s17, s17, 3787; GFX11-NEXT: s_add_i32 s16, s16, 3788; GFX11-NEXT: s_add_i32 s3, s3, 3789; GFX11-NEXT: s_add_i32 s2, s2, 3790; GFX11-NEXT: s_add_i32 s1, s1, 3791; GFX11-NEXT: s_add_i32 s0, s0, 3792; GFX11-NEXT: .LBB5_3: ; %end793; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)794; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1795; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3796; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s17797; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s19798; GFX11-NEXT: v_mov_b32_e32 v8, s20799; GFX11-NEXT: s_setpc_b64 s[30:31]800; GFX11-NEXT: .LBB5_4:801; GFX11-NEXT: s_branch .LBB5_2802 %cmp = icmp eq i32 %b, 0803 br i1 %cmp, label %cmp.true, label %cmp.false804 805cmp.true:806 %a1 = add <9 x i32> %a, splat (i32 3)807 %a2 = bitcast <9 x i32> %a1 to <18 x i16>808 br label %end809 810cmp.false:811 %a3 = bitcast <9 x i32> %a to <18 x i16>812 br label %end813 814end:815 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]816 ret <18 x i16> %phi817}818 819define <9 x i32> @bitcast_v18i16_to_v9i32(<18 x i16> %a, i32 %b) {820; SI-LABEL: bitcast_v18i16_to_v9i32:821; SI: ; %bb.0:822; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)823; SI-NEXT: v_mov_b32_e32 v23, v8824; SI-NEXT: v_mov_b32_e32 v22, v6825; SI-NEXT: v_mov_b32_e32 v21, v4826; SI-NEXT: v_mov_b32_e32 v20, v2827; SI-NEXT: v_mov_b32_e32 v19, v0828; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v18829; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v1830; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v3831; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v5832; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v7833; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v9834; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v11835; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v13836; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v15837; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v17838; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8839; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc840; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]841; SI-NEXT: s_cbranch_execnz .LBB6_3842; SI-NEXT: ; %bb.1: ; %Flow843; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]844; SI-NEXT: s_cbranch_execnz .LBB6_4845; SI-NEXT: .LBB6_2: ; %end846; SI-NEXT: s_or_b64 exec, exec, s[4:5]847; SI-NEXT: s_setpc_b64 s[30:31]848; SI-NEXT: .LBB6_3: ; %cmp.false849; SI-NEXT: v_and_b32_e32 v0, 0xffff, v19850; SI-NEXT: v_and_b32_e32 v1, 0xffff, v20851; SI-NEXT: v_and_b32_e32 v2, 0xffff, v21852; SI-NEXT: v_and_b32_e32 v3, 0xffff, v22853; SI-NEXT: v_and_b32_e32 v4, 0xffff, v23854; SI-NEXT: v_and_b32_e32 v5, 0xffff, v10855; SI-NEXT: v_and_b32_e32 v6, 0xffff, v12856; SI-NEXT: v_and_b32_e32 v7, 0xffff, v14857; SI-NEXT: v_and_b32_e32 v8, 0xffff, v16858; SI-NEXT: v_or_b32_e32 v0, v0, v28859; SI-NEXT: v_or_b32_e32 v1, v1, v27860; SI-NEXT: v_or_b32_e32 v2, v2, v26861; SI-NEXT: v_or_b32_e32 v3, v3, v25862; SI-NEXT: v_or_b32_e32 v4, v4, v24863; SI-NEXT: v_or_b32_e32 v5, v5, v18864; SI-NEXT: v_or_b32_e32 v6, v6, v13865; SI-NEXT: v_or_b32_e32 v7, v7, v11866; SI-NEXT: v_or_b32_e32 v8, v8, v9867; SI-NEXT: ; implicit-def: $vgpr19868; SI-NEXT: ; implicit-def: $vgpr20869; SI-NEXT: ; implicit-def: $vgpr21870; SI-NEXT: ; implicit-def: $vgpr22871; SI-NEXT: ; implicit-def: $vgpr23872; SI-NEXT: ; implicit-def: $vgpr10873; SI-NEXT: ; implicit-def: $vgpr12874; SI-NEXT: ; implicit-def: $vgpr14875; SI-NEXT: ; implicit-def: $vgpr16876; SI-NEXT: ; implicit-def: $vgpr28877; SI-NEXT: ; implicit-def: $vgpr27878; SI-NEXT: ; implicit-def: $vgpr26879; SI-NEXT: ; implicit-def: $vgpr25880; SI-NEXT: ; implicit-def: $vgpr24881; SI-NEXT: ; implicit-def: $vgpr18882; SI-NEXT: ; implicit-def: $vgpr13883; SI-NEXT: ; implicit-def: $vgpr11884; SI-NEXT: ; implicit-def: $vgpr9885; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]886; SI-NEXT: s_cbranch_execz .LBB6_2887; SI-NEXT: .LBB6_4: ; %cmp.true888; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v19889; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v20890; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v21891; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v22892; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v23893; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v10894; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v12895; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v14896; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v16897; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0898; SI-NEXT: v_and_b32_e32 v1, 0xffff, v1899; SI-NEXT: v_and_b32_e32 v2, 0xffff, v2900; SI-NEXT: v_and_b32_e32 v3, 0xffff, v3901; SI-NEXT: v_and_b32_e32 v4, 0xffff, v4902; SI-NEXT: v_and_b32_e32 v5, 0xffff, v5903; SI-NEXT: v_and_b32_e32 v6, 0xffff, v6904; SI-NEXT: v_and_b32_e32 v7, 0xffff, v7905; SI-NEXT: v_and_b32_e32 v8, 0xffff, v8906; SI-NEXT: v_or_b32_e32 v0, v28, v0907; SI-NEXT: s_mov_b32 s6, 0x30000908; SI-NEXT: v_or_b32_e32 v1, v27, v1909; SI-NEXT: v_or_b32_e32 v2, v26, v2910; SI-NEXT: v_or_b32_e32 v3, v25, v3911; SI-NEXT: v_or_b32_e32 v4, v24, v4912; SI-NEXT: v_or_b32_e32 v5, v18, v5913; SI-NEXT: v_or_b32_e32 v6, v13, v6914; SI-NEXT: v_or_b32_e32 v7, v11, v7915; SI-NEXT: v_or_b32_e32 v8, v9, v8916; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v0917; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v1918; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v2919; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v3920; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v4921; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v5922; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v6923; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v7924; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v8925; SI-NEXT: s_or_b64 exec, exec, s[4:5]926; SI-NEXT: s_setpc_b64 s[30:31]927;928; VI-LABEL: bitcast_v18i16_to_v9i32:929; VI: ; %bb.0:930; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)931; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9932; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc933; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]934; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]935; VI-NEXT: s_cbranch_execz .LBB6_2936; VI-NEXT: ; %bb.1: ; %cmp.true937; VI-NEXT: v_mov_b32_e32 v10, 3938; VI-NEXT: v_add_u16_e32 v9, 3, v8939; VI-NEXT: v_add_u16_sdwa v8, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD940; VI-NEXT: v_or_b32_e32 v8, v9, v8941; VI-NEXT: v_add_u16_e32 v9, 3, v7942; VI-NEXT: v_add_u16_sdwa v7, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD943; VI-NEXT: v_or_b32_e32 v7, v9, v7944; VI-NEXT: v_add_u16_e32 v9, 3, v6945; VI-NEXT: v_add_u16_sdwa v6, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD946; VI-NEXT: v_or_b32_e32 v6, v9, v6947; VI-NEXT: v_add_u16_e32 v9, 3, v5948; VI-NEXT: v_add_u16_sdwa v5, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD949; VI-NEXT: v_or_b32_e32 v5, v9, v5950; VI-NEXT: v_add_u16_e32 v9, 3, v4951; VI-NEXT: v_add_u16_sdwa v4, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD952; VI-NEXT: v_or_b32_e32 v4, v9, v4953; VI-NEXT: v_add_u16_e32 v9, 3, v3954; VI-NEXT: v_add_u16_sdwa v3, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD955; VI-NEXT: v_or_b32_e32 v3, v9, v3956; VI-NEXT: v_add_u16_e32 v9, 3, v2957; VI-NEXT: v_add_u16_sdwa v2, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD958; VI-NEXT: v_or_b32_e32 v2, v9, v2959; VI-NEXT: v_add_u16_e32 v9, 3, v1960; VI-NEXT: v_add_u16_sdwa v1, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD961; VI-NEXT: v_or_b32_e32 v1, v9, v1962; VI-NEXT: v_add_u16_e32 v9, 3, v0963; VI-NEXT: v_add_u16_sdwa v0, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD964; VI-NEXT: v_or_b32_e32 v0, v9, v0965; VI-NEXT: .LBB6_2: ; %end966; VI-NEXT: s_or_b64 exec, exec, s[4:5]967; VI-NEXT: s_setpc_b64 s[30:31]968;969; GFX9-LABEL: bitcast_v18i16_to_v9i32:970; GFX9: ; %bb.0:971; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)972; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9973; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc974; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]975; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]976; GFX9-NEXT: ; %bb.1: ; %cmp.true977; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]978; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]979; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]980; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]981; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]982; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]983; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]984; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]985; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]986; GFX9-NEXT: ; %bb.2: ; %end987; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]988; GFX9-NEXT: s_setpc_b64 s[30:31]989;990; GFX11-LABEL: bitcast_v18i16_to_v9i32:991; GFX11: ; %bb.0:992; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)993; GFX11-NEXT: s_mov_b32 s0, exec_lo994; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v9995; GFX11-NEXT: s_xor_b32 s0, exec_lo, s0996; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)997; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s0998; GFX11-NEXT: s_cbranch_execz .LBB6_2999; GFX11-NEXT: ; %bb.1: ; %cmp.true1000; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]1001; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]1002; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]1003; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]1004; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]1005; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]1006; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]1007; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]1008; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]1009; GFX11-NEXT: .LBB6_2: ; %end1010; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01011; GFX11-NEXT: s_setpc_b64 s[30:31]1012 %cmp = icmp eq i32 %b, 01013 br i1 %cmp, label %cmp.true, label %cmp.false1014 1015cmp.true:1016 %a1 = add <18 x i16> %a, splat (i16 3)1017 %a2 = bitcast <18 x i16> %a1 to <9 x i32>1018 br label %end1019 1020cmp.false:1021 %a3 = bitcast <18 x i16> %a to <9 x i32>1022 br label %end1023 1024end:1025 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1026 ret <9 x i32> %phi1027}1028 1029define inreg <9 x i32> @bitcast_v18i16_to_v9i32_scalar(<18 x i16> inreg %a, i32 inreg %b) {1030; SI-LABEL: bitcast_v18i16_to_v9i32_scalar:1031; SI: ; %bb.0:1032; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1033; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v41034; SI-NEXT: v_mov_b32_e32 v9, v21035; SI-NEXT: v_mov_b32_e32 v10, v01036; SI-NEXT: s_and_b64 s[4:5], vcc, exec1037; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v11038; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v31039; SI-NEXT: s_cbranch_scc0 .LBB7_41040; SI-NEXT: ; %bb.1: ; %cmp.false1041; SI-NEXT: s_and_b32 s4, s16, 0xffff1042; SI-NEXT: s_lshl_b32 s5, s17, 161043; SI-NEXT: s_or_b32 s4, s4, s51044; SI-NEXT: s_and_b32 s5, s18, 0xffff1045; SI-NEXT: s_lshl_b32 s6, s19, 161046; SI-NEXT: s_or_b32 s5, s5, s61047; SI-NEXT: s_and_b32 s6, s20, 0xffff1048; SI-NEXT: s_lshl_b32 s7, s21, 161049; SI-NEXT: s_or_b32 s6, s6, s71050; SI-NEXT: s_and_b32 s7, s22, 0xffff1051; SI-NEXT: s_lshl_b32 s8, s23, 161052; SI-NEXT: s_or_b32 s7, s7, s81053; SI-NEXT: s_and_b32 s8, s24, 0xffff1054; SI-NEXT: s_lshl_b32 s9, s25, 161055; SI-NEXT: s_or_b32 s8, s8, s91056; SI-NEXT: s_and_b32 s9, s26, 0xffff1057; SI-NEXT: s_lshl_b32 s10, s27, 161058; SI-NEXT: s_or_b32 s9, s9, s101059; SI-NEXT: s_and_b32 s10, s28, 0xffff1060; SI-NEXT: s_lshl_b32 s11, s29, 161061; SI-NEXT: v_and_b32_e32 v0, 0xffff, v101062; SI-NEXT: s_or_b32 s10, s10, s111063; SI-NEXT: v_or_b32_e32 v7, v0, v121064; SI-NEXT: v_and_b32_e32 v0, 0xffff, v91065; SI-NEXT: v_or_b32_e32 v8, v0, v111066; SI-NEXT: v_mov_b32_e32 v0, s41067; SI-NEXT: v_mov_b32_e32 v1, s51068; SI-NEXT: v_mov_b32_e32 v2, s61069; SI-NEXT: v_mov_b32_e32 v3, s71070; SI-NEXT: v_mov_b32_e32 v4, s81071; SI-NEXT: v_mov_b32_e32 v5, s91072; SI-NEXT: v_mov_b32_e32 v6, s101073; SI-NEXT: s_cbranch_execnz .LBB7_31074; SI-NEXT: .LBB7_2: ; %cmp.true1075; SI-NEXT: s_add_i32 s16, s16, 31076; SI-NEXT: s_and_b32 s4, s16, 0xffff1077; SI-NEXT: s_lshl_b32 s5, s17, 161078; SI-NEXT: s_add_i32 s18, s18, 31079; SI-NEXT: s_or_b32 s4, s5, s41080; SI-NEXT: s_and_b32 s5, s18, 0xffff1081; SI-NEXT: s_lshl_b32 s6, s19, 161082; SI-NEXT: s_add_i32 s20, s20, 31083; SI-NEXT: s_or_b32 s5, s6, s51084; SI-NEXT: s_and_b32 s6, s20, 0xffff1085; SI-NEXT: s_lshl_b32 s7, s21, 161086; SI-NEXT: s_add_i32 s22, s22, 31087; SI-NEXT: s_or_b32 s6, s7, s61088; SI-NEXT: s_and_b32 s7, s22, 0xffff1089; SI-NEXT: s_lshl_b32 s8, s23, 161090; SI-NEXT: s_add_i32 s24, s24, 31091; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v101092; SI-NEXT: s_or_b32 s7, s8, s71093; SI-NEXT: s_and_b32 s8, s24, 0xffff1094; SI-NEXT: s_lshl_b32 s9, s25, 161095; SI-NEXT: s_add_i32 s26, s26, 31096; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01097; SI-NEXT: s_or_b32 s8, s9, s81098; SI-NEXT: s_and_b32 s9, s26, 0xffff1099; SI-NEXT: s_lshl_b32 s10, s27, 161100; SI-NEXT: s_add_i32 s28, s28, 31101; SI-NEXT: v_or_b32_e32 v0, v12, v01102; SI-NEXT: s_or_b32 s9, s10, s91103; SI-NEXT: s_and_b32 s10, s28, 0xffff1104; SI-NEXT: s_lshl_b32 s11, s29, 161105; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v01106; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v91107; SI-NEXT: s_or_b32 s10, s11, s101108; SI-NEXT: v_and_b32_e32 v0, 0xffff, v01109; SI-NEXT: s_add_i32 s4, s4, 0x300001110; SI-NEXT: s_add_i32 s5, s5, 0x300001111; SI-NEXT: s_add_i32 s6, s6, 0x300001112; SI-NEXT: s_add_i32 s7, s7, 0x300001113; SI-NEXT: s_add_i32 s8, s8, 0x300001114; SI-NEXT: s_add_i32 s9, s9, 0x300001115; SI-NEXT: s_add_i32 s10, s10, 0x300001116; SI-NEXT: v_or_b32_e32 v0, v11, v01117; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v01118; SI-NEXT: v_mov_b32_e32 v0, s41119; SI-NEXT: v_mov_b32_e32 v1, s51120; SI-NEXT: v_mov_b32_e32 v2, s61121; SI-NEXT: v_mov_b32_e32 v3, s71122; SI-NEXT: v_mov_b32_e32 v4, s81123; SI-NEXT: v_mov_b32_e32 v5, s91124; SI-NEXT: v_mov_b32_e32 v6, s101125; SI-NEXT: .LBB7_3: ; %end1126; SI-NEXT: s_setpc_b64 s[30:31]1127; SI-NEXT: .LBB7_4:1128; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr81129; SI-NEXT: s_branch .LBB7_21130;1131; VI-LABEL: bitcast_v18i16_to_v9i32_scalar:1132; VI: ; %bb.0:1133; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1134; VI-NEXT: s_cmp_lg_u32 s25, 01135; VI-NEXT: s_cbranch_scc0 .LBB7_41136; VI-NEXT: ; %bb.1: ; %cmp.false1137; VI-NEXT: s_cbranch_execnz .LBB7_31138; VI-NEXT: .LBB7_2: ; %cmp.true1139; VI-NEXT: s_add_i32 s5, s24, 31140; VI-NEXT: s_and_b32 s4, s24, 0xffff00001141; VI-NEXT: s_and_b32 s5, s5, 0xffff1142; VI-NEXT: s_or_b32 s4, s4, s51143; VI-NEXT: s_add_i32 s5, s23, 31144; VI-NEXT: s_add_i32 s24, s4, 0x300001145; VI-NEXT: s_and_b32 s4, s23, 0xffff00001146; VI-NEXT: s_and_b32 s5, s5, 0xffff1147; VI-NEXT: s_or_b32 s4, s4, s51148; VI-NEXT: s_add_i32 s5, s22, 31149; VI-NEXT: s_add_i32 s23, s4, 0x300001150; VI-NEXT: s_and_b32 s4, s22, 0xffff00001151; VI-NEXT: s_and_b32 s5, s5, 0xffff1152; VI-NEXT: s_or_b32 s4, s4, s51153; VI-NEXT: s_add_i32 s5, s21, 31154; VI-NEXT: s_add_i32 s22, s4, 0x300001155; VI-NEXT: s_and_b32 s4, s21, 0xffff00001156; VI-NEXT: s_and_b32 s5, s5, 0xffff1157; VI-NEXT: s_or_b32 s4, s4, s51158; VI-NEXT: s_add_i32 s5, s20, 31159; VI-NEXT: s_add_i32 s21, s4, 0x300001160; VI-NEXT: s_and_b32 s4, s20, 0xffff00001161; VI-NEXT: s_and_b32 s5, s5, 0xffff1162; VI-NEXT: s_or_b32 s4, s4, s51163; VI-NEXT: s_add_i32 s5, s19, 31164; VI-NEXT: s_add_i32 s20, s4, 0x300001165; VI-NEXT: s_and_b32 s4, s19, 0xffff00001166; VI-NEXT: s_and_b32 s5, s5, 0xffff1167; VI-NEXT: s_or_b32 s4, s4, s51168; VI-NEXT: s_add_i32 s5, s18, 31169; VI-NEXT: s_add_i32 s19, s4, 0x300001170; VI-NEXT: s_and_b32 s4, s18, 0xffff00001171; VI-NEXT: s_and_b32 s5, s5, 0xffff1172; VI-NEXT: s_or_b32 s4, s4, s51173; VI-NEXT: s_add_i32 s5, s17, 31174; VI-NEXT: s_add_i32 s18, s4, 0x300001175; VI-NEXT: s_and_b32 s4, s17, 0xffff00001176; VI-NEXT: s_and_b32 s5, s5, 0xffff1177; VI-NEXT: s_or_b32 s4, s4, s51178; VI-NEXT: s_add_i32 s5, s16, 31179; VI-NEXT: s_add_i32 s17, s4, 0x300001180; VI-NEXT: s_and_b32 s4, s16, 0xffff00001181; VI-NEXT: s_and_b32 s5, s5, 0xffff1182; VI-NEXT: s_or_b32 s4, s4, s51183; VI-NEXT: s_add_i32 s16, s4, 0x300001184; VI-NEXT: .LBB7_3: ; %end1185; VI-NEXT: v_mov_b32_e32 v0, s161186; VI-NEXT: v_mov_b32_e32 v1, s171187; VI-NEXT: v_mov_b32_e32 v2, s181188; VI-NEXT: v_mov_b32_e32 v3, s191189; VI-NEXT: v_mov_b32_e32 v4, s201190; VI-NEXT: v_mov_b32_e32 v5, s211191; VI-NEXT: v_mov_b32_e32 v6, s221192; VI-NEXT: v_mov_b32_e32 v7, s231193; VI-NEXT: v_mov_b32_e32 v8, s241194; VI-NEXT: s_setpc_b64 s[30:31]1195; VI-NEXT: .LBB7_4:1196; VI-NEXT: s_branch .LBB7_21197;1198; GFX9-LABEL: bitcast_v18i16_to_v9i32_scalar:1199; GFX9: ; %bb.0:1200; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1201; GFX9-NEXT: s_cmp_lg_u32 s25, 01202; GFX9-NEXT: s_cbranch_scc0 .LBB7_31203; GFX9-NEXT: ; %bb.1: ; %cmp.false1204; GFX9-NEXT: s_cbranch_execnz .LBB7_41205; GFX9-NEXT: .LBB7_2: ; %cmp.true1206; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]1207; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]1208; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]1209; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]1210; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]1211; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]1212; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]1213; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]1214; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]1215; GFX9-NEXT: s_setpc_b64 s[30:31]1216; GFX9-NEXT: .LBB7_3:1217; GFX9-NEXT: s_branch .LBB7_21218; GFX9-NEXT: .LBB7_4:1219; GFX9-NEXT: v_mov_b32_e32 v0, s161220; GFX9-NEXT: v_mov_b32_e32 v1, s171221; GFX9-NEXT: v_mov_b32_e32 v2, s181222; GFX9-NEXT: v_mov_b32_e32 v3, s191223; GFX9-NEXT: v_mov_b32_e32 v4, s201224; GFX9-NEXT: v_mov_b32_e32 v5, s211225; GFX9-NEXT: v_mov_b32_e32 v6, s221226; GFX9-NEXT: v_mov_b32_e32 v7, s231227; GFX9-NEXT: v_mov_b32_e32 v8, s241228; GFX9-NEXT: s_setpc_b64 s[30:31]1229;1230; GFX11-LABEL: bitcast_v18i16_to_v9i32_scalar:1231; GFX11: ; %bb.0:1232; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1233; GFX11-NEXT: s_mov_b32 s15, s31234; GFX11-NEXT: s_mov_b32 s14, s21235; GFX11-NEXT: s_mov_b32 s13, s11236; GFX11-NEXT: s_mov_b32 s12, s01237; GFX11-NEXT: s_cmp_lg_u32 s21, 01238; GFX11-NEXT: s_mov_b32 s0, 01239; GFX11-NEXT: s_cbranch_scc0 .LBB7_31240; GFX11-NEXT: ; %bb.1: ; %Flow1241; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s01242; GFX11-NEXT: s_cbranch_vccnz .LBB7_41243; GFX11-NEXT: .LBB7_2: ; %cmp.true1244; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]1245; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]1246; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]1247; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]1248; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]1249; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]1250; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]1251; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]1252; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]1253; GFX11-NEXT: s_setpc_b64 s[30:31]1254; GFX11-NEXT: .LBB7_3:1255; GFX11-NEXT: s_branch .LBB7_21256; GFX11-NEXT: .LBB7_4:1257; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s131258; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s151259; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171260; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191261; GFX11-NEXT: v_mov_b32_e32 v8, s201262; GFX11-NEXT: s_setpc_b64 s[30:31]1263 %cmp = icmp eq i32 %b, 01264 br i1 %cmp, label %cmp.true, label %cmp.false1265 1266cmp.true:1267 %a1 = add <18 x i16> %a, splat (i16 3)1268 %a2 = bitcast <18 x i16> %a1 to <9 x i32>1269 br label %end1270 1271cmp.false:1272 %a3 = bitcast <18 x i16> %a to <9 x i32>1273 br label %end1274 1275end:1276 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1277 ret <9 x i32> %phi1278}1279 1280define <18 x half> @bitcast_v9i32_to_v18f16(<9 x i32> %a, i32 %b) {1281; SI-LABEL: bitcast_v9i32_to_v18f16:1282; SI: ; %bb.0:1283; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1284; SI-NEXT: v_mov_b32_e32 v26, v81285; SI-NEXT: v_mov_b32_e32 v25, v71286; SI-NEXT: v_mov_b32_e32 v24, v61287; SI-NEXT: v_mov_b32_e32 v23, v51288; SI-NEXT: v_mov_b32_e32 v22, v41289; SI-NEXT: v_mov_b32_e32 v21, v31290; SI-NEXT: v_mov_b32_e32 v20, v21291; SI-NEXT: v_mov_b32_e32 v19, v11292; SI-NEXT: v_mov_b32_e32 v18, v01293; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v91294; SI-NEXT: ; implicit-def: $vgpr01295; SI-NEXT: ; implicit-def: $vgpr11296; SI-NEXT: ; implicit-def: $vgpr21297; SI-NEXT: ; implicit-def: $vgpr31298; SI-NEXT: ; implicit-def: $vgpr41299; SI-NEXT: ; implicit-def: $vgpr51300; SI-NEXT: ; implicit-def: $vgpr61301; SI-NEXT: ; implicit-def: $vgpr71302; SI-NEXT: ; implicit-def: $vgpr81303; SI-NEXT: ; implicit-def: $vgpr91304; SI-NEXT: ; implicit-def: $vgpr101305; SI-NEXT: ; implicit-def: $vgpr111306; SI-NEXT: ; implicit-def: $vgpr121307; SI-NEXT: ; implicit-def: $vgpr131308; SI-NEXT: ; implicit-def: $vgpr141309; SI-NEXT: ; implicit-def: $vgpr151310; SI-NEXT: ; implicit-def: $vgpr161311; SI-NEXT: ; implicit-def: $vgpr171312; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1313; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1314; SI-NEXT: s_cbranch_execnz .LBB8_31315; SI-NEXT: ; %bb.1: ; %Flow1316; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1317; SI-NEXT: s_cbranch_execnz .LBB8_41318; SI-NEXT: .LBB8_2: ; %end1319; SI-NEXT: s_or_b64 exec, exec, s[4:5]1320; SI-NEXT: s_setpc_b64 s[30:31]1321; SI-NEXT: .LBB8_3: ; %cmp.false1322; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v261323; SI-NEXT: v_cvt_f32_f16_e32 v17, v01324; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v251325; SI-NEXT: v_cvt_f32_f16_e32 v15, v01326; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v241327; SI-NEXT: v_cvt_f32_f16_e32 v13, v01328; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v231329; SI-NEXT: v_cvt_f32_f16_e32 v11, v01330; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v221331; SI-NEXT: v_cvt_f32_f16_e32 v9, v01332; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v211333; SI-NEXT: v_cvt_f32_f16_e32 v7, v01334; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v201335; SI-NEXT: v_cvt_f32_f16_e32 v5, v01336; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v191337; SI-NEXT: v_cvt_f32_f16_e32 v3, v01338; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v181339; SI-NEXT: v_cvt_f32_f16_e32 v1, v01340; SI-NEXT: v_cvt_f32_f16_e32 v16, v261341; SI-NEXT: v_cvt_f32_f16_e32 v14, v251342; SI-NEXT: v_cvt_f32_f16_e32 v12, v241343; SI-NEXT: v_cvt_f32_f16_e32 v10, v231344; SI-NEXT: v_cvt_f32_f16_e32 v8, v221345; SI-NEXT: v_cvt_f32_f16_e32 v6, v211346; SI-NEXT: v_cvt_f32_f16_e32 v4, v201347; SI-NEXT: v_cvt_f32_f16_e32 v2, v191348; SI-NEXT: v_cvt_f32_f16_e32 v0, v181349; SI-NEXT: ; implicit-def: $vgpr181350; SI-NEXT: ; implicit-def: $vgpr191351; SI-NEXT: ; implicit-def: $vgpr201352; SI-NEXT: ; implicit-def: $vgpr211353; SI-NEXT: ; implicit-def: $vgpr221354; SI-NEXT: ; implicit-def: $vgpr231355; SI-NEXT: ; implicit-def: $vgpr241356; SI-NEXT: ; implicit-def: $vgpr251357; SI-NEXT: ; implicit-def: $vgpr261358; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1359; SI-NEXT: s_cbranch_execz .LBB8_21360; SI-NEXT: .LBB8_4: ; %cmp.true1361; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v181362; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v191363; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v201364; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v211365; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v221366; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v231367; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v241368; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v251369; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v261370; SI-NEXT: v_cvt_f32_f16_e32 v16, v171371; SI-NEXT: v_cvt_f32_f16_e32 v14, v151372; SI-NEXT: v_cvt_f32_f16_e32 v12, v131373; SI-NEXT: v_cvt_f32_f16_e32 v10, v111374; SI-NEXT: v_cvt_f32_f16_e32 v8, v91375; SI-NEXT: v_cvt_f32_f16_e32 v6, v71376; SI-NEXT: v_cvt_f32_f16_e32 v4, v51377; SI-NEXT: v_cvt_f32_f16_e32 v2, v31378; SI-NEXT: v_cvt_f32_f16_e32 v0, v11379; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v171380; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v151381; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v131382; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v111383; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v91384; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v71385; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v51386; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v31387; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v11388; SI-NEXT: v_cvt_f32_f16_e32 v17, v171389; SI-NEXT: v_cvt_f32_f16_e32 v15, v151390; SI-NEXT: v_cvt_f32_f16_e32 v13, v131391; SI-NEXT: v_cvt_f32_f16_e32 v11, v111392; SI-NEXT: v_cvt_f32_f16_e32 v9, v91393; SI-NEXT: v_cvt_f32_f16_e32 v7, v71394; SI-NEXT: v_cvt_f32_f16_e32 v5, v51395; SI-NEXT: v_cvt_f32_f16_e32 v3, v31396; SI-NEXT: v_cvt_f32_f16_e32 v1, v11397; SI-NEXT: s_or_b64 exec, exec, s[4:5]1398; SI-NEXT: s_setpc_b64 s[30:31]1399;1400; VI-LABEL: bitcast_v9i32_to_v18f16:1401; VI: ; %bb.0:1402; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1403; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v91404; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1405; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1406; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1407; VI-NEXT: ; %bb.1: ; %cmp.true1408; VI-NEXT: v_add_u32_e32 v8, vcc, 3, v81409; VI-NEXT: v_add_u32_e32 v7, vcc, 3, v71410; VI-NEXT: v_add_u32_e32 v6, vcc, 3, v61411; VI-NEXT: v_add_u32_e32 v5, vcc, 3, v51412; VI-NEXT: v_add_u32_e32 v4, vcc, 3, v41413; VI-NEXT: v_add_u32_e32 v3, vcc, 3, v31414; VI-NEXT: v_add_u32_e32 v2, vcc, 3, v21415; VI-NEXT: v_add_u32_e32 v1, vcc, 3, v11416; VI-NEXT: v_add_u32_e32 v0, vcc, 3, v01417; VI-NEXT: ; %bb.2: ; %end1418; VI-NEXT: s_or_b64 exec, exec, s[4:5]1419; VI-NEXT: s_setpc_b64 s[30:31]1420;1421; GFX9-LABEL: bitcast_v9i32_to_v18f16:1422; GFX9: ; %bb.0:1423; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1424; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v91425; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1426; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1427; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1428; GFX9-NEXT: ; %bb.1: ; %cmp.true1429; GFX9-NEXT: v_add_u32_e32 v8, 3, v81430; GFX9-NEXT: v_add_u32_e32 v7, 3, v71431; GFX9-NEXT: v_add_u32_e32 v6, 3, v61432; GFX9-NEXT: v_add_u32_e32 v5, 3, v51433; GFX9-NEXT: v_add_u32_e32 v4, 3, v41434; GFX9-NEXT: v_add_u32_e32 v3, 3, v31435; GFX9-NEXT: v_add_u32_e32 v2, 3, v21436; GFX9-NEXT: v_add_u32_e32 v1, 3, v11437; GFX9-NEXT: v_add_u32_e32 v0, 3, v01438; GFX9-NEXT: ; %bb.2: ; %end1439; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1440; GFX9-NEXT: s_setpc_b64 s[30:31]1441;1442; GFX11-LABEL: bitcast_v9i32_to_v18f16:1443; GFX11: ; %bb.0:1444; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1445; GFX11-NEXT: s_mov_b32 s0, exec_lo1446; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v91447; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01448; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1449; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01450; GFX11-NEXT: s_cbranch_execz .LBB8_21451; GFX11-NEXT: ; %bb.1: ; %cmp.true1452; GFX11-NEXT: v_add_nc_u32_e32 v8, 3, v81453; GFX11-NEXT: v_add_nc_u32_e32 v7, 3, v71454; GFX11-NEXT: v_add_nc_u32_e32 v6, 3, v61455; GFX11-NEXT: v_add_nc_u32_e32 v5, 3, v51456; GFX11-NEXT: v_add_nc_u32_e32 v4, 3, v41457; GFX11-NEXT: v_add_nc_u32_e32 v3, 3, v31458; GFX11-NEXT: v_add_nc_u32_e32 v2, 3, v21459; GFX11-NEXT: v_add_nc_u32_e32 v1, 3, v11460; GFX11-NEXT: v_add_nc_u32_e32 v0, 3, v01461; GFX11-NEXT: .LBB8_2: ; %end1462; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01463; GFX11-NEXT: s_setpc_b64 s[30:31]1464 %cmp = icmp eq i32 %b, 01465 br i1 %cmp, label %cmp.true, label %cmp.false1466 1467cmp.true:1468 %a1 = add <9 x i32> %a, splat (i32 3)1469 %a2 = bitcast <9 x i32> %a1 to <18 x half>1470 br label %end1471 1472cmp.false:1473 %a3 = bitcast <9 x i32> %a to <18 x half>1474 br label %end1475 1476end:1477 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1478 ret <18 x half> %phi1479}1480 1481define inreg <18 x half> @bitcast_v9i32_to_v18f16_scalar(<9 x i32> inreg %a, i32 inreg %b) {1482; SI-LABEL: bitcast_v9i32_to_v18f16_scalar:1483; SI: ; %bb.0:1484; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1485; SI-NEXT: s_cmp_lg_u32 s25, 01486; SI-NEXT: s_cbranch_scc0 .LBB9_41487; SI-NEXT: ; %bb.1: ; %cmp.false1488; SI-NEXT: s_lshr_b32 s4, s24, 161489; SI-NEXT: v_cvt_f32_f16_e32 v17, s41490; SI-NEXT: s_lshr_b32 s4, s23, 161491; SI-NEXT: v_cvt_f32_f16_e32 v15, s41492; SI-NEXT: s_lshr_b32 s4, s22, 161493; SI-NEXT: v_cvt_f32_f16_e32 v13, s41494; SI-NEXT: s_lshr_b32 s4, s21, 161495; SI-NEXT: v_cvt_f32_f16_e32 v11, s41496; SI-NEXT: s_lshr_b32 s4, s20, 161497; SI-NEXT: v_cvt_f32_f16_e32 v9, s41498; SI-NEXT: s_lshr_b32 s4, s19, 161499; SI-NEXT: v_cvt_f32_f16_e32 v7, s41500; SI-NEXT: s_lshr_b32 s4, s18, 161501; SI-NEXT: v_cvt_f32_f16_e32 v5, s41502; SI-NEXT: s_lshr_b32 s4, s17, 161503; SI-NEXT: v_cvt_f32_f16_e32 v3, s41504; SI-NEXT: s_lshr_b32 s4, s16, 161505; SI-NEXT: v_cvt_f32_f16_e32 v1, s41506; SI-NEXT: v_cvt_f32_f16_e32 v16, s241507; SI-NEXT: v_cvt_f32_f16_e32 v14, s231508; SI-NEXT: v_cvt_f32_f16_e32 v12, s221509; SI-NEXT: v_cvt_f32_f16_e32 v10, s211510; SI-NEXT: v_cvt_f32_f16_e32 v8, s201511; SI-NEXT: v_cvt_f32_f16_e32 v6, s191512; SI-NEXT: v_cvt_f32_f16_e32 v4, s181513; SI-NEXT: v_cvt_f32_f16_e32 v2, s171514; SI-NEXT: v_cvt_f32_f16_e32 v0, s161515; SI-NEXT: s_cbranch_execnz .LBB9_31516; SI-NEXT: .LBB9_2: ; %cmp.true1517; SI-NEXT: s_add_i32 s24, s24, 31518; SI-NEXT: s_add_i32 s23, s23, 31519; SI-NEXT: s_lshr_b32 s4, s24, 161520; SI-NEXT: s_add_i32 s22, s22, 31521; SI-NEXT: v_cvt_f32_f16_e32 v17, s41522; SI-NEXT: s_lshr_b32 s4, s23, 161523; SI-NEXT: s_add_i32 s21, s21, 31524; SI-NEXT: v_cvt_f32_f16_e32 v15, s41525; SI-NEXT: s_lshr_b32 s4, s22, 161526; SI-NEXT: s_add_i32 s20, s20, 31527; SI-NEXT: v_cvt_f32_f16_e32 v13, s41528; SI-NEXT: s_lshr_b32 s4, s21, 161529; SI-NEXT: s_add_i32 s19, s19, 31530; SI-NEXT: v_cvt_f32_f16_e32 v11, s41531; SI-NEXT: s_lshr_b32 s4, s20, 161532; SI-NEXT: s_add_i32 s18, s18, 31533; SI-NEXT: v_cvt_f32_f16_e32 v9, s41534; SI-NEXT: s_lshr_b32 s4, s19, 161535; SI-NEXT: s_add_i32 s17, s17, 31536; SI-NEXT: v_cvt_f32_f16_e32 v7, s41537; SI-NEXT: s_lshr_b32 s4, s18, 161538; SI-NEXT: s_add_i32 s16, s16, 31539; SI-NEXT: v_cvt_f32_f16_e32 v5, s41540; SI-NEXT: s_lshr_b32 s4, s17, 161541; SI-NEXT: v_cvt_f32_f16_e32 v3, s41542; SI-NEXT: s_lshr_b32 s4, s16, 161543; SI-NEXT: v_cvt_f32_f16_e32 v16, s241544; SI-NEXT: v_cvt_f32_f16_e32 v14, s231545; SI-NEXT: v_cvt_f32_f16_e32 v12, s221546; SI-NEXT: v_cvt_f32_f16_e32 v10, s211547; SI-NEXT: v_cvt_f32_f16_e32 v8, s201548; SI-NEXT: v_cvt_f32_f16_e32 v6, s191549; SI-NEXT: v_cvt_f32_f16_e32 v4, s181550; SI-NEXT: v_cvt_f32_f16_e32 v2, s171551; SI-NEXT: v_cvt_f32_f16_e32 v0, s161552; SI-NEXT: v_cvt_f32_f16_e32 v1, s41553; SI-NEXT: .LBB9_3: ; %end1554; SI-NEXT: s_setpc_b64 s[30:31]1555; SI-NEXT: .LBB9_4:1556; SI-NEXT: ; implicit-def: $vgpr01557; SI-NEXT: ; implicit-def: $vgpr11558; SI-NEXT: ; implicit-def: $vgpr21559; SI-NEXT: ; implicit-def: $vgpr31560; SI-NEXT: ; implicit-def: $vgpr41561; SI-NEXT: ; implicit-def: $vgpr51562; SI-NEXT: ; implicit-def: $vgpr61563; SI-NEXT: ; implicit-def: $vgpr71564; SI-NEXT: ; implicit-def: $vgpr81565; SI-NEXT: ; implicit-def: $vgpr91566; SI-NEXT: ; implicit-def: $vgpr101567; SI-NEXT: ; implicit-def: $vgpr111568; SI-NEXT: ; implicit-def: $vgpr121569; SI-NEXT: ; implicit-def: $vgpr131570; SI-NEXT: ; implicit-def: $vgpr141571; SI-NEXT: ; implicit-def: $vgpr151572; SI-NEXT: ; implicit-def: $vgpr161573; SI-NEXT: ; implicit-def: $vgpr171574; SI-NEXT: s_branch .LBB9_21575;1576; VI-LABEL: bitcast_v9i32_to_v18f16_scalar:1577; VI: ; %bb.0:1578; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1579; VI-NEXT: s_cmp_lg_u32 s25, 01580; VI-NEXT: s_cbranch_scc0 .LBB9_41581; VI-NEXT: ; %bb.1: ; %cmp.false1582; VI-NEXT: s_cbranch_execnz .LBB9_31583; VI-NEXT: .LBB9_2: ; %cmp.true1584; VI-NEXT: s_add_i32 s24, s24, 31585; VI-NEXT: s_add_i32 s23, s23, 31586; VI-NEXT: s_add_i32 s22, s22, 31587; VI-NEXT: s_add_i32 s21, s21, 31588; VI-NEXT: s_add_i32 s20, s20, 31589; VI-NEXT: s_add_i32 s19, s19, 31590; VI-NEXT: s_add_i32 s18, s18, 31591; VI-NEXT: s_add_i32 s17, s17, 31592; VI-NEXT: s_add_i32 s16, s16, 31593; VI-NEXT: .LBB9_3: ; %end1594; VI-NEXT: v_mov_b32_e32 v0, s161595; VI-NEXT: v_mov_b32_e32 v1, s171596; VI-NEXT: v_mov_b32_e32 v2, s181597; VI-NEXT: v_mov_b32_e32 v3, s191598; VI-NEXT: v_mov_b32_e32 v4, s201599; VI-NEXT: v_mov_b32_e32 v5, s211600; VI-NEXT: v_mov_b32_e32 v6, s221601; VI-NEXT: v_mov_b32_e32 v7, s231602; VI-NEXT: v_mov_b32_e32 v8, s241603; VI-NEXT: s_setpc_b64 s[30:31]1604; VI-NEXT: .LBB9_4:1605; VI-NEXT: s_branch .LBB9_21606;1607; GFX9-LABEL: bitcast_v9i32_to_v18f16_scalar:1608; GFX9: ; %bb.0:1609; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1610; GFX9-NEXT: s_cmp_lg_u32 s25, 01611; GFX9-NEXT: s_cbranch_scc0 .LBB9_41612; GFX9-NEXT: ; %bb.1: ; %cmp.false1613; GFX9-NEXT: s_cbranch_execnz .LBB9_31614; GFX9-NEXT: .LBB9_2: ; %cmp.true1615; GFX9-NEXT: s_add_i32 s24, s24, 31616; GFX9-NEXT: s_add_i32 s23, s23, 31617; GFX9-NEXT: s_add_i32 s22, s22, 31618; GFX9-NEXT: s_add_i32 s21, s21, 31619; GFX9-NEXT: s_add_i32 s20, s20, 31620; GFX9-NEXT: s_add_i32 s19, s19, 31621; GFX9-NEXT: s_add_i32 s18, s18, 31622; GFX9-NEXT: s_add_i32 s17, s17, 31623; GFX9-NEXT: s_add_i32 s16, s16, 31624; GFX9-NEXT: .LBB9_3: ; %end1625; GFX9-NEXT: v_mov_b32_e32 v0, s161626; GFX9-NEXT: v_mov_b32_e32 v1, s171627; GFX9-NEXT: v_mov_b32_e32 v2, s181628; GFX9-NEXT: v_mov_b32_e32 v3, s191629; GFX9-NEXT: v_mov_b32_e32 v4, s201630; GFX9-NEXT: v_mov_b32_e32 v5, s211631; GFX9-NEXT: v_mov_b32_e32 v6, s221632; GFX9-NEXT: v_mov_b32_e32 v7, s231633; GFX9-NEXT: v_mov_b32_e32 v8, s241634; GFX9-NEXT: s_setpc_b64 s[30:31]1635; GFX9-NEXT: .LBB9_4:1636; GFX9-NEXT: s_branch .LBB9_21637;1638; GFX11-LABEL: bitcast_v9i32_to_v18f16_scalar:1639; GFX11: ; %bb.0:1640; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1641; GFX11-NEXT: s_cmp_lg_u32 s21, 01642; GFX11-NEXT: s_mov_b32 s4, 01643; GFX11-NEXT: s_cbranch_scc0 .LBB9_41644; GFX11-NEXT: ; %bb.1: ; %Flow1645; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s41646; GFX11-NEXT: s_cbranch_vccnz .LBB9_31647; GFX11-NEXT: .LBB9_2: ; %cmp.true1648; GFX11-NEXT: s_add_i32 s20, s20, 31649; GFX11-NEXT: s_add_i32 s19, s19, 31650; GFX11-NEXT: s_add_i32 s18, s18, 31651; GFX11-NEXT: s_add_i32 s17, s17, 31652; GFX11-NEXT: s_add_i32 s16, s16, 31653; GFX11-NEXT: s_add_i32 s3, s3, 31654; GFX11-NEXT: s_add_i32 s2, s2, 31655; GFX11-NEXT: s_add_i32 s1, s1, 31656; GFX11-NEXT: s_add_i32 s0, s0, 31657; GFX11-NEXT: .LBB9_3: ; %end1658; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1659; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s11660; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s31661; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s171662; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s191663; GFX11-NEXT: v_mov_b32_e32 v8, s201664; GFX11-NEXT: s_setpc_b64 s[30:31]1665; GFX11-NEXT: .LBB9_4:1666; GFX11-NEXT: s_branch .LBB9_21667 %cmp = icmp eq i32 %b, 01668 br i1 %cmp, label %cmp.true, label %cmp.false1669 1670cmp.true:1671 %a1 = add <9 x i32> %a, splat (i32 3)1672 %a2 = bitcast <9 x i32> %a1 to <18 x half>1673 br label %end1674 1675cmp.false:1676 %a3 = bitcast <9 x i32> %a to <18 x half>1677 br label %end1678 1679end:1680 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1681 ret <18 x half> %phi1682}1683 1684define <9 x i32> @bitcast_v18f16_to_v9i32(<18 x half> %a, i32 %b) {1685; SI-LABEL: bitcast_v18f16_to_v9i32:1686; SI: ; %bb.0:1687; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1688; SI-NEXT: v_cvt_f16_f32_e32 v31, v11689; SI-NEXT: v_cvt_f16_f32_e32 v30, v01690; SI-NEXT: v_cvt_f16_f32_e32 v29, v31691; SI-NEXT: v_cvt_f16_f32_e32 v28, v21692; SI-NEXT: v_cvt_f16_f32_e32 v27, v51693; SI-NEXT: v_cvt_f16_f32_e32 v26, v41694; SI-NEXT: v_cvt_f16_f32_e32 v25, v71695; SI-NEXT: v_cvt_f16_f32_e32 v24, v61696; SI-NEXT: v_cvt_f16_f32_e32 v23, v91697; SI-NEXT: v_cvt_f16_f32_e32 v22, v81698; SI-NEXT: v_cvt_f16_f32_e32 v21, v111699; SI-NEXT: v_cvt_f16_f32_e32 v20, v101700; SI-NEXT: v_cvt_f16_f32_e32 v19, v131701; SI-NEXT: v_cvt_f16_f32_e32 v13, v121702; SI-NEXT: v_cvt_f16_f32_e32 v12, v151703; SI-NEXT: v_cvt_f16_f32_e32 v11, v141704; SI-NEXT: v_cvt_f16_f32_e32 v10, v171705; SI-NEXT: v_cvt_f16_f32_e32 v9, v161706; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v181707; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr81708; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc1709; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1710; SI-NEXT: s_cbranch_execnz .LBB10_31711; SI-NEXT: ; %bb.1: ; %Flow1712; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1713; SI-NEXT: s_cbranch_execnz .LBB10_41714; SI-NEXT: .LBB10_2: ; %end1715; SI-NEXT: s_or_b64 exec, exec, s[4:5]1716; SI-NEXT: s_setpc_b64 s[30:31]1717; SI-NEXT: .LBB10_3: ; %cmp.false1718; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v311719; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v291720; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v271721; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v251722; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v231723; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v211724; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v191725; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v121726; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v101727; SI-NEXT: v_or_b32_e32 v0, v30, v01728; SI-NEXT: v_or_b32_e32 v1, v28, v11729; SI-NEXT: v_or_b32_e32 v2, v26, v21730; SI-NEXT: v_or_b32_e32 v3, v24, v31731; SI-NEXT: v_or_b32_e32 v4, v22, v41732; SI-NEXT: v_or_b32_e32 v5, v20, v51733; SI-NEXT: v_or_b32_e32 v6, v13, v61734; SI-NEXT: v_or_b32_e32 v7, v11, v71735; SI-NEXT: v_or_b32_e32 v8, v9, v81736; SI-NEXT: ; implicit-def: $vgpr311737; SI-NEXT: ; implicit-def: $vgpr301738; SI-NEXT: ; implicit-def: $vgpr291739; SI-NEXT: ; implicit-def: $vgpr281740; SI-NEXT: ; implicit-def: $vgpr271741; SI-NEXT: ; implicit-def: $vgpr261742; SI-NEXT: ; implicit-def: $vgpr251743; SI-NEXT: ; implicit-def: $vgpr241744; SI-NEXT: ; implicit-def: $vgpr231745; SI-NEXT: ; implicit-def: $vgpr221746; SI-NEXT: ; implicit-def: $vgpr211747; SI-NEXT: ; implicit-def: $vgpr201748; SI-NEXT: ; implicit-def: $vgpr191749; SI-NEXT: ; implicit-def: $vgpr131750; SI-NEXT: ; implicit-def: $vgpr121751; SI-NEXT: ; implicit-def: $vgpr111752; SI-NEXT: ; implicit-def: $vgpr101753; SI-NEXT: ; implicit-def: $vgpr91754; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1755; SI-NEXT: s_cbranch_execz .LBB10_21756; SI-NEXT: .LBB10_4: ; %cmp.true1757; SI-NEXT: v_cvt_f32_f16_e32 v0, v311758; SI-NEXT: v_cvt_f32_f16_e32 v2, v291759; SI-NEXT: v_cvt_f32_f16_e32 v1, v301760; SI-NEXT: v_cvt_f32_f16_e32 v3, v281761; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01762; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21763; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11764; SI-NEXT: v_cvt_f16_f32_e32 v0, v01765; SI-NEXT: v_cvt_f16_f32_e32 v2, v21766; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v31767; SI-NEXT: v_cvt_f16_f32_e32 v1, v11768; SI-NEXT: v_cvt_f16_f32_e32 v3, v31769; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01770; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21771; SI-NEXT: v_or_b32_e32 v0, v1, v01772; SI-NEXT: v_or_b32_e32 v1, v3, v21773; SI-NEXT: v_cvt_f32_f16_e32 v2, v271774; SI-NEXT: v_cvt_f32_f16_e32 v3, v261775; SI-NEXT: v_cvt_f32_f16_e32 v4, v251776; SI-NEXT: v_cvt_f32_f16_e32 v5, v241777; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21778; SI-NEXT: v_cvt_f16_f32_e32 v2, v21779; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v31780; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41781; SI-NEXT: v_cvt_f16_f32_e32 v3, v31782; SI-NEXT: v_cvt_f16_f32_e32 v4, v41783; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v51784; SI-NEXT: v_cvt_f16_f32_e32 v5, v51785; SI-NEXT: v_cvt_f32_f16_e32 v6, v231786; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21787; SI-NEXT: v_or_b32_e32 v2, v3, v21788; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v41789; SI-NEXT: v_or_b32_e32 v3, v5, v31790; SI-NEXT: v_cvt_f32_f16_e32 v4, v221791; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v61792; SI-NEXT: v_cvt_f32_f16_e32 v6, v211793; SI-NEXT: v_cvt_f16_f32_e32 v5, v51794; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v41795; SI-NEXT: v_cvt_f16_f32_e32 v4, v41796; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61797; SI-NEXT: v_cvt_f16_f32_e32 v6, v61798; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v51799; SI-NEXT: v_cvt_f32_f16_e32 v7, v201800; SI-NEXT: v_or_b32_e32 v4, v4, v51801; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v61802; SI-NEXT: v_cvt_f32_f16_e32 v6, v191803; SI-NEXT: v_cvt_f32_f16_e32 v8, v131804; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v71805; SI-NEXT: v_cvt_f16_f32_e32 v7, v71806; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v61807; SI-NEXT: v_cvt_f16_f32_e32 v6, v61808; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v81809; SI-NEXT: v_cvt_f16_f32_e32 v8, v81810; SI-NEXT: v_or_b32_e32 v5, v7, v51811; SI-NEXT: v_cvt_f32_f16_e32 v7, v121812; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v61813; SI-NEXT: v_or_b32_e32 v6, v8, v61814; SI-NEXT: v_cvt_f32_f16_e32 v8, v111815; SI-NEXT: v_cvt_f32_f16_e32 v10, v101816; SI-NEXT: v_cvt_f32_f16_e32 v9, v91817; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v71818; SI-NEXT: v_cvt_f16_f32_e32 v7, v71819; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v81820; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v101821; SI-NEXT: v_cvt_f16_f32_e32 v8, v81822; SI-NEXT: v_cvt_f16_f32_e32 v10, v101823; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v91824; SI-NEXT: v_cvt_f16_f32_e32 v9, v91825; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v71826; SI-NEXT: v_or_b32_e32 v7, v8, v71827; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v101828; SI-NEXT: v_or_b32_e32 v8, v9, v81829; SI-NEXT: s_or_b64 exec, exec, s[4:5]1830; SI-NEXT: s_setpc_b64 s[30:31]1831;1832; VI-LABEL: bitcast_v18f16_to_v9i32:1833; VI: ; %bb.0:1834; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1835; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v91836; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc1837; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1838; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1839; VI-NEXT: s_cbranch_execz .LBB10_21840; VI-NEXT: ; %bb.1: ; %cmp.true1841; VI-NEXT: v_mov_b32_e32 v9, 0x2001842; VI-NEXT: v_add_f16_sdwa v10, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1843; VI-NEXT: v_add_f16_e32 v8, 0x200, v81844; VI-NEXT: v_or_b32_e32 v8, v8, v101845; VI-NEXT: v_add_f16_sdwa v10, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1846; VI-NEXT: v_add_f16_e32 v7, 0x200, v71847; VI-NEXT: v_or_b32_e32 v7, v7, v101848; VI-NEXT: v_add_f16_sdwa v10, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1849; VI-NEXT: v_add_f16_e32 v6, 0x200, v61850; VI-NEXT: v_or_b32_e32 v6, v6, v101851; VI-NEXT: v_add_f16_sdwa v10, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1852; VI-NEXT: v_add_f16_e32 v5, 0x200, v51853; VI-NEXT: v_or_b32_e32 v5, v5, v101854; VI-NEXT: v_add_f16_sdwa v10, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1855; VI-NEXT: v_add_f16_e32 v4, 0x200, v41856; VI-NEXT: v_or_b32_e32 v4, v4, v101857; VI-NEXT: v_add_f16_sdwa v10, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1858; VI-NEXT: v_add_f16_e32 v3, 0x200, v31859; VI-NEXT: v_or_b32_e32 v3, v3, v101860; VI-NEXT: v_add_f16_sdwa v10, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1861; VI-NEXT: v_add_f16_e32 v2, 0x200, v21862; VI-NEXT: v_or_b32_e32 v2, v2, v101863; VI-NEXT: v_add_f16_sdwa v10, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1864; VI-NEXT: v_add_f16_e32 v1, 0x200, v11865; VI-NEXT: v_add_f16_sdwa v9, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD1866; VI-NEXT: v_add_f16_e32 v0, 0x200, v01867; VI-NEXT: v_or_b32_e32 v1, v1, v101868; VI-NEXT: v_or_b32_e32 v0, v0, v91869; VI-NEXT: .LBB10_2: ; %end1870; VI-NEXT: s_or_b64 exec, exec, s[4:5]1871; VI-NEXT: s_setpc_b64 s[30:31]1872;1873; GFX9-LABEL: bitcast_v18f16_to_v9i32:1874; GFX9: ; %bb.0:1875; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1876; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v91877; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc1878; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]1879; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]1880; GFX9-NEXT: s_cbranch_execz .LBB10_21881; GFX9-NEXT: ; %bb.1: ; %cmp.true1882; GFX9-NEXT: s_movk_i32 s6, 0x2001883; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]1884; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]1885; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]1886; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]1887; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]1888; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]1889; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]1890; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]1891; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]1892; GFX9-NEXT: .LBB10_2: ; %end1893; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]1894; GFX9-NEXT: s_setpc_b64 s[30:31]1895;1896; GFX11-LABEL: bitcast_v18f16_to_v9i32:1897; GFX11: ; %bb.0:1898; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1899; GFX11-NEXT: s_mov_b32 s0, exec_lo1900; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v91901; GFX11-NEXT: s_xor_b32 s0, exec_lo, s01902; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1903; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s01904; GFX11-NEXT: s_cbranch_execz .LBB10_21905; GFX11-NEXT: ; %bb.1: ; %cmp.true1906; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]1907; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]1908; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]1909; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]1910; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]1911; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]1912; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]1913; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]1914; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]1915; GFX11-NEXT: .LBB10_2: ; %end1916; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s01917; GFX11-NEXT: s_setpc_b64 s[30:31]1918 %cmp = icmp eq i32 %b, 01919 br i1 %cmp, label %cmp.true, label %cmp.false1920 1921cmp.true:1922 %a1 = fadd <18 x half> %a, splat (half 0xH0200)1923 %a2 = bitcast <18 x half> %a1 to <9 x i32>1924 br label %end1925 1926cmp.false:1927 %a3 = bitcast <18 x half> %a to <9 x i32>1928 br label %end1929 1930end:1931 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1932 ret <9 x i32> %phi1933}1934 1935define inreg <9 x i32> @bitcast_v18f16_to_v9i32_scalar(<18 x half> inreg %a, i32 inreg %b) {1936; SI-LABEL: bitcast_v18f16_to_v9i32_scalar:1937; SI: ; %bb.0:1938; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1939; SI-NEXT: v_cvt_f16_f32_e32 v26, s171940; SI-NEXT: v_cvt_f16_f32_e32 v25, s161941; SI-NEXT: v_cvt_f16_f32_e32 v24, s191942; SI-NEXT: v_cvt_f16_f32_e32 v23, s181943; SI-NEXT: v_cvt_f16_f32_e32 v22, s211944; SI-NEXT: v_cvt_f16_f32_e32 v21, s201945; SI-NEXT: v_cvt_f16_f32_e32 v20, s231946; SI-NEXT: v_cvt_f16_f32_e32 v19, s221947; SI-NEXT: v_cvt_f16_f32_e32 v18, s251948; SI-NEXT: v_cvt_f16_f32_e32 v17, s241949; SI-NEXT: v_cvt_f16_f32_e32 v16, s271950; SI-NEXT: v_cvt_f16_f32_e32 v15, s261951; SI-NEXT: v_cvt_f16_f32_e32 v14, s291952; SI-NEXT: v_cvt_f16_f32_e32 v13, s281953; SI-NEXT: v_cvt_f16_f32_e32 v12, v11954; SI-NEXT: v_cvt_f16_f32_e32 v11, v01955; SI-NEXT: v_cvt_f16_f32_e32 v10, v31956; SI-NEXT: v_cvt_f16_f32_e32 v9, v21957; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v41958; SI-NEXT: s_and_b64 s[4:5], vcc, exec1959; SI-NEXT: s_cbranch_scc0 .LBB11_41960; SI-NEXT: ; %bb.1: ; %cmp.false1961; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v261962; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v241963; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v221964; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v201965; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v181966; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v161967; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v141968; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v121969; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v101970; SI-NEXT: v_or_b32_e32 v0, v25, v01971; SI-NEXT: v_or_b32_e32 v1, v23, v11972; SI-NEXT: v_or_b32_e32 v2, v21, v21973; SI-NEXT: v_or_b32_e32 v3, v19, v31974; SI-NEXT: v_or_b32_e32 v4, v17, v41975; SI-NEXT: v_or_b32_e32 v5, v15, v51976; SI-NEXT: v_or_b32_e32 v6, v13, v61977; SI-NEXT: v_or_b32_e32 v7, v11, v71978; SI-NEXT: v_or_b32_e32 v8, v9, v81979; SI-NEXT: s_cbranch_execnz .LBB11_31980; SI-NEXT: .LBB11_2: ; %cmp.true1981; SI-NEXT: v_cvt_f32_f16_e32 v0, v261982; SI-NEXT: v_cvt_f32_f16_e32 v2, v241983; SI-NEXT: v_cvt_f32_f16_e32 v1, v251984; SI-NEXT: v_cvt_f32_f16_e32 v3, v231985; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v01986; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v21987; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v11988; SI-NEXT: v_cvt_f16_f32_e32 v0, v01989; SI-NEXT: v_cvt_f16_f32_e32 v2, v21990; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v31991; SI-NEXT: v_cvt_f16_f32_e32 v1, v11992; SI-NEXT: v_cvt_f16_f32_e32 v3, v31993; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v01994; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v21995; SI-NEXT: v_or_b32_e32 v0, v1, v01996; SI-NEXT: v_or_b32_e32 v1, v3, v21997; SI-NEXT: v_cvt_f32_f16_e32 v2, v221998; SI-NEXT: v_cvt_f32_f16_e32 v3, v211999; SI-NEXT: v_cvt_f32_f16_e32 v4, v202000; SI-NEXT: v_cvt_f32_f16_e32 v5, v192001; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v22002; SI-NEXT: v_cvt_f16_f32_e32 v2, v22003; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v32004; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42005; SI-NEXT: v_cvt_f16_f32_e32 v3, v32006; SI-NEXT: v_cvt_f16_f32_e32 v4, v42007; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v52008; SI-NEXT: v_cvt_f16_f32_e32 v5, v52009; SI-NEXT: v_cvt_f32_f16_e32 v6, v182010; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v22011; SI-NEXT: v_or_b32_e32 v2, v3, v22012; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v42013; SI-NEXT: v_or_b32_e32 v3, v5, v32014; SI-NEXT: v_cvt_f32_f16_e32 v4, v172015; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v62016; SI-NEXT: v_cvt_f32_f16_e32 v6, v162017; SI-NEXT: v_cvt_f16_f32_e32 v5, v52018; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v42019; SI-NEXT: v_cvt_f16_f32_e32 v4, v42020; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v62021; SI-NEXT: v_cvt_f16_f32_e32 v6, v62022; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v52023; SI-NEXT: v_cvt_f32_f16_e32 v7, v152024; SI-NEXT: v_or_b32_e32 v4, v4, v52025; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v62026; SI-NEXT: v_cvt_f32_f16_e32 v6, v142027; SI-NEXT: v_cvt_f32_f16_e32 v8, v132028; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v72029; SI-NEXT: v_cvt_f16_f32_e32 v7, v72030; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v62031; SI-NEXT: v_cvt_f16_f32_e32 v6, v62032; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v82033; SI-NEXT: v_cvt_f16_f32_e32 v8, v82034; SI-NEXT: v_or_b32_e32 v5, v7, v52035; SI-NEXT: v_cvt_f32_f16_e32 v7, v122036; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v62037; SI-NEXT: v_or_b32_e32 v6, v8, v62038; SI-NEXT: v_cvt_f32_f16_e32 v8, v112039; SI-NEXT: v_cvt_f32_f16_e32 v10, v102040; SI-NEXT: v_cvt_f32_f16_e32 v9, v92041; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v72042; SI-NEXT: v_cvt_f16_f32_e32 v7, v72043; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v82044; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v102045; SI-NEXT: v_cvt_f16_f32_e32 v8, v82046; SI-NEXT: v_cvt_f16_f32_e32 v10, v102047; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v92048; SI-NEXT: v_cvt_f16_f32_e32 v9, v92049; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v72050; SI-NEXT: v_or_b32_e32 v7, v8, v72051; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v102052; SI-NEXT: v_or_b32_e32 v8, v9, v82053; SI-NEXT: .LBB11_3: ; %end2054; SI-NEXT: s_setpc_b64 s[30:31]2055; SI-NEXT: .LBB11_4:2056; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr82057; SI-NEXT: s_branch .LBB11_22058;2059; VI-LABEL: bitcast_v18f16_to_v9i32_scalar:2060; VI: ; %bb.0:2061; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2062; VI-NEXT: s_cmp_lg_u32 s25, 02063; VI-NEXT: s_cbranch_scc0 .LBB11_32064; VI-NEXT: ; %bb.1: ; %cmp.false2065; VI-NEXT: s_cbranch_execnz .LBB11_42066; VI-NEXT: .LBB11_2: ; %cmp.true2067; VI-NEXT: s_lshr_b32 s4, s24, 162068; VI-NEXT: v_mov_b32_e32 v0, 0x2002069; VI-NEXT: v_mov_b32_e32 v1, s42070; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2071; VI-NEXT: v_add_f16_e32 v2, s24, v02072; VI-NEXT: s_lshr_b32 s4, s23, 162073; VI-NEXT: v_or_b32_e32 v8, v2, v12074; VI-NEXT: v_mov_b32_e32 v1, s42075; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2076; VI-NEXT: v_add_f16_e32 v2, s23, v02077; VI-NEXT: s_lshr_b32 s4, s22, 162078; VI-NEXT: v_or_b32_e32 v7, v2, v12079; VI-NEXT: v_mov_b32_e32 v1, s42080; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2081; VI-NEXT: v_add_f16_e32 v2, s22, v02082; VI-NEXT: s_lshr_b32 s4, s21, 162083; VI-NEXT: v_or_b32_e32 v6, v2, v12084; VI-NEXT: v_mov_b32_e32 v1, s42085; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2086; VI-NEXT: v_add_f16_e32 v2, s21, v02087; VI-NEXT: s_lshr_b32 s4, s20, 162088; VI-NEXT: v_or_b32_e32 v5, v2, v12089; VI-NEXT: v_mov_b32_e32 v1, s42090; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2091; VI-NEXT: v_add_f16_e32 v2, s20, v02092; VI-NEXT: s_lshr_b32 s4, s19, 162093; VI-NEXT: v_or_b32_e32 v4, v2, v12094; VI-NEXT: v_mov_b32_e32 v1, s42095; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2096; VI-NEXT: v_add_f16_e32 v2, s19, v02097; VI-NEXT: s_lshr_b32 s4, s18, 162098; VI-NEXT: v_or_b32_e32 v3, v2, v12099; VI-NEXT: v_mov_b32_e32 v1, s42100; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2101; VI-NEXT: v_add_f16_e32 v2, s18, v02102; VI-NEXT: s_lshr_b32 s4, s17, 162103; VI-NEXT: v_or_b32_e32 v2, v2, v12104; VI-NEXT: v_mov_b32_e32 v1, s42105; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2106; VI-NEXT: v_add_f16_e32 v9, s17, v02107; VI-NEXT: s_lshr_b32 s4, s16, 162108; VI-NEXT: v_or_b32_e32 v1, v9, v12109; VI-NEXT: v_mov_b32_e32 v9, s42110; VI-NEXT: v_add_f16_sdwa v9, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2111; VI-NEXT: v_add_f16_e32 v0, s16, v02112; VI-NEXT: v_or_b32_e32 v0, v0, v92113; VI-NEXT: s_setpc_b64 s[30:31]2114; VI-NEXT: .LBB11_3:2115; VI-NEXT: s_branch .LBB11_22116; VI-NEXT: .LBB11_4:2117; VI-NEXT: v_mov_b32_e32 v0, s162118; VI-NEXT: v_mov_b32_e32 v1, s172119; VI-NEXT: v_mov_b32_e32 v2, s182120; VI-NEXT: v_mov_b32_e32 v3, s192121; VI-NEXT: v_mov_b32_e32 v4, s202122; VI-NEXT: v_mov_b32_e32 v5, s212123; VI-NEXT: v_mov_b32_e32 v6, s222124; VI-NEXT: v_mov_b32_e32 v7, s232125; VI-NEXT: v_mov_b32_e32 v8, s242126; VI-NEXT: s_setpc_b64 s[30:31]2127;2128; GFX9-LABEL: bitcast_v18f16_to_v9i32_scalar:2129; GFX9: ; %bb.0:2130; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2131; GFX9-NEXT: s_cmp_lg_u32 s25, 02132; GFX9-NEXT: s_cbranch_scc0 .LBB11_32133; GFX9-NEXT: ; %bb.1: ; %cmp.false2134; GFX9-NEXT: s_cbranch_execnz .LBB11_42135; GFX9-NEXT: .LBB11_2: ; %cmp.true2136; GFX9-NEXT: v_mov_b32_e32 v0, 0x2002137; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]2138; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]2139; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]2140; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]2141; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]2142; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]2143; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]2144; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]2145; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]2146; GFX9-NEXT: s_setpc_b64 s[30:31]2147; GFX9-NEXT: .LBB11_3:2148; GFX9-NEXT: s_branch .LBB11_22149; GFX9-NEXT: .LBB11_4:2150; GFX9-NEXT: v_mov_b32_e32 v0, s162151; GFX9-NEXT: v_mov_b32_e32 v1, s172152; GFX9-NEXT: v_mov_b32_e32 v2, s182153; GFX9-NEXT: v_mov_b32_e32 v3, s192154; GFX9-NEXT: v_mov_b32_e32 v4, s202155; GFX9-NEXT: v_mov_b32_e32 v5, s212156; GFX9-NEXT: v_mov_b32_e32 v6, s222157; GFX9-NEXT: v_mov_b32_e32 v7, s232158; GFX9-NEXT: v_mov_b32_e32 v8, s242159; GFX9-NEXT: s_setpc_b64 s[30:31]2160;2161; GFX11-LABEL: bitcast_v18f16_to_v9i32_scalar:2162; GFX11: ; %bb.0:2163; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2164; GFX11-NEXT: s_mov_b32 s15, s32165; GFX11-NEXT: s_mov_b32 s14, s22166; GFX11-NEXT: s_mov_b32 s13, s12167; GFX11-NEXT: s_mov_b32 s12, s02168; GFX11-NEXT: s_cmp_lg_u32 s21, 02169; GFX11-NEXT: s_mov_b32 s0, 02170; GFX11-NEXT: s_cbranch_scc0 .LBB11_32171; GFX11-NEXT: ; %bb.1: ; %Flow2172; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s02173; GFX11-NEXT: s_cbranch_vccnz .LBB11_42174; GFX11-NEXT: .LBB11_2: ; %cmp.true2175; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]2176; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]2177; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]2178; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]2179; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]2180; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]2181; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]2182; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]2183; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]2184; GFX11-NEXT: s_setpc_b64 s[30:31]2185; GFX11-NEXT: .LBB11_3:2186; GFX11-NEXT: s_branch .LBB11_22187; GFX11-NEXT: .LBB11_4:2188; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s132189; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s152190; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172191; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192192; GFX11-NEXT: v_mov_b32_e32 v8, s202193; GFX11-NEXT: s_setpc_b64 s[30:31]2194 %cmp = icmp eq i32 %b, 02195 br i1 %cmp, label %cmp.true, label %cmp.false2196 2197cmp.true:2198 %a1 = fadd <18 x half> %a, splat (half 0xH0200)2199 %a2 = bitcast <18 x half> %a1 to <9 x i32>2200 br label %end2201 2202cmp.false:2203 %a3 = bitcast <18 x half> %a to <9 x i32>2204 br label %end2205 2206end:2207 %phi = phi <9 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2208 ret <9 x i32> %phi2209}2210 2211define <18 x i16> @bitcast_v9f32_to_v18i16(<9 x float> %a, i32 %b) {2212; SI-LABEL: bitcast_v9f32_to_v18i16:2213; SI: ; %bb.0:2214; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2215; SI-NEXT: v_mov_b32_e32 v16, v82216; SI-NEXT: v_mov_b32_e32 v14, v72217; SI-NEXT: v_mov_b32_e32 v12, v62218; SI-NEXT: v_mov_b32_e32 v10, v52219; SI-NEXT: v_mov_b32_e32 v8, v42220; SI-NEXT: v_mov_b32_e32 v6, v32221; SI-NEXT: v_mov_b32_e32 v4, v22222; SI-NEXT: v_mov_b32_e32 v2, v12223; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v92224; SI-NEXT: ; implicit-def: $vgpr12225; SI-NEXT: ; implicit-def: $vgpr32226; SI-NEXT: ; implicit-def: $vgpr52227; SI-NEXT: ; implicit-def: $vgpr72228; SI-NEXT: ; implicit-def: $vgpr92229; SI-NEXT: ; implicit-def: $vgpr112230; SI-NEXT: ; implicit-def: $vgpr132231; SI-NEXT: ; implicit-def: $vgpr152232; SI-NEXT: ; implicit-def: $vgpr172233; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2234; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2235; SI-NEXT: s_cbranch_execnz .LBB12_32236; SI-NEXT: ; %bb.1: ; %Flow2237; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2238; SI-NEXT: s_cbranch_execnz .LBB12_42239; SI-NEXT: .LBB12_2: ; %end2240; SI-NEXT: s_or_b64 exec, exec, s[4:5]2241; SI-NEXT: s_setpc_b64 s[30:31]2242; SI-NEXT: .LBB12_3: ; %cmp.false2243; SI-NEXT: v_alignbit_b32 v17, v0, v16, 162244; SI-NEXT: v_alignbit_b32 v13, v14, v12, 162245; SI-NEXT: v_alignbit_b32 v9, v10, v8, 162246; SI-NEXT: v_alignbit_b32 v5, v6, v4, 162247; SI-NEXT: v_alignbit_b32 v1, v2, v0, 162248; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v142249; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v102250; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v62251; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22252; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2253; SI-NEXT: s_cbranch_execz .LBB12_22254; SI-NEXT: .LBB12_4: ; %cmp.true2255; SI-NEXT: v_add_f32_e32 v16, 1.0, v162256; SI-NEXT: v_add_f32_e32 v2, 1.0, v22257; SI-NEXT: v_add_f32_e32 v0, 1.0, v02258; SI-NEXT: v_add_f32_e32 v6, 1.0, v62259; SI-NEXT: v_add_f32_e32 v4, 1.0, v42260; SI-NEXT: v_add_f32_e32 v10, 1.0, v102261; SI-NEXT: v_add_f32_e32 v8, 1.0, v82262; SI-NEXT: v_add_f32_e32 v14, 1.0, v142263; SI-NEXT: v_add_f32_e32 v12, 1.0, v122264; SI-NEXT: v_alignbit_b32 v13, v14, v12, 162265; SI-NEXT: v_alignbit_b32 v9, v10, v8, 162266; SI-NEXT: v_alignbit_b32 v5, v6, v4, 162267; SI-NEXT: v_alignbit_b32 v1, v2, v0, 162268; SI-NEXT: v_alignbit_b32 v17, v0, v16, 162269; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v142270; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v102271; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v62272; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v22273; SI-NEXT: s_or_b64 exec, exec, s[4:5]2274; SI-NEXT: s_setpc_b64 s[30:31]2275;2276; VI-LABEL: bitcast_v9f32_to_v18i16:2277; VI: ; %bb.0:2278; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2279; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v92280; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2281; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2282; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2283; VI-NEXT: ; %bb.1: ; %cmp.true2284; VI-NEXT: v_add_f32_e32 v8, 1.0, v82285; VI-NEXT: v_add_f32_e32 v7, 1.0, v72286; VI-NEXT: v_add_f32_e32 v6, 1.0, v62287; VI-NEXT: v_add_f32_e32 v5, 1.0, v52288; VI-NEXT: v_add_f32_e32 v4, 1.0, v42289; VI-NEXT: v_add_f32_e32 v3, 1.0, v32290; VI-NEXT: v_add_f32_e32 v2, 1.0, v22291; VI-NEXT: v_add_f32_e32 v1, 1.0, v12292; VI-NEXT: v_add_f32_e32 v0, 1.0, v02293; VI-NEXT: ; %bb.2: ; %end2294; VI-NEXT: s_or_b64 exec, exec, s[4:5]2295; VI-NEXT: s_setpc_b64 s[30:31]2296;2297; GFX9-LABEL: bitcast_v9f32_to_v18i16:2298; GFX9: ; %bb.0:2299; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2300; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v92301; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2302; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2303; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2304; GFX9-NEXT: ; %bb.1: ; %cmp.true2305; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v82306; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v72307; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v62308; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v52309; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v42310; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v32311; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v22312; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v12313; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v02314; GFX9-NEXT: ; %bb.2: ; %end2315; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2316; GFX9-NEXT: s_setpc_b64 s[30:31]2317;2318; GFX11-LABEL: bitcast_v9f32_to_v18i16:2319; GFX11: ; %bb.0:2320; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2321; GFX11-NEXT: s_mov_b32 s0, exec_lo2322; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v92323; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02324; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2325; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02326; GFX11-NEXT: ; %bb.1: ; %cmp.true2327; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v72328; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v52329; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v32330; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v12331; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v02332; GFX11-NEXT: ; %bb.2: ; %end2333; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02334; GFX11-NEXT: s_setpc_b64 s[30:31]2335 %cmp = icmp eq i32 %b, 02336 br i1 %cmp, label %cmp.true, label %cmp.false2337 2338cmp.true:2339 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)2340 %a2 = bitcast <9 x float> %a1 to <18 x i16>2341 br label %end2342 2343cmp.false:2344 %a3 = bitcast <9 x float> %a to <18 x i16>2345 br label %end2346 2347end:2348 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2349 ret <18 x i16> %phi2350}2351 2352define inreg <18 x i16> @bitcast_v9f32_to_v18i16_scalar(<9 x float> inreg %a, i32 inreg %b) {2353; SI-LABEL: bitcast_v9f32_to_v18i16_scalar:2354; SI: ; %bb.0:2355; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2356; SI-NEXT: s_cmp_lg_u32 s25, 02357; SI-NEXT: s_cbranch_scc0 .LBB13_32358; SI-NEXT: ; %bb.1: ; %cmp.false2359; SI-NEXT: s_lshr_b32 s25, s17, 162360; SI-NEXT: s_lshr_b32 s28, s23, 162361; SI-NEXT: s_lshr_b32 s27, s21, 162362; SI-NEXT: s_lshr_b32 s26, s19, 162363; SI-NEXT: s_lshr_b64 s[8:9], s[24:25], 162364; SI-NEXT: s_lshr_b64 s[4:5], s[22:23], 162365; SI-NEXT: s_lshr_b64 s[6:7], s[20:21], 162366; SI-NEXT: s_lshr_b64 s[10:11], s[18:19], 162367; SI-NEXT: s_lshr_b64 s[12:13], s[16:17], 162368; SI-NEXT: s_cbranch_execnz .LBB13_42369; SI-NEXT: .LBB13_2: ; %cmp.true2370; SI-NEXT: v_add_f32_e64 v16, s24, 1.02371; SI-NEXT: v_add_f32_e64 v26, s17, 1.02372; SI-NEXT: v_add_f32_e64 v25, s16, 1.02373; SI-NEXT: v_add_f32_e64 v24, s19, 1.02374; SI-NEXT: v_add_f32_e64 v23, s18, 1.02375; SI-NEXT: v_add_f32_e64 v22, s21, 1.02376; SI-NEXT: v_add_f32_e64 v21, s20, 1.02377; SI-NEXT: v_add_f32_e64 v20, s23, 1.02378; SI-NEXT: v_add_f32_e64 v19, s22, 1.02379; SI-NEXT: v_lshr_b64 v[13:14], v[19:20], 162380; SI-NEXT: v_lshr_b64 v[9:10], v[21:22], 162381; SI-NEXT: v_lshr_b64 v[5:6], v[23:24], 162382; SI-NEXT: v_lshr_b64 v[1:2], v[25:26], 162383; SI-NEXT: v_lshr_b64 v[17:18], v[16:17], 162384; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v202385; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v222386; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v242387; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v262388; SI-NEXT: s_branch .LBB13_52389; SI-NEXT: .LBB13_3:2390; SI-NEXT: ; implicit-def: $sgpr122391; SI-NEXT: ; implicit-def: $sgpr252392; SI-NEXT: ; implicit-def: $sgpr102393; SI-NEXT: ; implicit-def: $sgpr262394; SI-NEXT: ; implicit-def: $sgpr62395; SI-NEXT: ; implicit-def: $sgpr272396; SI-NEXT: ; implicit-def: $sgpr42397; SI-NEXT: ; implicit-def: $sgpr282398; SI-NEXT: ; implicit-def: $sgpr82399; SI-NEXT: s_branch .LBB13_22400; SI-NEXT: .LBB13_4:2401; SI-NEXT: v_mov_b32_e32 v25, s162402; SI-NEXT: v_mov_b32_e32 v26, s172403; SI-NEXT: v_mov_b32_e32 v23, s182404; SI-NEXT: v_mov_b32_e32 v24, s192405; SI-NEXT: v_mov_b32_e32 v21, s202406; SI-NEXT: v_mov_b32_e32 v22, s212407; SI-NEXT: v_mov_b32_e32 v19, s222408; SI-NEXT: v_mov_b32_e32 v20, s232409; SI-NEXT: v_mov_b32_e32 v16, s242410; SI-NEXT: v_mov_b32_e32 v3, s252411; SI-NEXT: v_mov_b32_e32 v7, s262412; SI-NEXT: v_mov_b32_e32 v11, s272413; SI-NEXT: v_mov_b32_e32 v15, s282414; SI-NEXT: v_mov_b32_e32 v17, s82415; SI-NEXT: v_mov_b32_e32 v1, s122416; SI-NEXT: v_mov_b32_e32 v5, s102417; SI-NEXT: v_mov_b32_e32 v9, s62418; SI-NEXT: v_mov_b32_e32 v13, s42419; SI-NEXT: .LBB13_5: ; %end2420; SI-NEXT: v_mov_b32_e32 v0, v252421; SI-NEXT: v_mov_b32_e32 v2, v262422; SI-NEXT: v_mov_b32_e32 v4, v232423; SI-NEXT: v_mov_b32_e32 v6, v242424; SI-NEXT: v_mov_b32_e32 v8, v212425; SI-NEXT: v_mov_b32_e32 v10, v222426; SI-NEXT: v_mov_b32_e32 v12, v192427; SI-NEXT: v_mov_b32_e32 v14, v202428; SI-NEXT: s_setpc_b64 s[30:31]2429;2430; VI-LABEL: bitcast_v9f32_to_v18i16_scalar:2431; VI: ; %bb.0:2432; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2433; VI-NEXT: s_cmp_lg_u32 s25, 02434; VI-NEXT: s_cbranch_scc0 .LBB13_32435; VI-NEXT: ; %bb.1: ; %cmp.false2436; VI-NEXT: s_cbranch_execnz .LBB13_42437; VI-NEXT: .LBB13_2: ; %cmp.true2438; VI-NEXT: v_add_f32_e64 v8, s24, 1.02439; VI-NEXT: v_add_f32_e64 v7, s23, 1.02440; VI-NEXT: v_add_f32_e64 v6, s22, 1.02441; VI-NEXT: v_add_f32_e64 v5, s21, 1.02442; VI-NEXT: v_add_f32_e64 v4, s20, 1.02443; VI-NEXT: v_add_f32_e64 v3, s19, 1.02444; VI-NEXT: v_add_f32_e64 v2, s18, 1.02445; VI-NEXT: v_add_f32_e64 v1, s17, 1.02446; VI-NEXT: v_add_f32_e64 v0, s16, 1.02447; VI-NEXT: s_setpc_b64 s[30:31]2448; VI-NEXT: .LBB13_3:2449; VI-NEXT: s_branch .LBB13_22450; VI-NEXT: .LBB13_4:2451; VI-NEXT: v_mov_b32_e32 v0, s162452; VI-NEXT: v_mov_b32_e32 v1, s172453; VI-NEXT: v_mov_b32_e32 v2, s182454; VI-NEXT: v_mov_b32_e32 v3, s192455; VI-NEXT: v_mov_b32_e32 v4, s202456; VI-NEXT: v_mov_b32_e32 v5, s212457; VI-NEXT: v_mov_b32_e32 v6, s222458; VI-NEXT: v_mov_b32_e32 v7, s232459; VI-NEXT: v_mov_b32_e32 v8, s242460; VI-NEXT: v_mov_b32_e32 v9, s252461; VI-NEXT: v_mov_b32_e32 v10, s262462; VI-NEXT: v_mov_b32_e32 v11, s272463; VI-NEXT: v_mov_b32_e32 v12, s282464; VI-NEXT: v_mov_b32_e32 v13, s292465; VI-NEXT: v_mov_b32_e32 v14, s302466; VI-NEXT: v_mov_b32_e32 v15, s312467; VI-NEXT: s_setpc_b64 s[30:31]2468;2469; GFX9-LABEL: bitcast_v9f32_to_v18i16_scalar:2470; GFX9: ; %bb.0:2471; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2472; GFX9-NEXT: s_cmp_lg_u32 s25, 02473; GFX9-NEXT: s_cbranch_scc0 .LBB13_32474; GFX9-NEXT: ; %bb.1: ; %cmp.false2475; GFX9-NEXT: s_cbranch_execnz .LBB13_42476; GFX9-NEXT: .LBB13_2: ; %cmp.true2477; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.02478; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.02479; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.02480; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.02481; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.02482; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.02483; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.02484; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.02485; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.02486; GFX9-NEXT: s_setpc_b64 s[30:31]2487; GFX9-NEXT: .LBB13_3:2488; GFX9-NEXT: s_branch .LBB13_22489; GFX9-NEXT: .LBB13_4:2490; GFX9-NEXT: v_mov_b32_e32 v0, s162491; GFX9-NEXT: v_mov_b32_e32 v1, s172492; GFX9-NEXT: v_mov_b32_e32 v2, s182493; GFX9-NEXT: v_mov_b32_e32 v3, s192494; GFX9-NEXT: v_mov_b32_e32 v4, s202495; GFX9-NEXT: v_mov_b32_e32 v5, s212496; GFX9-NEXT: v_mov_b32_e32 v6, s222497; GFX9-NEXT: v_mov_b32_e32 v7, s232498; GFX9-NEXT: v_mov_b32_e32 v8, s242499; GFX9-NEXT: v_mov_b32_e32 v9, s252500; GFX9-NEXT: v_mov_b32_e32 v10, s262501; GFX9-NEXT: v_mov_b32_e32 v11, s272502; GFX9-NEXT: v_mov_b32_e32 v12, s282503; GFX9-NEXT: v_mov_b32_e32 v13, s292504; GFX9-NEXT: v_mov_b32_e32 v14, s302505; GFX9-NEXT: v_mov_b32_e32 v15, s312506; GFX9-NEXT: s_setpc_b64 s[30:31]2507;2508; GFX11-LABEL: bitcast_v9f32_to_v18i16_scalar:2509; GFX11: ; %bb.0:2510; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2511; GFX11-NEXT: s_mov_b32 s15, s32512; GFX11-NEXT: s_mov_b32 s14, s22513; GFX11-NEXT: s_mov_b32 s13, s12514; GFX11-NEXT: s_mov_b32 s12, s02515; GFX11-NEXT: s_cmp_lg_u32 s21, 02516; GFX11-NEXT: s_mov_b32 s0, 02517; GFX11-NEXT: s_cbranch_scc0 .LBB13_32518; GFX11-NEXT: ; %bb.1: ; %Flow2519; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s02520; GFX11-NEXT: s_cbranch_vccnz .LBB13_42521; GFX11-NEXT: .LBB13_2: ; %cmp.true2522; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.02523; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.02524; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.02525; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.02526; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.02527; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.02528; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.02529; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.02530; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.02531; GFX11-NEXT: s_setpc_b64 s[30:31]2532; GFX11-NEXT: .LBB13_3:2533; GFX11-NEXT: s_branch .LBB13_22534; GFX11-NEXT: .LBB13_4:2535; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s132536; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s152537; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s172538; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s192539; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s212540; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s232541; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s252542; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s272543; GFX11-NEXT: s_setpc_b64 s[30:31]2544 %cmp = icmp eq i32 %b, 02545 br i1 %cmp, label %cmp.true, label %cmp.false2546 2547cmp.true:2548 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)2549 %a2 = bitcast <9 x float> %a1 to <18 x i16>2550 br label %end2551 2552cmp.false:2553 %a3 = bitcast <9 x float> %a to <18 x i16>2554 br label %end2555 2556end:2557 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2558 ret <18 x i16> %phi2559}2560 2561define <9 x float> @bitcast_v18i16_to_v9f32(<18 x i16> %a, i32 %b) {2562; SI-LABEL: bitcast_v18i16_to_v9f32:2563; SI: ; %bb.0:2564; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2565; SI-NEXT: v_mov_b32_e32 v23, v82566; SI-NEXT: v_mov_b32_e32 v22, v62567; SI-NEXT: v_mov_b32_e32 v21, v42568; SI-NEXT: v_mov_b32_e32 v20, v22569; SI-NEXT: v_mov_b32_e32 v19, v02570; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v182571; SI-NEXT: v_lshlrev_b32_e32 v28, 16, v12572; SI-NEXT: v_lshlrev_b32_e32 v27, 16, v32573; SI-NEXT: v_lshlrev_b32_e32 v26, 16, v52574; SI-NEXT: v_lshlrev_b32_e32 v25, 16, v72575; SI-NEXT: v_lshlrev_b32_e32 v24, 16, v92576; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v112577; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v132578; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v152579; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v172580; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr82581; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc2582; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2583; SI-NEXT: s_cbranch_execnz .LBB14_32584; SI-NEXT: ; %bb.1: ; %Flow2585; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2586; SI-NEXT: s_cbranch_execnz .LBB14_42587; SI-NEXT: .LBB14_2: ; %end2588; SI-NEXT: s_or_b64 exec, exec, s[4:5]2589; SI-NEXT: s_setpc_b64 s[30:31]2590; SI-NEXT: .LBB14_3: ; %cmp.false2591; SI-NEXT: v_and_b32_e32 v0, 0xffff, v192592; SI-NEXT: v_and_b32_e32 v1, 0xffff, v202593; SI-NEXT: v_and_b32_e32 v2, 0xffff, v212594; SI-NEXT: v_and_b32_e32 v3, 0xffff, v222595; SI-NEXT: v_and_b32_e32 v4, 0xffff, v232596; SI-NEXT: v_and_b32_e32 v5, 0xffff, v102597; SI-NEXT: v_and_b32_e32 v6, 0xffff, v122598; SI-NEXT: v_and_b32_e32 v7, 0xffff, v142599; SI-NEXT: v_and_b32_e32 v8, 0xffff, v162600; SI-NEXT: v_or_b32_e32 v0, v0, v282601; SI-NEXT: v_or_b32_e32 v1, v1, v272602; SI-NEXT: v_or_b32_e32 v2, v2, v262603; SI-NEXT: v_or_b32_e32 v3, v3, v252604; SI-NEXT: v_or_b32_e32 v4, v4, v242605; SI-NEXT: v_or_b32_e32 v5, v5, v182606; SI-NEXT: v_or_b32_e32 v6, v6, v132607; SI-NEXT: v_or_b32_e32 v7, v7, v112608; SI-NEXT: v_or_b32_e32 v8, v8, v92609; SI-NEXT: ; implicit-def: $vgpr192610; SI-NEXT: ; implicit-def: $vgpr202611; SI-NEXT: ; implicit-def: $vgpr212612; SI-NEXT: ; implicit-def: $vgpr222613; SI-NEXT: ; implicit-def: $vgpr232614; SI-NEXT: ; implicit-def: $vgpr102615; SI-NEXT: ; implicit-def: $vgpr122616; SI-NEXT: ; implicit-def: $vgpr142617; SI-NEXT: ; implicit-def: $vgpr162618; SI-NEXT: ; implicit-def: $vgpr282619; SI-NEXT: ; implicit-def: $vgpr272620; SI-NEXT: ; implicit-def: $vgpr262621; SI-NEXT: ; implicit-def: $vgpr252622; SI-NEXT: ; implicit-def: $vgpr242623; SI-NEXT: ; implicit-def: $vgpr182624; SI-NEXT: ; implicit-def: $vgpr132625; SI-NEXT: ; implicit-def: $vgpr112626; SI-NEXT: ; implicit-def: $vgpr92627; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2628; SI-NEXT: s_cbranch_execz .LBB14_22629; SI-NEXT: .LBB14_4: ; %cmp.true2630; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v192631; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v202632; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v212633; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v222634; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v232635; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v102636; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v122637; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v142638; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v162639; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02640; SI-NEXT: v_and_b32_e32 v1, 0xffff, v12641; SI-NEXT: v_and_b32_e32 v2, 0xffff, v22642; SI-NEXT: v_and_b32_e32 v3, 0xffff, v32643; SI-NEXT: v_and_b32_e32 v4, 0xffff, v42644; SI-NEXT: v_and_b32_e32 v5, 0xffff, v52645; SI-NEXT: v_and_b32_e32 v6, 0xffff, v62646; SI-NEXT: v_and_b32_e32 v7, 0xffff, v72647; SI-NEXT: v_and_b32_e32 v8, 0xffff, v82648; SI-NEXT: v_or_b32_e32 v0, v28, v02649; SI-NEXT: s_mov_b32 s6, 0x300002650; SI-NEXT: v_or_b32_e32 v1, v27, v12651; SI-NEXT: v_or_b32_e32 v2, v26, v22652; SI-NEXT: v_or_b32_e32 v3, v25, v32653; SI-NEXT: v_or_b32_e32 v4, v24, v42654; SI-NEXT: v_or_b32_e32 v5, v18, v52655; SI-NEXT: v_or_b32_e32 v6, v13, v62656; SI-NEXT: v_or_b32_e32 v7, v11, v72657; SI-NEXT: v_or_b32_e32 v8, v9, v82658; SI-NEXT: v_add_i32_e32 v0, vcc, 0x30000, v02659; SI-NEXT: v_add_i32_e32 v1, vcc, s6, v12660; SI-NEXT: v_add_i32_e32 v2, vcc, s6, v22661; SI-NEXT: v_add_i32_e32 v3, vcc, s6, v32662; SI-NEXT: v_add_i32_e32 v4, vcc, s6, v42663; SI-NEXT: v_add_i32_e32 v5, vcc, s6, v52664; SI-NEXT: v_add_i32_e32 v6, vcc, 0x30000, v62665; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v72666; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v82667; SI-NEXT: s_or_b64 exec, exec, s[4:5]2668; SI-NEXT: s_setpc_b64 s[30:31]2669;2670; VI-LABEL: bitcast_v18i16_to_v9f32:2671; VI: ; %bb.0:2672; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2673; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v92674; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc2675; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2676; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2677; VI-NEXT: s_cbranch_execz .LBB14_22678; VI-NEXT: ; %bb.1: ; %cmp.true2679; VI-NEXT: v_mov_b32_e32 v10, 32680; VI-NEXT: v_add_u16_e32 v9, 3, v82681; VI-NEXT: v_add_u16_sdwa v8, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2682; VI-NEXT: v_or_b32_e32 v8, v9, v82683; VI-NEXT: v_add_u16_e32 v9, 3, v72684; VI-NEXT: v_add_u16_sdwa v7, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2685; VI-NEXT: v_or_b32_e32 v7, v9, v72686; VI-NEXT: v_add_u16_e32 v9, 3, v62687; VI-NEXT: v_add_u16_sdwa v6, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2688; VI-NEXT: v_or_b32_e32 v6, v9, v62689; VI-NEXT: v_add_u16_e32 v9, 3, v52690; VI-NEXT: v_add_u16_sdwa v5, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2691; VI-NEXT: v_or_b32_e32 v5, v9, v52692; VI-NEXT: v_add_u16_e32 v9, 3, v42693; VI-NEXT: v_add_u16_sdwa v4, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2694; VI-NEXT: v_or_b32_e32 v4, v9, v42695; VI-NEXT: v_add_u16_e32 v9, 3, v32696; VI-NEXT: v_add_u16_sdwa v3, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2697; VI-NEXT: v_or_b32_e32 v3, v9, v32698; VI-NEXT: v_add_u16_e32 v9, 3, v22699; VI-NEXT: v_add_u16_sdwa v2, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2700; VI-NEXT: v_or_b32_e32 v2, v9, v22701; VI-NEXT: v_add_u16_e32 v9, 3, v12702; VI-NEXT: v_add_u16_sdwa v1, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2703; VI-NEXT: v_or_b32_e32 v1, v9, v12704; VI-NEXT: v_add_u16_e32 v9, 3, v02705; VI-NEXT: v_add_u16_sdwa v0, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2706; VI-NEXT: v_or_b32_e32 v0, v9, v02707; VI-NEXT: .LBB14_2: ; %end2708; VI-NEXT: s_or_b64 exec, exec, s[4:5]2709; VI-NEXT: s_setpc_b64 s[30:31]2710;2711; GFX9-LABEL: bitcast_v18i16_to_v9f32:2712; GFX9: ; %bb.0:2713; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2714; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v92715; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc2716; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]2717; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]2718; GFX9-NEXT: ; %bb.1: ; %cmp.true2719; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]2720; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]2721; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2722; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2723; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2724; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2725; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2726; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2727; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2728; GFX9-NEXT: ; %bb.2: ; %end2729; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]2730; GFX9-NEXT: s_setpc_b64 s[30:31]2731;2732; GFX11-LABEL: bitcast_v18i16_to_v9f32:2733; GFX11: ; %bb.0:2734; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2735; GFX11-NEXT: s_mov_b32 s0, exec_lo2736; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v92737; GFX11-NEXT: s_xor_b32 s0, exec_lo, s02738; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)2739; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s02740; GFX11-NEXT: s_cbranch_execz .LBB14_22741; GFX11-NEXT: ; %bb.1: ; %cmp.true2742; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]2743; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]2744; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]2745; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]2746; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]2747; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]2748; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]2749; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]2750; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2751; GFX11-NEXT: .LBB14_2: ; %end2752; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s02753; GFX11-NEXT: s_setpc_b64 s[30:31]2754 %cmp = icmp eq i32 %b, 02755 br i1 %cmp, label %cmp.true, label %cmp.false2756 2757cmp.true:2758 %a1 = add <18 x i16> %a, splat (i16 3)2759 %a2 = bitcast <18 x i16> %a1 to <9 x float>2760 br label %end2761 2762cmp.false:2763 %a3 = bitcast <18 x i16> %a to <9 x float>2764 br label %end2765 2766end:2767 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2768 ret <9 x float> %phi2769}2770 2771define inreg <9 x float> @bitcast_v18i16_to_v9f32_scalar(<18 x i16> inreg %a, i32 inreg %b) {2772; SI-LABEL: bitcast_v18i16_to_v9f32_scalar:2773; SI: ; %bb.0:2774; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2775; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v42776; SI-NEXT: v_mov_b32_e32 v9, v22777; SI-NEXT: v_mov_b32_e32 v10, v02778; SI-NEXT: s_and_b64 s[4:5], vcc, exec2779; SI-NEXT: v_lshlrev_b32_e32 v12, 16, v12780; SI-NEXT: v_lshlrev_b32_e32 v11, 16, v32781; SI-NEXT: s_cbranch_scc0 .LBB15_42782; SI-NEXT: ; %bb.1: ; %cmp.false2783; SI-NEXT: s_and_b32 s4, s16, 0xffff2784; SI-NEXT: s_lshl_b32 s5, s17, 162785; SI-NEXT: s_or_b32 s4, s4, s52786; SI-NEXT: s_and_b32 s5, s18, 0xffff2787; SI-NEXT: s_lshl_b32 s6, s19, 162788; SI-NEXT: s_or_b32 s5, s5, s62789; SI-NEXT: s_and_b32 s6, s20, 0xffff2790; SI-NEXT: s_lshl_b32 s7, s21, 162791; SI-NEXT: s_or_b32 s6, s6, s72792; SI-NEXT: s_and_b32 s7, s22, 0xffff2793; SI-NEXT: s_lshl_b32 s8, s23, 162794; SI-NEXT: s_or_b32 s7, s7, s82795; SI-NEXT: s_and_b32 s8, s24, 0xffff2796; SI-NEXT: s_lshl_b32 s9, s25, 162797; SI-NEXT: s_or_b32 s8, s8, s92798; SI-NEXT: s_and_b32 s9, s26, 0xffff2799; SI-NEXT: s_lshl_b32 s10, s27, 162800; SI-NEXT: s_or_b32 s9, s9, s102801; SI-NEXT: s_and_b32 s10, s28, 0xffff2802; SI-NEXT: s_lshl_b32 s11, s29, 162803; SI-NEXT: v_and_b32_e32 v0, 0xffff, v102804; SI-NEXT: s_or_b32 s10, s10, s112805; SI-NEXT: v_or_b32_e32 v7, v0, v122806; SI-NEXT: v_and_b32_e32 v0, 0xffff, v92807; SI-NEXT: v_or_b32_e32 v8, v0, v112808; SI-NEXT: v_mov_b32_e32 v0, s42809; SI-NEXT: v_mov_b32_e32 v1, s52810; SI-NEXT: v_mov_b32_e32 v2, s62811; SI-NEXT: v_mov_b32_e32 v3, s72812; SI-NEXT: v_mov_b32_e32 v4, s82813; SI-NEXT: v_mov_b32_e32 v5, s92814; SI-NEXT: v_mov_b32_e32 v6, s102815; SI-NEXT: s_cbranch_execnz .LBB15_32816; SI-NEXT: .LBB15_2: ; %cmp.true2817; SI-NEXT: s_add_i32 s16, s16, 32818; SI-NEXT: s_and_b32 s4, s16, 0xffff2819; SI-NEXT: s_lshl_b32 s5, s17, 162820; SI-NEXT: s_add_i32 s18, s18, 32821; SI-NEXT: s_or_b32 s4, s5, s42822; SI-NEXT: s_and_b32 s5, s18, 0xffff2823; SI-NEXT: s_lshl_b32 s6, s19, 162824; SI-NEXT: s_add_i32 s20, s20, 32825; SI-NEXT: s_or_b32 s5, s6, s52826; SI-NEXT: s_and_b32 s6, s20, 0xffff2827; SI-NEXT: s_lshl_b32 s7, s21, 162828; SI-NEXT: s_add_i32 s22, s22, 32829; SI-NEXT: s_or_b32 s6, s7, s62830; SI-NEXT: s_and_b32 s7, s22, 0xffff2831; SI-NEXT: s_lshl_b32 s8, s23, 162832; SI-NEXT: s_add_i32 s24, s24, 32833; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v102834; SI-NEXT: s_or_b32 s7, s8, s72835; SI-NEXT: s_and_b32 s8, s24, 0xffff2836; SI-NEXT: s_lshl_b32 s9, s25, 162837; SI-NEXT: s_add_i32 s26, s26, 32838; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02839; SI-NEXT: s_or_b32 s8, s9, s82840; SI-NEXT: s_and_b32 s9, s26, 0xffff2841; SI-NEXT: s_lshl_b32 s10, s27, 162842; SI-NEXT: s_add_i32 s28, s28, 32843; SI-NEXT: v_or_b32_e32 v0, v12, v02844; SI-NEXT: s_or_b32 s9, s10, s92845; SI-NEXT: s_and_b32 s10, s28, 0xffff2846; SI-NEXT: s_lshl_b32 s11, s29, 162847; SI-NEXT: v_add_i32_e32 v7, vcc, 0x30000, v02848; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v92849; SI-NEXT: s_or_b32 s10, s11, s102850; SI-NEXT: v_and_b32_e32 v0, 0xffff, v02851; SI-NEXT: s_add_i32 s4, s4, 0x300002852; SI-NEXT: s_add_i32 s5, s5, 0x300002853; SI-NEXT: s_add_i32 s6, s6, 0x300002854; SI-NEXT: s_add_i32 s7, s7, 0x300002855; SI-NEXT: s_add_i32 s8, s8, 0x300002856; SI-NEXT: s_add_i32 s9, s9, 0x300002857; SI-NEXT: s_add_i32 s10, s10, 0x300002858; SI-NEXT: v_or_b32_e32 v0, v11, v02859; SI-NEXT: v_add_i32_e32 v8, vcc, 0x30000, v02860; SI-NEXT: v_mov_b32_e32 v0, s42861; SI-NEXT: v_mov_b32_e32 v1, s52862; SI-NEXT: v_mov_b32_e32 v2, s62863; SI-NEXT: v_mov_b32_e32 v3, s72864; SI-NEXT: v_mov_b32_e32 v4, s82865; SI-NEXT: v_mov_b32_e32 v5, s92866; SI-NEXT: v_mov_b32_e32 v6, s102867; SI-NEXT: .LBB15_3: ; %end2868; SI-NEXT: s_setpc_b64 s[30:31]2869; SI-NEXT: .LBB15_4:2870; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr82871; SI-NEXT: s_branch .LBB15_22872;2873; VI-LABEL: bitcast_v18i16_to_v9f32_scalar:2874; VI: ; %bb.0:2875; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2876; VI-NEXT: s_cmp_lg_u32 s25, 02877; VI-NEXT: s_cbranch_scc0 .LBB15_42878; VI-NEXT: ; %bb.1: ; %cmp.false2879; VI-NEXT: s_cbranch_execnz .LBB15_32880; VI-NEXT: .LBB15_2: ; %cmp.true2881; VI-NEXT: s_add_i32 s5, s24, 32882; VI-NEXT: s_and_b32 s4, s24, 0xffff00002883; VI-NEXT: s_and_b32 s5, s5, 0xffff2884; VI-NEXT: s_or_b32 s4, s4, s52885; VI-NEXT: s_add_i32 s5, s23, 32886; VI-NEXT: s_add_i32 s24, s4, 0x300002887; VI-NEXT: s_and_b32 s4, s23, 0xffff00002888; VI-NEXT: s_and_b32 s5, s5, 0xffff2889; VI-NEXT: s_or_b32 s4, s4, s52890; VI-NEXT: s_add_i32 s5, s22, 32891; VI-NEXT: s_add_i32 s23, s4, 0x300002892; VI-NEXT: s_and_b32 s4, s22, 0xffff00002893; VI-NEXT: s_and_b32 s5, s5, 0xffff2894; VI-NEXT: s_or_b32 s4, s4, s52895; VI-NEXT: s_add_i32 s5, s21, 32896; VI-NEXT: s_add_i32 s22, s4, 0x300002897; VI-NEXT: s_and_b32 s4, s21, 0xffff00002898; VI-NEXT: s_and_b32 s5, s5, 0xffff2899; VI-NEXT: s_or_b32 s4, s4, s52900; VI-NEXT: s_add_i32 s5, s20, 32901; VI-NEXT: s_add_i32 s21, s4, 0x300002902; VI-NEXT: s_and_b32 s4, s20, 0xffff00002903; VI-NEXT: s_and_b32 s5, s5, 0xffff2904; VI-NEXT: s_or_b32 s4, s4, s52905; VI-NEXT: s_add_i32 s5, s19, 32906; VI-NEXT: s_add_i32 s20, s4, 0x300002907; VI-NEXT: s_and_b32 s4, s19, 0xffff00002908; VI-NEXT: s_and_b32 s5, s5, 0xffff2909; VI-NEXT: s_or_b32 s4, s4, s52910; VI-NEXT: s_add_i32 s5, s18, 32911; VI-NEXT: s_add_i32 s19, s4, 0x300002912; VI-NEXT: s_and_b32 s4, s18, 0xffff00002913; VI-NEXT: s_and_b32 s5, s5, 0xffff2914; VI-NEXT: s_or_b32 s4, s4, s52915; VI-NEXT: s_add_i32 s5, s17, 32916; VI-NEXT: s_add_i32 s18, s4, 0x300002917; VI-NEXT: s_and_b32 s4, s17, 0xffff00002918; VI-NEXT: s_and_b32 s5, s5, 0xffff2919; VI-NEXT: s_or_b32 s4, s4, s52920; VI-NEXT: s_add_i32 s5, s16, 32921; VI-NEXT: s_add_i32 s17, s4, 0x300002922; VI-NEXT: s_and_b32 s4, s16, 0xffff00002923; VI-NEXT: s_and_b32 s5, s5, 0xffff2924; VI-NEXT: s_or_b32 s4, s4, s52925; VI-NEXT: s_add_i32 s16, s4, 0x300002926; VI-NEXT: .LBB15_3: ; %end2927; VI-NEXT: v_mov_b32_e32 v0, s162928; VI-NEXT: v_mov_b32_e32 v1, s172929; VI-NEXT: v_mov_b32_e32 v2, s182930; VI-NEXT: v_mov_b32_e32 v3, s192931; VI-NEXT: v_mov_b32_e32 v4, s202932; VI-NEXT: v_mov_b32_e32 v5, s212933; VI-NEXT: v_mov_b32_e32 v6, s222934; VI-NEXT: v_mov_b32_e32 v7, s232935; VI-NEXT: v_mov_b32_e32 v8, s242936; VI-NEXT: s_setpc_b64 s[30:31]2937; VI-NEXT: .LBB15_4:2938; VI-NEXT: s_branch .LBB15_22939;2940; GFX9-LABEL: bitcast_v18i16_to_v9f32_scalar:2941; GFX9: ; %bb.0:2942; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2943; GFX9-NEXT: s_cmp_lg_u32 s25, 02944; GFX9-NEXT: s_cbranch_scc0 .LBB15_32945; GFX9-NEXT: ; %bb.1: ; %cmp.false2946; GFX9-NEXT: s_cbranch_execnz .LBB15_42947; GFX9-NEXT: .LBB15_2: ; %cmp.true2948; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]2949; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]2950; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]2951; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]2952; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]2953; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]2954; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]2955; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]2956; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]2957; GFX9-NEXT: s_setpc_b64 s[30:31]2958; GFX9-NEXT: .LBB15_3:2959; GFX9-NEXT: s_branch .LBB15_22960; GFX9-NEXT: .LBB15_4:2961; GFX9-NEXT: v_mov_b32_e32 v0, s162962; GFX9-NEXT: v_mov_b32_e32 v1, s172963; GFX9-NEXT: v_mov_b32_e32 v2, s182964; GFX9-NEXT: v_mov_b32_e32 v3, s192965; GFX9-NEXT: v_mov_b32_e32 v4, s202966; GFX9-NEXT: v_mov_b32_e32 v5, s212967; GFX9-NEXT: v_mov_b32_e32 v6, s222968; GFX9-NEXT: v_mov_b32_e32 v7, s232969; GFX9-NEXT: v_mov_b32_e32 v8, s242970; GFX9-NEXT: s_setpc_b64 s[30:31]2971;2972; GFX11-LABEL: bitcast_v18i16_to_v9f32_scalar:2973; GFX11: ; %bb.0:2974; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2975; GFX11-NEXT: s_mov_b32 s15, s32976; GFX11-NEXT: s_mov_b32 s14, s22977; GFX11-NEXT: s_mov_b32 s13, s12978; GFX11-NEXT: s_mov_b32 s12, s02979; GFX11-NEXT: s_cmp_lg_u32 s21, 02980; GFX11-NEXT: s_mov_b32 s0, 02981; GFX11-NEXT: s_cbranch_scc0 .LBB15_32982; GFX11-NEXT: ; %bb.1: ; %Flow2983; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s02984; GFX11-NEXT: s_cbranch_vccnz .LBB15_42985; GFX11-NEXT: .LBB15_2: ; %cmp.true2986; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]2987; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]2988; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]2989; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]2990; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]2991; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]2992; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]2993; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]2994; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]2995; GFX11-NEXT: s_setpc_b64 s[30:31]2996; GFX11-NEXT: .LBB15_3:2997; GFX11-NEXT: s_branch .LBB15_22998; GFX11-NEXT: .LBB15_4:2999; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s133000; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s153001; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173002; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193003; GFX11-NEXT: v_mov_b32_e32 v8, s203004; GFX11-NEXT: s_setpc_b64 s[30:31]3005 %cmp = icmp eq i32 %b, 03006 br i1 %cmp, label %cmp.true, label %cmp.false3007 3008cmp.true:3009 %a1 = add <18 x i16> %a, splat (i16 3)3010 %a2 = bitcast <18 x i16> %a1 to <9 x float>3011 br label %end3012 3013cmp.false:3014 %a3 = bitcast <18 x i16> %a to <9 x float>3015 br label %end3016 3017end:3018 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3019 ret <9 x float> %phi3020}3021 3022define <18 x half> @bitcast_v9f32_to_v18f16(<9 x float> %a, i32 %b) {3023; SI-LABEL: bitcast_v9f32_to_v18f16:3024; SI: ; %bb.0:3025; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3026; SI-NEXT: v_mov_b32_e32 v26, v83027; SI-NEXT: v_mov_b32_e32 v25, v73028; SI-NEXT: v_mov_b32_e32 v24, v63029; SI-NEXT: v_mov_b32_e32 v23, v53030; SI-NEXT: v_mov_b32_e32 v22, v43031; SI-NEXT: v_mov_b32_e32 v21, v33032; SI-NEXT: v_mov_b32_e32 v20, v23033; SI-NEXT: v_mov_b32_e32 v19, v13034; SI-NEXT: v_mov_b32_e32 v18, v03035; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v93036; SI-NEXT: ; implicit-def: $vgpr03037; SI-NEXT: ; implicit-def: $vgpr13038; SI-NEXT: ; implicit-def: $vgpr23039; SI-NEXT: ; implicit-def: $vgpr33040; SI-NEXT: ; implicit-def: $vgpr43041; SI-NEXT: ; implicit-def: $vgpr53042; SI-NEXT: ; implicit-def: $vgpr63043; SI-NEXT: ; implicit-def: $vgpr73044; SI-NEXT: ; implicit-def: $vgpr83045; SI-NEXT: ; implicit-def: $vgpr93046; SI-NEXT: ; implicit-def: $vgpr103047; SI-NEXT: ; implicit-def: $vgpr113048; SI-NEXT: ; implicit-def: $vgpr123049; SI-NEXT: ; implicit-def: $vgpr133050; SI-NEXT: ; implicit-def: $vgpr143051; SI-NEXT: ; implicit-def: $vgpr153052; SI-NEXT: ; implicit-def: $vgpr163053; SI-NEXT: ; implicit-def: $vgpr173054; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3055; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3056; SI-NEXT: s_cbranch_execnz .LBB16_33057; SI-NEXT: ; %bb.1: ; %Flow3058; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3059; SI-NEXT: s_cbranch_execnz .LBB16_43060; SI-NEXT: .LBB16_2: ; %end3061; SI-NEXT: s_or_b64 exec, exec, s[4:5]3062; SI-NEXT: s_setpc_b64 s[30:31]3063; SI-NEXT: .LBB16_3: ; %cmp.false3064; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v263065; SI-NEXT: v_cvt_f32_f16_e32 v17, v03066; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v253067; SI-NEXT: v_cvt_f32_f16_e32 v15, v03068; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v243069; SI-NEXT: v_cvt_f32_f16_e32 v13, v03070; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v233071; SI-NEXT: v_cvt_f32_f16_e32 v11, v03072; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v223073; SI-NEXT: v_cvt_f32_f16_e32 v9, v03074; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v213075; SI-NEXT: v_cvt_f32_f16_e32 v7, v03076; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v203077; SI-NEXT: v_cvt_f32_f16_e32 v5, v03078; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v193079; SI-NEXT: v_cvt_f32_f16_e32 v3, v03080; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v183081; SI-NEXT: v_cvt_f32_f16_e32 v1, v03082; SI-NEXT: v_cvt_f32_f16_e32 v16, v263083; SI-NEXT: v_cvt_f32_f16_e32 v14, v253084; SI-NEXT: v_cvt_f32_f16_e32 v12, v243085; SI-NEXT: v_cvt_f32_f16_e32 v10, v233086; SI-NEXT: v_cvt_f32_f16_e32 v8, v223087; SI-NEXT: v_cvt_f32_f16_e32 v6, v213088; SI-NEXT: v_cvt_f32_f16_e32 v4, v203089; SI-NEXT: v_cvt_f32_f16_e32 v2, v193090; SI-NEXT: v_cvt_f32_f16_e32 v0, v183091; SI-NEXT: ; implicit-def: $vgpr183092; SI-NEXT: ; implicit-def: $vgpr193093; SI-NEXT: ; implicit-def: $vgpr203094; SI-NEXT: ; implicit-def: $vgpr213095; SI-NEXT: ; implicit-def: $vgpr223096; SI-NEXT: ; implicit-def: $vgpr233097; SI-NEXT: ; implicit-def: $vgpr243098; SI-NEXT: ; implicit-def: $vgpr253099; SI-NEXT: ; implicit-def: $vgpr263100; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3101; SI-NEXT: s_cbranch_execz .LBB16_23102; SI-NEXT: .LBB16_4: ; %cmp.true3103; SI-NEXT: v_add_f32_e32 v1, 1.0, v183104; SI-NEXT: v_add_f32_e32 v3, 1.0, v193105; SI-NEXT: v_add_f32_e32 v5, 1.0, v203106; SI-NEXT: v_add_f32_e32 v7, 1.0, v213107; SI-NEXT: v_add_f32_e32 v9, 1.0, v223108; SI-NEXT: v_add_f32_e32 v11, 1.0, v233109; SI-NEXT: v_add_f32_e32 v13, 1.0, v243110; SI-NEXT: v_add_f32_e32 v15, 1.0, v253111; SI-NEXT: v_add_f32_e32 v17, 1.0, v263112; SI-NEXT: v_cvt_f32_f16_e32 v16, v173113; SI-NEXT: v_cvt_f32_f16_e32 v14, v153114; SI-NEXT: v_cvt_f32_f16_e32 v12, v133115; SI-NEXT: v_cvt_f32_f16_e32 v10, v113116; SI-NEXT: v_cvt_f32_f16_e32 v8, v93117; SI-NEXT: v_cvt_f32_f16_e32 v6, v73118; SI-NEXT: v_cvt_f32_f16_e32 v4, v53119; SI-NEXT: v_cvt_f32_f16_e32 v2, v33120; SI-NEXT: v_cvt_f32_f16_e32 v0, v13121; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v173122; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v153123; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v133124; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v113125; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v93126; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v73127; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v53128; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v33129; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13130; SI-NEXT: v_cvt_f32_f16_e32 v17, v173131; SI-NEXT: v_cvt_f32_f16_e32 v15, v153132; SI-NEXT: v_cvt_f32_f16_e32 v13, v133133; SI-NEXT: v_cvt_f32_f16_e32 v11, v113134; SI-NEXT: v_cvt_f32_f16_e32 v9, v93135; SI-NEXT: v_cvt_f32_f16_e32 v7, v73136; SI-NEXT: v_cvt_f32_f16_e32 v5, v53137; SI-NEXT: v_cvt_f32_f16_e32 v3, v33138; SI-NEXT: v_cvt_f32_f16_e32 v1, v13139; SI-NEXT: s_or_b64 exec, exec, s[4:5]3140; SI-NEXT: s_setpc_b64 s[30:31]3141;3142; VI-LABEL: bitcast_v9f32_to_v18f16:3143; VI: ; %bb.0:3144; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3145; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v93146; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3147; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3148; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3149; VI-NEXT: ; %bb.1: ; %cmp.true3150; VI-NEXT: v_add_f32_e32 v8, 1.0, v83151; VI-NEXT: v_add_f32_e32 v7, 1.0, v73152; VI-NEXT: v_add_f32_e32 v6, 1.0, v63153; VI-NEXT: v_add_f32_e32 v5, 1.0, v53154; VI-NEXT: v_add_f32_e32 v4, 1.0, v43155; VI-NEXT: v_add_f32_e32 v3, 1.0, v33156; VI-NEXT: v_add_f32_e32 v2, 1.0, v23157; VI-NEXT: v_add_f32_e32 v1, 1.0, v13158; VI-NEXT: v_add_f32_e32 v0, 1.0, v03159; VI-NEXT: ; %bb.2: ; %end3160; VI-NEXT: s_or_b64 exec, exec, s[4:5]3161; VI-NEXT: s_setpc_b64 s[30:31]3162;3163; GFX9-LABEL: bitcast_v9f32_to_v18f16:3164; GFX9: ; %bb.0:3165; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3166; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v93167; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3168; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3169; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3170; GFX9-NEXT: ; %bb.1: ; %cmp.true3171; GFX9-NEXT: v_add_f32_e32 v8, 1.0, v83172; GFX9-NEXT: v_add_f32_e32 v7, 1.0, v73173; GFX9-NEXT: v_add_f32_e32 v6, 1.0, v63174; GFX9-NEXT: v_add_f32_e32 v5, 1.0, v53175; GFX9-NEXT: v_add_f32_e32 v4, 1.0, v43176; GFX9-NEXT: v_add_f32_e32 v3, 1.0, v33177; GFX9-NEXT: v_add_f32_e32 v2, 1.0, v23178; GFX9-NEXT: v_add_f32_e32 v1, 1.0, v13179; GFX9-NEXT: v_add_f32_e32 v0, 1.0, v03180; GFX9-NEXT: ; %bb.2: ; %end3181; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3182; GFX9-NEXT: s_setpc_b64 s[30:31]3183;3184; GFX11-LABEL: bitcast_v9f32_to_v18f16:3185; GFX11: ; %bb.0:3186; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3187; GFX11-NEXT: s_mov_b32 s0, exec_lo3188; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v93189; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03190; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3191; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03192; GFX11-NEXT: ; %bb.1: ; %cmp.true3193; GFX11-NEXT: v_dual_add_f32 v8, 1.0, v8 :: v_dual_add_f32 v7, 1.0, v73194; GFX11-NEXT: v_dual_add_f32 v6, 1.0, v6 :: v_dual_add_f32 v5, 1.0, v53195; GFX11-NEXT: v_dual_add_f32 v4, 1.0, v4 :: v_dual_add_f32 v3, 1.0, v33196; GFX11-NEXT: v_dual_add_f32 v2, 1.0, v2 :: v_dual_add_f32 v1, 1.0, v13197; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v03198; GFX11-NEXT: ; %bb.2: ; %end3199; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03200; GFX11-NEXT: s_setpc_b64 s[30:31]3201 %cmp = icmp eq i32 %b, 03202 br i1 %cmp, label %cmp.true, label %cmp.false3203 3204cmp.true:3205 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)3206 %a2 = bitcast <9 x float> %a1 to <18 x half>3207 br label %end3208 3209cmp.false:3210 %a3 = bitcast <9 x float> %a to <18 x half>3211 br label %end3212 3213end:3214 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3215 ret <18 x half> %phi3216}3217 3218define inreg <18 x half> @bitcast_v9f32_to_v18f16_scalar(<9 x float> inreg %a, i32 inreg %b) {3219; SI-LABEL: bitcast_v9f32_to_v18f16_scalar:3220; SI: ; %bb.0:3221; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3222; SI-NEXT: s_cmp_lg_u32 s25, 03223; SI-NEXT: s_cbranch_scc0 .LBB17_43224; SI-NEXT: ; %bb.1: ; %cmp.false3225; SI-NEXT: s_lshr_b32 s4, s24, 163226; SI-NEXT: v_cvt_f32_f16_e32 v17, s43227; SI-NEXT: s_lshr_b32 s4, s23, 163228; SI-NEXT: v_cvt_f32_f16_e32 v15, s43229; SI-NEXT: s_lshr_b32 s4, s22, 163230; SI-NEXT: v_cvt_f32_f16_e32 v13, s43231; SI-NEXT: s_lshr_b32 s4, s21, 163232; SI-NEXT: v_cvt_f32_f16_e32 v11, s43233; SI-NEXT: s_lshr_b32 s4, s20, 163234; SI-NEXT: v_cvt_f32_f16_e32 v9, s43235; SI-NEXT: s_lshr_b32 s4, s19, 163236; SI-NEXT: v_cvt_f32_f16_e32 v7, s43237; SI-NEXT: s_lshr_b32 s4, s18, 163238; SI-NEXT: v_cvt_f32_f16_e32 v5, s43239; SI-NEXT: s_lshr_b32 s4, s17, 163240; SI-NEXT: v_cvt_f32_f16_e32 v3, s43241; SI-NEXT: s_lshr_b32 s4, s16, 163242; SI-NEXT: v_cvt_f32_f16_e32 v1, s43243; SI-NEXT: v_cvt_f32_f16_e32 v16, s243244; SI-NEXT: v_cvt_f32_f16_e32 v14, s233245; SI-NEXT: v_cvt_f32_f16_e32 v12, s223246; SI-NEXT: v_cvt_f32_f16_e32 v10, s213247; SI-NEXT: v_cvt_f32_f16_e32 v8, s203248; SI-NEXT: v_cvt_f32_f16_e32 v6, s193249; SI-NEXT: v_cvt_f32_f16_e32 v4, s183250; SI-NEXT: v_cvt_f32_f16_e32 v2, s173251; SI-NEXT: v_cvt_f32_f16_e32 v0, s163252; SI-NEXT: s_cbranch_execnz .LBB17_33253; SI-NEXT: .LBB17_2: ; %cmp.true3254; SI-NEXT: v_add_f32_e64 v1, s16, 1.03255; SI-NEXT: v_add_f32_e64 v3, s17, 1.03256; SI-NEXT: v_add_f32_e64 v5, s18, 1.03257; SI-NEXT: v_add_f32_e64 v7, s19, 1.03258; SI-NEXT: v_add_f32_e64 v9, s20, 1.03259; SI-NEXT: v_add_f32_e64 v11, s21, 1.03260; SI-NEXT: v_add_f32_e64 v13, s22, 1.03261; SI-NEXT: v_add_f32_e64 v15, s23, 1.03262; SI-NEXT: v_add_f32_e64 v17, s24, 1.03263; SI-NEXT: v_cvt_f32_f16_e32 v16, v173264; SI-NEXT: v_cvt_f32_f16_e32 v14, v153265; SI-NEXT: v_cvt_f32_f16_e32 v12, v133266; SI-NEXT: v_cvt_f32_f16_e32 v10, v113267; SI-NEXT: v_cvt_f32_f16_e32 v8, v93268; SI-NEXT: v_cvt_f32_f16_e32 v6, v73269; SI-NEXT: v_cvt_f32_f16_e32 v4, v53270; SI-NEXT: v_cvt_f32_f16_e32 v2, v33271; SI-NEXT: v_cvt_f32_f16_e32 v0, v13272; SI-NEXT: v_lshrrev_b32_e32 v17, 16, v173273; SI-NEXT: v_lshrrev_b32_e32 v15, 16, v153274; SI-NEXT: v_lshrrev_b32_e32 v13, 16, v133275; SI-NEXT: v_lshrrev_b32_e32 v11, 16, v113276; SI-NEXT: v_lshrrev_b32_e32 v9, 16, v93277; SI-NEXT: v_lshrrev_b32_e32 v7, 16, v73278; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v53279; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v33280; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v13281; SI-NEXT: v_cvt_f32_f16_e32 v17, v173282; SI-NEXT: v_cvt_f32_f16_e32 v15, v153283; SI-NEXT: v_cvt_f32_f16_e32 v13, v133284; SI-NEXT: v_cvt_f32_f16_e32 v11, v113285; SI-NEXT: v_cvt_f32_f16_e32 v9, v93286; SI-NEXT: v_cvt_f32_f16_e32 v7, v73287; SI-NEXT: v_cvt_f32_f16_e32 v5, v53288; SI-NEXT: v_cvt_f32_f16_e32 v3, v33289; SI-NEXT: v_cvt_f32_f16_e32 v1, v13290; SI-NEXT: .LBB17_3: ; %end3291; SI-NEXT: s_setpc_b64 s[30:31]3292; SI-NEXT: .LBB17_4:3293; SI-NEXT: ; implicit-def: $vgpr03294; SI-NEXT: ; implicit-def: $vgpr13295; SI-NEXT: ; implicit-def: $vgpr23296; SI-NEXT: ; implicit-def: $vgpr33297; SI-NEXT: ; implicit-def: $vgpr43298; SI-NEXT: ; implicit-def: $vgpr53299; SI-NEXT: ; implicit-def: $vgpr63300; SI-NEXT: ; implicit-def: $vgpr73301; SI-NEXT: ; implicit-def: $vgpr83302; SI-NEXT: ; implicit-def: $vgpr93303; SI-NEXT: ; implicit-def: $vgpr103304; SI-NEXT: ; implicit-def: $vgpr113305; SI-NEXT: ; implicit-def: $vgpr123306; SI-NEXT: ; implicit-def: $vgpr133307; SI-NEXT: ; implicit-def: $vgpr143308; SI-NEXT: ; implicit-def: $vgpr153309; SI-NEXT: ; implicit-def: $vgpr163310; SI-NEXT: ; implicit-def: $vgpr173311; SI-NEXT: s_branch .LBB17_23312;3313; VI-LABEL: bitcast_v9f32_to_v18f16_scalar:3314; VI: ; %bb.0:3315; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3316; VI-NEXT: s_cmp_lg_u32 s25, 03317; VI-NEXT: s_cbranch_scc0 .LBB17_33318; VI-NEXT: ; %bb.1: ; %cmp.false3319; VI-NEXT: s_cbranch_execnz .LBB17_43320; VI-NEXT: .LBB17_2: ; %cmp.true3321; VI-NEXT: v_add_f32_e64 v8, s24, 1.03322; VI-NEXT: v_add_f32_e64 v7, s23, 1.03323; VI-NEXT: v_add_f32_e64 v6, s22, 1.03324; VI-NEXT: v_add_f32_e64 v5, s21, 1.03325; VI-NEXT: v_add_f32_e64 v4, s20, 1.03326; VI-NEXT: v_add_f32_e64 v3, s19, 1.03327; VI-NEXT: v_add_f32_e64 v2, s18, 1.03328; VI-NEXT: v_add_f32_e64 v1, s17, 1.03329; VI-NEXT: v_add_f32_e64 v0, s16, 1.03330; VI-NEXT: s_setpc_b64 s[30:31]3331; VI-NEXT: .LBB17_3:3332; VI-NEXT: s_branch .LBB17_23333; VI-NEXT: .LBB17_4:3334; VI-NEXT: v_mov_b32_e32 v0, s163335; VI-NEXT: v_mov_b32_e32 v1, s173336; VI-NEXT: v_mov_b32_e32 v2, s183337; VI-NEXT: v_mov_b32_e32 v3, s193338; VI-NEXT: v_mov_b32_e32 v4, s203339; VI-NEXT: v_mov_b32_e32 v5, s213340; VI-NEXT: v_mov_b32_e32 v6, s223341; VI-NEXT: v_mov_b32_e32 v7, s233342; VI-NEXT: v_mov_b32_e32 v8, s243343; VI-NEXT: v_mov_b32_e32 v9, s253344; VI-NEXT: v_mov_b32_e32 v10, s263345; VI-NEXT: v_mov_b32_e32 v11, s273346; VI-NEXT: v_mov_b32_e32 v12, s283347; VI-NEXT: v_mov_b32_e32 v13, s293348; VI-NEXT: v_mov_b32_e32 v14, s303349; VI-NEXT: v_mov_b32_e32 v15, s313350; VI-NEXT: s_setpc_b64 s[30:31]3351;3352; GFX9-LABEL: bitcast_v9f32_to_v18f16_scalar:3353; GFX9: ; %bb.0:3354; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3355; GFX9-NEXT: s_cmp_lg_u32 s25, 03356; GFX9-NEXT: s_cbranch_scc0 .LBB17_33357; GFX9-NEXT: ; %bb.1: ; %cmp.false3358; GFX9-NEXT: s_cbranch_execnz .LBB17_43359; GFX9-NEXT: .LBB17_2: ; %cmp.true3360; GFX9-NEXT: v_add_f32_e64 v8, s24, 1.03361; GFX9-NEXT: v_add_f32_e64 v7, s23, 1.03362; GFX9-NEXT: v_add_f32_e64 v6, s22, 1.03363; GFX9-NEXT: v_add_f32_e64 v5, s21, 1.03364; GFX9-NEXT: v_add_f32_e64 v4, s20, 1.03365; GFX9-NEXT: v_add_f32_e64 v3, s19, 1.03366; GFX9-NEXT: v_add_f32_e64 v2, s18, 1.03367; GFX9-NEXT: v_add_f32_e64 v1, s17, 1.03368; GFX9-NEXT: v_add_f32_e64 v0, s16, 1.03369; GFX9-NEXT: s_setpc_b64 s[30:31]3370; GFX9-NEXT: .LBB17_3:3371; GFX9-NEXT: s_branch .LBB17_23372; GFX9-NEXT: .LBB17_4:3373; GFX9-NEXT: v_mov_b32_e32 v0, s163374; GFX9-NEXT: v_mov_b32_e32 v1, s173375; GFX9-NEXT: v_mov_b32_e32 v2, s183376; GFX9-NEXT: v_mov_b32_e32 v3, s193377; GFX9-NEXT: v_mov_b32_e32 v4, s203378; GFX9-NEXT: v_mov_b32_e32 v5, s213379; GFX9-NEXT: v_mov_b32_e32 v6, s223380; GFX9-NEXT: v_mov_b32_e32 v7, s233381; GFX9-NEXT: v_mov_b32_e32 v8, s243382; GFX9-NEXT: v_mov_b32_e32 v9, s253383; GFX9-NEXT: v_mov_b32_e32 v10, s263384; GFX9-NEXT: v_mov_b32_e32 v11, s273385; GFX9-NEXT: v_mov_b32_e32 v12, s283386; GFX9-NEXT: v_mov_b32_e32 v13, s293387; GFX9-NEXT: v_mov_b32_e32 v14, s303388; GFX9-NEXT: v_mov_b32_e32 v15, s313389; GFX9-NEXT: s_setpc_b64 s[30:31]3390;3391; GFX11-LABEL: bitcast_v9f32_to_v18f16_scalar:3392; GFX11: ; %bb.0:3393; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3394; GFX11-NEXT: s_mov_b32 s15, s33395; GFX11-NEXT: s_mov_b32 s14, s23396; GFX11-NEXT: s_mov_b32 s13, s13397; GFX11-NEXT: s_mov_b32 s12, s03398; GFX11-NEXT: s_cmp_lg_u32 s21, 03399; GFX11-NEXT: s_mov_b32 s0, 03400; GFX11-NEXT: s_cbranch_scc0 .LBB17_33401; GFX11-NEXT: ; %bb.1: ; %Flow3402; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s03403; GFX11-NEXT: s_cbranch_vccnz .LBB17_43404; GFX11-NEXT: .LBB17_2: ; %cmp.true3405; GFX11-NEXT: v_add_f32_e64 v8, s20, 1.03406; GFX11-NEXT: v_add_f32_e64 v7, s19, 1.03407; GFX11-NEXT: v_add_f32_e64 v6, s18, 1.03408; GFX11-NEXT: v_add_f32_e64 v5, s17, 1.03409; GFX11-NEXT: v_add_f32_e64 v4, s16, 1.03410; GFX11-NEXT: v_add_f32_e64 v3, s15, 1.03411; GFX11-NEXT: v_add_f32_e64 v2, s14, 1.03412; GFX11-NEXT: v_add_f32_e64 v1, s13, 1.03413; GFX11-NEXT: v_add_f32_e64 v0, s12, 1.03414; GFX11-NEXT: s_setpc_b64 s[30:31]3415; GFX11-NEXT: .LBB17_3:3416; GFX11-NEXT: s_branch .LBB17_23417; GFX11-NEXT: .LBB17_4:3418; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s133419; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s153420; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173421; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193422; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s213423; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s233424; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s253425; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s273426; GFX11-NEXT: s_setpc_b64 s[30:31]3427 %cmp = icmp eq i32 %b, 03428 br i1 %cmp, label %cmp.true, label %cmp.false3429 3430cmp.true:3431 %a1 = fadd <9 x float> %a, splat (float 1.000000e+00)3432 %a2 = bitcast <9 x float> %a1 to <18 x half>3433 br label %end3434 3435cmp.false:3436 %a3 = bitcast <9 x float> %a to <18 x half>3437 br label %end3438 3439end:3440 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3441 ret <18 x half> %phi3442}3443 3444define <9 x float> @bitcast_v18f16_to_v9f32(<18 x half> %a, i32 %b) {3445; SI-LABEL: bitcast_v18f16_to_v9f32:3446; SI: ; %bb.0:3447; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3448; SI-NEXT: v_cvt_f16_f32_e32 v31, v13449; SI-NEXT: v_cvt_f16_f32_e32 v30, v03450; SI-NEXT: v_cvt_f16_f32_e32 v29, v33451; SI-NEXT: v_cvt_f16_f32_e32 v28, v23452; SI-NEXT: v_cvt_f16_f32_e32 v27, v53453; SI-NEXT: v_cvt_f16_f32_e32 v26, v43454; SI-NEXT: v_cvt_f16_f32_e32 v25, v73455; SI-NEXT: v_cvt_f16_f32_e32 v24, v63456; SI-NEXT: v_cvt_f16_f32_e32 v23, v93457; SI-NEXT: v_cvt_f16_f32_e32 v22, v83458; SI-NEXT: v_cvt_f16_f32_e32 v21, v113459; SI-NEXT: v_cvt_f16_f32_e32 v20, v103460; SI-NEXT: v_cvt_f16_f32_e32 v19, v133461; SI-NEXT: v_cvt_f16_f32_e32 v13, v123462; SI-NEXT: v_cvt_f16_f32_e32 v12, v153463; SI-NEXT: v_cvt_f16_f32_e32 v11, v143464; SI-NEXT: v_cvt_f16_f32_e32 v10, v173465; SI-NEXT: v_cvt_f16_f32_e32 v9, v163466; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v183467; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr83468; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc3469; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3470; SI-NEXT: s_cbranch_execnz .LBB18_33471; SI-NEXT: ; %bb.1: ; %Flow3472; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3473; SI-NEXT: s_cbranch_execnz .LBB18_43474; SI-NEXT: .LBB18_2: ; %end3475; SI-NEXT: s_or_b64 exec, exec, s[4:5]3476; SI-NEXT: s_setpc_b64 s[30:31]3477; SI-NEXT: .LBB18_3: ; %cmp.false3478; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v313479; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v293480; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v273481; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v253482; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v233483; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v213484; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v193485; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v123486; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v103487; SI-NEXT: v_or_b32_e32 v0, v30, v03488; SI-NEXT: v_or_b32_e32 v1, v28, v13489; SI-NEXT: v_or_b32_e32 v2, v26, v23490; SI-NEXT: v_or_b32_e32 v3, v24, v33491; SI-NEXT: v_or_b32_e32 v4, v22, v43492; SI-NEXT: v_or_b32_e32 v5, v20, v53493; SI-NEXT: v_or_b32_e32 v6, v13, v63494; SI-NEXT: v_or_b32_e32 v7, v11, v73495; SI-NEXT: v_or_b32_e32 v8, v9, v83496; SI-NEXT: ; implicit-def: $vgpr313497; SI-NEXT: ; implicit-def: $vgpr303498; SI-NEXT: ; implicit-def: $vgpr293499; SI-NEXT: ; implicit-def: $vgpr283500; SI-NEXT: ; implicit-def: $vgpr273501; SI-NEXT: ; implicit-def: $vgpr263502; SI-NEXT: ; implicit-def: $vgpr253503; SI-NEXT: ; implicit-def: $vgpr243504; SI-NEXT: ; implicit-def: $vgpr233505; SI-NEXT: ; implicit-def: $vgpr223506; SI-NEXT: ; implicit-def: $vgpr213507; SI-NEXT: ; implicit-def: $vgpr203508; SI-NEXT: ; implicit-def: $vgpr193509; SI-NEXT: ; implicit-def: $vgpr133510; SI-NEXT: ; implicit-def: $vgpr123511; SI-NEXT: ; implicit-def: $vgpr113512; SI-NEXT: ; implicit-def: $vgpr103513; SI-NEXT: ; implicit-def: $vgpr93514; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3515; SI-NEXT: s_cbranch_execz .LBB18_23516; SI-NEXT: .LBB18_4: ; %cmp.true3517; SI-NEXT: v_cvt_f32_f16_e32 v0, v313518; SI-NEXT: v_cvt_f32_f16_e32 v2, v293519; SI-NEXT: v_cvt_f32_f16_e32 v1, v303520; SI-NEXT: v_cvt_f32_f16_e32 v3, v283521; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03522; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23523; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13524; SI-NEXT: v_cvt_f16_f32_e32 v0, v03525; SI-NEXT: v_cvt_f16_f32_e32 v2, v23526; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33527; SI-NEXT: v_cvt_f16_f32_e32 v1, v13528; SI-NEXT: v_cvt_f16_f32_e32 v3, v33529; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03530; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23531; SI-NEXT: v_or_b32_e32 v0, v1, v03532; SI-NEXT: v_or_b32_e32 v1, v3, v23533; SI-NEXT: v_cvt_f32_f16_e32 v2, v273534; SI-NEXT: v_cvt_f32_f16_e32 v3, v263535; SI-NEXT: v_cvt_f32_f16_e32 v4, v253536; SI-NEXT: v_cvt_f32_f16_e32 v5, v243537; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23538; SI-NEXT: v_cvt_f16_f32_e32 v2, v23539; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33540; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43541; SI-NEXT: v_cvt_f16_f32_e32 v3, v33542; SI-NEXT: v_cvt_f16_f32_e32 v4, v43543; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53544; SI-NEXT: v_cvt_f16_f32_e32 v5, v53545; SI-NEXT: v_cvt_f32_f16_e32 v6, v233546; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23547; SI-NEXT: v_or_b32_e32 v2, v3, v23548; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43549; SI-NEXT: v_or_b32_e32 v3, v5, v33550; SI-NEXT: v_cvt_f32_f16_e32 v4, v223551; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v63552; SI-NEXT: v_cvt_f32_f16_e32 v6, v213553; SI-NEXT: v_cvt_f16_f32_e32 v5, v53554; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43555; SI-NEXT: v_cvt_f16_f32_e32 v4, v43556; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63557; SI-NEXT: v_cvt_f16_f32_e32 v6, v63558; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53559; SI-NEXT: v_cvt_f32_f16_e32 v7, v203560; SI-NEXT: v_or_b32_e32 v4, v4, v53561; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63562; SI-NEXT: v_cvt_f32_f16_e32 v6, v193563; SI-NEXT: v_cvt_f32_f16_e32 v8, v133564; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73565; SI-NEXT: v_cvt_f16_f32_e32 v7, v73566; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63567; SI-NEXT: v_cvt_f16_f32_e32 v6, v63568; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83569; SI-NEXT: v_cvt_f16_f32_e32 v8, v83570; SI-NEXT: v_or_b32_e32 v5, v7, v53571; SI-NEXT: v_cvt_f32_f16_e32 v7, v123572; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63573; SI-NEXT: v_or_b32_e32 v6, v8, v63574; SI-NEXT: v_cvt_f32_f16_e32 v8, v113575; SI-NEXT: v_cvt_f32_f16_e32 v10, v103576; SI-NEXT: v_cvt_f32_f16_e32 v9, v93577; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73578; SI-NEXT: v_cvt_f16_f32_e32 v7, v73579; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83580; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103581; SI-NEXT: v_cvt_f16_f32_e32 v8, v83582; SI-NEXT: v_cvt_f16_f32_e32 v10, v103583; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93584; SI-NEXT: v_cvt_f16_f32_e32 v9, v93585; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v73586; SI-NEXT: v_or_b32_e32 v7, v8, v73587; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v103588; SI-NEXT: v_or_b32_e32 v8, v9, v83589; SI-NEXT: s_or_b64 exec, exec, s[4:5]3590; SI-NEXT: s_setpc_b64 s[30:31]3591;3592; VI-LABEL: bitcast_v18f16_to_v9f32:3593; VI: ; %bb.0:3594; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3595; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v93596; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc3597; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3598; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3599; VI-NEXT: s_cbranch_execz .LBB18_23600; VI-NEXT: ; %bb.1: ; %cmp.true3601; VI-NEXT: v_mov_b32_e32 v9, 0x2003602; VI-NEXT: v_add_f16_sdwa v10, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3603; VI-NEXT: v_add_f16_e32 v8, 0x200, v83604; VI-NEXT: v_or_b32_e32 v8, v8, v103605; VI-NEXT: v_add_f16_sdwa v10, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3606; VI-NEXT: v_add_f16_e32 v7, 0x200, v73607; VI-NEXT: v_or_b32_e32 v7, v7, v103608; VI-NEXT: v_add_f16_sdwa v10, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3609; VI-NEXT: v_add_f16_e32 v6, 0x200, v63610; VI-NEXT: v_or_b32_e32 v6, v6, v103611; VI-NEXT: v_add_f16_sdwa v10, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3612; VI-NEXT: v_add_f16_e32 v5, 0x200, v53613; VI-NEXT: v_or_b32_e32 v5, v5, v103614; VI-NEXT: v_add_f16_sdwa v10, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3615; VI-NEXT: v_add_f16_e32 v4, 0x200, v43616; VI-NEXT: v_or_b32_e32 v4, v4, v103617; VI-NEXT: v_add_f16_sdwa v10, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3618; VI-NEXT: v_add_f16_e32 v3, 0x200, v33619; VI-NEXT: v_or_b32_e32 v3, v3, v103620; VI-NEXT: v_add_f16_sdwa v10, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3621; VI-NEXT: v_add_f16_e32 v2, 0x200, v23622; VI-NEXT: v_or_b32_e32 v2, v2, v103623; VI-NEXT: v_add_f16_sdwa v10, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3624; VI-NEXT: v_add_f16_e32 v1, 0x200, v13625; VI-NEXT: v_add_f16_sdwa v9, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3626; VI-NEXT: v_add_f16_e32 v0, 0x200, v03627; VI-NEXT: v_or_b32_e32 v1, v1, v103628; VI-NEXT: v_or_b32_e32 v0, v0, v93629; VI-NEXT: .LBB18_2: ; %end3630; VI-NEXT: s_or_b64 exec, exec, s[4:5]3631; VI-NEXT: s_setpc_b64 s[30:31]3632;3633; GFX9-LABEL: bitcast_v18f16_to_v9f32:3634; GFX9: ; %bb.0:3635; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3636; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v93637; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc3638; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]3639; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]3640; GFX9-NEXT: s_cbranch_execz .LBB18_23641; GFX9-NEXT: ; %bb.1: ; %cmp.true3642; GFX9-NEXT: s_movk_i32 s6, 0x2003643; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]3644; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]3645; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]3646; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]3647; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]3648; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]3649; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]3650; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]3651; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3652; GFX9-NEXT: .LBB18_2: ; %end3653; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]3654; GFX9-NEXT: s_setpc_b64 s[30:31]3655;3656; GFX11-LABEL: bitcast_v18f16_to_v9f32:3657; GFX11: ; %bb.0:3658; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3659; GFX11-NEXT: s_mov_b32 s0, exec_lo3660; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v93661; GFX11-NEXT: s_xor_b32 s0, exec_lo, s03662; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)3663; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s03664; GFX11-NEXT: s_cbranch_execz .LBB18_23665; GFX11-NEXT: ; %bb.1: ; %cmp.true3666; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]3667; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]3668; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]3669; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]3670; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]3671; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]3672; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]3673; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]3674; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3675; GFX11-NEXT: .LBB18_2: ; %end3676; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s03677; GFX11-NEXT: s_setpc_b64 s[30:31]3678 %cmp = icmp eq i32 %b, 03679 br i1 %cmp, label %cmp.true, label %cmp.false3680 3681cmp.true:3682 %a1 = fadd <18 x half> %a, splat (half 0xH0200)3683 %a2 = bitcast <18 x half> %a1 to <9 x float>3684 br label %end3685 3686cmp.false:3687 %a3 = bitcast <18 x half> %a to <9 x float>3688 br label %end3689 3690end:3691 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3692 ret <9 x float> %phi3693}3694 3695define inreg <9 x float> @bitcast_v18f16_to_v9f32_scalar(<18 x half> inreg %a, i32 inreg %b) {3696; SI-LABEL: bitcast_v18f16_to_v9f32_scalar:3697; SI: ; %bb.0:3698; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3699; SI-NEXT: v_cvt_f16_f32_e32 v26, s173700; SI-NEXT: v_cvt_f16_f32_e32 v25, s163701; SI-NEXT: v_cvt_f16_f32_e32 v24, s193702; SI-NEXT: v_cvt_f16_f32_e32 v23, s183703; SI-NEXT: v_cvt_f16_f32_e32 v22, s213704; SI-NEXT: v_cvt_f16_f32_e32 v21, s203705; SI-NEXT: v_cvt_f16_f32_e32 v20, s233706; SI-NEXT: v_cvt_f16_f32_e32 v19, s223707; SI-NEXT: v_cvt_f16_f32_e32 v18, s253708; SI-NEXT: v_cvt_f16_f32_e32 v17, s243709; SI-NEXT: v_cvt_f16_f32_e32 v16, s273710; SI-NEXT: v_cvt_f16_f32_e32 v15, s263711; SI-NEXT: v_cvt_f16_f32_e32 v14, s293712; SI-NEXT: v_cvt_f16_f32_e32 v13, s283713; SI-NEXT: v_cvt_f16_f32_e32 v12, v13714; SI-NEXT: v_cvt_f16_f32_e32 v11, v03715; SI-NEXT: v_cvt_f16_f32_e32 v10, v33716; SI-NEXT: v_cvt_f16_f32_e32 v9, v23717; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v43718; SI-NEXT: s_and_b64 s[4:5], vcc, exec3719; SI-NEXT: s_cbranch_scc0 .LBB19_43720; SI-NEXT: ; %bb.1: ; %cmp.false3721; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v263722; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v243723; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v223724; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v203725; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v183726; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v163727; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v143728; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v123729; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v103730; SI-NEXT: v_or_b32_e32 v0, v25, v03731; SI-NEXT: v_or_b32_e32 v1, v23, v13732; SI-NEXT: v_or_b32_e32 v2, v21, v23733; SI-NEXT: v_or_b32_e32 v3, v19, v33734; SI-NEXT: v_or_b32_e32 v4, v17, v43735; SI-NEXT: v_or_b32_e32 v5, v15, v53736; SI-NEXT: v_or_b32_e32 v6, v13, v63737; SI-NEXT: v_or_b32_e32 v7, v11, v73738; SI-NEXT: v_or_b32_e32 v8, v9, v83739; SI-NEXT: s_cbranch_execnz .LBB19_33740; SI-NEXT: .LBB19_2: ; %cmp.true3741; SI-NEXT: v_cvt_f32_f16_e32 v0, v263742; SI-NEXT: v_cvt_f32_f16_e32 v2, v243743; SI-NEXT: v_cvt_f32_f16_e32 v1, v253744; SI-NEXT: v_cvt_f32_f16_e32 v3, v233745; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v03746; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23747; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v13748; SI-NEXT: v_cvt_f16_f32_e32 v0, v03749; SI-NEXT: v_cvt_f16_f32_e32 v2, v23750; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33751; SI-NEXT: v_cvt_f16_f32_e32 v1, v13752; SI-NEXT: v_cvt_f16_f32_e32 v3, v33753; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v03754; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23755; SI-NEXT: v_or_b32_e32 v0, v1, v03756; SI-NEXT: v_or_b32_e32 v1, v3, v23757; SI-NEXT: v_cvt_f32_f16_e32 v2, v223758; SI-NEXT: v_cvt_f32_f16_e32 v3, v213759; SI-NEXT: v_cvt_f32_f16_e32 v4, v203760; SI-NEXT: v_cvt_f32_f16_e32 v5, v193761; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v23762; SI-NEXT: v_cvt_f16_f32_e32 v2, v23763; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v33764; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43765; SI-NEXT: v_cvt_f16_f32_e32 v3, v33766; SI-NEXT: v_cvt_f16_f32_e32 v4, v43767; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v53768; SI-NEXT: v_cvt_f16_f32_e32 v5, v53769; SI-NEXT: v_cvt_f32_f16_e32 v6, v183770; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v23771; SI-NEXT: v_or_b32_e32 v2, v3, v23772; SI-NEXT: v_lshlrev_b32_e32 v3, 16, v43773; SI-NEXT: v_or_b32_e32 v3, v5, v33774; SI-NEXT: v_cvt_f32_f16_e32 v4, v173775; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v63776; SI-NEXT: v_cvt_f32_f16_e32 v6, v163777; SI-NEXT: v_cvt_f16_f32_e32 v5, v53778; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v43779; SI-NEXT: v_cvt_f16_f32_e32 v4, v43780; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63781; SI-NEXT: v_cvt_f16_f32_e32 v6, v63782; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v53783; SI-NEXT: v_cvt_f32_f16_e32 v7, v153784; SI-NEXT: v_or_b32_e32 v4, v4, v53785; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v63786; SI-NEXT: v_cvt_f32_f16_e32 v6, v143787; SI-NEXT: v_cvt_f32_f16_e32 v8, v133788; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73789; SI-NEXT: v_cvt_f16_f32_e32 v7, v73790; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v63791; SI-NEXT: v_cvt_f16_f32_e32 v6, v63792; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83793; SI-NEXT: v_cvt_f16_f32_e32 v8, v83794; SI-NEXT: v_or_b32_e32 v5, v7, v53795; SI-NEXT: v_cvt_f32_f16_e32 v7, v123796; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v63797; SI-NEXT: v_or_b32_e32 v6, v8, v63798; SI-NEXT: v_cvt_f32_f16_e32 v8, v113799; SI-NEXT: v_cvt_f32_f16_e32 v10, v103800; SI-NEXT: v_cvt_f32_f16_e32 v9, v93801; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v73802; SI-NEXT: v_cvt_f16_f32_e32 v7, v73803; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v83804; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v103805; SI-NEXT: v_cvt_f16_f32_e32 v8, v83806; SI-NEXT: v_cvt_f16_f32_e32 v10, v103807; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v93808; SI-NEXT: v_cvt_f16_f32_e32 v9, v93809; SI-NEXT: v_lshlrev_b32_e32 v7, 16, v73810; SI-NEXT: v_or_b32_e32 v7, v8, v73811; SI-NEXT: v_lshlrev_b32_e32 v8, 16, v103812; SI-NEXT: v_or_b32_e32 v8, v9, v83813; SI-NEXT: .LBB19_3: ; %end3814; SI-NEXT: s_setpc_b64 s[30:31]3815; SI-NEXT: .LBB19_4:3816; SI-NEXT: ; implicit-def: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr83817; SI-NEXT: s_branch .LBB19_23818;3819; VI-LABEL: bitcast_v18f16_to_v9f32_scalar:3820; VI: ; %bb.0:3821; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3822; VI-NEXT: s_cmp_lg_u32 s25, 03823; VI-NEXT: s_cbranch_scc0 .LBB19_33824; VI-NEXT: ; %bb.1: ; %cmp.false3825; VI-NEXT: s_cbranch_execnz .LBB19_43826; VI-NEXT: .LBB19_2: ; %cmp.true3827; VI-NEXT: s_lshr_b32 s4, s24, 163828; VI-NEXT: v_mov_b32_e32 v0, 0x2003829; VI-NEXT: v_mov_b32_e32 v1, s43830; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3831; VI-NEXT: v_add_f16_e32 v2, s24, v03832; VI-NEXT: s_lshr_b32 s4, s23, 163833; VI-NEXT: v_or_b32_e32 v8, v2, v13834; VI-NEXT: v_mov_b32_e32 v1, s43835; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3836; VI-NEXT: v_add_f16_e32 v2, s23, v03837; VI-NEXT: s_lshr_b32 s4, s22, 163838; VI-NEXT: v_or_b32_e32 v7, v2, v13839; VI-NEXT: v_mov_b32_e32 v1, s43840; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3841; VI-NEXT: v_add_f16_e32 v2, s22, v03842; VI-NEXT: s_lshr_b32 s4, s21, 163843; VI-NEXT: v_or_b32_e32 v6, v2, v13844; VI-NEXT: v_mov_b32_e32 v1, s43845; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3846; VI-NEXT: v_add_f16_e32 v2, s21, v03847; VI-NEXT: s_lshr_b32 s4, s20, 163848; VI-NEXT: v_or_b32_e32 v5, v2, v13849; VI-NEXT: v_mov_b32_e32 v1, s43850; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3851; VI-NEXT: v_add_f16_e32 v2, s20, v03852; VI-NEXT: s_lshr_b32 s4, s19, 163853; VI-NEXT: v_or_b32_e32 v4, v2, v13854; VI-NEXT: v_mov_b32_e32 v1, s43855; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3856; VI-NEXT: v_add_f16_e32 v2, s19, v03857; VI-NEXT: s_lshr_b32 s4, s18, 163858; VI-NEXT: v_or_b32_e32 v3, v2, v13859; VI-NEXT: v_mov_b32_e32 v1, s43860; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3861; VI-NEXT: v_add_f16_e32 v2, s18, v03862; VI-NEXT: s_lshr_b32 s4, s17, 163863; VI-NEXT: v_or_b32_e32 v2, v2, v13864; VI-NEXT: v_mov_b32_e32 v1, s43865; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3866; VI-NEXT: v_add_f16_e32 v9, s17, v03867; VI-NEXT: s_lshr_b32 s4, s16, 163868; VI-NEXT: v_or_b32_e32 v1, v9, v13869; VI-NEXT: v_mov_b32_e32 v9, s43870; VI-NEXT: v_add_f16_sdwa v9, v9, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3871; VI-NEXT: v_add_f16_e32 v0, s16, v03872; VI-NEXT: v_or_b32_e32 v0, v0, v93873; VI-NEXT: s_setpc_b64 s[30:31]3874; VI-NEXT: .LBB19_3:3875; VI-NEXT: s_branch .LBB19_23876; VI-NEXT: .LBB19_4:3877; VI-NEXT: v_mov_b32_e32 v0, s163878; VI-NEXT: v_mov_b32_e32 v1, s173879; VI-NEXT: v_mov_b32_e32 v2, s183880; VI-NEXT: v_mov_b32_e32 v3, s193881; VI-NEXT: v_mov_b32_e32 v4, s203882; VI-NEXT: v_mov_b32_e32 v5, s213883; VI-NEXT: v_mov_b32_e32 v6, s223884; VI-NEXT: v_mov_b32_e32 v7, s233885; VI-NEXT: v_mov_b32_e32 v8, s243886; VI-NEXT: s_setpc_b64 s[30:31]3887;3888; GFX9-LABEL: bitcast_v18f16_to_v9f32_scalar:3889; GFX9: ; %bb.0:3890; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3891; GFX9-NEXT: s_cmp_lg_u32 s25, 03892; GFX9-NEXT: s_cbranch_scc0 .LBB19_33893; GFX9-NEXT: ; %bb.1: ; %cmp.false3894; GFX9-NEXT: s_cbranch_execnz .LBB19_43895; GFX9-NEXT: .LBB19_2: ; %cmp.true3896; GFX9-NEXT: v_mov_b32_e32 v0, 0x2003897; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]3898; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]3899; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]3900; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]3901; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]3902; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]3903; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]3904; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]3905; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]3906; GFX9-NEXT: s_setpc_b64 s[30:31]3907; GFX9-NEXT: .LBB19_3:3908; GFX9-NEXT: s_branch .LBB19_23909; GFX9-NEXT: .LBB19_4:3910; GFX9-NEXT: v_mov_b32_e32 v0, s163911; GFX9-NEXT: v_mov_b32_e32 v1, s173912; GFX9-NEXT: v_mov_b32_e32 v2, s183913; GFX9-NEXT: v_mov_b32_e32 v3, s193914; GFX9-NEXT: v_mov_b32_e32 v4, s203915; GFX9-NEXT: v_mov_b32_e32 v5, s213916; GFX9-NEXT: v_mov_b32_e32 v6, s223917; GFX9-NEXT: v_mov_b32_e32 v7, s233918; GFX9-NEXT: v_mov_b32_e32 v8, s243919; GFX9-NEXT: s_setpc_b64 s[30:31]3920;3921; GFX11-LABEL: bitcast_v18f16_to_v9f32_scalar:3922; GFX11: ; %bb.0:3923; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3924; GFX11-NEXT: s_mov_b32 s15, s33925; GFX11-NEXT: s_mov_b32 s14, s23926; GFX11-NEXT: s_mov_b32 s13, s13927; GFX11-NEXT: s_mov_b32 s12, s03928; GFX11-NEXT: s_cmp_lg_u32 s21, 03929; GFX11-NEXT: s_mov_b32 s0, 03930; GFX11-NEXT: s_cbranch_scc0 .LBB19_33931; GFX11-NEXT: ; %bb.1: ; %Flow3932; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s03933; GFX11-NEXT: s_cbranch_vccnz .LBB19_43934; GFX11-NEXT: .LBB19_2: ; %cmp.true3935; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]3936; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]3937; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]3938; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]3939; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]3940; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]3941; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]3942; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]3943; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]3944; GFX11-NEXT: s_setpc_b64 s[30:31]3945; GFX11-NEXT: .LBB19_3:3946; GFX11-NEXT: s_branch .LBB19_23947; GFX11-NEXT: .LBB19_4:3948; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s133949; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s153950; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s173951; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s193952; GFX11-NEXT: v_mov_b32_e32 v8, s203953; GFX11-NEXT: s_setpc_b64 s[30:31]3954 %cmp = icmp eq i32 %b, 03955 br i1 %cmp, label %cmp.true, label %cmp.false3956 3957cmp.true:3958 %a1 = fadd <18 x half> %a, splat (half 0xH0200)3959 %a2 = bitcast <18 x half> %a1 to <9 x float>3960 br label %end3961 3962cmp.false:3963 %a3 = bitcast <18 x half> %a to <9 x float>3964 br label %end3965 3966end:3967 %phi = phi <9 x float> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3968 ret <9 x float> %phi3969}3970 3971define <18 x half> @bitcast_v18i16_to_v18f16(<18 x i16> %a, i32 %b) {3972; SI-LABEL: bitcast_v18i16_to_v18f16:3973; SI: ; %bb.0:3974; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3975; SI-NEXT: v_mov_b32_e32 v35, v173976; SI-NEXT: v_mov_b32_e32 v34, v163977; SI-NEXT: v_mov_b32_e32 v33, v153978; SI-NEXT: v_mov_b32_e32 v32, v143979; SI-NEXT: v_mov_b32_e32 v31, v133980; SI-NEXT: v_mov_b32_e32 v30, v123981; SI-NEXT: v_mov_b32_e32 v29, v113982; SI-NEXT: v_mov_b32_e32 v28, v103983; SI-NEXT: v_mov_b32_e32 v27, v93984; SI-NEXT: v_mov_b32_e32 v26, v83985; SI-NEXT: v_mov_b32_e32 v25, v73986; SI-NEXT: v_mov_b32_e32 v24, v63987; SI-NEXT: v_mov_b32_e32 v23, v53988; SI-NEXT: v_mov_b32_e32 v22, v43989; SI-NEXT: v_mov_b32_e32 v21, v33990; SI-NEXT: v_mov_b32_e32 v20, v23991; SI-NEXT: v_mov_b32_e32 v19, v13992; SI-NEXT: v_mov_b32_e32 v36, v03993; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v183994; SI-NEXT: ; implicit-def: $vgpr03995; SI-NEXT: ; implicit-def: $vgpr13996; SI-NEXT: ; implicit-def: $vgpr23997; SI-NEXT: ; implicit-def: $vgpr33998; SI-NEXT: ; implicit-def: $vgpr43999; SI-NEXT: ; implicit-def: $vgpr54000; SI-NEXT: ; implicit-def: $vgpr64001; SI-NEXT: ; implicit-def: $vgpr74002; SI-NEXT: ; implicit-def: $vgpr84003; SI-NEXT: ; implicit-def: $vgpr94004; SI-NEXT: ; implicit-def: $vgpr104005; SI-NEXT: ; implicit-def: $vgpr114006; SI-NEXT: ; implicit-def: $vgpr124007; SI-NEXT: ; implicit-def: $vgpr134008; SI-NEXT: ; implicit-def: $vgpr144009; SI-NEXT: ; implicit-def: $vgpr154010; SI-NEXT: ; implicit-def: $vgpr164011; SI-NEXT: ; implicit-def: $vgpr174012; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4013; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4014; SI-NEXT: s_cbranch_execnz .LBB20_34015; SI-NEXT: ; %bb.1: ; %Flow4016; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4017; SI-NEXT: s_cbranch_execnz .LBB20_44018; SI-NEXT: .LBB20_2: ; %end4019; SI-NEXT: s_or_b64 exec, exec, s[4:5]4020; SI-NEXT: s_setpc_b64 s[30:31]4021; SI-NEXT: .LBB20_3: ; %cmp.false4022; SI-NEXT: v_cvt_f32_f16_e32 v0, v364023; SI-NEXT: v_cvt_f32_f16_e32 v1, v194024; SI-NEXT: v_cvt_f32_f16_e32 v2, v204025; SI-NEXT: v_cvt_f32_f16_e32 v3, v214026; SI-NEXT: v_cvt_f32_f16_e32 v4, v224027; SI-NEXT: v_cvt_f32_f16_e32 v5, v234028; SI-NEXT: v_cvt_f32_f16_e32 v6, v244029; SI-NEXT: v_cvt_f32_f16_e32 v7, v254030; SI-NEXT: v_cvt_f32_f16_e32 v8, v264031; SI-NEXT: v_cvt_f32_f16_e32 v9, v274032; SI-NEXT: v_cvt_f32_f16_e32 v10, v284033; SI-NEXT: v_cvt_f32_f16_e32 v11, v294034; SI-NEXT: v_cvt_f32_f16_e32 v12, v304035; SI-NEXT: v_cvt_f32_f16_e32 v13, v314036; SI-NEXT: v_cvt_f32_f16_e32 v14, v324037; SI-NEXT: v_cvt_f32_f16_e32 v15, v334038; SI-NEXT: v_cvt_f32_f16_e32 v16, v344039; SI-NEXT: v_cvt_f32_f16_e32 v17, v354040; SI-NEXT: ; implicit-def: $vgpr364041; SI-NEXT: ; implicit-def: $vgpr194042; SI-NEXT: ; implicit-def: $vgpr204043; SI-NEXT: ; implicit-def: $vgpr214044; SI-NEXT: ; implicit-def: $vgpr224045; SI-NEXT: ; implicit-def: $vgpr234046; SI-NEXT: ; implicit-def: $vgpr244047; SI-NEXT: ; implicit-def: $vgpr254048; SI-NEXT: ; implicit-def: $vgpr264049; SI-NEXT: ; implicit-def: $vgpr274050; SI-NEXT: ; implicit-def: $vgpr284051; SI-NEXT: ; implicit-def: $vgpr294052; SI-NEXT: ; implicit-def: $vgpr304053; SI-NEXT: ; implicit-def: $vgpr314054; SI-NEXT: ; implicit-def: $vgpr324055; SI-NEXT: ; implicit-def: $vgpr334056; SI-NEXT: ; implicit-def: $vgpr344057; SI-NEXT: ; implicit-def: $vgpr354058; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4059; SI-NEXT: s_cbranch_execz .LBB20_24060; SI-NEXT: .LBB20_4: ; %cmp.true4061; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v354062; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v344063; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v334064; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v324065; SI-NEXT: v_add_i32_e32 v13, vcc, 3, v314066; SI-NEXT: v_add_i32_e32 v12, vcc, 3, v304067; SI-NEXT: v_add_i32_e32 v11, vcc, 3, v294068; SI-NEXT: v_add_i32_e32 v10, vcc, 3, v284069; SI-NEXT: v_add_i32_e32 v9, vcc, 3, v274070; SI-NEXT: v_add_i32_e32 v8, vcc, 3, v264071; SI-NEXT: v_add_i32_e32 v7, vcc, 3, v254072; SI-NEXT: v_add_i32_e32 v6, vcc, 3, v244073; SI-NEXT: v_add_i32_e32 v5, vcc, 3, v234074; SI-NEXT: v_add_i32_e32 v4, vcc, 3, v224075; SI-NEXT: v_add_i32_e32 v3, vcc, 3, v214076; SI-NEXT: v_add_i32_e32 v2, vcc, 3, v204077; SI-NEXT: v_add_i32_e32 v1, vcc, 3, v194078; SI-NEXT: v_add_i32_e32 v0, vcc, 3, v364079; SI-NEXT: v_cvt_f32_f16_e32 v0, v04080; SI-NEXT: v_cvt_f32_f16_e32 v1, v14081; SI-NEXT: v_cvt_f32_f16_e32 v2, v24082; SI-NEXT: v_cvt_f32_f16_e32 v3, v34083; SI-NEXT: v_cvt_f32_f16_e32 v4, v44084; SI-NEXT: v_cvt_f32_f16_e32 v5, v54085; SI-NEXT: v_cvt_f32_f16_e32 v6, v64086; SI-NEXT: v_cvt_f32_f16_e32 v7, v74087; SI-NEXT: v_cvt_f32_f16_e32 v8, v84088; SI-NEXT: v_cvt_f32_f16_e32 v9, v94089; SI-NEXT: v_cvt_f32_f16_e32 v10, v104090; SI-NEXT: v_cvt_f32_f16_e32 v11, v114091; SI-NEXT: v_cvt_f32_f16_e32 v12, v124092; SI-NEXT: v_cvt_f32_f16_e32 v13, v134093; SI-NEXT: v_cvt_f32_f16_e32 v14, v144094; SI-NEXT: v_cvt_f32_f16_e32 v15, v154095; SI-NEXT: v_cvt_f32_f16_e32 v16, v164096; SI-NEXT: v_cvt_f32_f16_e32 v17, v174097; SI-NEXT: s_or_b64 exec, exec, s[4:5]4098; SI-NEXT: s_setpc_b64 s[30:31]4099;4100; VI-LABEL: bitcast_v18i16_to_v18f16:4101; VI: ; %bb.0:4102; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4103; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v94104; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4105; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4106; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4107; VI-NEXT: s_cbranch_execz .LBB20_24108; VI-NEXT: ; %bb.1: ; %cmp.true4109; VI-NEXT: v_mov_b32_e32 v9, 34110; VI-NEXT: v_add_u16_sdwa v10, v0, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4111; VI-NEXT: v_add_u16_sdwa v11, v1, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4112; VI-NEXT: v_add_u16_sdwa v12, v2, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4113; VI-NEXT: v_add_u16_sdwa v13, v3, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4114; VI-NEXT: v_add_u16_sdwa v14, v4, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4115; VI-NEXT: v_add_u16_sdwa v15, v5, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4116; VI-NEXT: v_add_u16_sdwa v16, v6, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4117; VI-NEXT: v_add_u16_sdwa v17, v7, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4118; VI-NEXT: v_add_u16_sdwa v9, v8, v9 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4119; VI-NEXT: v_add_u16_e32 v8, 3, v84120; VI-NEXT: v_add_u16_e32 v7, 3, v74121; VI-NEXT: v_add_u16_e32 v6, 3, v64122; VI-NEXT: v_add_u16_e32 v5, 3, v54123; VI-NEXT: v_add_u16_e32 v4, 3, v44124; VI-NEXT: v_add_u16_e32 v3, 3, v34125; VI-NEXT: v_add_u16_e32 v2, 3, v24126; VI-NEXT: v_add_u16_e32 v1, 3, v14127; VI-NEXT: v_add_u16_e32 v0, 3, v04128; VI-NEXT: v_or_b32_e32 v8, v8, v94129; VI-NEXT: v_or_b32_e32 v7, v7, v174130; VI-NEXT: v_or_b32_e32 v6, v6, v164131; VI-NEXT: v_or_b32_e32 v5, v5, v154132; VI-NEXT: v_or_b32_e32 v4, v4, v144133; VI-NEXT: v_or_b32_e32 v3, v3, v134134; VI-NEXT: v_or_b32_e32 v2, v2, v124135; VI-NEXT: v_or_b32_e32 v1, v1, v114136; VI-NEXT: v_or_b32_e32 v0, v0, v104137; VI-NEXT: .LBB20_2: ; %end4138; VI-NEXT: s_or_b64 exec, exec, s[4:5]4139; VI-NEXT: s_setpc_b64 s[30:31]4140;4141; GFX9-LABEL: bitcast_v18i16_to_v18f16:4142; GFX9: ; %bb.0:4143; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4144; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v94145; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4146; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4147; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4148; GFX9-NEXT: ; %bb.1: ; %cmp.true4149; GFX9-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]4150; GFX9-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]4151; GFX9-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]4152; GFX9-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]4153; GFX9-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]4154; GFX9-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]4155; GFX9-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]4156; GFX9-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4157; GFX9-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4158; GFX9-NEXT: ; %bb.2: ; %end4159; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4160; GFX9-NEXT: s_setpc_b64 s[30:31]4161;4162; GFX11-LABEL: bitcast_v18i16_to_v18f16:4163; GFX11: ; %bb.0:4164; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4165; GFX11-NEXT: s_mov_b32 s0, exec_lo4166; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v94167; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04168; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4169; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04170; GFX11-NEXT: s_cbranch_execz .LBB20_24171; GFX11-NEXT: ; %bb.1: ; %cmp.true4172; GFX11-NEXT: v_pk_add_u16 v8, v8, 3 op_sel_hi:[1,0]4173; GFX11-NEXT: v_pk_add_u16 v7, v7, 3 op_sel_hi:[1,0]4174; GFX11-NEXT: v_pk_add_u16 v6, v6, 3 op_sel_hi:[1,0]4175; GFX11-NEXT: v_pk_add_u16 v5, v5, 3 op_sel_hi:[1,0]4176; GFX11-NEXT: v_pk_add_u16 v4, v4, 3 op_sel_hi:[1,0]4177; GFX11-NEXT: v_pk_add_u16 v3, v3, 3 op_sel_hi:[1,0]4178; GFX11-NEXT: v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]4179; GFX11-NEXT: v_pk_add_u16 v1, v1, 3 op_sel_hi:[1,0]4180; GFX11-NEXT: v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4181; GFX11-NEXT: .LBB20_2: ; %end4182; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04183; GFX11-NEXT: s_setpc_b64 s[30:31]4184 %cmp = icmp eq i32 %b, 04185 br i1 %cmp, label %cmp.true, label %cmp.false4186 4187cmp.true:4188 %a1 = add <18 x i16> %a, splat (i16 3)4189 %a2 = bitcast <18 x i16> %a1 to <18 x half>4190 br label %end4191 4192cmp.false:4193 %a3 = bitcast <18 x i16> %a to <18 x half>4194 br label %end4195 4196end:4197 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4198 ret <18 x half> %phi4199}4200 4201define inreg <18 x half> @bitcast_v18i16_to_v18f16_scalar(<18 x i16> inreg %a, i32 inreg %b) {4202; SI-LABEL: bitcast_v18i16_to_v18f16_scalar:4203; SI: ; %bb.0:4204; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4205; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44206; SI-NEXT: v_mov_b32_e32 v18, v34207; SI-NEXT: v_mov_b32_e32 v21, v24208; SI-NEXT: v_mov_b32_e32 v20, v14209; SI-NEXT: v_mov_b32_e32 v19, v04210; SI-NEXT: s_and_b64 s[4:5], vcc, exec4211; SI-NEXT: s_cbranch_scc0 .LBB21_44212; SI-NEXT: ; %bb.1: ; %cmp.false4213; SI-NEXT: v_cvt_f32_f16_e32 v0, s164214; SI-NEXT: v_cvt_f32_f16_e32 v1, s174215; SI-NEXT: v_cvt_f32_f16_e32 v2, s184216; SI-NEXT: v_cvt_f32_f16_e32 v3, s194217; SI-NEXT: v_cvt_f32_f16_e32 v4, s204218; SI-NEXT: v_cvt_f32_f16_e32 v5, s214219; SI-NEXT: v_cvt_f32_f16_e32 v6, s224220; SI-NEXT: v_cvt_f32_f16_e32 v7, s234221; SI-NEXT: v_cvt_f32_f16_e32 v8, s244222; SI-NEXT: v_cvt_f32_f16_e32 v9, s254223; SI-NEXT: v_cvt_f32_f16_e32 v10, s264224; SI-NEXT: v_cvt_f32_f16_e32 v11, s274225; SI-NEXT: v_cvt_f32_f16_e32 v12, s284226; SI-NEXT: v_cvt_f32_f16_e32 v13, s294227; SI-NEXT: v_cvt_f32_f16_e32 v14, v194228; SI-NEXT: v_cvt_f32_f16_e32 v15, v204229; SI-NEXT: v_cvt_f32_f16_e32 v16, v214230; SI-NEXT: v_cvt_f32_f16_e32 v17, v184231; SI-NEXT: s_cbranch_execnz .LBB21_34232; SI-NEXT: .LBB21_2: ; %cmp.true4233; SI-NEXT: v_add_i32_e32 v17, vcc, 3, v184234; SI-NEXT: v_add_i32_e32 v16, vcc, 3, v214235; SI-NEXT: v_add_i32_e32 v15, vcc, 3, v204236; SI-NEXT: v_add_i32_e32 v14, vcc, 3, v194237; SI-NEXT: s_add_i32 s29, s29, 34238; SI-NEXT: s_add_i32 s28, s28, 34239; SI-NEXT: s_add_i32 s27, s27, 34240; SI-NEXT: s_add_i32 s26, s26, 34241; SI-NEXT: s_add_i32 s25, s25, 34242; SI-NEXT: s_add_i32 s24, s24, 34243; SI-NEXT: s_add_i32 s23, s23, 34244; SI-NEXT: s_add_i32 s22, s22, 34245; SI-NEXT: s_add_i32 s21, s21, 34246; SI-NEXT: s_add_i32 s20, s20, 34247; SI-NEXT: s_add_i32 s19, s19, 34248; SI-NEXT: s_add_i32 s18, s18, 34249; SI-NEXT: s_add_i32 s17, s17, 34250; SI-NEXT: s_add_i32 s16, s16, 34251; SI-NEXT: v_cvt_f32_f16_e32 v0, s164252; SI-NEXT: v_cvt_f32_f16_e32 v1, s174253; SI-NEXT: v_cvt_f32_f16_e32 v2, s184254; SI-NEXT: v_cvt_f32_f16_e32 v3, s194255; SI-NEXT: v_cvt_f32_f16_e32 v4, s204256; SI-NEXT: v_cvt_f32_f16_e32 v5, s214257; SI-NEXT: v_cvt_f32_f16_e32 v6, s224258; SI-NEXT: v_cvt_f32_f16_e32 v7, s234259; SI-NEXT: v_cvt_f32_f16_e32 v8, s244260; SI-NEXT: v_cvt_f32_f16_e32 v9, s254261; SI-NEXT: v_cvt_f32_f16_e32 v10, s264262; SI-NEXT: v_cvt_f32_f16_e32 v11, s274263; SI-NEXT: v_cvt_f32_f16_e32 v12, s284264; SI-NEXT: v_cvt_f32_f16_e32 v13, s294265; SI-NEXT: v_cvt_f32_f16_e32 v14, v144266; SI-NEXT: v_cvt_f32_f16_e32 v15, v154267; SI-NEXT: v_cvt_f32_f16_e32 v16, v164268; SI-NEXT: v_cvt_f32_f16_e32 v17, v174269; SI-NEXT: .LBB21_3: ; %end4270; SI-NEXT: s_setpc_b64 s[30:31]4271; SI-NEXT: .LBB21_4:4272; SI-NEXT: ; implicit-def: $vgpr04273; SI-NEXT: ; implicit-def: $vgpr14274; SI-NEXT: ; implicit-def: $vgpr24275; SI-NEXT: ; implicit-def: $vgpr34276; SI-NEXT: ; implicit-def: $vgpr44277; SI-NEXT: ; implicit-def: $vgpr54278; SI-NEXT: ; implicit-def: $vgpr64279; SI-NEXT: ; implicit-def: $vgpr74280; SI-NEXT: ; implicit-def: $vgpr84281; SI-NEXT: ; implicit-def: $vgpr94282; SI-NEXT: ; implicit-def: $vgpr104283; SI-NEXT: ; implicit-def: $vgpr114284; SI-NEXT: ; implicit-def: $vgpr124285; SI-NEXT: ; implicit-def: $vgpr134286; SI-NEXT: ; implicit-def: $vgpr144287; SI-NEXT: ; implicit-def: $vgpr154288; SI-NEXT: ; implicit-def: $vgpr164289; SI-NEXT: ; implicit-def: $vgpr174290; SI-NEXT: s_branch .LBB21_24291;4292; VI-LABEL: bitcast_v18i16_to_v18f16_scalar:4293; VI: ; %bb.0:4294; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4295; VI-NEXT: s_cmp_lg_u32 s25, 04296; VI-NEXT: s_cbranch_scc0 .LBB21_44297; VI-NEXT: ; %bb.1: ; %cmp.false4298; VI-NEXT: s_cbranch_execnz .LBB21_34299; VI-NEXT: .LBB21_2: ; %cmp.true4300; VI-NEXT: s_add_i32 s5, s16, 34301; VI-NEXT: s_and_b32 s6, s17, 0xffff00004302; VI-NEXT: s_add_i32 s7, s17, 34303; VI-NEXT: s_add_i32 s9, s18, 34304; VI-NEXT: s_and_b32 s10, s19, 0xffff00004305; VI-NEXT: s_add_i32 s11, s19, 34306; VI-NEXT: s_add_i32 s13, s20, 34307; VI-NEXT: s_and_b32 s14, s21, 0xffff00004308; VI-NEXT: s_add_i32 s15, s21, 34309; VI-NEXT: s_add_i32 s17, s22, 34310; VI-NEXT: s_add_i32 s19, s23, 34311; VI-NEXT: s_add_i32 s21, s24, 34312; VI-NEXT: s_and_b32 s4, s16, 0xffff00004313; VI-NEXT: s_and_b32 s8, s18, 0xffff00004314; VI-NEXT: s_and_b32 s12, s20, 0xffff00004315; VI-NEXT: s_and_b32 s16, s22, 0xffff00004316; VI-NEXT: s_and_b32 s18, s23, 0xffff00004317; VI-NEXT: s_and_b32 s20, s24, 0xffff00004318; VI-NEXT: s_and_b32 s21, s21, 0xffff4319; VI-NEXT: s_and_b32 s19, s19, 0xffff4320; VI-NEXT: s_and_b32 s17, s17, 0xffff4321; VI-NEXT: s_and_b32 s15, s15, 0xffff4322; VI-NEXT: s_and_b32 s13, s13, 0xffff4323; VI-NEXT: s_and_b32 s11, s11, 0xffff4324; VI-NEXT: s_and_b32 s9, s9, 0xffff4325; VI-NEXT: s_and_b32 s7, s7, 0xffff4326; VI-NEXT: s_and_b32 s5, s5, 0xffff4327; VI-NEXT: s_or_b32 s20, s20, s214328; VI-NEXT: s_or_b32 s18, s18, s194329; VI-NEXT: s_or_b32 s16, s16, s174330; VI-NEXT: s_or_b32 s14, s14, s154331; VI-NEXT: s_or_b32 s12, s12, s134332; VI-NEXT: s_or_b32 s10, s10, s114333; VI-NEXT: s_or_b32 s8, s8, s94334; VI-NEXT: s_or_b32 s6, s6, s74335; VI-NEXT: s_or_b32 s4, s4, s54336; VI-NEXT: s_add_i32 s24, s20, 0x300004337; VI-NEXT: s_add_i32 s23, s18, 0x300004338; VI-NEXT: s_add_i32 s22, s16, 0x300004339; VI-NEXT: s_add_i32 s21, s14, 0x300004340; VI-NEXT: s_add_i32 s20, s12, 0x300004341; VI-NEXT: s_add_i32 s19, s10, 0x300004342; VI-NEXT: s_add_i32 s18, s8, 0x300004343; VI-NEXT: s_add_i32 s17, s6, 0x300004344; VI-NEXT: s_add_i32 s16, s4, 0x300004345; VI-NEXT: .LBB21_3: ; %end4346; VI-NEXT: v_mov_b32_e32 v0, s164347; VI-NEXT: v_mov_b32_e32 v1, s174348; VI-NEXT: v_mov_b32_e32 v2, s184349; VI-NEXT: v_mov_b32_e32 v3, s194350; VI-NEXT: v_mov_b32_e32 v4, s204351; VI-NEXT: v_mov_b32_e32 v5, s214352; VI-NEXT: v_mov_b32_e32 v6, s224353; VI-NEXT: v_mov_b32_e32 v7, s234354; VI-NEXT: v_mov_b32_e32 v8, s244355; VI-NEXT: s_setpc_b64 s[30:31]4356; VI-NEXT: .LBB21_4:4357; VI-NEXT: s_branch .LBB21_24358;4359; GFX9-LABEL: bitcast_v18i16_to_v18f16_scalar:4360; GFX9: ; %bb.0:4361; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4362; GFX9-NEXT: s_cmp_lg_u32 s25, 04363; GFX9-NEXT: s_cbranch_scc0 .LBB21_34364; GFX9-NEXT: ; %bb.1: ; %cmp.false4365; GFX9-NEXT: s_cbranch_execnz .LBB21_44366; GFX9-NEXT: .LBB21_2: ; %cmp.true4367; GFX9-NEXT: v_pk_add_u16 v8, s24, 3 op_sel_hi:[1,0]4368; GFX9-NEXT: v_pk_add_u16 v7, s23, 3 op_sel_hi:[1,0]4369; GFX9-NEXT: v_pk_add_u16 v6, s22, 3 op_sel_hi:[1,0]4370; GFX9-NEXT: v_pk_add_u16 v5, s21, 3 op_sel_hi:[1,0]4371; GFX9-NEXT: v_pk_add_u16 v4, s20, 3 op_sel_hi:[1,0]4372; GFX9-NEXT: v_pk_add_u16 v3, s19, 3 op_sel_hi:[1,0]4373; GFX9-NEXT: v_pk_add_u16 v2, s18, 3 op_sel_hi:[1,0]4374; GFX9-NEXT: v_pk_add_u16 v1, s17, 3 op_sel_hi:[1,0]4375; GFX9-NEXT: v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]4376; GFX9-NEXT: s_setpc_b64 s[30:31]4377; GFX9-NEXT: .LBB21_3:4378; GFX9-NEXT: s_branch .LBB21_24379; GFX9-NEXT: .LBB21_4:4380; GFX9-NEXT: v_mov_b32_e32 v0, s164381; GFX9-NEXT: v_mov_b32_e32 v1, s174382; GFX9-NEXT: v_mov_b32_e32 v2, s184383; GFX9-NEXT: v_mov_b32_e32 v3, s194384; GFX9-NEXT: v_mov_b32_e32 v4, s204385; GFX9-NEXT: v_mov_b32_e32 v5, s214386; GFX9-NEXT: v_mov_b32_e32 v6, s224387; GFX9-NEXT: v_mov_b32_e32 v7, s234388; GFX9-NEXT: v_mov_b32_e32 v8, s244389; GFX9-NEXT: v_mov_b32_e32 v9, s254390; GFX9-NEXT: v_mov_b32_e32 v10, s264391; GFX9-NEXT: v_mov_b32_e32 v11, s274392; GFX9-NEXT: v_mov_b32_e32 v12, s284393; GFX9-NEXT: v_mov_b32_e32 v13, s294394; GFX9-NEXT: v_mov_b32_e32 v14, s304395; GFX9-NEXT: v_mov_b32_e32 v15, s314396; GFX9-NEXT: s_setpc_b64 s[30:31]4397;4398; GFX11-LABEL: bitcast_v18i16_to_v18f16_scalar:4399; GFX11: ; %bb.0:4400; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4401; GFX11-NEXT: s_mov_b32 s15, s34402; GFX11-NEXT: s_mov_b32 s14, s24403; GFX11-NEXT: s_mov_b32 s13, s14404; GFX11-NEXT: s_mov_b32 s12, s04405; GFX11-NEXT: s_cmp_lg_u32 s21, 04406; GFX11-NEXT: s_mov_b32 s0, 04407; GFX11-NEXT: s_cbranch_scc0 .LBB21_34408; GFX11-NEXT: ; %bb.1: ; %Flow4409; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s04410; GFX11-NEXT: s_cbranch_vccnz .LBB21_44411; GFX11-NEXT: .LBB21_2: ; %cmp.true4412; GFX11-NEXT: v_pk_add_u16 v8, s20, 3 op_sel_hi:[1,0]4413; GFX11-NEXT: v_pk_add_u16 v7, s19, 3 op_sel_hi:[1,0]4414; GFX11-NEXT: v_pk_add_u16 v6, s18, 3 op_sel_hi:[1,0]4415; GFX11-NEXT: v_pk_add_u16 v5, s17, 3 op_sel_hi:[1,0]4416; GFX11-NEXT: v_pk_add_u16 v4, s16, 3 op_sel_hi:[1,0]4417; GFX11-NEXT: v_pk_add_u16 v3, s15, 3 op_sel_hi:[1,0]4418; GFX11-NEXT: v_pk_add_u16 v2, s14, 3 op_sel_hi:[1,0]4419; GFX11-NEXT: v_pk_add_u16 v1, s13, 3 op_sel_hi:[1,0]4420; GFX11-NEXT: v_pk_add_u16 v0, s12, 3 op_sel_hi:[1,0]4421; GFX11-NEXT: s_setpc_b64 s[30:31]4422; GFX11-NEXT: .LBB21_3:4423; GFX11-NEXT: s_branch .LBB21_24424; GFX11-NEXT: .LBB21_4:4425; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s134426; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s154427; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174428; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194429; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214430; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s234431; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s254432; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s274433; GFX11-NEXT: s_setpc_b64 s[30:31]4434 %cmp = icmp eq i32 %b, 04435 br i1 %cmp, label %cmp.true, label %cmp.false4436 4437cmp.true:4438 %a1 = add <18 x i16> %a, splat (i16 3)4439 %a2 = bitcast <18 x i16> %a1 to <18 x half>4440 br label %end4441 4442cmp.false:4443 %a3 = bitcast <18 x i16> %a to <18 x half>4444 br label %end4445 4446end:4447 %phi = phi <18 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4448 ret <18 x half> %phi4449}4450 4451define <18 x i16> @bitcast_v18f16_to_v18i16(<18 x half> %a, i32 %b) {4452; SI-LABEL: bitcast_v18f16_to_v18i16:4453; SI: ; %bb.0:4454; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4455; SI-NEXT: v_cvt_f16_f32_e32 v0, v04456; SI-NEXT: v_cvt_f16_f32_e32 v1, v14457; SI-NEXT: v_cvt_f16_f32_e32 v2, v24458; SI-NEXT: v_cvt_f16_f32_e32 v3, v34459; SI-NEXT: v_cvt_f16_f32_e32 v4, v44460; SI-NEXT: v_cvt_f16_f32_e32 v5, v54461; SI-NEXT: v_cvt_f16_f32_e32 v6, v64462; SI-NEXT: v_cvt_f16_f32_e32 v7, v74463; SI-NEXT: v_cvt_f16_f32_e32 v8, v84464; SI-NEXT: v_cvt_f16_f32_e32 v9, v94465; SI-NEXT: v_cvt_f16_f32_e32 v10, v104466; SI-NEXT: v_cvt_f16_f32_e32 v11, v114467; SI-NEXT: v_cvt_f16_f32_e32 v12, v124468; SI-NEXT: v_cvt_f16_f32_e32 v13, v134469; SI-NEXT: v_cvt_f16_f32_e32 v14, v144470; SI-NEXT: v_cvt_f16_f32_e32 v15, v154471; SI-NEXT: v_cvt_f16_f32_e32 v16, v164472; SI-NEXT: v_cvt_f16_f32_e32 v17, v174473; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v184474; SI-NEXT: s_and_saveexec_b64 s[4:5], vcc4475; SI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4476; SI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4477; SI-NEXT: s_cbranch_execz .LBB22_24478; SI-NEXT: ; %bb.1: ; %cmp.true4479; SI-NEXT: v_cvt_f32_f16_e32 v17, v174480; SI-NEXT: v_cvt_f32_f16_e32 v16, v164481; SI-NEXT: v_cvt_f32_f16_e32 v15, v154482; SI-NEXT: v_cvt_f32_f16_e32 v14, v144483; SI-NEXT: v_cvt_f32_f16_e32 v11, v114484; SI-NEXT: v_cvt_f32_f16_e32 v10, v104485; SI-NEXT: v_cvt_f32_f16_e32 v7, v74486; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v174487; SI-NEXT: v_cvt_f32_f16_e32 v6, v64488; SI-NEXT: v_cvt_f32_f16_e32 v3, v34489; SI-NEXT: v_cvt_f32_f16_e32 v1, v14490; SI-NEXT: v_cvt_f32_f16_e32 v5, v54491; SI-NEXT: v_cvt_f32_f16_e32 v9, v94492; SI-NEXT: v_cvt_f32_f16_e32 v13, v134493; SI-NEXT: v_cvt_f16_f32_e32 v17, v174494; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v164495; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v154496; SI-NEXT: v_cvt_f32_f16_e32 v2, v24497; SI-NEXT: v_cvt_f32_f16_e32 v0, v04498; SI-NEXT: v_cvt_f32_f16_e32 v4, v44499; SI-NEXT: v_cvt_f32_f16_e32 v8, v84500; SI-NEXT: v_cvt_f32_f16_e32 v12, v124501; SI-NEXT: v_cvt_f16_f32_e32 v16, v164502; SI-NEXT: v_cvt_f16_f32_e32 v15, v154503; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v144504; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v114505; SI-NEXT: v_cvt_f16_f32_e32 v14, v144506; SI-NEXT: v_cvt_f16_f32_e32 v11, v114507; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v104508; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v74509; SI-NEXT: v_cvt_f16_f32_e32 v10, v104510; SI-NEXT: v_cvt_f16_f32_e32 v7, v74511; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v64512; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v34513; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14514; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v54515; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v94516; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v134517; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v174518; SI-NEXT: v_cvt_f16_f32_e32 v6, v64519; SI-NEXT: v_cvt_f16_f32_e32 v3, v34520; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24521; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v04522; SI-NEXT: v_cvt_f16_f32_e32 v1, v14523; SI-NEXT: v_cvt_f16_f32_e32 v5, v54524; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44525; SI-NEXT: v_cvt_f16_f32_e32 v9, v94526; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v84527; SI-NEXT: v_cvt_f16_f32_e32 v13, v134528; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v124529; SI-NEXT: v_or_b32_e32 v16, v16, v184530; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v154531; SI-NEXT: v_cvt_f16_f32_e32 v2, v24532; SI-NEXT: v_cvt_f16_f32_e32 v0, v04533; SI-NEXT: v_cvt_f16_f32_e32 v4, v44534; SI-NEXT: v_cvt_f16_f32_e32 v8, v84535; SI-NEXT: v_cvt_f16_f32_e32 v12, v124536; SI-NEXT: v_or_b32_e32 v14, v14, v184537; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v114538; SI-NEXT: v_or_b32_e32 v10, v10, v184539; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v74540; SI-NEXT: v_or_b32_e32 v6, v6, v184541; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v34542; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14543; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54544; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v94545; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v134546; SI-NEXT: v_or_b32_e32 v2, v2, v184547; SI-NEXT: v_or_b32_e32 v0, v0, v14548; SI-NEXT: v_or_b32_e32 v4, v4, v54549; SI-NEXT: v_or_b32_e32 v8, v8, v94550; SI-NEXT: v_or_b32_e32 v12, v12, v134551; SI-NEXT: v_alignbit_b32 v1, v2, v1, 164552; SI-NEXT: v_alignbit_b32 v5, v6, v5, 164553; SI-NEXT: v_alignbit_b32 v9, v10, v9, 164554; SI-NEXT: v_alignbit_b32 v13, v14, v13, 164555; SI-NEXT: .LBB22_2: ; %end4556; SI-NEXT: s_or_b64 exec, exec, s[4:5]4557; SI-NEXT: s_setpc_b64 s[30:31]4558;4559; VI-LABEL: bitcast_v18f16_to_v18i16:4560; VI: ; %bb.0:4561; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4562; VI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v94563; VI-NEXT: s_and_saveexec_b64 s[4:5], vcc4564; VI-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4565; VI-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4566; VI-NEXT: s_cbranch_execz .LBB22_24567; VI-NEXT: ; %bb.1: ; %cmp.true4568; VI-NEXT: v_mov_b32_e32 v10, 0x2004569; VI-NEXT: v_add_f16_e32 v9, 0x200, v04570; VI-NEXT: v_add_f16_sdwa v0, v0, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4571; VI-NEXT: v_add_f16_e32 v11, 0x200, v14572; VI-NEXT: v_add_f16_sdwa v1, v1, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4573; VI-NEXT: v_add_f16_e32 v12, 0x200, v24574; VI-NEXT: v_add_f16_sdwa v2, v2, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4575; VI-NEXT: v_add_f16_e32 v13, 0x200, v34576; VI-NEXT: v_add_f16_sdwa v3, v3, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4577; VI-NEXT: v_add_f16_e32 v14, 0x200, v44578; VI-NEXT: v_add_f16_sdwa v4, v4, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4579; VI-NEXT: v_add_f16_e32 v15, 0x200, v54580; VI-NEXT: v_add_f16_sdwa v5, v5, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4581; VI-NEXT: v_add_f16_e32 v16, 0x200, v64582; VI-NEXT: v_add_f16_sdwa v6, v6, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4583; VI-NEXT: v_add_f16_e32 v17, 0x200, v74584; VI-NEXT: v_add_f16_sdwa v7, v7, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4585; VI-NEXT: v_add_f16_e32 v18, 0x200, v84586; VI-NEXT: v_add_f16_sdwa v8, v8, v10 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4587; VI-NEXT: v_or_b32_e32 v8, v18, v84588; VI-NEXT: v_or_b32_e32 v7, v17, v74589; VI-NEXT: v_or_b32_e32 v6, v16, v64590; VI-NEXT: v_or_b32_e32 v5, v15, v54591; VI-NEXT: v_or_b32_e32 v4, v14, v44592; VI-NEXT: v_or_b32_e32 v3, v13, v34593; VI-NEXT: v_or_b32_e32 v2, v12, v24594; VI-NEXT: v_or_b32_e32 v1, v11, v14595; VI-NEXT: v_or_b32_e32 v0, v9, v04596; VI-NEXT: .LBB22_2: ; %end4597; VI-NEXT: s_or_b64 exec, exec, s[4:5]4598; VI-NEXT: s_setpc_b64 s[30:31]4599;4600; GFX9-LABEL: bitcast_v18f16_to_v18i16:4601; GFX9: ; %bb.0:4602; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4603; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v94604; GFX9-NEXT: s_and_saveexec_b64 s[4:5], vcc4605; GFX9-NEXT: s_xor_b64 s[4:5], exec, s[4:5]4606; GFX9-NEXT: s_andn2_saveexec_b64 s[4:5], s[4:5]4607; GFX9-NEXT: s_cbranch_execz .LBB22_24608; GFX9-NEXT: ; %bb.1: ; %cmp.true4609; GFX9-NEXT: s_movk_i32 s6, 0x2004610; GFX9-NEXT: v_pk_add_f16 v8, v8, s6 op_sel_hi:[1,0]4611; GFX9-NEXT: v_pk_add_f16 v7, v7, s6 op_sel_hi:[1,0]4612; GFX9-NEXT: v_pk_add_f16 v6, v6, s6 op_sel_hi:[1,0]4613; GFX9-NEXT: v_pk_add_f16 v5, v5, s6 op_sel_hi:[1,0]4614; GFX9-NEXT: v_pk_add_f16 v4, v4, s6 op_sel_hi:[1,0]4615; GFX9-NEXT: v_pk_add_f16 v3, v3, s6 op_sel_hi:[1,0]4616; GFX9-NEXT: v_pk_add_f16 v2, v2, s6 op_sel_hi:[1,0]4617; GFX9-NEXT: v_pk_add_f16 v1, v1, s6 op_sel_hi:[1,0]4618; GFX9-NEXT: v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]4619; GFX9-NEXT: .LBB22_2: ; %end4620; GFX9-NEXT: s_or_b64 exec, exec, s[4:5]4621; GFX9-NEXT: s_setpc_b64 s[30:31]4622;4623; GFX11-LABEL: bitcast_v18f16_to_v18i16:4624; GFX11: ; %bb.0:4625; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4626; GFX11-NEXT: s_mov_b32 s0, exec_lo4627; GFX11-NEXT: v_cmpx_ne_u32_e32 0, v94628; GFX11-NEXT: s_xor_b32 s0, exec_lo, s04629; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)4630; GFX11-NEXT: s_and_not1_saveexec_b32 s0, s04631; GFX11-NEXT: s_cbranch_execz .LBB22_24632; GFX11-NEXT: ; %bb.1: ; %cmp.true4633; GFX11-NEXT: v_pk_add_f16 v8, 0x200, v8 op_sel_hi:[0,1]4634; GFX11-NEXT: v_pk_add_f16 v7, 0x200, v7 op_sel_hi:[0,1]4635; GFX11-NEXT: v_pk_add_f16 v6, 0x200, v6 op_sel_hi:[0,1]4636; GFX11-NEXT: v_pk_add_f16 v5, 0x200, v5 op_sel_hi:[0,1]4637; GFX11-NEXT: v_pk_add_f16 v4, 0x200, v4 op_sel_hi:[0,1]4638; GFX11-NEXT: v_pk_add_f16 v3, 0x200, v3 op_sel_hi:[0,1]4639; GFX11-NEXT: v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]4640; GFX11-NEXT: v_pk_add_f16 v1, 0x200, v1 op_sel_hi:[0,1]4641; GFX11-NEXT: v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]4642; GFX11-NEXT: .LBB22_2: ; %end4643; GFX11-NEXT: s_or_b32 exec_lo, exec_lo, s04644; GFX11-NEXT: s_setpc_b64 s[30:31]4645 %cmp = icmp eq i32 %b, 04646 br i1 %cmp, label %cmp.true, label %cmp.false4647 4648cmp.true:4649 %a1 = fadd <18 x half> %a, splat (half 0xH0200)4650 %a2 = bitcast <18 x half> %a1 to <18 x i16>4651 br label %end4652 4653cmp.false:4654 %a3 = bitcast <18 x half> %a to <18 x i16>4655 br label %end4656 4657end:4658 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4659 ret <18 x i16> %phi4660}4661 4662define inreg <18 x i16> @bitcast_v18f16_to_v18i16_scalar(<18 x half> inreg %a, i32 inreg %b) {4663; SI-LABEL: bitcast_v18f16_to_v18i16_scalar:4664; SI: ; %bb.0:4665; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4666; SI-NEXT: v_mov_b32_e32 v5, v34667; SI-NEXT: v_mov_b32_e32 v9, v24668; SI-NEXT: v_mov_b32_e32 v10, v04669; SI-NEXT: v_cmp_ne_u32_e32 vcc, 0, v44670; SI-NEXT: v_cvt_f16_f32_e32 v0, s164671; SI-NEXT: v_cvt_f16_f32_e32 v23, s174672; SI-NEXT: v_cvt_f16_f32_e32 v2, s184673; SI-NEXT: v_cvt_f16_f32_e32 v3, s194674; SI-NEXT: v_cvt_f16_f32_e32 v4, s204675; SI-NEXT: v_cvt_f16_f32_e32 v18, s214676; SI-NEXT: v_cvt_f16_f32_e32 v6, s224677; SI-NEXT: v_cvt_f16_f32_e32 v7, s234678; SI-NEXT: v_cvt_f16_f32_e32 v8, s244679; SI-NEXT: v_cvt_f16_f32_e32 v11, s274680; SI-NEXT: v_cvt_f16_f32_e32 v12, s284681; SI-NEXT: v_cvt_f16_f32_e32 v14, v104682; SI-NEXT: v_cvt_f16_f32_e32 v15, v14683; SI-NEXT: v_cvt_f16_f32_e32 v16, v94684; SI-NEXT: v_cvt_f16_f32_e32 v17, v54685; SI-NEXT: v_cvt_f16_f32_e32 v21, s254686; SI-NEXT: v_cvt_f16_f32_e32 v10, s264687; SI-NEXT: v_cvt_f16_f32_e32 v19, s294688; SI-NEXT: s_and_b64 s[4:5], vcc, exec4689; SI-NEXT: s_cbranch_scc0 .LBB23_44690; SI-NEXT: ; %bb.1: ; %cmp.false4691; SI-NEXT: s_cbranch_execnz .LBB23_34692; SI-NEXT: .LBB23_2: ; %cmp.true4693; SI-NEXT: v_cvt_f32_f16_e32 v15, v154694; SI-NEXT: v_cvt_f32_f16_e32 v14, v144695; SI-NEXT: v_cvt_f32_f16_e32 v11, v114696; SI-NEXT: v_cvt_f32_f16_e32 v10, v104697; SI-NEXT: v_cvt_f32_f16_e32 v7, v74698; SI-NEXT: v_cvt_f32_f16_e32 v17, v174699; SI-NEXT: v_cvt_f32_f16_e32 v6, v64700; SI-NEXT: v_cvt_f32_f16_e32 v5, v184701; SI-NEXT: v_add_f32_e32 v15, 0x38000000, v154702; SI-NEXT: v_cvt_f32_f16_e32 v16, v164703; SI-NEXT: v_cvt_f32_f16_e32 v3, v34704; SI-NEXT: v_cvt_f32_f16_e32 v1, v234705; SI-NEXT: v_cvt_f32_f16_e32 v9, v214706; SI-NEXT: v_cvt_f32_f16_e32 v13, v194707; SI-NEXT: v_cvt_f16_f32_e32 v15, v154708; SI-NEXT: v_add_f32_e32 v14, 0x38000000, v144709; SI-NEXT: v_add_f32_e32 v11, 0x38000000, v114710; SI-NEXT: v_cvt_f32_f16_e32 v2, v24711; SI-NEXT: v_cvt_f16_f32_e32 v14, v144712; SI-NEXT: v_cvt_f16_f32_e32 v11, v114713; SI-NEXT: v_add_f32_e32 v10, 0x38000000, v104714; SI-NEXT: v_add_f32_e32 v7, 0x38000000, v74715; SI-NEXT: v_cvt_f32_f16_e32 v0, v04716; SI-NEXT: v_cvt_f32_f16_e32 v4, v44717; SI-NEXT: v_cvt_f32_f16_e32 v8, v84718; SI-NEXT: v_cvt_f32_f16_e32 v12, v124719; SI-NEXT: v_add_f32_e32 v17, 0x38000000, v174720; SI-NEXT: v_cvt_f16_f32_e32 v10, v104721; SI-NEXT: v_cvt_f16_f32_e32 v7, v74722; SI-NEXT: v_add_f32_e32 v6, 0x38000000, v64723; SI-NEXT: v_add_f32_e32 v5, 0x38000000, v54724; SI-NEXT: v_cvt_f16_f32_e32 v17, v174725; SI-NEXT: v_cvt_f16_f32_e32 v6, v64726; SI-NEXT: v_add_f32_e32 v16, 0x38000000, v164727; SI-NEXT: v_add_f32_e32 v3, 0x38000000, v34728; SI-NEXT: v_add_f32_e32 v1, 0x38000000, v14729; SI-NEXT: v_cvt_f16_f32_e32 v5, v54730; SI-NEXT: v_add_f32_e32 v9, 0x38000000, v94731; SI-NEXT: v_add_f32_e32 v13, 0x38000000, v134732; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v154733; SI-NEXT: v_cvt_f16_f32_e32 v16, v164734; SI-NEXT: v_cvt_f16_f32_e32 v3, v34735; SI-NEXT: v_add_f32_e32 v2, 0x38000000, v24736; SI-NEXT: v_cvt_f16_f32_e32 v1, v14737; SI-NEXT: v_cvt_f16_f32_e32 v9, v94738; SI-NEXT: v_cvt_f16_f32_e32 v13, v134739; SI-NEXT: v_or_b32_e32 v14, v14, v184740; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v114741; SI-NEXT: v_cvt_f16_f32_e32 v2, v24742; SI-NEXT: v_add_f32_e32 v0, 0x38000000, v04743; SI-NEXT: v_add_f32_e32 v4, 0x38000000, v44744; SI-NEXT: v_add_f32_e32 v8, 0x38000000, v84745; SI-NEXT: v_add_f32_e32 v12, 0x38000000, v124746; SI-NEXT: v_or_b32_e32 v10, v10, v184747; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v74748; SI-NEXT: v_cvt_f16_f32_e32 v0, v04749; SI-NEXT: v_cvt_f16_f32_e32 v4, v44750; SI-NEXT: v_cvt_f16_f32_e32 v8, v84751; SI-NEXT: v_cvt_f16_f32_e32 v12, v124752; SI-NEXT: v_or_b32_e32 v6, v6, v184753; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v174754; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v54755; SI-NEXT: v_or_b32_e32 v16, v16, v184756; SI-NEXT: v_lshlrev_b32_e32 v18, 16, v34757; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v14758; SI-NEXT: v_lshlrev_b32_e32 v9, 16, v94759; SI-NEXT: v_lshlrev_b32_e32 v13, 16, v134760; SI-NEXT: v_or_b32_e32 v2, v2, v184761; SI-NEXT: v_lshr_b64 v[18:19], v[5:6], 164762; SI-NEXT: v_lshr_b64 v[23:24], v[1:2], 164763; SI-NEXT: v_lshr_b64 v[21:22], v[9:10], 164764; SI-NEXT: v_lshr_b64 v[19:20], v[13:14], 164765; SI-NEXT: v_or_b32_e32 v0, v0, v14766; SI-NEXT: v_or_b32_e32 v4, v4, v54767; SI-NEXT: v_or_b32_e32 v8, v8, v94768; SI-NEXT: v_or_b32_e32 v12, v12, v134769; SI-NEXT: .LBB23_3: ; %end4770; SI-NEXT: v_mov_b32_e32 v1, v234771; SI-NEXT: v_mov_b32_e32 v5, v184772; SI-NEXT: v_mov_b32_e32 v9, v214773; SI-NEXT: v_mov_b32_e32 v13, v194774; SI-NEXT: s_setpc_b64 s[30:31]4775; SI-NEXT: .LBB23_4:4776; SI-NEXT: s_branch .LBB23_24777;4778; VI-LABEL: bitcast_v18f16_to_v18i16_scalar:4779; VI: ; %bb.0:4780; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4781; VI-NEXT: s_cmp_lg_u32 s25, 04782; VI-NEXT: s_cbranch_scc0 .LBB23_34783; VI-NEXT: ; %bb.1: ; %cmp.false4784; VI-NEXT: s_cbranch_execnz .LBB23_44785; VI-NEXT: .LBB23_2: ; %cmp.true4786; VI-NEXT: s_lshr_b32 s5, s23, 164787; VI-NEXT: v_mov_b32_e32 v0, 0x2004788; VI-NEXT: v_mov_b32_e32 v2, s54789; VI-NEXT: s_lshr_b32 s5, s24, 164790; VI-NEXT: v_add_f16_e32 v1, s23, v04791; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4792; VI-NEXT: v_mov_b32_e32 v4, s54793; VI-NEXT: s_lshr_b32 s5, s22, 164794; VI-NEXT: v_or_b32_e32 v7, v1, v24795; VI-NEXT: v_mov_b32_e32 v2, s54796; VI-NEXT: v_add_f16_e32 v1, s22, v04797; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4798; VI-NEXT: s_lshr_b32 s5, s21, 164799; VI-NEXT: v_or_b32_e32 v6, v1, v24800; VI-NEXT: v_mov_b32_e32 v2, s54801; VI-NEXT: v_add_f16_e32 v1, s21, v04802; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4803; VI-NEXT: s_lshr_b32 s5, s20, 164804; VI-NEXT: v_or_b32_e32 v5, v1, v24805; VI-NEXT: v_mov_b32_e32 v2, s54806; VI-NEXT: v_add_f16_e32 v3, s24, v04807; VI-NEXT: v_add_f16_sdwa v4, v4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4808; VI-NEXT: v_add_f16_e32 v1, s20, v04809; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4810; VI-NEXT: s_lshr_b32 s5, s19, 164811; VI-NEXT: v_or_b32_e32 v8, v3, v44812; VI-NEXT: v_or_b32_e32 v4, v1, v24813; VI-NEXT: v_mov_b32_e32 v2, s54814; VI-NEXT: v_add_f16_e32 v1, s19, v04815; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4816; VI-NEXT: s_lshr_b32 s5, s18, 164817; VI-NEXT: v_or_b32_e32 v3, v1, v24818; VI-NEXT: v_mov_b32_e32 v2, s54819; VI-NEXT: s_lshr_b32 s4, s16, 164820; VI-NEXT: v_add_f16_e32 v1, s18, v04821; VI-NEXT: v_add_f16_sdwa v2, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4822; VI-NEXT: v_or_b32_e32 v2, v1, v24823; VI-NEXT: v_mov_b32_e32 v1, s44824; VI-NEXT: s_lshr_b32 s4, s17, 164825; VI-NEXT: v_add_f16_sdwa v10, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4826; VI-NEXT: v_mov_b32_e32 v1, s44827; VI-NEXT: v_add_f16_e32 v9, s16, v04828; VI-NEXT: v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4829; VI-NEXT: v_add_f16_e32 v0, s17, v04830; VI-NEXT: v_or_b32_e32 v1, v0, v14831; VI-NEXT: v_or_b32_e32 v0, v9, v104832; VI-NEXT: s_setpc_b64 s[30:31]4833; VI-NEXT: .LBB23_3:4834; VI-NEXT: s_branch .LBB23_24835; VI-NEXT: .LBB23_4:4836; VI-NEXT: v_mov_b32_e32 v0, s164837; VI-NEXT: v_mov_b32_e32 v1, s174838; VI-NEXT: v_mov_b32_e32 v2, s184839; VI-NEXT: v_mov_b32_e32 v3, s194840; VI-NEXT: v_mov_b32_e32 v4, s204841; VI-NEXT: v_mov_b32_e32 v5, s214842; VI-NEXT: v_mov_b32_e32 v6, s224843; VI-NEXT: v_mov_b32_e32 v7, s234844; VI-NEXT: v_mov_b32_e32 v8, s244845; VI-NEXT: v_mov_b32_e32 v9, s254846; VI-NEXT: v_mov_b32_e32 v10, s264847; VI-NEXT: v_mov_b32_e32 v11, s274848; VI-NEXT: v_mov_b32_e32 v12, s284849; VI-NEXT: v_mov_b32_e32 v13, s294850; VI-NEXT: v_mov_b32_e32 v14, s304851; VI-NEXT: v_mov_b32_e32 v15, s314852; VI-NEXT: s_setpc_b64 s[30:31]4853;4854; GFX9-LABEL: bitcast_v18f16_to_v18i16_scalar:4855; GFX9: ; %bb.0:4856; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4857; GFX9-NEXT: s_cmp_lg_u32 s25, 04858; GFX9-NEXT: s_cbranch_scc0 .LBB23_34859; GFX9-NEXT: ; %bb.1: ; %cmp.false4860; GFX9-NEXT: s_cbranch_execnz .LBB23_44861; GFX9-NEXT: .LBB23_2: ; %cmp.true4862; GFX9-NEXT: v_mov_b32_e32 v0, 0x2004863; GFX9-NEXT: v_pk_add_f16 v8, s24, v0 op_sel_hi:[1,0]4864; GFX9-NEXT: v_pk_add_f16 v7, s23, v0 op_sel_hi:[1,0]4865; GFX9-NEXT: v_pk_add_f16 v6, s22, v0 op_sel_hi:[1,0]4866; GFX9-NEXT: v_pk_add_f16 v5, s21, v0 op_sel_hi:[1,0]4867; GFX9-NEXT: v_pk_add_f16 v4, s20, v0 op_sel_hi:[1,0]4868; GFX9-NEXT: v_pk_add_f16 v3, s19, v0 op_sel_hi:[1,0]4869; GFX9-NEXT: v_pk_add_f16 v2, s18, v0 op_sel_hi:[1,0]4870; GFX9-NEXT: v_pk_add_f16 v1, s17, v0 op_sel_hi:[1,0]4871; GFX9-NEXT: v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]4872; GFX9-NEXT: s_setpc_b64 s[30:31]4873; GFX9-NEXT: .LBB23_3:4874; GFX9-NEXT: s_branch .LBB23_24875; GFX9-NEXT: .LBB23_4:4876; GFX9-NEXT: v_mov_b32_e32 v0, s164877; GFX9-NEXT: v_mov_b32_e32 v1, s174878; GFX9-NEXT: v_mov_b32_e32 v2, s184879; GFX9-NEXT: v_mov_b32_e32 v3, s194880; GFX9-NEXT: v_mov_b32_e32 v4, s204881; GFX9-NEXT: v_mov_b32_e32 v5, s214882; GFX9-NEXT: v_mov_b32_e32 v6, s224883; GFX9-NEXT: v_mov_b32_e32 v7, s234884; GFX9-NEXT: v_mov_b32_e32 v8, s244885; GFX9-NEXT: v_mov_b32_e32 v9, s254886; GFX9-NEXT: v_mov_b32_e32 v10, s264887; GFX9-NEXT: v_mov_b32_e32 v11, s274888; GFX9-NEXT: v_mov_b32_e32 v12, s284889; GFX9-NEXT: v_mov_b32_e32 v13, s294890; GFX9-NEXT: v_mov_b32_e32 v14, s304891; GFX9-NEXT: v_mov_b32_e32 v15, s314892; GFX9-NEXT: s_setpc_b64 s[30:31]4893;4894; GFX11-LABEL: bitcast_v18f16_to_v18i16_scalar:4895; GFX11: ; %bb.0:4896; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4897; GFX11-NEXT: s_mov_b32 s15, s34898; GFX11-NEXT: s_mov_b32 s14, s24899; GFX11-NEXT: s_mov_b32 s13, s14900; GFX11-NEXT: s_mov_b32 s12, s04901; GFX11-NEXT: s_cmp_lg_u32 s21, 04902; GFX11-NEXT: s_mov_b32 s0, 04903; GFX11-NEXT: s_cbranch_scc0 .LBB23_34904; GFX11-NEXT: ; %bb.1: ; %Flow4905; GFX11-NEXT: s_and_not1_b32 vcc_lo, exec_lo, s04906; GFX11-NEXT: s_cbranch_vccnz .LBB23_44907; GFX11-NEXT: .LBB23_2: ; %cmp.true4908; GFX11-NEXT: v_pk_add_f16 v8, 0x200, s20 op_sel_hi:[0,1]4909; GFX11-NEXT: v_pk_add_f16 v7, 0x200, s19 op_sel_hi:[0,1]4910; GFX11-NEXT: v_pk_add_f16 v6, 0x200, s18 op_sel_hi:[0,1]4911; GFX11-NEXT: v_pk_add_f16 v5, 0x200, s17 op_sel_hi:[0,1]4912; GFX11-NEXT: v_pk_add_f16 v4, 0x200, s16 op_sel_hi:[0,1]4913; GFX11-NEXT: v_pk_add_f16 v3, 0x200, s15 op_sel_hi:[0,1]4914; GFX11-NEXT: v_pk_add_f16 v2, 0x200, s14 op_sel_hi:[0,1]4915; GFX11-NEXT: v_pk_add_f16 v1, 0x200, s13 op_sel_hi:[0,1]4916; GFX11-NEXT: v_pk_add_f16 v0, 0x200, s12 op_sel_hi:[0,1]4917; GFX11-NEXT: s_setpc_b64 s[30:31]4918; GFX11-NEXT: .LBB23_3:4919; GFX11-NEXT: s_branch .LBB23_24920; GFX11-NEXT: .LBB23_4:4921; GFX11-NEXT: v_dual_mov_b32 v0, s12 :: v_dual_mov_b32 v1, s134922; GFX11-NEXT: v_dual_mov_b32 v2, s14 :: v_dual_mov_b32 v3, s154923; GFX11-NEXT: v_dual_mov_b32 v4, s16 :: v_dual_mov_b32 v5, s174924; GFX11-NEXT: v_dual_mov_b32 v6, s18 :: v_dual_mov_b32 v7, s194925; GFX11-NEXT: v_dual_mov_b32 v8, s20 :: v_dual_mov_b32 v9, s214926; GFX11-NEXT: v_dual_mov_b32 v10, s22 :: v_dual_mov_b32 v11, s234927; GFX11-NEXT: v_dual_mov_b32 v12, s24 :: v_dual_mov_b32 v13, s254928; GFX11-NEXT: v_dual_mov_b32 v14, s26 :: v_dual_mov_b32 v15, s274929; GFX11-NEXT: s_setpc_b64 s[30:31]4930 %cmp = icmp eq i32 %b, 04931 br i1 %cmp, label %cmp.true, label %cmp.false4932 4933cmp.true:4934 %a1 = fadd <18 x half> %a, splat (half 0xH0200)4935 %a2 = bitcast <18 x half> %a1 to <18 x i16>4936 br label %end4937 4938cmp.false:4939 %a3 = bitcast <18 x half> %a to <18 x i16>4940 br label %end4941 4942end:4943 %phi = phi <18 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4944 ret <18 x i16> %phi4945}4946;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:4947; GFX11-FAKE16: {{.*}}4948; GFX11-TRUE16: {{.*}}4949