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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefix=SI %s4; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefix=VI %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefix=GFX9 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s8 9define float @bitcast_i32_to_f32(i32 %a, i32 %b) {10; SI-LABEL: bitcast_i32_to_f32:11; SI:       ; %bb.0:12; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v114; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc15; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]16; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]17; SI-NEXT:  ; %bb.1: ; %cmp.true18; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v019; SI-NEXT:  ; %bb.2: ; %end20; SI-NEXT:    s_or_b64 exec, exec, s[4:5]21; SI-NEXT:    s_setpc_b64 s[30:31]22;23; VI-LABEL: bitcast_i32_to_f32:24; VI:       ; %bb.0:25; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)26; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v127; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc28; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]29; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]30; VI-NEXT:  ; %bb.1: ; %cmp.true31; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v032; VI-NEXT:  ; %bb.2: ; %end33; VI-NEXT:    s_or_b64 exec, exec, s[4:5]34; VI-NEXT:    s_setpc_b64 s[30:31]35;36; GFX9-LABEL: bitcast_i32_to_f32:37; GFX9:       ; %bb.0:38; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)39; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v140; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc41; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]42; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]43; GFX9-NEXT:  ; %bb.1: ; %cmp.true44; GFX9-NEXT:    v_add_u32_e32 v0, 3, v045; GFX9-NEXT:  ; %bb.2: ; %end46; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]47; GFX9-NEXT:    s_setpc_b64 s[30:31]48;49; GFX11-LABEL: bitcast_i32_to_f32:50; GFX11:       ; %bb.0:51; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GFX11-NEXT:    s_mov_b32 s0, exec_lo53; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v154; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s055; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)56; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s057; GFX11-NEXT:  ; %bb.1: ; %cmp.true58; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v059; GFX11-NEXT:  ; %bb.2: ; %end60; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s061; GFX11-NEXT:    s_setpc_b64 s[30:31]62  %cmp = icmp eq i32 %b, 063  br i1 %cmp, label %cmp.true, label %cmp.false64 65cmp.true:66  %a1 = add i32 %a, 367  %a2 = bitcast i32 %a1 to float68  br label %end69 70cmp.false:71  %a3 = bitcast i32 %a to float72  br label %end73 74end:75  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]76  ret float %phi77}78 79define inreg float @bitcast_i32_to_f32_scalar(i32 inreg %a, i32 inreg %b) {80; SI-LABEL: bitcast_i32_to_f32_scalar:81; SI:       ; %bb.0:82; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; SI-NEXT:    s_cmp_lg_u32 s17, 084; SI-NEXT:    s_cbranch_scc0 .LBB1_485; SI-NEXT:  ; %bb.1: ; %cmp.false86; SI-NEXT:    s_cbranch_execnz .LBB1_387; SI-NEXT:  .LBB1_2: ; %cmp.true88; SI-NEXT:    s_add_i32 s16, s16, 389; SI-NEXT:  .LBB1_3: ; %end90; SI-NEXT:    v_mov_b32_e32 v0, s1691; SI-NEXT:    s_setpc_b64 s[30:31]92; SI-NEXT:  .LBB1_4:93; SI-NEXT:    s_branch .LBB1_294;95; VI-LABEL: bitcast_i32_to_f32_scalar:96; VI:       ; %bb.0:97; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)98; VI-NEXT:    s_cmp_lg_u32 s17, 099; VI-NEXT:    s_cbranch_scc0 .LBB1_4100; VI-NEXT:  ; %bb.1: ; %cmp.false101; VI-NEXT:    s_cbranch_execnz .LBB1_3102; VI-NEXT:  .LBB1_2: ; %cmp.true103; VI-NEXT:    s_add_i32 s16, s16, 3104; VI-NEXT:  .LBB1_3: ; %end105; VI-NEXT:    v_mov_b32_e32 v0, s16106; VI-NEXT:    s_setpc_b64 s[30:31]107; VI-NEXT:  .LBB1_4:108; VI-NEXT:    s_branch .LBB1_2109;110; GFX9-LABEL: bitcast_i32_to_f32_scalar:111; GFX9:       ; %bb.0:112; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)113; GFX9-NEXT:    s_cmp_lg_u32 s17, 0114; GFX9-NEXT:    s_cbranch_scc0 .LBB1_4115; GFX9-NEXT:  ; %bb.1: ; %cmp.false116; GFX9-NEXT:    s_cbranch_execnz .LBB1_3117; GFX9-NEXT:  .LBB1_2: ; %cmp.true118; GFX9-NEXT:    s_add_i32 s16, s16, 3119; GFX9-NEXT:  .LBB1_3: ; %end120; GFX9-NEXT:    v_mov_b32_e32 v0, s16121; GFX9-NEXT:    s_setpc_b64 s[30:31]122; GFX9-NEXT:  .LBB1_4:123; GFX9-NEXT:    s_branch .LBB1_2124;125; GFX11-LABEL: bitcast_i32_to_f32_scalar:126; GFX11:       ; %bb.0:127; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)128; GFX11-NEXT:    s_cmp_lg_u32 s1, 0129; GFX11-NEXT:    s_mov_b32 s1, 0130; GFX11-NEXT:    s_cbranch_scc0 .LBB1_3131; GFX11-NEXT:  ; %bb.1: ; %Flow132; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s1133; GFX11-NEXT:    s_cbranch_vccz .LBB1_4134; GFX11-NEXT:  ; %bb.2: ; %end135; GFX11-NEXT:    v_mov_b32_e32 v0, s0136; GFX11-NEXT:    s_setpc_b64 s[30:31]137; GFX11-NEXT:  .LBB1_3:138; GFX11-NEXT:  .LBB1_4: ; %cmp.true139; GFX11-NEXT:    s_add_i32 s0, s0, 3140; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)141; GFX11-NEXT:    v_mov_b32_e32 v0, s0142; GFX11-NEXT:    s_setpc_b64 s[30:31]143  %cmp = icmp eq i32 %b, 0144  br i1 %cmp, label %cmp.true, label %cmp.false145 146cmp.true:147  %a1 = add i32 %a, 3148  %a2 = bitcast i32 %a1 to float149  br label %end150 151cmp.false:152  %a3 = bitcast i32 %a to float153  br label %end154 155end:156  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]157  ret float %phi158}159 160define i32 @bitcast_f32_to_i32(float %a, i32 %b) {161; SI-LABEL: bitcast_f32_to_i32:162; SI:       ; %bb.0:163; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)164; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1165; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc166; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]167; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]168; SI-NEXT:  ; %bb.1: ; %cmp.true169; SI-NEXT:    v_add_f32_e32 v0, 1.0, v0170; SI-NEXT:  ; %bb.2: ; %end171; SI-NEXT:    s_or_b64 exec, exec, s[4:5]172; SI-NEXT:    s_setpc_b64 s[30:31]173;174; VI-LABEL: bitcast_f32_to_i32:175; VI:       ; %bb.0:176; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1178; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc179; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]180; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]181; VI-NEXT:  ; %bb.1: ; %cmp.true182; VI-NEXT:    v_add_f32_e32 v0, 1.0, v0183; VI-NEXT:  ; %bb.2: ; %end184; VI-NEXT:    s_or_b64 exec, exec, s[4:5]185; VI-NEXT:    s_setpc_b64 s[30:31]186;187; GFX9-LABEL: bitcast_f32_to_i32:188; GFX9:       ; %bb.0:189; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1191; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc192; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]193; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]194; GFX9-NEXT:  ; %bb.1: ; %cmp.true195; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0196; GFX9-NEXT:  ; %bb.2: ; %end197; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]198; GFX9-NEXT:    s_setpc_b64 s[30:31]199;200; GFX11-LABEL: bitcast_f32_to_i32:201; GFX11:       ; %bb.0:202; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)203; GFX11-NEXT:    s_mov_b32 s0, exec_lo204; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1205; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0206; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)207; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0208; GFX11-NEXT:  ; %bb.1: ; %cmp.true209; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0210; GFX11-NEXT:  ; %bb.2: ; %end211; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0212; GFX11-NEXT:    s_setpc_b64 s[30:31]213  %cmp = icmp eq i32 %b, 0214  br i1 %cmp, label %cmp.true, label %cmp.false215 216cmp.true:217  %a1 = fadd float %a, 1.000000e+00218  %a2 = bitcast float %a1 to i32219  br label %end220 221cmp.false:222  %a3 = bitcast float %a to i32223  br label %end224 225end:226  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]227  ret i32 %phi228}229 230define inreg i32 @bitcast_f32_to_i32_scalar(float inreg %a, i32 inreg %b) {231; SI-LABEL: bitcast_f32_to_i32_scalar:232; SI:       ; %bb.0:233; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)234; SI-NEXT:    s_cmp_lg_u32 s17, 0235; SI-NEXT:    s_cbranch_scc0 .LBB3_3236; SI-NEXT:  ; %bb.1: ; %cmp.false237; SI-NEXT:    s_cbranch_execnz .LBB3_4238; SI-NEXT:  .LBB3_2: ; %cmp.true239; SI-NEXT:    v_add_f32_e64 v0, s16, 1.0240; SI-NEXT:    s_setpc_b64 s[30:31]241; SI-NEXT:  .LBB3_3:242; SI-NEXT:    s_branch .LBB3_2243; SI-NEXT:  .LBB3_4:244; SI-NEXT:    v_mov_b32_e32 v0, s16245; SI-NEXT:    s_setpc_b64 s[30:31]246;247; VI-LABEL: bitcast_f32_to_i32_scalar:248; VI:       ; %bb.0:249; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)250; VI-NEXT:    s_cmp_lg_u32 s17, 0251; VI-NEXT:    s_cbranch_scc0 .LBB3_3252; VI-NEXT:  ; %bb.1: ; %cmp.false253; VI-NEXT:    s_cbranch_execnz .LBB3_4254; VI-NEXT:  .LBB3_2: ; %cmp.true255; VI-NEXT:    v_add_f32_e64 v0, s16, 1.0256; VI-NEXT:    s_setpc_b64 s[30:31]257; VI-NEXT:  .LBB3_3:258; VI-NEXT:    s_branch .LBB3_2259; VI-NEXT:  .LBB3_4:260; VI-NEXT:    v_mov_b32_e32 v0, s16261; VI-NEXT:    s_setpc_b64 s[30:31]262;263; GFX9-LABEL: bitcast_f32_to_i32_scalar:264; GFX9:       ; %bb.0:265; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)266; GFX9-NEXT:    s_cmp_lg_u32 s17, 0267; GFX9-NEXT:    s_cbranch_scc0 .LBB3_3268; GFX9-NEXT:  ; %bb.1: ; %cmp.false269; GFX9-NEXT:    s_cbranch_execnz .LBB3_4270; GFX9-NEXT:  .LBB3_2: ; %cmp.true271; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.0272; GFX9-NEXT:    s_setpc_b64 s[30:31]273; GFX9-NEXT:  .LBB3_3:274; GFX9-NEXT:    s_branch .LBB3_2275; GFX9-NEXT:  .LBB3_4:276; GFX9-NEXT:    v_mov_b32_e32 v0, s16277; GFX9-NEXT:    s_setpc_b64 s[30:31]278;279; GFX11-LABEL: bitcast_f32_to_i32_scalar:280; GFX11:       ; %bb.0:281; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)282; GFX11-NEXT:    s_cmp_lg_u32 s1, 0283; GFX11-NEXT:    s_mov_b32 s1, 0284; GFX11-NEXT:    s_cbranch_scc0 .LBB3_3285; GFX11-NEXT:  ; %bb.1: ; %Flow286; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s1287; GFX11-NEXT:    s_cbranch_vccnz .LBB3_4288; GFX11-NEXT:  .LBB3_2: ; %cmp.true289; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.0290; GFX11-NEXT:    s_setpc_b64 s[30:31]291; GFX11-NEXT:  .LBB3_3:292; GFX11-NEXT:    s_branch .LBB3_2293; GFX11-NEXT:  .LBB3_4:294; GFX11-NEXT:    v_mov_b32_e32 v0, s0295; GFX11-NEXT:    s_setpc_b64 s[30:31]296  %cmp = icmp eq i32 %b, 0297  br i1 %cmp, label %cmp.true, label %cmp.false298 299cmp.true:300  %a1 = fadd float %a, 1.000000e+00301  %a2 = bitcast float %a1 to i32302  br label %end303 304cmp.false:305  %a3 = bitcast float %a to i32306  br label %end307 308end:309  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]310  ret i32 %phi311}312 313define <2 x i16> @bitcast_i32_to_v2i16(i32 %a, i32 %b) {314; SI-LABEL: bitcast_i32_to_v2i16:315; SI:       ; %bb.0:316; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)317; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1318; SI-NEXT:    ; implicit-def: $vgpr1319; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc320; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]321; SI-NEXT:    s_cbranch_execnz .LBB4_3322; SI-NEXT:  ; %bb.1: ; %Flow323; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]324; SI-NEXT:    s_cbranch_execnz .LBB4_4325; SI-NEXT:  .LBB4_2: ; %end326; SI-NEXT:    s_or_b64 exec, exec, s[4:5]327; SI-NEXT:    s_setpc_b64 s[30:31]328; SI-NEXT:  .LBB4_3: ; %cmp.false329; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0330; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]331; SI-NEXT:    s_cbranch_execz .LBB4_2332; SI-NEXT:  .LBB4_4: ; %cmp.true333; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v0334; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0335; SI-NEXT:    s_or_b64 exec, exec, s[4:5]336; SI-NEXT:    s_setpc_b64 s[30:31]337;338; VI-LABEL: bitcast_i32_to_v2i16:339; VI:       ; %bb.0:340; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)341; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1342; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc343; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]344; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]345; VI-NEXT:  ; %bb.1: ; %cmp.true346; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0347; VI-NEXT:  ; %bb.2: ; %end348; VI-NEXT:    s_or_b64 exec, exec, s[4:5]349; VI-NEXT:    s_setpc_b64 s[30:31]350;351; GFX9-LABEL: bitcast_i32_to_v2i16:352; GFX9:       ; %bb.0:353; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)354; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1355; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc356; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]357; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]358; GFX9-NEXT:  ; %bb.1: ; %cmp.true359; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0360; GFX9-NEXT:  ; %bb.2: ; %end361; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]362; GFX9-NEXT:    s_setpc_b64 s[30:31]363;364; GFX11-LABEL: bitcast_i32_to_v2i16:365; GFX11:       ; %bb.0:366; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)367; GFX11-NEXT:    s_mov_b32 s0, exec_lo368; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1369; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0370; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)371; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0372; GFX11-NEXT:  ; %bb.1: ; %cmp.true373; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0374; GFX11-NEXT:  ; %bb.2: ; %end375; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0376; GFX11-NEXT:    s_setpc_b64 s[30:31]377  %cmp = icmp eq i32 %b, 0378  br i1 %cmp, label %cmp.true, label %cmp.false379 380cmp.true:381  %a1 = add i32 %a, 3382  %a2 = bitcast i32 %a1 to <2 x i16>383  br label %end384 385cmp.false:386  %a3 = bitcast i32 %a to <2 x i16>387  br label %end388 389end:390  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]391  ret <2 x i16> %phi392}393 394define inreg <2 x i16> @bitcast_i32_to_v2i16_scalar(i32 inreg %a, i32 inreg %b) {395; SI-LABEL: bitcast_i32_to_v2i16_scalar:396; SI:       ; %bb.0:397; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)398; SI-NEXT:    s_cmp_lg_u32 s17, 0399; SI-NEXT:    s_cbranch_scc0 .LBB5_4400; SI-NEXT:  ; %bb.1: ; %cmp.false401; SI-NEXT:    s_lshr_b32 s6, s16, 16402; SI-NEXT:    s_cbranch_execnz .LBB5_3403; SI-NEXT:  .LBB5_2: ; %cmp.true404; SI-NEXT:    s_add_i32 s16, s16, 3405; SI-NEXT:    s_lshr_b32 s6, s16, 16406; SI-NEXT:  .LBB5_3: ; %end407; SI-NEXT:    v_mov_b32_e32 v0, s16408; SI-NEXT:    v_mov_b32_e32 v1, s6409; SI-NEXT:    s_setpc_b64 s[30:31]410; SI-NEXT:  .LBB5_4:411; SI-NEXT:    ; implicit-def: $sgpr6412; SI-NEXT:    s_branch .LBB5_2413;414; VI-LABEL: bitcast_i32_to_v2i16_scalar:415; VI:       ; %bb.0:416; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)417; VI-NEXT:    s_cmp_lg_u32 s17, 0418; VI-NEXT:    s_cbranch_scc0 .LBB5_4419; VI-NEXT:  ; %bb.1: ; %cmp.false420; VI-NEXT:    s_cbranch_execnz .LBB5_3421; VI-NEXT:  .LBB5_2: ; %cmp.true422; VI-NEXT:    s_add_i32 s16, s16, 3423; VI-NEXT:  .LBB5_3: ; %end424; VI-NEXT:    v_mov_b32_e32 v0, s16425; VI-NEXT:    s_setpc_b64 s[30:31]426; VI-NEXT:  .LBB5_4:427; VI-NEXT:    s_branch .LBB5_2428;429; GFX9-LABEL: bitcast_i32_to_v2i16_scalar:430; GFX9:       ; %bb.0:431; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)432; GFX9-NEXT:    s_cmp_lg_u32 s17, 0433; GFX9-NEXT:    s_cbranch_scc0 .LBB5_4434; GFX9-NEXT:  ; %bb.1: ; %cmp.false435; GFX9-NEXT:    s_cbranch_execnz .LBB5_3436; GFX9-NEXT:  .LBB5_2: ; %cmp.true437; GFX9-NEXT:    s_add_i32 s16, s16, 3438; GFX9-NEXT:  .LBB5_3: ; %end439; GFX9-NEXT:    v_mov_b32_e32 v0, s16440; GFX9-NEXT:    s_setpc_b64 s[30:31]441; GFX9-NEXT:  .LBB5_4:442; GFX9-NEXT:    s_branch .LBB5_2443;444; GFX11-LABEL: bitcast_i32_to_v2i16_scalar:445; GFX11:       ; %bb.0:446; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)447; GFX11-NEXT:    s_cmp_lg_u32 s1, 0448; GFX11-NEXT:    s_mov_b32 s1, 0449; GFX11-NEXT:    s_cbranch_scc0 .LBB5_3450; GFX11-NEXT:  ; %bb.1: ; %Flow451; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s1452; GFX11-NEXT:    s_cbranch_vccz .LBB5_4453; GFX11-NEXT:  ; %bb.2: ; %end454; GFX11-NEXT:    v_mov_b32_e32 v0, s0455; GFX11-NEXT:    s_setpc_b64 s[30:31]456; GFX11-NEXT:  .LBB5_3:457; GFX11-NEXT:  .LBB5_4: ; %cmp.true458; GFX11-NEXT:    s_add_i32 s0, s0, 3459; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)460; GFX11-NEXT:    v_mov_b32_e32 v0, s0461; GFX11-NEXT:    s_setpc_b64 s[30:31]462  %cmp = icmp eq i32 %b, 0463  br i1 %cmp, label %cmp.true, label %cmp.false464 465cmp.true:466  %a1 = add i32 %a, 3467  %a2 = bitcast i32 %a1 to <2 x i16>468  br label %end469 470cmp.false:471  %a3 = bitcast i32 %a to <2 x i16>472  br label %end473 474end:475  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]476  ret <2 x i16> %phi477}478 479define i32 @bitcast_v2i16_to_i32(<2 x i16> %a, i32 %b) {480; SI-LABEL: bitcast_v2i16_to_i32:481; SI:       ; %bb.0:482; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)483; SI-NEXT:    v_mov_b32_e32 v3, v0484; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2485; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v1486; SI-NEXT:    ; implicit-def: $vgpr0487; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc488; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]489; SI-NEXT:    s_cbranch_execnz .LBB6_3490; SI-NEXT:  ; %bb.1: ; %Flow491; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]492; SI-NEXT:    s_cbranch_execnz .LBB6_4493; SI-NEXT:  .LBB6_2: ; %end494; SI-NEXT:    s_or_b64 exec, exec, s[4:5]495; SI-NEXT:    s_setpc_b64 s[30:31]496; SI-NEXT:  .LBB6_3: ; %cmp.false497; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v3498; SI-NEXT:    v_or_b32_e32 v0, v0, v1499; SI-NEXT:    ; implicit-def: $vgpr3500; SI-NEXT:    ; implicit-def: $vgpr1501; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]502; SI-NEXT:    s_cbranch_execz .LBB6_2503; SI-NEXT:  .LBB6_4: ; %cmp.true504; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v3505; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v0506; SI-NEXT:    v_or_b32_e32 v0, v1, v0507; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v0508; SI-NEXT:    s_or_b64 exec, exec, s[4:5]509; SI-NEXT:    s_setpc_b64 s[30:31]510;511; VI-LABEL: bitcast_v2i16_to_i32:512; VI:       ; %bb.0:513; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)514; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1515; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc516; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]517; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]518; VI-NEXT:  ; %bb.1: ; %cmp.true519; VI-NEXT:    v_mov_b32_e32 v2, 3520; VI-NEXT:    v_add_u16_e32 v1, 3, v0521; VI-NEXT:    v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD522; VI-NEXT:    v_or_b32_e32 v0, v1, v0523; VI-NEXT:  ; %bb.2: ; %end524; VI-NEXT:    s_or_b64 exec, exec, s[4:5]525; VI-NEXT:    s_setpc_b64 s[30:31]526;527; GFX9-LABEL: bitcast_v2i16_to_i32:528; GFX9:       ; %bb.0:529; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)530; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1531; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc532; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]533; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]534; GFX9-NEXT:  ; %bb.1: ; %cmp.true535; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]536; GFX9-NEXT:  ; %bb.2: ; %end537; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]538; GFX9-NEXT:    s_setpc_b64 s[30:31]539;540; GFX11-LABEL: bitcast_v2i16_to_i32:541; GFX11:       ; %bb.0:542; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)543; GFX11-NEXT:    s_mov_b32 s0, exec_lo544; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1545; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0546; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)547; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0548; GFX11-NEXT:  ; %bb.1: ; %cmp.true549; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]550; GFX11-NEXT:  ; %bb.2: ; %end551; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0552; GFX11-NEXT:    s_setpc_b64 s[30:31]553  %cmp = icmp eq i32 %b, 0554  br i1 %cmp, label %cmp.true, label %cmp.false555 556cmp.true:557  %a1 = add <2 x i16> %a, splat (i16 3)558  %a2 = bitcast <2 x i16> %a1 to i32559  br label %end560 561cmp.false:562  %a3 = bitcast <2 x i16> %a to i32563  br label %end564 565end:566  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]567  ret i32 %phi568}569 570define inreg i32 @bitcast_v2i16_to_i32_scalar(<2 x i16> inreg %a, i32 inreg %b) {571; SI-LABEL: bitcast_v2i16_to_i32_scalar:572; SI:       ; %bb.0:573; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)574; SI-NEXT:    s_cmp_lg_u32 s18, 0575; SI-NEXT:    s_cbranch_scc0 .LBB7_4576; SI-NEXT:  ; %bb.1: ; %cmp.false577; SI-NEXT:    s_and_b32 s4, s16, 0xffff578; SI-NEXT:    s_lshl_b32 s5, s17, 16579; SI-NEXT:    s_or_b32 s6, s4, s5580; SI-NEXT:    s_cbranch_execnz .LBB7_3581; SI-NEXT:  .LBB7_2: ; %cmp.true582; SI-NEXT:    s_add_i32 s16, s16, 3583; SI-NEXT:    s_and_b32 s4, s16, 0xffff584; SI-NEXT:    s_lshl_b32 s5, s17, 16585; SI-NEXT:    s_or_b32 s4, s5, s4586; SI-NEXT:    s_add_i32 s6, s4, 0x30000587; SI-NEXT:  .LBB7_3: ; %end588; SI-NEXT:    v_mov_b32_e32 v0, s6589; SI-NEXT:    s_setpc_b64 s[30:31]590; SI-NEXT:  .LBB7_4:591; SI-NEXT:    ; implicit-def: $sgpr6592; SI-NEXT:    s_branch .LBB7_2593;594; VI-LABEL: bitcast_v2i16_to_i32_scalar:595; VI:       ; %bb.0:596; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)597; VI-NEXT:    s_cmp_lg_u32 s17, 0598; VI-NEXT:    s_cbranch_scc0 .LBB7_4599; VI-NEXT:  ; %bb.1: ; %cmp.false600; VI-NEXT:    s_cbranch_execnz .LBB7_3601; VI-NEXT:  .LBB7_2: ; %cmp.true602; VI-NEXT:    s_add_i32 s5, s16, 3603; VI-NEXT:    s_and_b32 s4, s16, 0xffff0000604; VI-NEXT:    s_and_b32 s5, s5, 0xffff605; VI-NEXT:    s_or_b32 s4, s4, s5606; VI-NEXT:    s_add_i32 s16, s4, 0x30000607; VI-NEXT:  .LBB7_3: ; %end608; VI-NEXT:    v_mov_b32_e32 v0, s16609; VI-NEXT:    s_setpc_b64 s[30:31]610; VI-NEXT:  .LBB7_4:611; VI-NEXT:    s_branch .LBB7_2612;613; GFX9-LABEL: bitcast_v2i16_to_i32_scalar:614; GFX9:       ; %bb.0:615; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)616; GFX9-NEXT:    s_cmp_lg_u32 s17, 0617; GFX9-NEXT:    s_cbranch_scc0 .LBB7_3618; GFX9-NEXT:  ; %bb.1: ; %cmp.false619; GFX9-NEXT:    s_cbranch_execnz .LBB7_4620; GFX9-NEXT:  .LBB7_2: ; %cmp.true621; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]622; GFX9-NEXT:    s_setpc_b64 s[30:31]623; GFX9-NEXT:  .LBB7_3:624; GFX9-NEXT:    s_branch .LBB7_2625; GFX9-NEXT:  .LBB7_4:626; GFX9-NEXT:    v_mov_b32_e32 v0, s16627; GFX9-NEXT:    s_setpc_b64 s[30:31]628;629; GFX11-LABEL: bitcast_v2i16_to_i32_scalar:630; GFX11:       ; %bb.0:631; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)632; GFX11-NEXT:    s_cmp_lg_u32 s1, 0633; GFX11-NEXT:    s_mov_b32 s1, 0634; GFX11-NEXT:    s_cbranch_scc0 .LBB7_3635; GFX11-NEXT:  ; %bb.1: ; %Flow636; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s1637; GFX11-NEXT:    s_cbranch_vccnz .LBB7_4638; GFX11-NEXT:  .LBB7_2: ; %cmp.true639; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]640; GFX11-NEXT:    s_setpc_b64 s[30:31]641; GFX11-NEXT:  .LBB7_3:642; GFX11-NEXT:    s_branch .LBB7_2643; GFX11-NEXT:  .LBB7_4:644; GFX11-NEXT:    v_mov_b32_e32 v0, s0645; GFX11-NEXT:    s_setpc_b64 s[30:31]646  %cmp = icmp eq i32 %b, 0647  br i1 %cmp, label %cmp.true, label %cmp.false648 649cmp.true:650  %a1 = add <2 x i16> %a, splat (i16 3)651  %a2 = bitcast <2 x i16> %a1 to i32652  br label %end653 654cmp.false:655  %a3 = bitcast <2 x i16> %a to i32656  br label %end657 658end:659  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]660  ret i32 %phi661}662 663define <2 x half> @bitcast_i32_to_v2f16(i32 %a, i32 %b) {664; SI-LABEL: bitcast_i32_to_v2f16:665; SI:       ; %bb.0:666; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)667; SI-NEXT:    v_mov_b32_e32 v2, v0668; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1669; SI-NEXT:    ; implicit-def: $vgpr0670; SI-NEXT:    ; implicit-def: $vgpr1671; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc672; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]673; SI-NEXT:    s_cbranch_execnz .LBB8_3674; SI-NEXT:  ; %bb.1: ; %Flow675; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]676; SI-NEXT:    s_cbranch_execnz .LBB8_4677; SI-NEXT:  .LBB8_2: ; %end678; SI-NEXT:    s_or_b64 exec, exec, s[4:5]679; SI-NEXT:    s_setpc_b64 s[30:31]680; SI-NEXT:  .LBB8_3: ; %cmp.false681; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v2682; SI-NEXT:    v_cvt_f32_f16_e32 v1, v0683; SI-NEXT:    v_cvt_f32_f16_e32 v0, v2684; SI-NEXT:    ; implicit-def: $vgpr2685; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]686; SI-NEXT:    s_cbranch_execz .LBB8_2687; SI-NEXT:  .LBB8_4: ; %cmp.true688; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v2689; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v0690; SI-NEXT:    v_cvt_f32_f16_e32 v0, v0691; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1692; SI-NEXT:    s_or_b64 exec, exec, s[4:5]693; SI-NEXT:    s_setpc_b64 s[30:31]694;695; VI-LABEL: bitcast_i32_to_v2f16:696; VI:       ; %bb.0:697; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)698; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1699; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc700; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]701; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]702; VI-NEXT:  ; %bb.1: ; %cmp.true703; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v0704; VI-NEXT:  ; %bb.2: ; %end705; VI-NEXT:    s_or_b64 exec, exec, s[4:5]706; VI-NEXT:    s_setpc_b64 s[30:31]707;708; GFX9-LABEL: bitcast_i32_to_v2f16:709; GFX9:       ; %bb.0:710; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)711; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1712; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc713; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]714; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]715; GFX9-NEXT:  ; %bb.1: ; %cmp.true716; GFX9-NEXT:    v_add_u32_e32 v0, 3, v0717; GFX9-NEXT:  ; %bb.2: ; %end718; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]719; GFX9-NEXT:    s_setpc_b64 s[30:31]720;721; GFX11-LABEL: bitcast_i32_to_v2f16:722; GFX11:       ; %bb.0:723; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)724; GFX11-NEXT:    s_mov_b32 s0, exec_lo725; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1726; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0727; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)728; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0729; GFX11-NEXT:  ; %bb.1: ; %cmp.true730; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v0731; GFX11-NEXT:  ; %bb.2: ; %end732; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0733; GFX11-NEXT:    s_setpc_b64 s[30:31]734  %cmp = icmp eq i32 %b, 0735  br i1 %cmp, label %cmp.true, label %cmp.false736 737cmp.true:738  %a1 = add i32 %a, 3739  %a2 = bitcast i32 %a1 to <2 x half>740  br label %end741 742cmp.false:743  %a3 = bitcast i32 %a to <2 x half>744  br label %end745 746end:747  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]748  ret <2 x half> %phi749}750 751define inreg <2 x half> @bitcast_i32_to_v2f16_scalar(i32 inreg %a, i32 inreg %b) {752; SI-LABEL: bitcast_i32_to_v2f16_scalar:753; SI:       ; %bb.0:754; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)755; SI-NEXT:    s_cmp_lg_u32 s17, 0756; SI-NEXT:    s_cbranch_scc0 .LBB9_4757; SI-NEXT:  ; %bb.1: ; %cmp.false758; SI-NEXT:    s_lshr_b32 s4, s16, 16759; SI-NEXT:    v_cvt_f32_f16_e32 v1, s4760; SI-NEXT:    v_cvt_f32_f16_e32 v0, s16761; SI-NEXT:    s_cbranch_execnz .LBB9_3762; SI-NEXT:  .LBB9_2: ; %cmp.true763; SI-NEXT:    s_add_i32 s16, s16, 3764; SI-NEXT:    s_lshr_b32 s4, s16, 16765; SI-NEXT:    v_cvt_f32_f16_e32 v0, s16766; SI-NEXT:    v_cvt_f32_f16_e32 v1, s4767; SI-NEXT:  .LBB9_3: ; %end768; SI-NEXT:    s_setpc_b64 s[30:31]769; SI-NEXT:  .LBB9_4:770; SI-NEXT:    ; implicit-def: $vgpr0771; SI-NEXT:    ; implicit-def: $vgpr1772; SI-NEXT:    s_branch .LBB9_2773;774; VI-LABEL: bitcast_i32_to_v2f16_scalar:775; VI:       ; %bb.0:776; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)777; VI-NEXT:    s_cmp_lg_u32 s17, 0778; VI-NEXT:    s_cbranch_scc0 .LBB9_4779; VI-NEXT:  ; %bb.1: ; %cmp.false780; VI-NEXT:    s_cbranch_execnz .LBB9_3781; VI-NEXT:  .LBB9_2: ; %cmp.true782; VI-NEXT:    s_add_i32 s16, s16, 3783; VI-NEXT:  .LBB9_3: ; %end784; VI-NEXT:    v_mov_b32_e32 v0, s16785; VI-NEXT:    s_setpc_b64 s[30:31]786; VI-NEXT:  .LBB9_4:787; VI-NEXT:    s_branch .LBB9_2788;789; GFX9-LABEL: bitcast_i32_to_v2f16_scalar:790; GFX9:       ; %bb.0:791; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)792; GFX9-NEXT:    s_cmp_lg_u32 s17, 0793; GFX9-NEXT:    s_cbranch_scc0 .LBB9_4794; GFX9-NEXT:  ; %bb.1: ; %cmp.false795; GFX9-NEXT:    s_cbranch_execnz .LBB9_3796; GFX9-NEXT:  .LBB9_2: ; %cmp.true797; GFX9-NEXT:    s_add_i32 s16, s16, 3798; GFX9-NEXT:  .LBB9_3: ; %end799; GFX9-NEXT:    v_mov_b32_e32 v0, s16800; GFX9-NEXT:    s_setpc_b64 s[30:31]801; GFX9-NEXT:  .LBB9_4:802; GFX9-NEXT:    s_branch .LBB9_2803;804; GFX11-LABEL: bitcast_i32_to_v2f16_scalar:805; GFX11:       ; %bb.0:806; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)807; GFX11-NEXT:    s_cmp_lg_u32 s1, 0808; GFX11-NEXT:    s_mov_b32 s1, 0809; GFX11-NEXT:    s_cbranch_scc0 .LBB9_3810; GFX11-NEXT:  ; %bb.1: ; %Flow811; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s1812; GFX11-NEXT:    s_cbranch_vccz .LBB9_4813; GFX11-NEXT:  ; %bb.2: ; %end814; GFX11-NEXT:    v_mov_b32_e32 v0, s0815; GFX11-NEXT:    s_setpc_b64 s[30:31]816; GFX11-NEXT:  .LBB9_3:817; GFX11-NEXT:  .LBB9_4: ; %cmp.true818; GFX11-NEXT:    s_add_i32 s0, s0, 3819; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)820; GFX11-NEXT:    v_mov_b32_e32 v0, s0821; GFX11-NEXT:    s_setpc_b64 s[30:31]822  %cmp = icmp eq i32 %b, 0823  br i1 %cmp, label %cmp.true, label %cmp.false824 825cmp.true:826  %a1 = add i32 %a, 3827  %a2 = bitcast i32 %a1 to <2 x half>828  br label %end829 830cmp.false:831  %a3 = bitcast i32 %a to <2 x half>832  br label %end833 834end:835  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]836  ret <2 x half> %phi837}838 839define i32 @bitcast_v2f16_to_i32(<2 x half> %a, i32 %b) {840; SI-LABEL: bitcast_v2f16_to_i32:841; SI:       ; %bb.0:842; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)843; SI-NEXT:    v_cvt_f16_f32_e32 v3, v1844; SI-NEXT:    v_cvt_f16_f32_e32 v1, v0845; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v2846; SI-NEXT:    ; implicit-def: $vgpr0847; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc848; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]849; SI-NEXT:    s_cbranch_execnz .LBB10_3850; SI-NEXT:  ; %bb.1: ; %Flow851; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]852; SI-NEXT:    s_cbranch_execnz .LBB10_4853; SI-NEXT:  .LBB10_2: ; %end854; SI-NEXT:    s_or_b64 exec, exec, s[4:5]855; SI-NEXT:    s_setpc_b64 s[30:31]856; SI-NEXT:  .LBB10_3: ; %cmp.false857; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v3858; SI-NEXT:    v_or_b32_e32 v0, v1, v0859; SI-NEXT:    ; implicit-def: $vgpr3860; SI-NEXT:    ; implicit-def: $vgpr1861; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]862; SI-NEXT:    s_cbranch_execz .LBB10_2863; SI-NEXT:  .LBB10_4: ; %cmp.true864; SI-NEXT:    v_cvt_f32_f16_e32 v0, v3865; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1866; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0867; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0868; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1869; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1870; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0871; SI-NEXT:    v_or_b32_e32 v0, v1, v0872; SI-NEXT:    s_or_b64 exec, exec, s[4:5]873; SI-NEXT:    s_setpc_b64 s[30:31]874;875; VI-LABEL: bitcast_v2f16_to_i32:876; VI:       ; %bb.0:877; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)878; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1879; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc880; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]881; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]882; VI-NEXT:  ; %bb.1: ; %cmp.true883; VI-NEXT:    v_mov_b32_e32 v1, 0x200884; VI-NEXT:    v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD885; VI-NEXT:    v_add_f16_e32 v0, 0x200, v0886; VI-NEXT:    v_or_b32_e32 v0, v0, v1887; VI-NEXT:  ; %bb.2: ; %end888; VI-NEXT:    s_or_b64 exec, exec, s[4:5]889; VI-NEXT:    s_setpc_b64 s[30:31]890;891; GFX9-LABEL: bitcast_v2f16_to_i32:892; GFX9:       ; %bb.0:893; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)894; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v1895; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc896; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]897; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]898; GFX9-NEXT:  ; %bb.1: ; %cmp.true899; GFX9-NEXT:    s_movk_i32 s6, 0x200900; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]901; GFX9-NEXT:  ; %bb.2: ; %end902; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]903; GFX9-NEXT:    s_setpc_b64 s[30:31]904;905; GFX11-LABEL: bitcast_v2f16_to_i32:906; GFX11:       ; %bb.0:907; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)908; GFX11-NEXT:    s_mov_b32 s0, exec_lo909; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v1910; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s0911; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)912; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s0913; GFX11-NEXT:  ; %bb.1: ; %cmp.true914; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]915; GFX11-NEXT:  ; %bb.2: ; %end916; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s0917; GFX11-NEXT:    s_setpc_b64 s[30:31]918  %cmp = icmp eq i32 %b, 0919  br i1 %cmp, label %cmp.true, label %cmp.false920 921cmp.true:922  %a1 = fadd <2 x half> %a, splat (half 0xH0200)923  %a2 = bitcast <2 x half> %a1 to i32924  br label %end925 926cmp.false:927  %a3 = bitcast <2 x half> %a to i32928  br label %end929 930end:931  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]932  ret i32 %phi933}934 935define inreg i32 @bitcast_v2f16_to_i32_scalar(<2 x half> inreg %a, i32 inreg %b) {936; SI-LABEL: bitcast_v2f16_to_i32_scalar:937; SI:       ; %bb.0:938; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)939; SI-NEXT:    v_cvt_f16_f32_e32 v2, s17940; SI-NEXT:    v_cvt_f16_f32_e32 v1, s16941; SI-NEXT:    s_cmp_lg_u32 s18, 0942; SI-NEXT:    s_cbranch_scc0 .LBB11_4943; SI-NEXT:  ; %bb.1: ; %cmp.false944; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v2945; SI-NEXT:    v_or_b32_e32 v0, v1, v0946; SI-NEXT:    s_cbranch_execnz .LBB11_3947; SI-NEXT:  .LBB11_2: ; %cmp.true948; SI-NEXT:    v_cvt_f32_f16_e32 v0, v2949; SI-NEXT:    v_cvt_f32_f16_e32 v1, v1950; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v0951; SI-NEXT:    v_cvt_f16_f32_e32 v0, v0952; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v1953; SI-NEXT:    v_cvt_f16_f32_e32 v1, v1954; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v0955; SI-NEXT:    v_or_b32_e32 v0, v1, v0956; SI-NEXT:  .LBB11_3: ; %end957; SI-NEXT:    s_setpc_b64 s[30:31]958; SI-NEXT:  .LBB11_4:959; SI-NEXT:    ; implicit-def: $vgpr0960; SI-NEXT:    s_branch .LBB11_2961;962; VI-LABEL: bitcast_v2f16_to_i32_scalar:963; VI:       ; %bb.0:964; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)965; VI-NEXT:    s_cmp_lg_u32 s17, 0966; VI-NEXT:    s_cbranch_scc0 .LBB11_3967; VI-NEXT:  ; %bb.1: ; %cmp.false968; VI-NEXT:    s_cbranch_execnz .LBB11_4969; VI-NEXT:  .LBB11_2: ; %cmp.true970; VI-NEXT:    s_lshr_b32 s4, s16, 16971; VI-NEXT:    v_mov_b32_e32 v0, 0x200972; VI-NEXT:    v_mov_b32_e32 v1, s4973; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD974; VI-NEXT:    v_add_f16_e32 v0, s16, v0975; VI-NEXT:    v_or_b32_e32 v0, v0, v1976; VI-NEXT:    s_setpc_b64 s[30:31]977; VI-NEXT:  .LBB11_3:978; VI-NEXT:    s_branch .LBB11_2979; VI-NEXT:  .LBB11_4:980; VI-NEXT:    v_mov_b32_e32 v0, s16981; VI-NEXT:    s_setpc_b64 s[30:31]982;983; GFX9-LABEL: bitcast_v2f16_to_i32_scalar:984; GFX9:       ; %bb.0:985; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)986; GFX9-NEXT:    s_cmp_lg_u32 s17, 0987; GFX9-NEXT:    s_cbranch_scc0 .LBB11_3988; GFX9-NEXT:  ; %bb.1: ; %cmp.false989; GFX9-NEXT:    s_cbranch_execnz .LBB11_4990; GFX9-NEXT:  .LBB11_2: ; %cmp.true991; GFX9-NEXT:    v_mov_b32_e32 v0, 0x200992; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]993; GFX9-NEXT:    s_setpc_b64 s[30:31]994; GFX9-NEXT:  .LBB11_3:995; GFX9-NEXT:    s_branch .LBB11_2996; GFX9-NEXT:  .LBB11_4:997; GFX9-NEXT:    v_mov_b32_e32 v0, s16998; GFX9-NEXT:    s_setpc_b64 s[30:31]999;1000; GFX11-LABEL: bitcast_v2f16_to_i32_scalar:1001; GFX11:       ; %bb.0:1002; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1003; GFX11-NEXT:    s_cmp_lg_u32 s1, 01004; GFX11-NEXT:    s_mov_b32 s1, 01005; GFX11-NEXT:    s_cbranch_scc0 .LBB11_31006; GFX11-NEXT:  ; %bb.1: ; %Flow1007; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11008; GFX11-NEXT:    s_cbranch_vccnz .LBB11_41009; GFX11-NEXT:  .LBB11_2: ; %cmp.true1010; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]1011; GFX11-NEXT:    s_setpc_b64 s[30:31]1012; GFX11-NEXT:  .LBB11_3:1013; GFX11-NEXT:    s_branch .LBB11_21014; GFX11-NEXT:  .LBB11_4:1015; GFX11-NEXT:    v_mov_b32_e32 v0, s01016; GFX11-NEXT:    s_setpc_b64 s[30:31]1017  %cmp = icmp eq i32 %b, 01018  br i1 %cmp, label %cmp.true, label %cmp.false1019 1020cmp.true:1021  %a1 = fadd <2 x half> %a, splat (half 0xH0200)1022  %a2 = bitcast <2 x half> %a1 to i321023  br label %end1024 1025cmp.false:1026  %a3 = bitcast <2 x half> %a to i321027  br label %end1028 1029end:1030  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1031  ret i32 %phi1032}1033 1034define <2 x bfloat> @bitcast_i32_to_v2bf16(i32 %a, i32 %b) {1035; SI-LABEL: bitcast_i32_to_v2bf16:1036; SI:       ; %bb.0:1037; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1038; SI-NEXT:    v_mov_b32_e32 v2, v01039; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11040; SI-NEXT:    ; implicit-def: $vgpr01041; SI-NEXT:    ; implicit-def: $vgpr11042; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1043; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1044; SI-NEXT:    s_cbranch_execnz .LBB12_31045; SI-NEXT:  ; %bb.1: ; %Flow1046; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1047; SI-NEXT:    s_cbranch_execnz .LBB12_41048; SI-NEXT:  .LBB12_2: ; %end1049; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1050; SI-NEXT:    s_setpc_b64 s[30:31]1051; SI-NEXT:  .LBB12_3: ; %cmp.false1052; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v21053; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v21054; SI-NEXT:    ; implicit-def: $vgpr21055; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1056; SI-NEXT:    s_cbranch_execz .LBB12_21057; SI-NEXT:  .LBB12_4: ; %cmp.true1058; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v21059; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v01060; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v01061; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1062; SI-NEXT:    s_setpc_b64 s[30:31]1063;1064; VI-LABEL: bitcast_i32_to_v2bf16:1065; VI:       ; %bb.0:1066; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1067; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11068; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1069; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1070; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1071; VI-NEXT:  ; %bb.1: ; %cmp.true1072; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01073; VI-NEXT:  ; %bb.2: ; %end1074; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1075; VI-NEXT:    s_setpc_b64 s[30:31]1076;1077; GFX9-LABEL: bitcast_i32_to_v2bf16:1078; GFX9:       ; %bb.0:1079; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1080; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11081; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1082; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1083; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1084; GFX9-NEXT:  ; %bb.1: ; %cmp.true1085; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01086; GFX9-NEXT:  ; %bb.2: ; %end1087; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1088; GFX9-NEXT:    s_setpc_b64 s[30:31]1089;1090; GFX11-LABEL: bitcast_i32_to_v2bf16:1091; GFX11:       ; %bb.0:1092; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1093; GFX11-NEXT:    s_mov_b32 s0, exec_lo1094; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v11095; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01096; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1097; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01098; GFX11-NEXT:  ; %bb.1: ; %cmp.true1099; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v01100; GFX11-NEXT:  ; %bb.2: ; %end1101; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01102; GFX11-NEXT:    s_setpc_b64 s[30:31]1103  %cmp = icmp eq i32 %b, 01104  br i1 %cmp, label %cmp.true, label %cmp.false1105 1106cmp.true:1107  %a1 = add i32 %a, 31108  %a2 = bitcast i32 %a1 to <2 x bfloat>1109  br label %end1110 1111cmp.false:1112  %a3 = bitcast i32 %a to <2 x bfloat>1113  br label %end1114 1115end:1116  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1117  ret <2 x bfloat> %phi1118}1119 1120define inreg <2 x bfloat> @bitcast_i32_to_v2bf16_scalar(i32 inreg %a, i32 inreg %b) {1121; SI-LABEL: bitcast_i32_to_v2bf16_scalar:1122; SI:       ; %bb.0:1123; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1124; SI-NEXT:    s_cmp_lg_u32 s17, 01125; SI-NEXT:    s_cbranch_scc0 .LBB13_41126; SI-NEXT:  ; %bb.1: ; %cmp.false1127; SI-NEXT:    s_and_b32 s6, s16, 0xffff00001128; SI-NEXT:    s_lshl_b32 s7, s16, 161129; SI-NEXT:    s_cbranch_execnz .LBB13_31130; SI-NEXT:  .LBB13_2: ; %cmp.true1131; SI-NEXT:    s_add_i32 s16, s16, 31132; SI-NEXT:    s_and_b32 s6, s16, 0xffff00001133; SI-NEXT:    s_lshl_b32 s7, s16, 161134; SI-NEXT:  .LBB13_3: ; %end1135; SI-NEXT:    v_mov_b32_e32 v0, s71136; SI-NEXT:    v_mov_b32_e32 v1, s61137; SI-NEXT:    s_setpc_b64 s[30:31]1138; SI-NEXT:  .LBB13_4:1139; SI-NEXT:    ; implicit-def: $sgpr71140; SI-NEXT:    ; implicit-def: $sgpr61141; SI-NEXT:    s_branch .LBB13_21142;1143; VI-LABEL: bitcast_i32_to_v2bf16_scalar:1144; VI:       ; %bb.0:1145; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1146; VI-NEXT:    s_cmp_lg_u32 s17, 01147; VI-NEXT:    s_cbranch_scc0 .LBB13_41148; VI-NEXT:  ; %bb.1: ; %cmp.false1149; VI-NEXT:    s_cbranch_execnz .LBB13_31150; VI-NEXT:  .LBB13_2: ; %cmp.true1151; VI-NEXT:    s_add_i32 s16, s16, 31152; VI-NEXT:  .LBB13_3: ; %end1153; VI-NEXT:    v_mov_b32_e32 v0, s161154; VI-NEXT:    s_setpc_b64 s[30:31]1155; VI-NEXT:  .LBB13_4:1156; VI-NEXT:    s_branch .LBB13_21157;1158; GFX9-LABEL: bitcast_i32_to_v2bf16_scalar:1159; GFX9:       ; %bb.0:1160; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1161; GFX9-NEXT:    s_cmp_lg_u32 s17, 01162; GFX9-NEXT:    s_cbranch_scc0 .LBB13_41163; GFX9-NEXT:  ; %bb.1: ; %cmp.false1164; GFX9-NEXT:    s_cbranch_execnz .LBB13_31165; GFX9-NEXT:  .LBB13_2: ; %cmp.true1166; GFX9-NEXT:    s_add_i32 s16, s16, 31167; GFX9-NEXT:  .LBB13_3: ; %end1168; GFX9-NEXT:    v_mov_b32_e32 v0, s161169; GFX9-NEXT:    s_setpc_b64 s[30:31]1170; GFX9-NEXT:  .LBB13_4:1171; GFX9-NEXT:    s_branch .LBB13_21172;1173; GFX11-LABEL: bitcast_i32_to_v2bf16_scalar:1174; GFX11:       ; %bb.0:1175; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1176; GFX11-NEXT:    s_cmp_lg_u32 s1, 01177; GFX11-NEXT:    s_mov_b32 s1, 01178; GFX11-NEXT:    s_cbranch_scc0 .LBB13_31179; GFX11-NEXT:  ; %bb.1: ; %Flow1180; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11181; GFX11-NEXT:    s_cbranch_vccz .LBB13_41182; GFX11-NEXT:  ; %bb.2: ; %end1183; GFX11-NEXT:    v_mov_b32_e32 v0, s01184; GFX11-NEXT:    s_setpc_b64 s[30:31]1185; GFX11-NEXT:  .LBB13_3:1186; GFX11-NEXT:  .LBB13_4: ; %cmp.true1187; GFX11-NEXT:    s_add_i32 s0, s0, 31188; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1189; GFX11-NEXT:    v_mov_b32_e32 v0, s01190; GFX11-NEXT:    s_setpc_b64 s[30:31]1191  %cmp = icmp eq i32 %b, 01192  br i1 %cmp, label %cmp.true, label %cmp.false1193 1194cmp.true:1195  %a1 = add i32 %a, 31196  %a2 = bitcast i32 %a1 to <2 x bfloat>1197  br label %end1198 1199cmp.false:1200  %a3 = bitcast i32 %a to <2 x bfloat>1201  br label %end1202 1203end:1204  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1205  ret <2 x bfloat> %phi1206}1207 1208define i32 @bitcast_v2bf16_to_i32(<2 x bfloat> %a, i32 %b) {1209; SI-LABEL: bitcast_v2bf16_to_i32:1210; SI:       ; %bb.0:1211; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1212; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v21213; SI-NEXT:    v_mul_f32_e32 v1, 1.0, v11214; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v01215; SI-NEXT:    ; implicit-def: $vgpr01216; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1217; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1218; SI-NEXT:    s_cbranch_execnz .LBB14_31219; SI-NEXT:  ; %bb.1: ; %Flow1220; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1221; SI-NEXT:    s_cbranch_execnz .LBB14_41222; SI-NEXT:  .LBB14_2: ; %end1223; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1224; SI-NEXT:    s_setpc_b64 s[30:31]1225; SI-NEXT:  .LBB14_3: ; %cmp.false1226; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v11227; SI-NEXT:    v_alignbit_b32 v0, v0, v2, 161228; SI-NEXT:    ; implicit-def: $vgpr21229; SI-NEXT:    ; implicit-def: $vgpr11230; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1231; SI-NEXT:    s_cbranch_execz .LBB14_21232; SI-NEXT:  .LBB14_4: ; %cmp.true1233; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v11234; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v21235; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v11236; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v01237; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11238; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 161239; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1240; SI-NEXT:    s_setpc_b64 s[30:31]1241;1242; VI-LABEL: bitcast_v2bf16_to_i32:1243; VI:       ; %bb.0:1244; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1245; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11246; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1247; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1248; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1249; VI-NEXT:    s_cbranch_execz .LBB14_21250; VI-NEXT:  ; %bb.1: ; %cmp.true1251; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v01252; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v11253; VI-NEXT:    v_bfe_u32 v2, v1, 16, 11254; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v11255; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v21256; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01257; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v11258; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v11259; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v01260; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc1261; VI-NEXT:    v_bfe_u32 v2, v0, 16, 11262; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v01263; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v21264; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v01265; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v01266; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc1267; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v01268; VI-NEXT:    v_alignbit_b32 v0, v0, v1, 161269; VI-NEXT:  .LBB14_2: ; %end1270; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1271; VI-NEXT:    s_setpc_b64 s[30:31]1272;1273; GFX9-LABEL: bitcast_v2bf16_to_i32:1274; GFX9:       ; %bb.0:1275; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1276; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11277; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1278; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1279; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1280; GFX9-NEXT:    s_cbranch_execz .LBB14_21281; GFX9-NEXT:  ; %bb.1: ; %cmp.true1282; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v01283; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v11284; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 11285; GFX9-NEXT:    s_movk_i32 s6, 0x7fff1286; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01287; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s61288; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v11289; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v11290; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v01291; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc1292; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 11293; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s61294; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v01295; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v01296; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc1297; GFX9-NEXT:    s_mov_b32 s6, 0x70603021298; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s61299; GFX9-NEXT:  .LBB14_2: ; %end1300; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1301; GFX9-NEXT:    s_setpc_b64 s[30:31]1302;1303; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_i32:1304; GFX11-TRUE16:       ; %bb.0:1305; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1306; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11307; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr11308; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo1309; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1310; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s01311; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false1312; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v01313; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr01314; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow1315; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s01316; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB14_41317; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true1318; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v01319; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01320; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1321; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v01322; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 11323; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1324; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 11325; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v11326; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v11327; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v01328; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff1329; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff1330; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1331; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo1332; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v01333; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo1334; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)1335; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h1336; GFX11-TRUE16-NEXT:  .LBB14_4: ; %end1337; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s01338; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1339; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v11340; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1341;1342; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_i32:1343; GFX11-FAKE16:       ; %bb.0:1344; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1345; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo1346; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v11347; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s01348; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1349; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s01350; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB14_21351; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true1352; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v01353; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v01354; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1355; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v01356; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 11357; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1358; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 11359; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v11360; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v11361; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v01362; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff1363; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff1364; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)1365; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo1366; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v01367; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo1368; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1369; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x70603021370; GFX11-FAKE16-NEXT:  .LBB14_2: ; %end1371; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s01372; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1373  %cmp = icmp eq i32 %b, 01374  br i1 %cmp, label %cmp.true, label %cmp.false1375 1376cmp.true:1377  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)1378  %a2 = bitcast <2 x bfloat> %a1 to i321379  br label %end1380 1381cmp.false:1382  %a3 = bitcast <2 x bfloat> %a to i321383  br label %end1384 1385end:1386  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1387  ret i32 %phi1388}1389 1390define inreg i32 @bitcast_v2bf16_to_i32_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {1391; SI-LABEL: bitcast_v2bf16_to_i32_scalar:1392; SI:       ; %bb.0:1393; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1394; SI-NEXT:    s_cmp_lg_u32 s18, 01395; SI-NEXT:    v_mul_f32_e64 v4, 1.0, s171396; SI-NEXT:    v_mul_f32_e64 v2, 1.0, s161397; SI-NEXT:    s_cbranch_scc0 .LBB15_41398; SI-NEXT:  ; %bb.1: ; %cmp.false1399; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v41400; SI-NEXT:    v_lshr_b64 v[0:1], v[2:3], 161401; SI-NEXT:    s_cbranch_execnz .LBB15_31402; SI-NEXT:  .LBB15_2: ; %cmp.true1403; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v41404; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v21405; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v11406; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v01407; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11408; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 161409; SI-NEXT:  .LBB15_3: ; %end1410; SI-NEXT:    s_setpc_b64 s[30:31]1411; SI-NEXT:  .LBB15_4:1412; SI-NEXT:    ; implicit-def: $vgpr01413; SI-NEXT:    s_branch .LBB15_21414;1415; VI-LABEL: bitcast_v2bf16_to_i32_scalar:1416; VI:       ; %bb.0:1417; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1418; VI-NEXT:    s_cmp_lg_u32 s17, 01419; VI-NEXT:    s_cbranch_scc0 .LBB15_31420; VI-NEXT:  ; %bb.1: ; %cmp.false1421; VI-NEXT:    s_cbranch_execnz .LBB15_41422; VI-NEXT:  .LBB15_2: ; %cmp.true1423; VI-NEXT:    s_lshl_b32 s4, s16, 161424; VI-NEXT:    v_mov_b32_e32 v1, 0x40c000001425; VI-NEXT:    v_add_f32_e32 v0, s4, v11426; VI-NEXT:    v_bfe_u32 v2, v0, 16, 11427; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v01428; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v21429; VI-NEXT:    s_and_b32 s4, s16, 0xffff00001430; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v01431; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v01432; VI-NEXT:    v_add_f32_e32 v1, s4, v11433; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc1434; VI-NEXT:    v_bfe_u32 v2, v1, 16, 11435; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v11436; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v21437; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v11438; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v11439; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc1440; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v11441; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]1442; VI-NEXT:    s_setpc_b64 s[30:31]1443; VI-NEXT:  .LBB15_3:1444; VI-NEXT:    s_branch .LBB15_21445; VI-NEXT:  .LBB15_4:1446; VI-NEXT:    v_mov_b32_e32 v0, s161447; VI-NEXT:    s_setpc_b64 s[30:31]1448;1449; GFX9-LABEL: bitcast_v2bf16_to_i32_scalar:1450; GFX9:       ; %bb.0:1451; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1452; GFX9-NEXT:    s_cmp_lg_u32 s17, 01453; GFX9-NEXT:    s_cbranch_scc0 .LBB15_31454; GFX9-NEXT:  ; %bb.1: ; %cmp.false1455; GFX9-NEXT:    s_cbranch_execnz .LBB15_41456; GFX9-NEXT:  .LBB15_2: ; %cmp.true1457; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00001458; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000001459; GFX9-NEXT:    v_add_f32_e32 v1, s4, v01460; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 11461; GFX9-NEXT:    v_add_u32_e32 v2, v2, v11462; GFX9-NEXT:    s_lshl_b32 s4, s16, 161463; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v21464; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v11465; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v11466; GFX9-NEXT:    v_add_f32_e32 v0, s4, v01467; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc1468; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 11469; GFX9-NEXT:    v_add_u32_e32 v2, v2, v01470; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v21471; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v01472; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v01473; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc1474; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff1475; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v11476; GFX9-NEXT:    v_and_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_11477; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v01478; GFX9-NEXT:    s_setpc_b64 s[30:31]1479; GFX9-NEXT:  .LBB15_3:1480; GFX9-NEXT:    s_branch .LBB15_21481; GFX9-NEXT:  .LBB15_4:1482; GFX9-NEXT:    v_mov_b32_e32 v0, s161483; GFX9-NEXT:    s_setpc_b64 s[30:31]1484;1485; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_i32_scalar:1486; GFX11-TRUE16:       ; %bb.0:1487; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1488; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 01489; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 01490; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB15_31491; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow1492; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11493; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB15_41494; GFX11-TRUE16-NEXT:  .LBB15_2: ; %cmp.true1495; GFX11-TRUE16-NEXT:    s_and_b32 s1, s0, 0xffff00001496; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 161497; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s11498; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s01499; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1500; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 11501; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 11502; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v01503; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v01504; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v11505; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)1506; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v11507; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v31508; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v01509; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1510; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v21511; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo1512; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v11513; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)1514; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v01515; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo1516; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v11517; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)1518; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l1519; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1520; GFX11-TRUE16-NEXT:  .LBB15_3:1521; GFX11-TRUE16-NEXT:    s_branch .LBB15_21522; GFX11-TRUE16-NEXT:  .LBB15_4:1523; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s01524; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]1525;1526; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_i32_scalar:1527; GFX11-FAKE16:       ; %bb.0:1528; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1529; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 01530; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 01531; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB15_31532; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow1533; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11534; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB15_41535; GFX11-FAKE16-NEXT:  .LBB15_2: ; %cmp.true1536; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 161537; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00001538; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s11539; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s01540; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)1541; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 11542; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 11543; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v01544; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v01545; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v11546; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)1547; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v11548; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v31549; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v01550; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1551; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v21552; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo1553; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v11554; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)1555; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v01556; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_and_b32 v0, 0xffff, v01557; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1558; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v11559; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v01560; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1561; GFX11-FAKE16-NEXT:  .LBB15_3:1562; GFX11-FAKE16-NEXT:    s_branch .LBB15_21563; GFX11-FAKE16-NEXT:  .LBB15_4:1564; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s01565; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]1566  %cmp = icmp eq i32 %b, 01567  br i1 %cmp, label %cmp.true, label %cmp.false1568 1569cmp.true:1570  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)1571  %a2 = bitcast <2 x bfloat> %a1 to i321572  br label %end1573 1574cmp.false:1575  %a3 = bitcast <2 x bfloat> %a to i321576  br label %end1577 1578end:1579  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1580  ret i32 %phi1581}1582 1583define <1 x i32> @bitcast_i32_to_v1i32(i32 %a, i32 %b) {1584; SI-LABEL: bitcast_i32_to_v1i32:1585; SI:       ; %bb.0:1586; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1587; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11588; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1589; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1590; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1591; SI-NEXT:  ; %bb.1: ; %cmp.true1592; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v01593; SI-NEXT:  ; %bb.2: ; %end1594; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1595; SI-NEXT:    s_setpc_b64 s[30:31]1596;1597; VI-LABEL: bitcast_i32_to_v1i32:1598; VI:       ; %bb.0:1599; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1600; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11601; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1602; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1603; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1604; VI-NEXT:  ; %bb.1: ; %cmp.true1605; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01606; VI-NEXT:  ; %bb.2: ; %end1607; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1608; VI-NEXT:    s_setpc_b64 s[30:31]1609;1610; GFX9-LABEL: bitcast_i32_to_v1i32:1611; GFX9:       ; %bb.0:1612; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1613; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11614; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1615; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1616; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1617; GFX9-NEXT:  ; %bb.1: ; %cmp.true1618; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01619; GFX9-NEXT:  ; %bb.2: ; %end1620; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1621; GFX9-NEXT:    s_setpc_b64 s[30:31]1622;1623; GFX11-LABEL: bitcast_i32_to_v1i32:1624; GFX11:       ; %bb.0:1625; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1626; GFX11-NEXT:    s_mov_b32 s0, exec_lo1627; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v11628; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01629; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1630; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01631; GFX11-NEXT:  ; %bb.1: ; %cmp.true1632; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v01633; GFX11-NEXT:  ; %bb.2: ; %end1634; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01635; GFX11-NEXT:    s_setpc_b64 s[30:31]1636  %cmp = icmp eq i32 %b, 01637  br i1 %cmp, label %cmp.true, label %cmp.false1638 1639cmp.true:1640  %a1 = add i32 %a, 31641  %a2 = bitcast i32 %a1 to <1 x i32>1642  br label %end1643 1644cmp.false:1645  %a3 = bitcast i32 %a to <1 x i32>1646  br label %end1647 1648end:1649  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1650  ret <1 x i32> %phi1651}1652 1653define inreg <1 x i32> @bitcast_i32_to_v1i32_scalar(i32 inreg %a, i32 inreg %b) {1654; SI-LABEL: bitcast_i32_to_v1i32_scalar:1655; SI:       ; %bb.0:1656; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1657; SI-NEXT:    s_cmp_lg_u32 s17, 01658; SI-NEXT:    s_cbranch_scc0 .LBB17_41659; SI-NEXT:  ; %bb.1: ; %cmp.false1660; SI-NEXT:    s_cbranch_execnz .LBB17_31661; SI-NEXT:  .LBB17_2: ; %cmp.true1662; SI-NEXT:    s_add_i32 s16, s16, 31663; SI-NEXT:  .LBB17_3: ; %end1664; SI-NEXT:    v_mov_b32_e32 v0, s161665; SI-NEXT:    s_setpc_b64 s[30:31]1666; SI-NEXT:  .LBB17_4:1667; SI-NEXT:    s_branch .LBB17_21668;1669; VI-LABEL: bitcast_i32_to_v1i32_scalar:1670; VI:       ; %bb.0:1671; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1672; VI-NEXT:    s_cmp_lg_u32 s17, 01673; VI-NEXT:    s_cbranch_scc0 .LBB17_41674; VI-NEXT:  ; %bb.1: ; %cmp.false1675; VI-NEXT:    s_cbranch_execnz .LBB17_31676; VI-NEXT:  .LBB17_2: ; %cmp.true1677; VI-NEXT:    s_add_i32 s16, s16, 31678; VI-NEXT:  .LBB17_3: ; %end1679; VI-NEXT:    v_mov_b32_e32 v0, s161680; VI-NEXT:    s_setpc_b64 s[30:31]1681; VI-NEXT:  .LBB17_4:1682; VI-NEXT:    s_branch .LBB17_21683;1684; GFX9-LABEL: bitcast_i32_to_v1i32_scalar:1685; GFX9:       ; %bb.0:1686; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1687; GFX9-NEXT:    s_cmp_lg_u32 s17, 01688; GFX9-NEXT:    s_cbranch_scc0 .LBB17_41689; GFX9-NEXT:  ; %bb.1: ; %cmp.false1690; GFX9-NEXT:    s_cbranch_execnz .LBB17_31691; GFX9-NEXT:  .LBB17_2: ; %cmp.true1692; GFX9-NEXT:    s_add_i32 s16, s16, 31693; GFX9-NEXT:  .LBB17_3: ; %end1694; GFX9-NEXT:    v_mov_b32_e32 v0, s161695; GFX9-NEXT:    s_setpc_b64 s[30:31]1696; GFX9-NEXT:  .LBB17_4:1697; GFX9-NEXT:    s_branch .LBB17_21698;1699; GFX11-LABEL: bitcast_i32_to_v1i32_scalar:1700; GFX11:       ; %bb.0:1701; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1702; GFX11-NEXT:    s_cmp_lg_u32 s1, 01703; GFX11-NEXT:    s_mov_b32 s1, 01704; GFX11-NEXT:    s_cbranch_scc0 .LBB17_31705; GFX11-NEXT:  ; %bb.1: ; %Flow1706; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11707; GFX11-NEXT:    s_cbranch_vccz .LBB17_41708; GFX11-NEXT:  ; %bb.2: ; %end1709; GFX11-NEXT:    v_mov_b32_e32 v0, s01710; GFX11-NEXT:    s_setpc_b64 s[30:31]1711; GFX11-NEXT:  .LBB17_3:1712; GFX11-NEXT:  .LBB17_4: ; %cmp.true1713; GFX11-NEXT:    s_add_i32 s0, s0, 31714; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1715; GFX11-NEXT:    v_mov_b32_e32 v0, s01716; GFX11-NEXT:    s_setpc_b64 s[30:31]1717  %cmp = icmp eq i32 %b, 01718  br i1 %cmp, label %cmp.true, label %cmp.false1719 1720cmp.true:1721  %a1 = add i32 %a, 31722  %a2 = bitcast i32 %a1 to <1 x i32>1723  br label %end1724 1725cmp.false:1726  %a3 = bitcast i32 %a to <1 x i32>1727  br label %end1728 1729end:1730  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]1731  ret <1 x i32> %phi1732}1733 1734define i32 @bitcast_v1i32_to_i32(<1 x i32> %a, i32 %b) {1735; SI-LABEL: bitcast_v1i32_to_i32:1736; SI:       ; %bb.0:1737; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1738; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11739; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1740; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1741; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1742; SI-NEXT:  ; %bb.1: ; %cmp.true1743; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v01744; SI-NEXT:  ; %bb.2: ; %end1745; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1746; SI-NEXT:    s_setpc_b64 s[30:31]1747;1748; VI-LABEL: bitcast_v1i32_to_i32:1749; VI:       ; %bb.0:1750; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1751; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11752; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1753; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1754; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1755; VI-NEXT:  ; %bb.1: ; %cmp.true1756; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01757; VI-NEXT:  ; %bb.2: ; %end1758; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1759; VI-NEXT:    s_setpc_b64 s[30:31]1760;1761; GFX9-LABEL: bitcast_v1i32_to_i32:1762; GFX9:       ; %bb.0:1763; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1764; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11765; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1766; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1767; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1768; GFX9-NEXT:  ; %bb.1: ; %cmp.true1769; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01770; GFX9-NEXT:  ; %bb.2: ; %end1771; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1772; GFX9-NEXT:    s_setpc_b64 s[30:31]1773;1774; GFX11-LABEL: bitcast_v1i32_to_i32:1775; GFX11:       ; %bb.0:1776; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1777; GFX11-NEXT:    s_mov_b32 s0, exec_lo1778; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v11779; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s01780; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1781; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s01782; GFX11-NEXT:  ; %bb.1: ; %cmp.true1783; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v01784; GFX11-NEXT:  ; %bb.2: ; %end1785; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s01786; GFX11-NEXT:    s_setpc_b64 s[30:31]1787  %cmp = icmp eq i32 %b, 01788  br i1 %cmp, label %cmp.true, label %cmp.false1789 1790cmp.true:1791  %a1 = add <1 x i32> %a, splat (i32 3)1792  %a2 = bitcast <1 x i32> %a1 to i321793  br label %end1794 1795cmp.false:1796  %a3 = bitcast <1 x i32> %a to i321797  br label %end1798 1799end:1800  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1801  ret i32 %phi1802}1803 1804define inreg i32 @bitcast_v1i32_to_i32_scalar(<1 x i32> inreg %a, i32 inreg %b) {1805; SI-LABEL: bitcast_v1i32_to_i32_scalar:1806; SI:       ; %bb.0:1807; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1808; SI-NEXT:    s_cmp_lg_u32 s17, 01809; SI-NEXT:    s_cbranch_scc0 .LBB19_41810; SI-NEXT:  ; %bb.1: ; %cmp.false1811; SI-NEXT:    s_cbranch_execnz .LBB19_31812; SI-NEXT:  .LBB19_2: ; %cmp.true1813; SI-NEXT:    s_add_i32 s16, s16, 31814; SI-NEXT:  .LBB19_3: ; %end1815; SI-NEXT:    v_mov_b32_e32 v0, s161816; SI-NEXT:    s_setpc_b64 s[30:31]1817; SI-NEXT:  .LBB19_4:1818; SI-NEXT:    s_branch .LBB19_21819;1820; VI-LABEL: bitcast_v1i32_to_i32_scalar:1821; VI:       ; %bb.0:1822; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1823; VI-NEXT:    s_cmp_lg_u32 s17, 01824; VI-NEXT:    s_cbranch_scc0 .LBB19_41825; VI-NEXT:  ; %bb.1: ; %cmp.false1826; VI-NEXT:    s_cbranch_execnz .LBB19_31827; VI-NEXT:  .LBB19_2: ; %cmp.true1828; VI-NEXT:    s_add_i32 s16, s16, 31829; VI-NEXT:  .LBB19_3: ; %end1830; VI-NEXT:    v_mov_b32_e32 v0, s161831; VI-NEXT:    s_setpc_b64 s[30:31]1832; VI-NEXT:  .LBB19_4:1833; VI-NEXT:    s_branch .LBB19_21834;1835; GFX9-LABEL: bitcast_v1i32_to_i32_scalar:1836; GFX9:       ; %bb.0:1837; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1838; GFX9-NEXT:    s_cmp_lg_u32 s17, 01839; GFX9-NEXT:    s_cbranch_scc0 .LBB19_41840; GFX9-NEXT:  ; %bb.1: ; %cmp.false1841; GFX9-NEXT:    s_cbranch_execnz .LBB19_31842; GFX9-NEXT:  .LBB19_2: ; %cmp.true1843; GFX9-NEXT:    s_add_i32 s16, s16, 31844; GFX9-NEXT:  .LBB19_3: ; %end1845; GFX9-NEXT:    v_mov_b32_e32 v0, s161846; GFX9-NEXT:    s_setpc_b64 s[30:31]1847; GFX9-NEXT:  .LBB19_4:1848; GFX9-NEXT:    s_branch .LBB19_21849;1850; GFX11-LABEL: bitcast_v1i32_to_i32_scalar:1851; GFX11:       ; %bb.0:1852; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1853; GFX11-NEXT:    s_cmp_lg_u32 s1, 01854; GFX11-NEXT:    s_mov_b32 s1, 01855; GFX11-NEXT:    s_cbranch_scc0 .LBB19_31856; GFX11-NEXT:  ; %bb.1: ; %Flow1857; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s11858; GFX11-NEXT:    s_cbranch_vccz .LBB19_41859; GFX11-NEXT:  ; %bb.2: ; %end1860; GFX11-NEXT:    v_mov_b32_e32 v0, s01861; GFX11-NEXT:    s_setpc_b64 s[30:31]1862; GFX11-NEXT:  .LBB19_3:1863; GFX11-NEXT:  .LBB19_4: ; %cmp.true1864; GFX11-NEXT:    s_add_i32 s0, s0, 31865; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1866; GFX11-NEXT:    v_mov_b32_e32 v0, s01867; GFX11-NEXT:    s_setpc_b64 s[30:31]1868  %cmp = icmp eq i32 %b, 01869  br i1 %cmp, label %cmp.true, label %cmp.false1870 1871cmp.true:1872  %a1 = add <1 x i32> %a, splat (i32 3)1873  %a2 = bitcast <1 x i32> %a1 to i321874  br label %end1875 1876cmp.false:1877  %a3 = bitcast <1 x i32> %a to i321878  br label %end1879 1880end:1881  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]1882  ret i32 %phi1883}1884 1885define <4 x i8> @bitcast_i32_to_v4i8(i32 %a, i32 %b) {1886; SI-LABEL: bitcast_i32_to_v4i8:1887; SI:       ; %bb.0:1888; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1889; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11890; SI-NEXT:    ; implicit-def: $vgpr11891; SI-NEXT:    ; implicit-def: $vgpr21892; SI-NEXT:    ; implicit-def: $vgpr31893; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1894; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1895; SI-NEXT:    s_cbranch_execnz .LBB20_31896; SI-NEXT:  ; %bb.1: ; %Flow1897; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1898; SI-NEXT:    s_cbranch_execnz .LBB20_41899; SI-NEXT:  .LBB20_2: ; %end1900; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1901; SI-NEXT:    s_setpc_b64 s[30:31]1902; SI-NEXT:  .LBB20_3: ; %cmp.false1903; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v01904; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v01905; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v01906; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1907; SI-NEXT:    s_cbranch_execz .LBB20_21908; SI-NEXT:  .LBB20_4: ; %cmp.true1909; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v01910; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v01911; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v01912; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v01913; SI-NEXT:    s_or_b64 exec, exec, s[4:5]1914; SI-NEXT:    s_setpc_b64 s[30:31]1915;1916; VI-LABEL: bitcast_i32_to_v4i8:1917; VI:       ; %bb.0:1918; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1919; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11920; VI-NEXT:    ; implicit-def: $vgpr11921; VI-NEXT:    ; implicit-def: $vgpr21922; VI-NEXT:    ; implicit-def: $vgpr31923; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc1924; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1925; VI-NEXT:    s_cbranch_execnz .LBB20_31926; VI-NEXT:  ; %bb.1: ; %Flow1927; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1928; VI-NEXT:    s_cbranch_execnz .LBB20_41929; VI-NEXT:  .LBB20_2: ; %end1930; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1931; VI-NEXT:    s_setpc_b64 s[30:31]1932; VI-NEXT:  .LBB20_3: ; %cmp.false1933; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v01934; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v01935; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v01936; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1937; VI-NEXT:    s_cbranch_execz .LBB20_21938; VI-NEXT:  .LBB20_4: ; %cmp.true1939; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v01940; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v01941; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v01942; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v01943; VI-NEXT:    s_or_b64 exec, exec, s[4:5]1944; VI-NEXT:    s_setpc_b64 s[30:31]1945;1946; GFX9-LABEL: bitcast_i32_to_v4i8:1947; GFX9:       ; %bb.0:1948; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1949; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v11950; GFX9-NEXT:    ; implicit-def: $vgpr11951; GFX9-NEXT:    ; implicit-def: $vgpr21952; GFX9-NEXT:    ; implicit-def: $vgpr31953; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc1954; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]1955; GFX9-NEXT:    s_cbranch_execnz .LBB20_31956; GFX9-NEXT:  ; %bb.1: ; %Flow1957; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1958; GFX9-NEXT:    s_cbranch_execnz .LBB20_41959; GFX9-NEXT:  .LBB20_2: ; %end1960; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1961; GFX9-NEXT:    s_setpc_b64 s[30:31]1962; GFX9-NEXT:  .LBB20_3: ; %cmp.false1963; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v01964; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v01965; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v01966; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]1967; GFX9-NEXT:    s_cbranch_execz .LBB20_21968; GFX9-NEXT:  .LBB20_4: ; %cmp.true1969; GFX9-NEXT:    v_add_u32_e32 v0, 3, v01970; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v01971; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v01972; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v01973; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]1974; GFX9-NEXT:    s_setpc_b64 s[30:31]1975;1976; GFX11-TRUE16-LABEL: bitcast_i32_to_v4i8:1977; GFX11-TRUE16:       ; %bb.0:1978; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)1979; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v01980; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v11981; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo161982; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo161983; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo1984; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)1985; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s01986; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false1987; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)1988; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v21989; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v21990; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow1991; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s01992; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true1993; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v21994; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)1995; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v21996; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v21997; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end1998; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s01999; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l2000; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h2001; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2002;2003; GFX11-FAKE16-LABEL: bitcast_i32_to_v4i8:2004; GFX11-FAKE16:       ; %bb.0:2005; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2006; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v12007; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12008; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22009; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32010; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo2011; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2012; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s02013; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_32014; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow2015; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02016; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB20_42017; GFX11-FAKE16-NEXT:  .LBB20_2: ; %end2018; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02019; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2020; GFX11-FAKE16-NEXT:  .LBB20_3: ; %cmp.false2021; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v02022; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v02023; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v02024; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02025; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB20_22026; GFX11-FAKE16-NEXT:  .LBB20_4: ; %cmp.true2027; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 3, v02028; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2029; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v02030; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v02031; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v02032; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02033; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2034  %cmp = icmp eq i32 %b, 02035  br i1 %cmp, label %cmp.true, label %cmp.false2036 2037cmp.true:2038  %a1 = add i32 %a, 32039  %a2 = bitcast i32 %a1 to <4 x i8>2040  br label %end2041 2042cmp.false:2043  %a3 = bitcast i32 %a to <4 x i8>2044  br label %end2045 2046end:2047  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2048  ret <4 x i8> %phi2049}2050 2051define inreg <4 x i8> @bitcast_i32_to_v4i8_scalar(i32 inreg %a, i32 inreg %b) {2052; SI-LABEL: bitcast_i32_to_v4i8_scalar:2053; SI:       ; %bb.0:2054; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2055; SI-NEXT:    s_cmp_lg_u32 s17, 02056; SI-NEXT:    s_cbranch_scc0 .LBB21_42057; SI-NEXT:  ; %bb.1: ; %cmp.false2058; SI-NEXT:    s_lshr_b32 s6, s16, 242059; SI-NEXT:    s_lshr_b32 s7, s16, 162060; SI-NEXT:    s_lshr_b32 s8, s16, 82061; SI-NEXT:    s_cbranch_execnz .LBB21_32062; SI-NEXT:  .LBB21_2: ; %cmp.true2063; SI-NEXT:    s_add_i32 s16, s16, 32064; SI-NEXT:    s_lshr_b32 s7, s16, 162065; SI-NEXT:    s_lshr_b32 s6, s16, 242066; SI-NEXT:    s_lshr_b32 s8, s16, 82067; SI-NEXT:  .LBB21_3: ; %end2068; SI-NEXT:    v_mov_b32_e32 v0, s162069; SI-NEXT:    v_mov_b32_e32 v1, s82070; SI-NEXT:    v_mov_b32_e32 v2, s72071; SI-NEXT:    v_mov_b32_e32 v3, s62072; SI-NEXT:    s_setpc_b64 s[30:31]2073; SI-NEXT:  .LBB21_4:2074; SI-NEXT:    ; implicit-def: $sgpr82075; SI-NEXT:    ; implicit-def: $sgpr72076; SI-NEXT:    ; implicit-def: $sgpr62077; SI-NEXT:    s_branch .LBB21_22078;2079; VI-LABEL: bitcast_i32_to_v4i8_scalar:2080; VI:       ; %bb.0:2081; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2082; VI-NEXT:    s_cmp_lg_u32 s17, 02083; VI-NEXT:    s_cbranch_scc0 .LBB21_42084; VI-NEXT:  ; %bb.1: ; %cmp.false2085; VI-NEXT:    s_lshr_b32 s6, s16, 242086; VI-NEXT:    s_lshr_b32 s7, s16, 162087; VI-NEXT:    s_lshr_b32 s8, s16, 82088; VI-NEXT:    s_cbranch_execnz .LBB21_32089; VI-NEXT:  .LBB21_2: ; %cmp.true2090; VI-NEXT:    s_add_i32 s16, s16, 32091; VI-NEXT:    s_lshr_b32 s7, s16, 162092; VI-NEXT:    s_lshr_b32 s6, s16, 242093; VI-NEXT:    s_lshr_b32 s8, s16, 82094; VI-NEXT:  .LBB21_3: ; %end2095; VI-NEXT:    v_mov_b32_e32 v0, s162096; VI-NEXT:    v_mov_b32_e32 v1, s82097; VI-NEXT:    v_mov_b32_e32 v2, s72098; VI-NEXT:    v_mov_b32_e32 v3, s62099; VI-NEXT:    s_setpc_b64 s[30:31]2100; VI-NEXT:  .LBB21_4:2101; VI-NEXT:    ; implicit-def: $sgpr82102; VI-NEXT:    ; implicit-def: $sgpr72103; VI-NEXT:    ; implicit-def: $sgpr62104; VI-NEXT:    s_branch .LBB21_22105;2106; GFX9-LABEL: bitcast_i32_to_v4i8_scalar:2107; GFX9:       ; %bb.0:2108; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2109; GFX9-NEXT:    s_cmp_lg_u32 s17, 02110; GFX9-NEXT:    s_cbranch_scc0 .LBB21_42111; GFX9-NEXT:  ; %bb.1: ; %cmp.false2112; GFX9-NEXT:    s_lshr_b32 s6, s16, 242113; GFX9-NEXT:    s_lshr_b32 s7, s16, 162114; GFX9-NEXT:    s_lshr_b32 s8, s16, 82115; GFX9-NEXT:    s_cbranch_execnz .LBB21_32116; GFX9-NEXT:  .LBB21_2: ; %cmp.true2117; GFX9-NEXT:    s_add_i32 s16, s16, 32118; GFX9-NEXT:    s_lshr_b32 s7, s16, 162119; GFX9-NEXT:    s_lshr_b32 s6, s16, 242120; GFX9-NEXT:    s_lshr_b32 s8, s16, 82121; GFX9-NEXT:  .LBB21_3: ; %end2122; GFX9-NEXT:    v_mov_b32_e32 v0, s162123; GFX9-NEXT:    v_mov_b32_e32 v1, s82124; GFX9-NEXT:    v_mov_b32_e32 v2, s72125; GFX9-NEXT:    v_mov_b32_e32 v3, s62126; GFX9-NEXT:    s_setpc_b64 s[30:31]2127; GFX9-NEXT:  .LBB21_4:2128; GFX9-NEXT:    ; implicit-def: $sgpr82129; GFX9-NEXT:    ; implicit-def: $sgpr72130; GFX9-NEXT:    ; implicit-def: $sgpr62131; GFX9-NEXT:    s_branch .LBB21_22132;2133; GFX11-LABEL: bitcast_i32_to_v4i8_scalar:2134; GFX11:       ; %bb.0:2135; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2136; GFX11-NEXT:    s_cmp_lg_u32 s1, 02137; GFX11-NEXT:    s_mov_b32 s4, 02138; GFX11-NEXT:    s_cbranch_scc0 .LBB21_42139; GFX11-NEXT:  ; %bb.1: ; %cmp.false2140; GFX11-NEXT:    s_lshr_b32 s1, s0, 242141; GFX11-NEXT:    s_lshr_b32 s2, s0, 162142; GFX11-NEXT:    s_lshr_b32 s3, s0, 82143; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s42144; GFX11-NEXT:    s_cbranch_vccnz .LBB21_32145; GFX11-NEXT:  .LBB21_2: ; %cmp.true2146; GFX11-NEXT:    s_add_i32 s0, s0, 32147; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2148; GFX11-NEXT:    s_lshr_b32 s2, s0, 162149; GFX11-NEXT:    s_lshr_b32 s1, s0, 242150; GFX11-NEXT:    s_lshr_b32 s3, s0, 82151; GFX11-NEXT:  .LBB21_3: ; %end2152; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2153; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s32154; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s12155; GFX11-NEXT:    s_setpc_b64 s[30:31]2156; GFX11-NEXT:  .LBB21_4:2157; GFX11-NEXT:    ; implicit-def: $sgpr32158; GFX11-NEXT:    ; implicit-def: $sgpr22159; GFX11-NEXT:    ; implicit-def: $sgpr12160; GFX11-NEXT:    s_branch .LBB21_22161  %cmp = icmp eq i32 %b, 02162  br i1 %cmp, label %cmp.true, label %cmp.false2163 2164cmp.true:2165  %a1 = add i32 %a, 32166  %a2 = bitcast i32 %a1 to <4 x i8>2167  br label %end2168 2169cmp.false:2170  %a3 = bitcast i32 %a to <4 x i8>2171  br label %end2172 2173end:2174  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2175  ret <4 x i8> %phi2176}2177 2178define i32 @bitcast_v4i8_to_i32(<4 x i8> %a, i32 %b) {2179; SI-LABEL: bitcast_v4i8_to_i32:2180; SI:       ; %bb.0:2181; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2182; SI-NEXT:    v_mov_b32_e32 v5, v02183; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v42184; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v12185; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v32186; SI-NEXT:    ; implicit-def: $vgpr02187; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2188; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2189; SI-NEXT:    s_cbranch_execnz .LBB22_32190; SI-NEXT:  ; %bb.1: ; %Flow2191; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2192; SI-NEXT:    s_cbranch_execnz .LBB22_42193; SI-NEXT:  .LBB22_2: ; %end2194; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2195; SI-NEXT:    s_setpc_b64 s[30:31]2196; SI-NEXT:  .LBB22_3: ; %cmp.false2197; SI-NEXT:    v_and_b32_e32 v0, 0xff, v52198; SI-NEXT:    v_and_b32_e32 v2, 0xff, v22199; SI-NEXT:    v_or_b32_e32 v0, v0, v42200; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22201; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02202; SI-NEXT:    v_or_b32_e32 v1, v1, v22203; SI-NEXT:    v_or_b32_e32 v0, v0, v12204; SI-NEXT:    ; implicit-def: $vgpr52205; SI-NEXT:    ; implicit-def: $vgpr42206; SI-NEXT:    ; implicit-def: $vgpr22207; SI-NEXT:    ; implicit-def: $vgpr12208; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2209; SI-NEXT:    s_cbranch_execz .LBB22_22210; SI-NEXT:  .LBB22_4: ; %cmp.true2211; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v52212; SI-NEXT:    v_and_b32_e32 v0, 0xff, v02213; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v22214; SI-NEXT:    v_or_b32_e32 v0, v4, v02215; SI-NEXT:    v_and_b32_e32 v2, 0xff, v22216; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v02217; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v22218; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02219; SI-NEXT:    v_or_b32_e32 v1, v1, v22220; SI-NEXT:    v_or_b32_e32 v0, v1, v02221; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v02222; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2223; SI-NEXT:    s_setpc_b64 s[30:31]2224;2225; VI-LABEL: bitcast_v4i8_to_i32:2226; VI:       ; %bb.0:2227; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2228; VI-NEXT:    v_mov_b32_e32 v5, v02229; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v42230; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v12231; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v32232; VI-NEXT:    ; implicit-def: $vgpr02233; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2234; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2235; VI-NEXT:    s_cbranch_execnz .LBB22_32236; VI-NEXT:  ; %bb.1: ; %Flow2237; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2238; VI-NEXT:    s_cbranch_execnz .LBB22_42239; VI-NEXT:  .LBB22_2: ; %end2240; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2241; VI-NEXT:    s_setpc_b64 s[30:31]2242; VI-NEXT:  .LBB22_3: ; %cmp.false2243; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2244; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2245; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2246; VI-NEXT:    ; implicit-def: $vgpr52247; VI-NEXT:    ; implicit-def: $vgpr42248; VI-NEXT:    ; implicit-def: $vgpr22249; VI-NEXT:    ; implicit-def: $vgpr12250; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2251; VI-NEXT:    s_cbranch_execz .LBB22_22252; VI-NEXT:  .LBB22_4: ; %cmp.true2253; VI-NEXT:    v_add_u16_e32 v0, 3, v52254; VI-NEXT:    v_add_u16_e32 v2, 3, v22255; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_02256; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_02257; VI-NEXT:    v_mov_b32_e32 v2, 0x3002258; VI-NEXT:    v_add_u16_e32 v0, 0x300, v02259; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2260; VI-NEXT:    v_or_b32_e32 v0, v0, v12261; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2262; VI-NEXT:    s_setpc_b64 s[30:31]2263;2264; GFX9-LABEL: bitcast_v4i8_to_i32:2265; GFX9:       ; %bb.0:2266; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2267; GFX9-NEXT:    v_mov_b32_e32 v5, v02268; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v42269; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v12270; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v32271; GFX9-NEXT:    ; implicit-def: $vgpr02272; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2273; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2274; GFX9-NEXT:    s_cbranch_execnz .LBB22_32275; GFX9-NEXT:  ; %bb.1: ; %Flow2276; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2277; GFX9-NEXT:    s_cbranch_execnz .LBB22_42278; GFX9-NEXT:  .LBB22_2: ; %end2279; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2280; GFX9-NEXT:    s_setpc_b64 s[30:31]2281; GFX9-NEXT:  .LBB22_3: ; %cmp.false2282; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2283; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD2284; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD2285; GFX9-NEXT:    ; implicit-def: $vgpr52286; GFX9-NEXT:    ; implicit-def: $vgpr42287; GFX9-NEXT:    ; implicit-def: $vgpr22288; GFX9-NEXT:    ; implicit-def: $vgpr12289; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2290; GFX9-NEXT:    s_cbranch_execz .LBB22_22291; GFX9-NEXT:  .LBB22_4: ; %cmp.true2292; GFX9-NEXT:    v_add_u16_e32 v0, 3, v52293; GFX9-NEXT:    v_add_u16_e32 v2, 3, v22294; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_02295; GFX9-NEXT:    s_movk_i32 s6, 0x3002296; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_02297; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v02298; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD2299; GFX9-NEXT:    v_or_b32_e32 v0, v0, v12300; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2301; GFX9-NEXT:    s_setpc_b64 s[30:31]2302;2303; GFX11-TRUE16-LABEL: bitcast_v4i8_to_i32:2304; GFX11-TRUE16:       ; %bb.0:2305; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2306; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l2307; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l2308; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l2309; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo2310; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr02311; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v42312; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s02313; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB22_32314; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow2315; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s02316; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB22_42317; GFX11-TRUE16-NEXT:  .LBB22_2: ; %end2318; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02319; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2320; GFX11-TRUE16-NEXT:  .LBB22_3: ; %cmp.false2321; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h2322; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l2323; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi162324; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo162325; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2326; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l2327; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h2328; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo162329; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi162330; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s02331; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB22_22332; GFX11-TRUE16-NEXT:  .LBB22_4: ; %cmp.true2333; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 32334; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 32335; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2336; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l2337; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h2338; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2339; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l2340; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h2341; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2342; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l2343; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h2344; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02345; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]2346;2347; GFX11-FAKE16-LABEL: bitcast_v4i8_to_i32:2348; GFX11-FAKE16:       ; %bb.0:2349; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2350; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v02351; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v12352; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v32353; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo2354; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr02355; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v42356; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s02357; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB22_32358; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow2359; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02360; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB22_42361; GFX11-FAKE16-NEXT:  .LBB22_2: ; %end2362; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02363; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2364; GFX11-FAKE16-NEXT:  .LBB22_3: ; %cmp.false2365; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v52366; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v22367; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr52368; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2369; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v12370; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v32371; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr22372; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr32373; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2374; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v02375; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v12376; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2377; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v12378; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr12379; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s02380; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB22_22381; GFX11-FAKE16-NEXT:  .LBB22_4: ; %cmp.true2382; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 32383; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 32384; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2385; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v02386; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v22387; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2388; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v02389; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v22390; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2391; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v02392; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v12393; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)2394; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v02395; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v12396; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)2397; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v12398; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s02399; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]2400  %cmp = icmp eq i32 %b, 02401  br i1 %cmp, label %cmp.true, label %cmp.false2402 2403cmp.true:2404  %a1 = add <4 x i8> %a, splat (i8 3)2405  %a2 = bitcast <4 x i8> %a1 to i322406  br label %end2407 2408cmp.false:2409  %a3 = bitcast <4 x i8> %a to i322410  br label %end2411 2412end:2413  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]2414  ret i32 %phi2415}2416 2417define inreg i32 @bitcast_v4i8_to_i32_scalar(<4 x i8> inreg %a, i32 inreg %b) {2418; SI-LABEL: bitcast_v4i8_to_i32_scalar:2419; SI:       ; %bb.0:2420; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2421; SI-NEXT:    s_cmp_lg_u32 s20, 02422; SI-NEXT:    s_cbranch_scc0 .LBB23_42423; SI-NEXT:  ; %bb.1: ; %cmp.false2424; SI-NEXT:    s_and_b32 s4, s16, 0xff2425; SI-NEXT:    s_lshl_b32 s5, s17, 82426; SI-NEXT:    s_or_b32 s4, s4, s52427; SI-NEXT:    s_and_b32 s5, s18, 0xff2428; SI-NEXT:    s_lshl_b32 s5, s5, 162429; SI-NEXT:    s_lshl_b32 s6, s19, 242430; SI-NEXT:    s_and_b32 s4, s4, 0xffff2431; SI-NEXT:    s_or_b32 s5, s6, s52432; SI-NEXT:    s_or_b32 s6, s4, s52433; SI-NEXT:    s_cbranch_execnz .LBB23_32434; SI-NEXT:  .LBB23_2: ; %cmp.true2435; SI-NEXT:    s_add_i32 s16, s16, 32436; SI-NEXT:    s_and_b32 s4, s16, 0xff2437; SI-NEXT:    s_lshl_b32 s5, s17, 82438; SI-NEXT:    s_add_i32 s18, s18, 32439; SI-NEXT:    s_or_b32 s4, s5, s42440; SI-NEXT:    s_and_b32 s6, s18, 0xff2441; SI-NEXT:    s_addk_i32 s4, 0x3002442; SI-NEXT:    s_lshl_b32 s5, s19, 242443; SI-NEXT:    s_lshl_b32 s6, s6, 162444; SI-NEXT:    s_and_b32 s4, s4, 0xffff2445; SI-NEXT:    s_or_b32 s5, s5, s62446; SI-NEXT:    s_or_b32 s4, s5, s42447; SI-NEXT:    s_add_i32 s6, s4, 0x30000002448; SI-NEXT:  .LBB23_3: ; %end2449; SI-NEXT:    v_mov_b32_e32 v0, s62450; SI-NEXT:    s_setpc_b64 s[30:31]2451; SI-NEXT:  .LBB23_4:2452; SI-NEXT:    ; implicit-def: $sgpr62453; SI-NEXT:    s_branch .LBB23_22454;2455; VI-LABEL: bitcast_v4i8_to_i32_scalar:2456; VI:       ; %bb.0:2457; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2458; VI-NEXT:    s_cmp_lg_u32 s20, 02459; VI-NEXT:    s_cbranch_scc0 .LBB23_42460; VI-NEXT:  ; %bb.1: ; %cmp.false2461; VI-NEXT:    s_and_b32 s4, s16, 0xff2462; VI-NEXT:    s_lshl_b32 s5, s17, 82463; VI-NEXT:    s_or_b32 s4, s4, s52464; VI-NEXT:    s_and_b32 s5, s18, 0xff2465; VI-NEXT:    s_lshl_b32 s6, s19, 82466; VI-NEXT:    s_or_b32 s5, s5, s62467; VI-NEXT:    s_and_b32 s4, s4, 0xffff2468; VI-NEXT:    s_lshl_b32 s5, s5, 162469; VI-NEXT:    s_or_b32 s6, s4, s52470; VI-NEXT:    s_cbranch_execnz .LBB23_32471; VI-NEXT:  .LBB23_2: ; %cmp.true2472; VI-NEXT:    s_add_i32 s16, s16, 32473; VI-NEXT:    s_and_b32 s4, s16, 0xff2474; VI-NEXT:    s_lshl_b32 s5, s17, 82475; VI-NEXT:    s_add_i32 s18, s18, 32476; VI-NEXT:    s_or_b32 s4, s5, s42477; VI-NEXT:    s_and_b32 s5, s18, 0xff2478; VI-NEXT:    s_lshl_b32 s6, s19, 82479; VI-NEXT:    s_addk_i32 s4, 0x3002480; VI-NEXT:    s_or_b32 s5, s6, s52481; VI-NEXT:    s_and_b32 s4, s4, 0xffff2482; VI-NEXT:    s_lshl_b32 s5, s5, 162483; VI-NEXT:    s_or_b32 s4, s5, s42484; VI-NEXT:    s_add_i32 s6, s4, 0x30000002485; VI-NEXT:  .LBB23_3: ; %end2486; VI-NEXT:    v_mov_b32_e32 v0, s62487; VI-NEXT:    s_setpc_b64 s[30:31]2488; VI-NEXT:  .LBB23_4:2489; VI-NEXT:    ; implicit-def: $sgpr62490; VI-NEXT:    s_branch .LBB23_22491;2492; GFX9-LABEL: bitcast_v4i8_to_i32_scalar:2493; GFX9:       ; %bb.0:2494; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2495; GFX9-NEXT:    s_cmp_lg_u32 s20, 02496; GFX9-NEXT:    s_cbranch_scc0 .LBB23_42497; GFX9-NEXT:  ; %bb.1: ; %cmp.false2498; GFX9-NEXT:    s_and_b32 s4, s16, 0xff2499; GFX9-NEXT:    s_lshl_b32 s5, s17, 82500; GFX9-NEXT:    s_or_b32 s4, s4, s52501; GFX9-NEXT:    s_and_b32 s5, s18, 0xff2502; GFX9-NEXT:    s_lshl_b32 s6, s19, 82503; GFX9-NEXT:    s_or_b32 s5, s5, s62504; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff2505; GFX9-NEXT:    s_lshl_b32 s5, s5, 162506; GFX9-NEXT:    s_or_b32 s6, s4, s52507; GFX9-NEXT:    s_cbranch_execnz .LBB23_32508; GFX9-NEXT:  .LBB23_2: ; %cmp.true2509; GFX9-NEXT:    s_add_i32 s16, s16, 32510; GFX9-NEXT:    s_and_b32 s4, s16, 0xff2511; GFX9-NEXT:    s_lshl_b32 s5, s17, 82512; GFX9-NEXT:    s_add_i32 s18, s18, 32513; GFX9-NEXT:    s_or_b32 s4, s5, s42514; GFX9-NEXT:    s_and_b32 s5, s18, 0xff2515; GFX9-NEXT:    s_lshl_b32 s6, s19, 82516; GFX9-NEXT:    s_or_b32 s5, s6, s52517; GFX9-NEXT:    s_addk_i32 s4, 0x3002518; GFX9-NEXT:    s_addk_i32 s5, 0x3002519; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff2520; GFX9-NEXT:    s_lshl_b32 s5, s5, 162521; GFX9-NEXT:    s_or_b32 s6, s4, s52522; GFX9-NEXT:  .LBB23_3: ; %end2523; GFX9-NEXT:    v_mov_b32_e32 v0, s62524; GFX9-NEXT:    s_setpc_b64 s[30:31]2525; GFX9-NEXT:  .LBB23_4:2526; GFX9-NEXT:    ; implicit-def: $sgpr62527; GFX9-NEXT:    s_branch .LBB23_22528;2529; GFX11-LABEL: bitcast_v4i8_to_i32_scalar:2530; GFX11:       ; %bb.0:2531; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2532; GFX11-NEXT:    s_cmp_lg_u32 s16, 02533; GFX11-NEXT:    s_mov_b32 s4, 02534; GFX11-NEXT:    s_cbranch_scc0 .LBB23_42535; GFX11-NEXT:  ; %bb.1: ; %cmp.false2536; GFX11-NEXT:    s_and_b32 s5, s0, 0xff2537; GFX11-NEXT:    s_lshl_b32 s6, s1, 82538; GFX11-NEXT:    s_and_b32 s7, s2, 0xff2539; GFX11-NEXT:    s_lshl_b32 s8, s3, 82540; GFX11-NEXT:    s_or_b32 s5, s5, s62541; GFX11-NEXT:    s_or_b32 s6, s7, s82542; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff2543; GFX11-NEXT:    s_lshl_b32 s6, s6, 162544; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2545; GFX11-NEXT:    s_or_b32 s5, s5, s62546; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s42547; GFX11-NEXT:    s_cbranch_vccnz .LBB23_32548; GFX11-NEXT:  .LBB23_2: ; %cmp.true2549; GFX11-NEXT:    s_add_i32 s0, s0, 32550; GFX11-NEXT:    s_add_i32 s2, s2, 32551; GFX11-NEXT:    s_and_b32 s0, s0, 0xff2552; GFX11-NEXT:    s_lshl_b32 s1, s1, 82553; GFX11-NEXT:    s_and_b32 s2, s2, 0xff2554; GFX11-NEXT:    s_lshl_b32 s3, s3, 82555; GFX11-NEXT:    s_or_b32 s0, s1, s02556; GFX11-NEXT:    s_or_b32 s1, s3, s22557; GFX11-NEXT:    s_addk_i32 s0, 0x3002558; GFX11-NEXT:    s_addk_i32 s1, 0x3002559; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff2560; GFX11-NEXT:    s_lshl_b32 s1, s1, 162561; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2562; GFX11-NEXT:    s_or_b32 s5, s0, s12563; GFX11-NEXT:  .LBB23_3: ; %end2564; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2565; GFX11-NEXT:    v_mov_b32_e32 v0, s52566; GFX11-NEXT:    s_setpc_b64 s[30:31]2567; GFX11-NEXT:  .LBB23_4:2568; GFX11-NEXT:    ; implicit-def: $sgpr52569; GFX11-NEXT:    s_branch .LBB23_22570  %cmp = icmp eq i32 %b, 02571  br i1 %cmp, label %cmp.true, label %cmp.false2572 2573cmp.true:2574  %a1 = add <4 x i8> %a, splat (i8 3)2575  %a2 = bitcast <4 x i8> %a1 to i322576  br label %end2577 2578cmp.false:2579  %a3 = bitcast <4 x i8> %a to i322580  br label %end2581 2582end:2583  %phi = phi i32 [ %a2, %cmp.true ], [ %a3, %cmp.false ]2584  ret i32 %phi2585}2586 2587define <2 x i16> @bitcast_f32_to_v2i16(float %a, i32 %b) {2588; SI-LABEL: bitcast_f32_to_v2i16:2589; SI:       ; %bb.0:2590; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2591; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12592; SI-NEXT:    ; implicit-def: $vgpr12593; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2594; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2595; SI-NEXT:    s_cbranch_execnz .LBB24_32596; SI-NEXT:  ; %bb.1: ; %Flow2597; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2598; SI-NEXT:    s_cbranch_execnz .LBB24_42599; SI-NEXT:  .LBB24_2: ; %end2600; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2601; SI-NEXT:    s_setpc_b64 s[30:31]2602; SI-NEXT:  .LBB24_3: ; %cmp.false2603; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v02604; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2605; SI-NEXT:    s_cbranch_execz .LBB24_22606; SI-NEXT:  .LBB24_4: ; %cmp.true2607; SI-NEXT:    v_add_f32_e32 v0, 1.0, v02608; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v02609; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2610; SI-NEXT:    s_setpc_b64 s[30:31]2611;2612; VI-LABEL: bitcast_f32_to_v2i16:2613; VI:       ; %bb.0:2614; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2615; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12616; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2617; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2618; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2619; VI-NEXT:  ; %bb.1: ; %cmp.true2620; VI-NEXT:    v_add_f32_e32 v0, 1.0, v02621; VI-NEXT:  ; %bb.2: ; %end2622; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2623; VI-NEXT:    s_setpc_b64 s[30:31]2624;2625; GFX9-LABEL: bitcast_f32_to_v2i16:2626; GFX9:       ; %bb.0:2627; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2628; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12629; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2630; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2631; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2632; GFX9-NEXT:  ; %bb.1: ; %cmp.true2633; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v02634; GFX9-NEXT:  ; %bb.2: ; %end2635; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2636; GFX9-NEXT:    s_setpc_b64 s[30:31]2637;2638; GFX11-LABEL: bitcast_f32_to_v2i16:2639; GFX11:       ; %bb.0:2640; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2641; GFX11-NEXT:    s_mov_b32 s0, exec_lo2642; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v12643; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02644; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2645; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02646; GFX11-NEXT:  ; %bb.1: ; %cmp.true2647; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v02648; GFX11-NEXT:  ; %bb.2: ; %end2649; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02650; GFX11-NEXT:    s_setpc_b64 s[30:31]2651  %cmp = icmp eq i32 %b, 02652  br i1 %cmp, label %cmp.true, label %cmp.false2653 2654cmp.true:2655  %a1 = fadd float %a, 1.000000e+002656  %a2 = bitcast float %a1 to <2 x i16>2657  br label %end2658 2659cmp.false:2660  %a3 = bitcast float %a to <2 x i16>2661  br label %end2662 2663end:2664  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2665  ret <2 x i16> %phi2666}2667 2668define inreg <2 x i16> @bitcast_f32_to_v2i16_scalar(float inreg %a, i32 inreg %b) {2669; SI-LABEL: bitcast_f32_to_v2i16_scalar:2670; SI:       ; %bb.0:2671; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2672; SI-NEXT:    s_cmp_lg_u32 s17, 02673; SI-NEXT:    s_cbranch_scc0 .LBB25_32674; SI-NEXT:  ; %bb.1: ; %cmp.false2675; SI-NEXT:    s_lshr_b32 s6, s16, 162676; SI-NEXT:    s_cbranch_execnz .LBB25_42677; SI-NEXT:  .LBB25_2: ; %cmp.true2678; SI-NEXT:    v_add_f32_e64 v0, s16, 1.02679; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v02680; SI-NEXT:    s_setpc_b64 s[30:31]2681; SI-NEXT:  .LBB25_3:2682; SI-NEXT:    ; implicit-def: $sgpr62683; SI-NEXT:    s_branch .LBB25_22684; SI-NEXT:  .LBB25_4:2685; SI-NEXT:    v_mov_b32_e32 v0, s162686; SI-NEXT:    v_mov_b32_e32 v1, s62687; SI-NEXT:    s_setpc_b64 s[30:31]2688;2689; VI-LABEL: bitcast_f32_to_v2i16_scalar:2690; VI:       ; %bb.0:2691; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2692; VI-NEXT:    s_cmp_lg_u32 s17, 02693; VI-NEXT:    s_cbranch_scc0 .LBB25_32694; VI-NEXT:  ; %bb.1: ; %cmp.false2695; VI-NEXT:    s_cbranch_execnz .LBB25_42696; VI-NEXT:  .LBB25_2: ; %cmp.true2697; VI-NEXT:    v_add_f32_e64 v0, s16, 1.02698; VI-NEXT:    s_setpc_b64 s[30:31]2699; VI-NEXT:  .LBB25_3:2700; VI-NEXT:    s_branch .LBB25_22701; VI-NEXT:  .LBB25_4:2702; VI-NEXT:    v_mov_b32_e32 v0, s162703; VI-NEXT:    s_setpc_b64 s[30:31]2704;2705; GFX9-LABEL: bitcast_f32_to_v2i16_scalar:2706; GFX9:       ; %bb.0:2707; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2708; GFX9-NEXT:    s_cmp_lg_u32 s17, 02709; GFX9-NEXT:    s_cbranch_scc0 .LBB25_32710; GFX9-NEXT:  ; %bb.1: ; %cmp.false2711; GFX9-NEXT:    s_cbranch_execnz .LBB25_42712; GFX9-NEXT:  .LBB25_2: ; %cmp.true2713; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.02714; GFX9-NEXT:    s_setpc_b64 s[30:31]2715; GFX9-NEXT:  .LBB25_3:2716; GFX9-NEXT:    s_branch .LBB25_22717; GFX9-NEXT:  .LBB25_4:2718; GFX9-NEXT:    v_mov_b32_e32 v0, s162719; GFX9-NEXT:    s_setpc_b64 s[30:31]2720;2721; GFX11-LABEL: bitcast_f32_to_v2i16_scalar:2722; GFX11:       ; %bb.0:2723; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2724; GFX11-NEXT:    s_cmp_lg_u32 s1, 02725; GFX11-NEXT:    s_mov_b32 s1, 02726; GFX11-NEXT:    s_cbranch_scc0 .LBB25_32727; GFX11-NEXT:  ; %bb.1: ; %Flow2728; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s12729; GFX11-NEXT:    s_cbranch_vccnz .LBB25_42730; GFX11-NEXT:  .LBB25_2: ; %cmp.true2731; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.02732; GFX11-NEXT:    s_setpc_b64 s[30:31]2733; GFX11-NEXT:  .LBB25_3:2734; GFX11-NEXT:    s_branch .LBB25_22735; GFX11-NEXT:  .LBB25_4:2736; GFX11-NEXT:    v_mov_b32_e32 v0, s02737; GFX11-NEXT:    s_setpc_b64 s[30:31]2738  %cmp = icmp eq i32 %b, 02739  br i1 %cmp, label %cmp.true, label %cmp.false2740 2741cmp.true:2742  %a1 = fadd float %a, 1.000000e+002743  %a2 = bitcast float %a1 to <2 x i16>2744  br label %end2745 2746cmp.false:2747  %a3 = bitcast float %a to <2 x i16>2748  br label %end2749 2750end:2751  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]2752  ret <2 x i16> %phi2753}2754 2755define float @bitcast_v2i16_to_f32(<2 x i16> %a, i32 %b) {2756; SI-LABEL: bitcast_v2i16_to_f32:2757; SI:       ; %bb.0:2758; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2759; SI-NEXT:    v_mov_b32_e32 v3, v02760; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v22761; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v12762; SI-NEXT:    ; implicit-def: $vgpr02763; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2764; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2765; SI-NEXT:    s_cbranch_execnz .LBB26_32766; SI-NEXT:  ; %bb.1: ; %Flow2767; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2768; SI-NEXT:    s_cbranch_execnz .LBB26_42769; SI-NEXT:  .LBB26_2: ; %end2770; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2771; SI-NEXT:    s_setpc_b64 s[30:31]2772; SI-NEXT:  .LBB26_3: ; %cmp.false2773; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v32774; SI-NEXT:    v_or_b32_e32 v0, v0, v12775; SI-NEXT:    ; implicit-def: $vgpr32776; SI-NEXT:    ; implicit-def: $vgpr12777; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2778; SI-NEXT:    s_cbranch_execz .LBB26_22779; SI-NEXT:  .LBB26_4: ; %cmp.true2780; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v32781; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v02782; SI-NEXT:    v_or_b32_e32 v0, v1, v02783; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v02784; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2785; SI-NEXT:    s_setpc_b64 s[30:31]2786;2787; VI-LABEL: bitcast_v2i16_to_f32:2788; VI:       ; %bb.0:2789; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2790; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12791; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2792; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2793; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2794; VI-NEXT:  ; %bb.1: ; %cmp.true2795; VI-NEXT:    v_mov_b32_e32 v2, 32796; VI-NEXT:    v_add_u16_e32 v1, 3, v02797; VI-NEXT:    v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD2798; VI-NEXT:    v_or_b32_e32 v0, v1, v02799; VI-NEXT:  ; %bb.2: ; %end2800; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2801; VI-NEXT:    s_setpc_b64 s[30:31]2802;2803; GFX9-LABEL: bitcast_v2i16_to_f32:2804; GFX9:       ; %bb.0:2805; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2806; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12807; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2808; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2809; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2810; GFX9-NEXT:  ; %bb.1: ; %cmp.true2811; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2812; GFX9-NEXT:  ; %bb.2: ; %end2813; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2814; GFX9-NEXT:    s_setpc_b64 s[30:31]2815;2816; GFX11-LABEL: bitcast_v2i16_to_f32:2817; GFX11:       ; %bb.0:2818; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2819; GFX11-NEXT:    s_mov_b32 s0, exec_lo2820; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v12821; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s02822; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)2823; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s02824; GFX11-NEXT:  ; %bb.1: ; %cmp.true2825; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]2826; GFX11-NEXT:  ; %bb.2: ; %end2827; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s02828; GFX11-NEXT:    s_setpc_b64 s[30:31]2829  %cmp = icmp eq i32 %b, 02830  br i1 %cmp, label %cmp.true, label %cmp.false2831 2832cmp.true:2833  %a1 = add <2 x i16> %a, splat (i16 3)2834  %a2 = bitcast <2 x i16> %a1 to float2835  br label %end2836 2837cmp.false:2838  %a3 = bitcast <2 x i16> %a to float2839  br label %end2840 2841end:2842  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]2843  ret float %phi2844}2845 2846define inreg float @bitcast_v2i16_to_f32_scalar(<2 x i16> inreg %a, i32 inreg %b) {2847; SI-LABEL: bitcast_v2i16_to_f32_scalar:2848; SI:       ; %bb.0:2849; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2850; SI-NEXT:    s_cmp_lg_u32 s18, 02851; SI-NEXT:    s_cbranch_scc0 .LBB27_42852; SI-NEXT:  ; %bb.1: ; %cmp.false2853; SI-NEXT:    s_and_b32 s4, s16, 0xffff2854; SI-NEXT:    s_lshl_b32 s5, s17, 162855; SI-NEXT:    s_or_b32 s6, s4, s52856; SI-NEXT:    s_cbranch_execnz .LBB27_32857; SI-NEXT:  .LBB27_2: ; %cmp.true2858; SI-NEXT:    s_add_i32 s16, s16, 32859; SI-NEXT:    s_and_b32 s4, s16, 0xffff2860; SI-NEXT:    s_lshl_b32 s5, s17, 162861; SI-NEXT:    s_or_b32 s4, s5, s42862; SI-NEXT:    s_add_i32 s6, s4, 0x300002863; SI-NEXT:  .LBB27_3: ; %end2864; SI-NEXT:    v_mov_b32_e32 v0, s62865; SI-NEXT:    s_setpc_b64 s[30:31]2866; SI-NEXT:  .LBB27_4:2867; SI-NEXT:    ; implicit-def: $sgpr62868; SI-NEXT:    s_branch .LBB27_22869;2870; VI-LABEL: bitcast_v2i16_to_f32_scalar:2871; VI:       ; %bb.0:2872; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2873; VI-NEXT:    s_cmp_lg_u32 s17, 02874; VI-NEXT:    s_cbranch_scc0 .LBB27_42875; VI-NEXT:  ; %bb.1: ; %cmp.false2876; VI-NEXT:    s_cbranch_execnz .LBB27_32877; VI-NEXT:  .LBB27_2: ; %cmp.true2878; VI-NEXT:    s_add_i32 s5, s16, 32879; VI-NEXT:    s_and_b32 s4, s16, 0xffff00002880; VI-NEXT:    s_and_b32 s5, s5, 0xffff2881; VI-NEXT:    s_or_b32 s4, s4, s52882; VI-NEXT:    s_add_i32 s16, s4, 0x300002883; VI-NEXT:  .LBB27_3: ; %end2884; VI-NEXT:    v_mov_b32_e32 v0, s162885; VI-NEXT:    s_setpc_b64 s[30:31]2886; VI-NEXT:  .LBB27_4:2887; VI-NEXT:    s_branch .LBB27_22888;2889; GFX9-LABEL: bitcast_v2i16_to_f32_scalar:2890; GFX9:       ; %bb.0:2891; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2892; GFX9-NEXT:    s_cmp_lg_u32 s17, 02893; GFX9-NEXT:    s_cbranch_scc0 .LBB27_32894; GFX9-NEXT:  ; %bb.1: ; %cmp.false2895; GFX9-NEXT:    s_cbranch_execnz .LBB27_42896; GFX9-NEXT:  .LBB27_2: ; %cmp.true2897; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]2898; GFX9-NEXT:    s_setpc_b64 s[30:31]2899; GFX9-NEXT:  .LBB27_3:2900; GFX9-NEXT:    s_branch .LBB27_22901; GFX9-NEXT:  .LBB27_4:2902; GFX9-NEXT:    v_mov_b32_e32 v0, s162903; GFX9-NEXT:    s_setpc_b64 s[30:31]2904;2905; GFX11-LABEL: bitcast_v2i16_to_f32_scalar:2906; GFX11:       ; %bb.0:2907; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2908; GFX11-NEXT:    s_cmp_lg_u32 s1, 02909; GFX11-NEXT:    s_mov_b32 s1, 02910; GFX11-NEXT:    s_cbranch_scc0 .LBB27_32911; GFX11-NEXT:  ; %bb.1: ; %Flow2912; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s12913; GFX11-NEXT:    s_cbranch_vccnz .LBB27_42914; GFX11-NEXT:  .LBB27_2: ; %cmp.true2915; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]2916; GFX11-NEXT:    s_setpc_b64 s[30:31]2917; GFX11-NEXT:  .LBB27_3:2918; GFX11-NEXT:    s_branch .LBB27_22919; GFX11-NEXT:  .LBB27_4:2920; GFX11-NEXT:    v_mov_b32_e32 v0, s02921; GFX11-NEXT:    s_setpc_b64 s[30:31]2922  %cmp = icmp eq i32 %b, 02923  br i1 %cmp, label %cmp.true, label %cmp.false2924 2925cmp.true:2926  %a1 = add <2 x i16> %a, splat (i16 3)2927  %a2 = bitcast <2 x i16> %a1 to float2928  br label %end2929 2930cmp.false:2931  %a3 = bitcast <2 x i16> %a to float2932  br label %end2933 2934end:2935  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]2936  ret float %phi2937}2938 2939define <2 x half> @bitcast_f32_to_v2f16(float %a, i32 %b) {2940; SI-LABEL: bitcast_f32_to_v2f16:2941; SI:       ; %bb.0:2942; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2943; SI-NEXT:    v_mov_b32_e32 v2, v02944; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12945; SI-NEXT:    ; implicit-def: $vgpr02946; SI-NEXT:    ; implicit-def: $vgpr12947; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2948; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2949; SI-NEXT:    s_cbranch_execnz .LBB28_32950; SI-NEXT:  ; %bb.1: ; %Flow2951; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2952; SI-NEXT:    s_cbranch_execnz .LBB28_42953; SI-NEXT:  .LBB28_2: ; %end2954; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2955; SI-NEXT:    s_setpc_b64 s[30:31]2956; SI-NEXT:  .LBB28_3: ; %cmp.false2957; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v22958; SI-NEXT:    v_cvt_f32_f16_e32 v1, v02959; SI-NEXT:    v_cvt_f32_f16_e32 v0, v22960; SI-NEXT:    ; implicit-def: $vgpr22961; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2962; SI-NEXT:    s_cbranch_execz .LBB28_22963; SI-NEXT:  .LBB28_4: ; %cmp.true2964; SI-NEXT:    v_add_f32_e32 v0, 1.0, v22965; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v02966; SI-NEXT:    v_cvt_f32_f16_e32 v0, v02967; SI-NEXT:    v_cvt_f32_f16_e32 v1, v12968; SI-NEXT:    s_or_b64 exec, exec, s[4:5]2969; SI-NEXT:    s_setpc_b64 s[30:31]2970;2971; VI-LABEL: bitcast_f32_to_v2f16:2972; VI:       ; %bb.0:2973; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2974; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12975; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc2976; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2977; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2978; VI-NEXT:  ; %bb.1: ; %cmp.true2979; VI-NEXT:    v_add_f32_e32 v0, 1.0, v02980; VI-NEXT:  ; %bb.2: ; %end2981; VI-NEXT:    s_or_b64 exec, exec, s[4:5]2982; VI-NEXT:    s_setpc_b64 s[30:31]2983;2984; GFX9-LABEL: bitcast_f32_to_v2f16:2985; GFX9:       ; %bb.0:2986; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)2987; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v12988; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc2989; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]2990; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]2991; GFX9-NEXT:  ; %bb.1: ; %cmp.true2992; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v02993; GFX9-NEXT:  ; %bb.2: ; %end2994; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]2995; GFX9-NEXT:    s_setpc_b64 s[30:31]2996;2997; GFX11-LABEL: bitcast_f32_to_v2f16:2998; GFX11:       ; %bb.0:2999; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3000; GFX11-NEXT:    s_mov_b32 s0, exec_lo3001; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v13002; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03003; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3004; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03005; GFX11-NEXT:  ; %bb.1: ; %cmp.true3006; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v03007; GFX11-NEXT:  ; %bb.2: ; %end3008; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03009; GFX11-NEXT:    s_setpc_b64 s[30:31]3010  %cmp = icmp eq i32 %b, 03011  br i1 %cmp, label %cmp.true, label %cmp.false3012 3013cmp.true:3014  %a1 = fadd float %a, 1.000000e+003015  %a2 = bitcast float %a1 to <2 x half>3016  br label %end3017 3018cmp.false:3019  %a3 = bitcast float %a to <2 x half>3020  br label %end3021 3022end:3023  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3024  ret <2 x half> %phi3025}3026 3027define inreg <2 x half> @bitcast_f32_to_v2f16_scalar(float inreg %a, i32 inreg %b) {3028; SI-LABEL: bitcast_f32_to_v2f16_scalar:3029; SI:       ; %bb.0:3030; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3031; SI-NEXT:    s_cmp_lg_u32 s17, 03032; SI-NEXT:    s_cbranch_scc0 .LBB29_43033; SI-NEXT:  ; %bb.1: ; %cmp.false3034; SI-NEXT:    s_lshr_b32 s4, s16, 163035; SI-NEXT:    v_cvt_f32_f16_e32 v1, s43036; SI-NEXT:    v_cvt_f32_f16_e32 v0, s163037; SI-NEXT:    s_cbranch_execnz .LBB29_33038; SI-NEXT:  .LBB29_2: ; %cmp.true3039; SI-NEXT:    v_add_f32_e64 v0, s16, 1.03040; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v03041; SI-NEXT:    v_cvt_f32_f16_e32 v0, v03042; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13043; SI-NEXT:  .LBB29_3: ; %end3044; SI-NEXT:    s_setpc_b64 s[30:31]3045; SI-NEXT:  .LBB29_4:3046; SI-NEXT:    ; implicit-def: $vgpr03047; SI-NEXT:    ; implicit-def: $vgpr13048; SI-NEXT:    s_branch .LBB29_23049;3050; VI-LABEL: bitcast_f32_to_v2f16_scalar:3051; VI:       ; %bb.0:3052; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3053; VI-NEXT:    s_cmp_lg_u32 s17, 03054; VI-NEXT:    s_cbranch_scc0 .LBB29_33055; VI-NEXT:  ; %bb.1: ; %cmp.false3056; VI-NEXT:    s_cbranch_execnz .LBB29_43057; VI-NEXT:  .LBB29_2: ; %cmp.true3058; VI-NEXT:    v_add_f32_e64 v0, s16, 1.03059; VI-NEXT:    s_setpc_b64 s[30:31]3060; VI-NEXT:  .LBB29_3:3061; VI-NEXT:    s_branch .LBB29_23062; VI-NEXT:  .LBB29_4:3063; VI-NEXT:    v_mov_b32_e32 v0, s163064; VI-NEXT:    s_setpc_b64 s[30:31]3065;3066; GFX9-LABEL: bitcast_f32_to_v2f16_scalar:3067; GFX9:       ; %bb.0:3068; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3069; GFX9-NEXT:    s_cmp_lg_u32 s17, 03070; GFX9-NEXT:    s_cbranch_scc0 .LBB29_33071; GFX9-NEXT:  ; %bb.1: ; %cmp.false3072; GFX9-NEXT:    s_cbranch_execnz .LBB29_43073; GFX9-NEXT:  .LBB29_2: ; %cmp.true3074; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.03075; GFX9-NEXT:    s_setpc_b64 s[30:31]3076; GFX9-NEXT:  .LBB29_3:3077; GFX9-NEXT:    s_branch .LBB29_23078; GFX9-NEXT:  .LBB29_4:3079; GFX9-NEXT:    v_mov_b32_e32 v0, s163080; GFX9-NEXT:    s_setpc_b64 s[30:31]3081;3082; GFX11-LABEL: bitcast_f32_to_v2f16_scalar:3083; GFX11:       ; %bb.0:3084; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3085; GFX11-NEXT:    s_cmp_lg_u32 s1, 03086; GFX11-NEXT:    s_mov_b32 s1, 03087; GFX11-NEXT:    s_cbranch_scc0 .LBB29_33088; GFX11-NEXT:  ; %bb.1: ; %Flow3089; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13090; GFX11-NEXT:    s_cbranch_vccnz .LBB29_43091; GFX11-NEXT:  .LBB29_2: ; %cmp.true3092; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.03093; GFX11-NEXT:    s_setpc_b64 s[30:31]3094; GFX11-NEXT:  .LBB29_3:3095; GFX11-NEXT:    s_branch .LBB29_23096; GFX11-NEXT:  .LBB29_4:3097; GFX11-NEXT:    v_mov_b32_e32 v0, s03098; GFX11-NEXT:    s_setpc_b64 s[30:31]3099  %cmp = icmp eq i32 %b, 03100  br i1 %cmp, label %cmp.true, label %cmp.false3101 3102cmp.true:3103  %a1 = fadd float %a, 1.000000e+003104  %a2 = bitcast float %a1 to <2 x half>3105  br label %end3106 3107cmp.false:3108  %a3 = bitcast float %a to <2 x half>3109  br label %end3110 3111end:3112  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3113  ret <2 x half> %phi3114}3115 3116define float @bitcast_v2f16_to_f32(<2 x half> %a, i32 %b) {3117; SI-LABEL: bitcast_v2f16_to_f32:3118; SI:       ; %bb.0:3119; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3120; SI-NEXT:    v_cvt_f16_f32_e32 v3, v13121; SI-NEXT:    v_cvt_f16_f32_e32 v1, v03122; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23123; SI-NEXT:    ; implicit-def: $vgpr03124; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3125; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3126; SI-NEXT:    s_cbranch_execnz .LBB30_33127; SI-NEXT:  ; %bb.1: ; %Flow3128; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3129; SI-NEXT:    s_cbranch_execnz .LBB30_43130; SI-NEXT:  .LBB30_2: ; %end3131; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3132; SI-NEXT:    s_setpc_b64 s[30:31]3133; SI-NEXT:  .LBB30_3: ; %cmp.false3134; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v33135; SI-NEXT:    v_or_b32_e32 v0, v1, v03136; SI-NEXT:    ; implicit-def: $vgpr33137; SI-NEXT:    ; implicit-def: $vgpr13138; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3139; SI-NEXT:    s_cbranch_execz .LBB30_23140; SI-NEXT:  .LBB30_4: ; %cmp.true3141; SI-NEXT:    v_cvt_f32_f16_e32 v0, v33142; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13143; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v03144; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03145; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v13146; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13147; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v03148; SI-NEXT:    v_or_b32_e32 v0, v1, v03149; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3150; SI-NEXT:    s_setpc_b64 s[30:31]3151;3152; VI-LABEL: bitcast_v2f16_to_f32:3153; VI:       ; %bb.0:3154; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3155; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13156; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3157; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3158; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3159; VI-NEXT:  ; %bb.1: ; %cmp.true3160; VI-NEXT:    v_mov_b32_e32 v1, 0x2003161; VI-NEXT:    v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD3162; VI-NEXT:    v_add_f16_e32 v0, 0x200, v03163; VI-NEXT:    v_or_b32_e32 v0, v0, v13164; VI-NEXT:  ; %bb.2: ; %end3165; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3166; VI-NEXT:    s_setpc_b64 s[30:31]3167;3168; GFX9-LABEL: bitcast_v2f16_to_f32:3169; GFX9:       ; %bb.0:3170; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3171; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13172; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3173; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3174; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3175; GFX9-NEXT:  ; %bb.1: ; %cmp.true3176; GFX9-NEXT:    s_movk_i32 s6, 0x2003177; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]3178; GFX9-NEXT:  ; %bb.2: ; %end3179; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3180; GFX9-NEXT:    s_setpc_b64 s[30:31]3181;3182; GFX11-LABEL: bitcast_v2f16_to_f32:3183; GFX11:       ; %bb.0:3184; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3185; GFX11-NEXT:    s_mov_b32 s0, exec_lo3186; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v13187; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03188; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3189; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03190; GFX11-NEXT:  ; %bb.1: ; %cmp.true3191; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]3192; GFX11-NEXT:  ; %bb.2: ; %end3193; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03194; GFX11-NEXT:    s_setpc_b64 s[30:31]3195  %cmp = icmp eq i32 %b, 03196  br i1 %cmp, label %cmp.true, label %cmp.false3197 3198cmp.true:3199  %a1 = fadd <2 x half> %a, splat (half 0xH0200)3200  %a2 = bitcast <2 x half> %a1 to float3201  br label %end3202 3203cmp.false:3204  %a3 = bitcast <2 x half> %a to float3205  br label %end3206 3207end:3208  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]3209  ret float %phi3210}3211 3212define inreg float @bitcast_v2f16_to_f32_scalar(<2 x half> inreg %a, i32 inreg %b) {3213; SI-LABEL: bitcast_v2f16_to_f32_scalar:3214; SI:       ; %bb.0:3215; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3216; SI-NEXT:    v_cvt_f16_f32_e32 v2, s173217; SI-NEXT:    v_cvt_f16_f32_e32 v1, s163218; SI-NEXT:    s_cmp_lg_u32 s18, 03219; SI-NEXT:    s_cbranch_scc0 .LBB31_43220; SI-NEXT:  ; %bb.1: ; %cmp.false3221; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v23222; SI-NEXT:    v_or_b32_e32 v0, v1, v03223; SI-NEXT:    s_cbranch_execnz .LBB31_33224; SI-NEXT:  .LBB31_2: ; %cmp.true3225; SI-NEXT:    v_cvt_f32_f16_e32 v0, v23226; SI-NEXT:    v_cvt_f32_f16_e32 v1, v13227; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v03228; SI-NEXT:    v_cvt_f16_f32_e32 v0, v03229; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v13230; SI-NEXT:    v_cvt_f16_f32_e32 v1, v13231; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v03232; SI-NEXT:    v_or_b32_e32 v0, v1, v03233; SI-NEXT:  .LBB31_3: ; %end3234; SI-NEXT:    s_setpc_b64 s[30:31]3235; SI-NEXT:  .LBB31_4:3236; SI-NEXT:    ; implicit-def: $vgpr03237; SI-NEXT:    s_branch .LBB31_23238;3239; VI-LABEL: bitcast_v2f16_to_f32_scalar:3240; VI:       ; %bb.0:3241; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3242; VI-NEXT:    s_cmp_lg_u32 s17, 03243; VI-NEXT:    s_cbranch_scc0 .LBB31_33244; VI-NEXT:  ; %bb.1: ; %cmp.false3245; VI-NEXT:    s_cbranch_execnz .LBB31_43246; VI-NEXT:  .LBB31_2: ; %cmp.true3247; VI-NEXT:    s_lshr_b32 s4, s16, 163248; VI-NEXT:    v_mov_b32_e32 v0, 0x2003249; VI-NEXT:    v_mov_b32_e32 v1, s43250; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD3251; VI-NEXT:    v_add_f16_e32 v0, s16, v03252; VI-NEXT:    v_or_b32_e32 v0, v0, v13253; VI-NEXT:    s_setpc_b64 s[30:31]3254; VI-NEXT:  .LBB31_3:3255; VI-NEXT:    s_branch .LBB31_23256; VI-NEXT:  .LBB31_4:3257; VI-NEXT:    v_mov_b32_e32 v0, s163258; VI-NEXT:    s_setpc_b64 s[30:31]3259;3260; GFX9-LABEL: bitcast_v2f16_to_f32_scalar:3261; GFX9:       ; %bb.0:3262; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3263; GFX9-NEXT:    s_cmp_lg_u32 s17, 03264; GFX9-NEXT:    s_cbranch_scc0 .LBB31_33265; GFX9-NEXT:  ; %bb.1: ; %cmp.false3266; GFX9-NEXT:    s_cbranch_execnz .LBB31_43267; GFX9-NEXT:  .LBB31_2: ; %cmp.true3268; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2003269; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]3270; GFX9-NEXT:    s_setpc_b64 s[30:31]3271; GFX9-NEXT:  .LBB31_3:3272; GFX9-NEXT:    s_branch .LBB31_23273; GFX9-NEXT:  .LBB31_4:3274; GFX9-NEXT:    v_mov_b32_e32 v0, s163275; GFX9-NEXT:    s_setpc_b64 s[30:31]3276;3277; GFX11-LABEL: bitcast_v2f16_to_f32_scalar:3278; GFX11:       ; %bb.0:3279; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3280; GFX11-NEXT:    s_cmp_lg_u32 s1, 03281; GFX11-NEXT:    s_mov_b32 s1, 03282; GFX11-NEXT:    s_cbranch_scc0 .LBB31_33283; GFX11-NEXT:  ; %bb.1: ; %Flow3284; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13285; GFX11-NEXT:    s_cbranch_vccnz .LBB31_43286; GFX11-NEXT:  .LBB31_2: ; %cmp.true3287; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]3288; GFX11-NEXT:    s_setpc_b64 s[30:31]3289; GFX11-NEXT:  .LBB31_3:3290; GFX11-NEXT:    s_branch .LBB31_23291; GFX11-NEXT:  .LBB31_4:3292; GFX11-NEXT:    v_mov_b32_e32 v0, s03293; GFX11-NEXT:    s_setpc_b64 s[30:31]3294  %cmp = icmp eq i32 %b, 03295  br i1 %cmp, label %cmp.true, label %cmp.false3296 3297cmp.true:3298  %a1 = fadd <2 x half> %a, splat (half 0xH0200)3299  %a2 = bitcast <2 x half> %a1 to float3300  br label %end3301 3302cmp.false:3303  %a3 = bitcast <2 x half> %a to float3304  br label %end3305 3306end:3307  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]3308  ret float %phi3309}3310 3311define <2 x bfloat> @bitcast_f32_to_v2bf16(float %a, i32 %b) {3312; SI-LABEL: bitcast_f32_to_v2bf16:3313; SI:       ; %bb.0:3314; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3315; SI-NEXT:    v_mov_b32_e32 v2, v03316; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13317; SI-NEXT:    ; implicit-def: $vgpr03318; SI-NEXT:    ; implicit-def: $vgpr13319; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3320; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3321; SI-NEXT:    s_cbranch_execnz .LBB32_33322; SI-NEXT:  ; %bb.1: ; %Flow3323; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3324; SI-NEXT:    s_cbranch_execnz .LBB32_43325; SI-NEXT:  .LBB32_2: ; %end3326; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3327; SI-NEXT:    s_setpc_b64 s[30:31]3328; SI-NEXT:  .LBB32_3: ; %cmp.false3329; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v23330; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v23331; SI-NEXT:    ; implicit-def: $vgpr23332; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3333; SI-NEXT:    s_cbranch_execz .LBB32_23334; SI-NEXT:  .LBB32_4: ; %cmp.true3335; SI-NEXT:    v_add_f32_e32 v0, 1.0, v23336; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v03337; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v03338; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3339; SI-NEXT:    s_setpc_b64 s[30:31]3340;3341; VI-LABEL: bitcast_f32_to_v2bf16:3342; VI:       ; %bb.0:3343; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3344; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13345; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3346; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3347; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3348; VI-NEXT:  ; %bb.1: ; %cmp.true3349; VI-NEXT:    v_add_f32_e32 v0, 1.0, v03350; VI-NEXT:  ; %bb.2: ; %end3351; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3352; VI-NEXT:    s_setpc_b64 s[30:31]3353;3354; GFX9-LABEL: bitcast_f32_to_v2bf16:3355; GFX9:       ; %bb.0:3356; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3357; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13358; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3359; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3360; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3361; GFX9-NEXT:  ; %bb.1: ; %cmp.true3362; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v03363; GFX9-NEXT:  ; %bb.2: ; %end3364; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3365; GFX9-NEXT:    s_setpc_b64 s[30:31]3366;3367; GFX11-LABEL: bitcast_f32_to_v2bf16:3368; GFX11:       ; %bb.0:3369; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3370; GFX11-NEXT:    s_mov_b32 s0, exec_lo3371; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v13372; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03373; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3374; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03375; GFX11-NEXT:  ; %bb.1: ; %cmp.true3376; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v03377; GFX11-NEXT:  ; %bb.2: ; %end3378; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03379; GFX11-NEXT:    s_setpc_b64 s[30:31]3380  %cmp = icmp eq i32 %b, 03381  br i1 %cmp, label %cmp.true, label %cmp.false3382 3383cmp.true:3384  %a1 = fadd float %a, 1.000000e+003385  %a2 = bitcast float %a1 to <2 x bfloat>3386  br label %end3387 3388cmp.false:3389  %a3 = bitcast float %a to <2 x bfloat>3390  br label %end3391 3392end:3393  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3394  ret <2 x bfloat> %phi3395}3396 3397define inreg <2 x bfloat> @bitcast_f32_to_v2bf16_scalar(float inreg %a, i32 inreg %b) {3398; SI-LABEL: bitcast_f32_to_v2bf16_scalar:3399; SI:       ; %bb.0:3400; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3401; SI-NEXT:    s_cmp_lg_u32 s17, 03402; SI-NEXT:    s_cbranch_scc0 .LBB33_33403; SI-NEXT:  ; %bb.1: ; %cmp.false3404; SI-NEXT:    s_and_b32 s6, s16, 0xffff00003405; SI-NEXT:    s_lshl_b32 s7, s16, 163406; SI-NEXT:    s_cbranch_execnz .LBB33_43407; SI-NEXT:  .LBB33_2: ; %cmp.true3408; SI-NEXT:    v_add_f32_e64 v0, s16, 1.03409; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v03410; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v03411; SI-NEXT:    s_setpc_b64 s[30:31]3412; SI-NEXT:  .LBB33_3:3413; SI-NEXT:    ; implicit-def: $sgpr73414; SI-NEXT:    ; implicit-def: $sgpr63415; SI-NEXT:    s_branch .LBB33_23416; SI-NEXT:  .LBB33_4:3417; SI-NEXT:    v_mov_b32_e32 v0, s73418; SI-NEXT:    v_mov_b32_e32 v1, s63419; SI-NEXT:    s_setpc_b64 s[30:31]3420;3421; VI-LABEL: bitcast_f32_to_v2bf16_scalar:3422; VI:       ; %bb.0:3423; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3424; VI-NEXT:    s_cmp_lg_u32 s17, 03425; VI-NEXT:    s_cbranch_scc0 .LBB33_33426; VI-NEXT:  ; %bb.1: ; %cmp.false3427; VI-NEXT:    s_cbranch_execnz .LBB33_43428; VI-NEXT:  .LBB33_2: ; %cmp.true3429; VI-NEXT:    v_add_f32_e64 v0, s16, 1.03430; VI-NEXT:    s_setpc_b64 s[30:31]3431; VI-NEXT:  .LBB33_3:3432; VI-NEXT:    s_branch .LBB33_23433; VI-NEXT:  .LBB33_4:3434; VI-NEXT:    v_mov_b32_e32 v0, s163435; VI-NEXT:    s_setpc_b64 s[30:31]3436;3437; GFX9-LABEL: bitcast_f32_to_v2bf16_scalar:3438; GFX9:       ; %bb.0:3439; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3440; GFX9-NEXT:    s_cmp_lg_u32 s17, 03441; GFX9-NEXT:    s_cbranch_scc0 .LBB33_33442; GFX9-NEXT:  ; %bb.1: ; %cmp.false3443; GFX9-NEXT:    s_cbranch_execnz .LBB33_43444; GFX9-NEXT:  .LBB33_2: ; %cmp.true3445; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.03446; GFX9-NEXT:    s_setpc_b64 s[30:31]3447; GFX9-NEXT:  .LBB33_3:3448; GFX9-NEXT:    s_branch .LBB33_23449; GFX9-NEXT:  .LBB33_4:3450; GFX9-NEXT:    v_mov_b32_e32 v0, s163451; GFX9-NEXT:    s_setpc_b64 s[30:31]3452;3453; GFX11-LABEL: bitcast_f32_to_v2bf16_scalar:3454; GFX11:       ; %bb.0:3455; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3456; GFX11-NEXT:    s_cmp_lg_u32 s1, 03457; GFX11-NEXT:    s_mov_b32 s1, 03458; GFX11-NEXT:    s_cbranch_scc0 .LBB33_33459; GFX11-NEXT:  ; %bb.1: ; %Flow3460; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13461; GFX11-NEXT:    s_cbranch_vccnz .LBB33_43462; GFX11-NEXT:  .LBB33_2: ; %cmp.true3463; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.03464; GFX11-NEXT:    s_setpc_b64 s[30:31]3465; GFX11-NEXT:  .LBB33_3:3466; GFX11-NEXT:    s_branch .LBB33_23467; GFX11-NEXT:  .LBB33_4:3468; GFX11-NEXT:    v_mov_b32_e32 v0, s03469; GFX11-NEXT:    s_setpc_b64 s[30:31]3470  %cmp = icmp eq i32 %b, 03471  br i1 %cmp, label %cmp.true, label %cmp.false3472 3473cmp.true:3474  %a1 = fadd float %a, 1.000000e+003475  %a2 = bitcast float %a1 to <2 x bfloat>3476  br label %end3477 3478cmp.false:3479  %a3 = bitcast float %a to <2 x bfloat>3480  br label %end3481 3482end:3483  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3484  ret <2 x bfloat> %phi3485}3486 3487define float @bitcast_v2bf16_to_f32(<2 x bfloat> %a, i32 %b) {3488; SI-LABEL: bitcast_v2bf16_to_f32:3489; SI:       ; %bb.0:3490; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3491; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v23492; SI-NEXT:    v_mul_f32_e32 v1, 1.0, v13493; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v03494; SI-NEXT:    ; implicit-def: $vgpr03495; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3496; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3497; SI-NEXT:    s_cbranch_execnz .LBB34_33498; SI-NEXT:  ; %bb.1: ; %Flow3499; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3500; SI-NEXT:    s_cbranch_execnz .LBB34_43501; SI-NEXT:  .LBB34_2: ; %end3502; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3503; SI-NEXT:    s_setpc_b64 s[30:31]3504; SI-NEXT:  .LBB34_3: ; %cmp.false3505; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v13506; SI-NEXT:    v_alignbit_b32 v0, v0, v2, 163507; SI-NEXT:    ; implicit-def: $vgpr23508; SI-NEXT:    ; implicit-def: $vgpr13509; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3510; SI-NEXT:    s_cbranch_execz .LBB34_23511; SI-NEXT:  .LBB34_4: ; %cmp.true3512; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v13513; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v23514; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v13515; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v03516; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13517; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 163518; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3519; SI-NEXT:    s_setpc_b64 s[30:31]3520;3521; VI-LABEL: bitcast_v2bf16_to_f32:3522; VI:       ; %bb.0:3523; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3524; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13525; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3526; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3527; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3528; VI-NEXT:    s_cbranch_execz .LBB34_23529; VI-NEXT:  ; %bb.1: ; %cmp.true3530; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v03531; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v13532; VI-NEXT:    v_bfe_u32 v2, v1, 16, 13533; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v13534; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v23535; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03536; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v13537; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v13538; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v03539; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc3540; VI-NEXT:    v_bfe_u32 v2, v0, 16, 13541; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v03542; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v23543; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v03544; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v03545; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc3546; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v03547; VI-NEXT:    v_alignbit_b32 v0, v0, v1, 163548; VI-NEXT:  .LBB34_2: ; %end3549; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3550; VI-NEXT:    s_setpc_b64 s[30:31]3551;3552; GFX9-LABEL: bitcast_v2bf16_to_f32:3553; GFX9:       ; %bb.0:3554; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3555; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13556; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3557; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3558; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3559; GFX9-NEXT:    s_cbranch_execz .LBB34_23560; GFX9-NEXT:  ; %bb.1: ; %cmp.true3561; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v03562; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v13563; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 13564; GFX9-NEXT:    s_movk_i32 s6, 0x7fff3565; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03566; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s63567; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v13568; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v13569; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v03570; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc3571; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 13572; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s63573; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v03574; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v03575; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc3576; GFX9-NEXT:    s_mov_b32 s6, 0x70603023577; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s63578; GFX9-NEXT:  .LBB34_2: ; %end3579; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3580; GFX9-NEXT:    s_setpc_b64 s[30:31]3581;3582; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_f32:3583; GFX11-TRUE16:       ; %bb.0:3584; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3585; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v13586; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr13587; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo3588; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3589; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s03590; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false3591; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v03592; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr03593; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow3594; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s03595; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB34_43596; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true3597; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v03598; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03599; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3600; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v03601; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 13602; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3603; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 13604; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v13605; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v13606; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v03607; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff3608; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff3609; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)3610; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo3611; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v03612; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo3613; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)3614; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h3615; GFX11-TRUE16-NEXT:  .LBB34_4: ; %end3616; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03617; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3618; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v13619; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3620;3621; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_f32:3622; GFX11-FAKE16:       ; %bb.0:3623; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3624; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo3625; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v13626; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s03627; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3628; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s03629; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB34_23630; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true3631; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v03632; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v03633; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3634; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v03635; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 13636; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)3637; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 13638; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v13639; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v13640; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v03641; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff3642; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff3643; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)3644; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo3645; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v03646; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo3647; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)3648; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x70603023649; GFX11-FAKE16-NEXT:  .LBB34_2: ; %end3650; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s03651; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3652  %cmp = icmp eq i32 %b, 03653  br i1 %cmp, label %cmp.true, label %cmp.false3654 3655cmp.true:3656  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)3657  %a2 = bitcast <2 x bfloat> %a1 to float3658  br label %end3659 3660cmp.false:3661  %a3 = bitcast <2 x bfloat> %a to float3662  br label %end3663 3664end:3665  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]3666  ret float %phi3667}3668 3669define inreg float @bitcast_v2bf16_to_f32_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {3670; SI-LABEL: bitcast_v2bf16_to_f32_scalar:3671; SI:       ; %bb.0:3672; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3673; SI-NEXT:    s_cmp_lg_u32 s18, 03674; SI-NEXT:    v_mul_f32_e64 v4, 1.0, s173675; SI-NEXT:    v_mul_f32_e64 v2, 1.0, s163676; SI-NEXT:    s_cbranch_scc0 .LBB35_43677; SI-NEXT:  ; %bb.1: ; %cmp.false3678; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v43679; SI-NEXT:    v_lshr_b64 v[0:1], v[2:3], 163680; SI-NEXT:    s_cbranch_execnz .LBB35_33681; SI-NEXT:  .LBB35_2: ; %cmp.true3682; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v43683; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v23684; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v13685; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v03686; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13687; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 163688; SI-NEXT:  .LBB35_3: ; %end3689; SI-NEXT:    s_setpc_b64 s[30:31]3690; SI-NEXT:  .LBB35_4:3691; SI-NEXT:    ; implicit-def: $vgpr03692; SI-NEXT:    s_branch .LBB35_23693;3694; VI-LABEL: bitcast_v2bf16_to_f32_scalar:3695; VI:       ; %bb.0:3696; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3697; VI-NEXT:    s_cmp_lg_u32 s17, 03698; VI-NEXT:    s_cbranch_scc0 .LBB35_33699; VI-NEXT:  ; %bb.1: ; %cmp.false3700; VI-NEXT:    s_cbranch_execnz .LBB35_43701; VI-NEXT:  .LBB35_2: ; %cmp.true3702; VI-NEXT:    s_lshl_b32 s4, s16, 163703; VI-NEXT:    v_mov_b32_e32 v1, 0x40c000003704; VI-NEXT:    v_add_f32_e32 v0, s4, v13705; VI-NEXT:    v_bfe_u32 v2, v0, 16, 13706; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v03707; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v23708; VI-NEXT:    s_and_b32 s4, s16, 0xffff00003709; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v03710; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v03711; VI-NEXT:    v_add_f32_e32 v1, s4, v13712; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc3713; VI-NEXT:    v_bfe_u32 v2, v1, 16, 13714; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v13715; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v23716; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v13717; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v13718; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc3719; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v13720; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]3721; VI-NEXT:    s_setpc_b64 s[30:31]3722; VI-NEXT:  .LBB35_3:3723; VI-NEXT:    s_branch .LBB35_23724; VI-NEXT:  .LBB35_4:3725; VI-NEXT:    v_mov_b32_e32 v0, s163726; VI-NEXT:    s_setpc_b64 s[30:31]3727;3728; GFX9-LABEL: bitcast_v2bf16_to_f32_scalar:3729; GFX9:       ; %bb.0:3730; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3731; GFX9-NEXT:    s_cmp_lg_u32 s17, 03732; GFX9-NEXT:    s_cbranch_scc0 .LBB35_33733; GFX9-NEXT:  ; %bb.1: ; %cmp.false3734; GFX9-NEXT:    s_cbranch_execnz .LBB35_43735; GFX9-NEXT:  .LBB35_2: ; %cmp.true3736; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00003737; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000003738; GFX9-NEXT:    v_add_f32_e32 v1, s4, v03739; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 13740; GFX9-NEXT:    v_add_u32_e32 v2, v2, v13741; GFX9-NEXT:    s_lshl_b32 s4, s16, 163742; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v23743; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v13744; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v13745; GFX9-NEXT:    v_add_f32_e32 v0, s4, v03746; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc3747; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 13748; GFX9-NEXT:    v_add_u32_e32 v2, v2, v03749; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v23750; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v03751; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v03752; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc3753; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff3754; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v13755; GFX9-NEXT:    v_and_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_13756; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v03757; GFX9-NEXT:    s_setpc_b64 s[30:31]3758; GFX9-NEXT:  .LBB35_3:3759; GFX9-NEXT:    s_branch .LBB35_23760; GFX9-NEXT:  .LBB35_4:3761; GFX9-NEXT:    v_mov_b32_e32 v0, s163762; GFX9-NEXT:    s_setpc_b64 s[30:31]3763;3764; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_f32_scalar:3765; GFX11-TRUE16:       ; %bb.0:3766; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3767; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 03768; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 03769; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB35_33770; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow3771; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13772; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB35_43773; GFX11-TRUE16-NEXT:  .LBB35_2: ; %cmp.true3774; GFX11-TRUE16-NEXT:    s_and_b32 s1, s0, 0xffff00003775; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 163776; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s13777; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s03778; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3779; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 13780; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 13781; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v03782; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v03783; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v13784; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)3785; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v13786; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v33787; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v03788; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3789; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v23790; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo3791; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v13792; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)3793; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v03794; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo3795; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v13796; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)3797; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l3798; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3799; GFX11-TRUE16-NEXT:  .LBB35_3:3800; GFX11-TRUE16-NEXT:    s_branch .LBB35_23801; GFX11-TRUE16-NEXT:  .LBB35_4:3802; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s03803; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]3804;3805; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_f32_scalar:3806; GFX11-FAKE16:       ; %bb.0:3807; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3808; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 03809; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 03810; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB35_33811; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow3812; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13813; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB35_43814; GFX11-FAKE16-NEXT:  .LBB35_2: ; %cmp.true3815; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 163816; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00003817; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s13818; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s03819; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)3820; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 13821; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 13822; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v03823; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v03824; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v13825; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)3826; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v13827; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v33828; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v03829; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3830; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v23831; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo3832; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v13833; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)3834; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v03835; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_and_b32 v0, 0xffff, v03836; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)3837; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v13838; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v03839; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3840; GFX11-FAKE16-NEXT:  .LBB35_3:3841; GFX11-FAKE16-NEXT:    s_branch .LBB35_23842; GFX11-FAKE16-NEXT:  .LBB35_4:3843; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s03844; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]3845  %cmp = icmp eq i32 %b, 03846  br i1 %cmp, label %cmp.true, label %cmp.false3847 3848cmp.true:3849  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)3850  %a2 = bitcast <2 x bfloat> %a1 to float3851  br label %end3852 3853cmp.false:3854  %a3 = bitcast <2 x bfloat> %a to float3855  br label %end3856 3857end:3858  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]3859  ret float %phi3860}3861 3862define <1 x i32> @bitcast_f32_to_v1i32(float %a, i32 %b) {3863; SI-LABEL: bitcast_f32_to_v1i32:3864; SI:       ; %bb.0:3865; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3866; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13867; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3868; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3869; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3870; SI-NEXT:  ; %bb.1: ; %cmp.true3871; SI-NEXT:    v_add_f32_e32 v0, 1.0, v03872; SI-NEXT:  ; %bb.2: ; %end3873; SI-NEXT:    s_or_b64 exec, exec, s[4:5]3874; SI-NEXT:    s_setpc_b64 s[30:31]3875;3876; VI-LABEL: bitcast_f32_to_v1i32:3877; VI:       ; %bb.0:3878; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3879; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13880; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc3881; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3882; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3883; VI-NEXT:  ; %bb.1: ; %cmp.true3884; VI-NEXT:    v_add_f32_e32 v0, 1.0, v03885; VI-NEXT:  ; %bb.2: ; %end3886; VI-NEXT:    s_or_b64 exec, exec, s[4:5]3887; VI-NEXT:    s_setpc_b64 s[30:31]3888;3889; GFX9-LABEL: bitcast_f32_to_v1i32:3890; GFX9:       ; %bb.0:3891; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3892; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v13893; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc3894; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]3895; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]3896; GFX9-NEXT:  ; %bb.1: ; %cmp.true3897; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v03898; GFX9-NEXT:  ; %bb.2: ; %end3899; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]3900; GFX9-NEXT:    s_setpc_b64 s[30:31]3901;3902; GFX11-LABEL: bitcast_f32_to_v1i32:3903; GFX11:       ; %bb.0:3904; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3905; GFX11-NEXT:    s_mov_b32 s0, exec_lo3906; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v13907; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s03908; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)3909; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s03910; GFX11-NEXT:  ; %bb.1: ; %cmp.true3911; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v03912; GFX11-NEXT:  ; %bb.2: ; %end3913; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s03914; GFX11-NEXT:    s_setpc_b64 s[30:31]3915  %cmp = icmp eq i32 %b, 03916  br i1 %cmp, label %cmp.true, label %cmp.false3917 3918cmp.true:3919  %a1 = fadd float %a, 1.000000e+003920  %a2 = bitcast float %a1 to <1 x i32>3921  br label %end3922 3923cmp.false:3924  %a3 = bitcast float %a to <1 x i32>3925  br label %end3926 3927end:3928  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]3929  ret <1 x i32> %phi3930}3931 3932define inreg <1 x i32> @bitcast_f32_to_v1i32_scalar(float inreg %a, i32 inreg %b) {3933; SI-LABEL: bitcast_f32_to_v1i32_scalar:3934; SI:       ; %bb.0:3935; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3936; SI-NEXT:    s_cmp_lg_u32 s17, 03937; SI-NEXT:    s_cbranch_scc0 .LBB37_33938; SI-NEXT:  ; %bb.1: ; %cmp.false3939; SI-NEXT:    s_cbranch_execnz .LBB37_43940; SI-NEXT:  .LBB37_2: ; %cmp.true3941; SI-NEXT:    v_add_f32_e64 v0, s16, 1.03942; SI-NEXT:    s_setpc_b64 s[30:31]3943; SI-NEXT:  .LBB37_3:3944; SI-NEXT:    s_branch .LBB37_23945; SI-NEXT:  .LBB37_4:3946; SI-NEXT:    v_mov_b32_e32 v0, s163947; SI-NEXT:    s_setpc_b64 s[30:31]3948;3949; VI-LABEL: bitcast_f32_to_v1i32_scalar:3950; VI:       ; %bb.0:3951; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3952; VI-NEXT:    s_cmp_lg_u32 s17, 03953; VI-NEXT:    s_cbranch_scc0 .LBB37_33954; VI-NEXT:  ; %bb.1: ; %cmp.false3955; VI-NEXT:    s_cbranch_execnz .LBB37_43956; VI-NEXT:  .LBB37_2: ; %cmp.true3957; VI-NEXT:    v_add_f32_e64 v0, s16, 1.03958; VI-NEXT:    s_setpc_b64 s[30:31]3959; VI-NEXT:  .LBB37_3:3960; VI-NEXT:    s_branch .LBB37_23961; VI-NEXT:  .LBB37_4:3962; VI-NEXT:    v_mov_b32_e32 v0, s163963; VI-NEXT:    s_setpc_b64 s[30:31]3964;3965; GFX9-LABEL: bitcast_f32_to_v1i32_scalar:3966; GFX9:       ; %bb.0:3967; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3968; GFX9-NEXT:    s_cmp_lg_u32 s17, 03969; GFX9-NEXT:    s_cbranch_scc0 .LBB37_33970; GFX9-NEXT:  ; %bb.1: ; %cmp.false3971; GFX9-NEXT:    s_cbranch_execnz .LBB37_43972; GFX9-NEXT:  .LBB37_2: ; %cmp.true3973; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.03974; GFX9-NEXT:    s_setpc_b64 s[30:31]3975; GFX9-NEXT:  .LBB37_3:3976; GFX9-NEXT:    s_branch .LBB37_23977; GFX9-NEXT:  .LBB37_4:3978; GFX9-NEXT:    v_mov_b32_e32 v0, s163979; GFX9-NEXT:    s_setpc_b64 s[30:31]3980;3981; GFX11-LABEL: bitcast_f32_to_v1i32_scalar:3982; GFX11:       ; %bb.0:3983; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)3984; GFX11-NEXT:    s_cmp_lg_u32 s1, 03985; GFX11-NEXT:    s_mov_b32 s1, 03986; GFX11-NEXT:    s_cbranch_scc0 .LBB37_33987; GFX11-NEXT:  ; %bb.1: ; %Flow3988; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s13989; GFX11-NEXT:    s_cbranch_vccnz .LBB37_43990; GFX11-NEXT:  .LBB37_2: ; %cmp.true3991; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.03992; GFX11-NEXT:    s_setpc_b64 s[30:31]3993; GFX11-NEXT:  .LBB37_3:3994; GFX11-NEXT:    s_branch .LBB37_23995; GFX11-NEXT:  .LBB37_4:3996; GFX11-NEXT:    v_mov_b32_e32 v0, s03997; GFX11-NEXT:    s_setpc_b64 s[30:31]3998  %cmp = icmp eq i32 %b, 03999  br i1 %cmp, label %cmp.true, label %cmp.false4000 4001cmp.true:4002  %a1 = fadd float %a, 1.000000e+004003  %a2 = bitcast float %a1 to <1 x i32>4004  br label %end4005 4006cmp.false:4007  %a3 = bitcast float %a to <1 x i32>4008  br label %end4009 4010end:4011  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4012  ret <1 x i32> %phi4013}4014 4015define float @bitcast_v1i32_to_f32(<1 x i32> %a, i32 %b) {4016; SI-LABEL: bitcast_v1i32_to_f32:4017; SI:       ; %bb.0:4018; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4019; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14020; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4021; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4022; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4023; SI-NEXT:  ; %bb.1: ; %cmp.true4024; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v04025; SI-NEXT:  ; %bb.2: ; %end4026; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4027; SI-NEXT:    s_setpc_b64 s[30:31]4028;4029; VI-LABEL: bitcast_v1i32_to_f32:4030; VI:       ; %bb.0:4031; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4032; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14033; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4034; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4035; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4036; VI-NEXT:  ; %bb.1: ; %cmp.true4037; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v04038; VI-NEXT:  ; %bb.2: ; %end4039; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4040; VI-NEXT:    s_setpc_b64 s[30:31]4041;4042; GFX9-LABEL: bitcast_v1i32_to_f32:4043; GFX9:       ; %bb.0:4044; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4045; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14046; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4047; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4048; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4049; GFX9-NEXT:  ; %bb.1: ; %cmp.true4050; GFX9-NEXT:    v_add_u32_e32 v0, 3, v04051; GFX9-NEXT:  ; %bb.2: ; %end4052; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4053; GFX9-NEXT:    s_setpc_b64 s[30:31]4054;4055; GFX11-LABEL: bitcast_v1i32_to_f32:4056; GFX11:       ; %bb.0:4057; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4058; GFX11-NEXT:    s_mov_b32 s0, exec_lo4059; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v14060; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04061; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4062; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04063; GFX11-NEXT:  ; %bb.1: ; %cmp.true4064; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v04065; GFX11-NEXT:  ; %bb.2: ; %end4066; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04067; GFX11-NEXT:    s_setpc_b64 s[30:31]4068  %cmp = icmp eq i32 %b, 04069  br i1 %cmp, label %cmp.true, label %cmp.false4070 4071cmp.true:4072  %a1 = add <1 x i32> %a, splat (i32 3)4073  %a2 = bitcast <1 x i32> %a1 to float4074  br label %end4075 4076cmp.false:4077  %a3 = bitcast <1 x i32> %a to float4078  br label %end4079 4080end:4081  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]4082  ret float %phi4083}4084 4085define inreg float @bitcast_v1i32_to_f32_scalar(<1 x i32> inreg %a, i32 inreg %b) {4086; SI-LABEL: bitcast_v1i32_to_f32_scalar:4087; SI:       ; %bb.0:4088; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4089; SI-NEXT:    s_cmp_lg_u32 s17, 04090; SI-NEXT:    s_cbranch_scc0 .LBB39_44091; SI-NEXT:  ; %bb.1: ; %cmp.false4092; SI-NEXT:    s_cbranch_execnz .LBB39_34093; SI-NEXT:  .LBB39_2: ; %cmp.true4094; SI-NEXT:    s_add_i32 s16, s16, 34095; SI-NEXT:  .LBB39_3: ; %end4096; SI-NEXT:    v_mov_b32_e32 v0, s164097; SI-NEXT:    s_setpc_b64 s[30:31]4098; SI-NEXT:  .LBB39_4:4099; SI-NEXT:    s_branch .LBB39_24100;4101; VI-LABEL: bitcast_v1i32_to_f32_scalar:4102; VI:       ; %bb.0:4103; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4104; VI-NEXT:    s_cmp_lg_u32 s17, 04105; VI-NEXT:    s_cbranch_scc0 .LBB39_44106; VI-NEXT:  ; %bb.1: ; %cmp.false4107; VI-NEXT:    s_cbranch_execnz .LBB39_34108; VI-NEXT:  .LBB39_2: ; %cmp.true4109; VI-NEXT:    s_add_i32 s16, s16, 34110; VI-NEXT:  .LBB39_3: ; %end4111; VI-NEXT:    v_mov_b32_e32 v0, s164112; VI-NEXT:    s_setpc_b64 s[30:31]4113; VI-NEXT:  .LBB39_4:4114; VI-NEXT:    s_branch .LBB39_24115;4116; GFX9-LABEL: bitcast_v1i32_to_f32_scalar:4117; GFX9:       ; %bb.0:4118; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4119; GFX9-NEXT:    s_cmp_lg_u32 s17, 04120; GFX9-NEXT:    s_cbranch_scc0 .LBB39_44121; GFX9-NEXT:  ; %bb.1: ; %cmp.false4122; GFX9-NEXT:    s_cbranch_execnz .LBB39_34123; GFX9-NEXT:  .LBB39_2: ; %cmp.true4124; GFX9-NEXT:    s_add_i32 s16, s16, 34125; GFX9-NEXT:  .LBB39_3: ; %end4126; GFX9-NEXT:    v_mov_b32_e32 v0, s164127; GFX9-NEXT:    s_setpc_b64 s[30:31]4128; GFX9-NEXT:  .LBB39_4:4129; GFX9-NEXT:    s_branch .LBB39_24130;4131; GFX11-LABEL: bitcast_v1i32_to_f32_scalar:4132; GFX11:       ; %bb.0:4133; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4134; GFX11-NEXT:    s_cmp_lg_u32 s1, 04135; GFX11-NEXT:    s_mov_b32 s1, 04136; GFX11-NEXT:    s_cbranch_scc0 .LBB39_34137; GFX11-NEXT:  ; %bb.1: ; %Flow4138; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s14139; GFX11-NEXT:    s_cbranch_vccz .LBB39_44140; GFX11-NEXT:  ; %bb.2: ; %end4141; GFX11-NEXT:    v_mov_b32_e32 v0, s04142; GFX11-NEXT:    s_setpc_b64 s[30:31]4143; GFX11-NEXT:  .LBB39_3:4144; GFX11-NEXT:  .LBB39_4: ; %cmp.true4145; GFX11-NEXT:    s_add_i32 s0, s0, 34146; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4147; GFX11-NEXT:    v_mov_b32_e32 v0, s04148; GFX11-NEXT:    s_setpc_b64 s[30:31]4149  %cmp = icmp eq i32 %b, 04150  br i1 %cmp, label %cmp.true, label %cmp.false4151 4152cmp.true:4153  %a1 = add <1 x i32> %a, splat (i32 3)4154  %a2 = bitcast <1 x i32> %a1 to float4155  br label %end4156 4157cmp.false:4158  %a3 = bitcast <1 x i32> %a to float4159  br label %end4160 4161end:4162  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]4163  ret float %phi4164}4165 4166define <4 x i8> @bitcast_f32_to_v4i8(float %a, i32 %b) {4167; SI-LABEL: bitcast_f32_to_v4i8:4168; SI:       ; %bb.0:4169; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4170; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14171; SI-NEXT:    ; implicit-def: $vgpr14172; SI-NEXT:    ; implicit-def: $vgpr24173; SI-NEXT:    ; implicit-def: $vgpr34174; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4175; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4176; SI-NEXT:    s_cbranch_execnz .LBB40_34177; SI-NEXT:  ; %bb.1: ; %Flow4178; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4179; SI-NEXT:    s_cbranch_execnz .LBB40_44180; SI-NEXT:  .LBB40_2: ; %end4181; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4182; SI-NEXT:    s_setpc_b64 s[30:31]4183; SI-NEXT:  .LBB40_3: ; %cmp.false4184; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04185; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04186; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04187; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4188; SI-NEXT:    s_cbranch_execz .LBB40_24189; SI-NEXT:  .LBB40_4: ; %cmp.true4190; SI-NEXT:    v_add_f32_e32 v0, 1.0, v04191; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04192; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04193; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04194; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4195; SI-NEXT:    s_setpc_b64 s[30:31]4196;4197; VI-LABEL: bitcast_f32_to_v4i8:4198; VI:       ; %bb.0:4199; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4200; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14201; VI-NEXT:    ; implicit-def: $vgpr14202; VI-NEXT:    ; implicit-def: $vgpr24203; VI-NEXT:    ; implicit-def: $vgpr34204; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4205; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4206; VI-NEXT:    s_cbranch_execnz .LBB40_34207; VI-NEXT:  ; %bb.1: ; %Flow4208; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4209; VI-NEXT:    s_cbranch_execnz .LBB40_44210; VI-NEXT:  .LBB40_2: ; %end4211; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4212; VI-NEXT:    s_setpc_b64 s[30:31]4213; VI-NEXT:  .LBB40_3: ; %cmp.false4214; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04215; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04216; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04217; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4218; VI-NEXT:    s_cbranch_execz .LBB40_24219; VI-NEXT:  .LBB40_4: ; %cmp.true4220; VI-NEXT:    v_add_f32_e32 v0, 1.0, v04221; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04222; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04223; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04224; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4225; VI-NEXT:    s_setpc_b64 s[30:31]4226;4227; GFX9-LABEL: bitcast_f32_to_v4i8:4228; GFX9:       ; %bb.0:4229; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4230; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14231; GFX9-NEXT:    ; implicit-def: $vgpr14232; GFX9-NEXT:    ; implicit-def: $vgpr24233; GFX9-NEXT:    ; implicit-def: $vgpr34234; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4235; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4236; GFX9-NEXT:    s_cbranch_execnz .LBB40_34237; GFX9-NEXT:  ; %bb.1: ; %Flow4238; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4239; GFX9-NEXT:    s_cbranch_execnz .LBB40_44240; GFX9-NEXT:  .LBB40_2: ; %end4241; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4242; GFX9-NEXT:    s_setpc_b64 s[30:31]4243; GFX9-NEXT:  .LBB40_3: ; %cmp.false4244; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v04245; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v04246; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v04247; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4248; GFX9-NEXT:    s_cbranch_execz .LBB40_24249; GFX9-NEXT:  .LBB40_4: ; %cmp.true4250; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v04251; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v04252; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v04253; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v04254; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4255; GFX9-NEXT:    s_setpc_b64 s[30:31]4256;4257; GFX11-TRUE16-LABEL: bitcast_f32_to_v4i8:4258; GFX11-TRUE16:       ; %bb.0:4259; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4260; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v04261; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v14262; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo164263; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo164264; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo4265; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4266; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s04267; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false4268; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)4269; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v24270; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v24271; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow4272; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s04273; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true4274; GFX11-TRUE16-NEXT:    v_add_f32_e32 v2, 1.0, v24275; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4276; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v24277; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v24278; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end4279; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04280; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l4281; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h4282; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]4283;4284; GFX11-FAKE16-LABEL: bitcast_f32_to_v4i8:4285; GFX11-FAKE16:       ; %bb.0:4286; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4287; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v14288; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14289; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24290; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34291; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo4292; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4293; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s04294; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB40_34295; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow4296; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s04297; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB40_44298; GFX11-FAKE16-NEXT:  .LBB40_2: ; %end4299; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04300; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]4301; GFX11-FAKE16-NEXT:  .LBB40_3: ; %cmp.false4302; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v04303; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v04304; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v04305; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s04306; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB40_24307; GFX11-FAKE16-NEXT:  .LBB40_4: ; %cmp.true4308; GFX11-FAKE16-NEXT:    v_add_f32_e32 v0, 1.0, v04309; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4310; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v04311; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v04312; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v04313; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04314; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]4315  %cmp = icmp eq i32 %b, 04316  br i1 %cmp, label %cmp.true, label %cmp.false4317 4318cmp.true:4319  %a1 = fadd float %a, 1.000000e+004320  %a2 = bitcast float %a1 to <4 x i8>4321  br label %end4322 4323cmp.false:4324  %a3 = bitcast float %a to <4 x i8>4325  br label %end4326 4327end:4328  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4329  ret <4 x i8> %phi4330}4331 4332define inreg <4 x i8> @bitcast_f32_to_v4i8_scalar(float inreg %a, i32 inreg %b) {4333; SI-LABEL: bitcast_f32_to_v4i8_scalar:4334; SI:       ; %bb.0:4335; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4336; SI-NEXT:    s_cmp_lg_u32 s17, 04337; SI-NEXT:    s_cbranch_scc0 .LBB41_34338; SI-NEXT:  ; %bb.1: ; %cmp.false4339; SI-NEXT:    s_lshr_b32 s7, s16, 244340; SI-NEXT:    s_lshr_b32 s6, s16, 164341; SI-NEXT:    s_lshr_b32 s8, s16, 84342; SI-NEXT:    s_cbranch_execnz .LBB41_44343; SI-NEXT:  .LBB41_2: ; %cmp.true4344; SI-NEXT:    v_add_f32_e64 v0, s16, 1.04345; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04346; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04347; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04348; SI-NEXT:    s_setpc_b64 s[30:31]4349; SI-NEXT:  .LBB41_3:4350; SI-NEXT:    ; implicit-def: $sgpr84351; SI-NEXT:    ; implicit-def: $sgpr64352; SI-NEXT:    ; implicit-def: $sgpr74353; SI-NEXT:    s_branch .LBB41_24354; SI-NEXT:  .LBB41_4:4355; SI-NEXT:    v_mov_b32_e32 v0, s164356; SI-NEXT:    v_mov_b32_e32 v1, s84357; SI-NEXT:    v_mov_b32_e32 v3, s74358; SI-NEXT:    v_mov_b32_e32 v2, s64359; SI-NEXT:    s_setpc_b64 s[30:31]4360;4361; VI-LABEL: bitcast_f32_to_v4i8_scalar:4362; VI:       ; %bb.0:4363; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4364; VI-NEXT:    s_cmp_lg_u32 s17, 04365; VI-NEXT:    s_cbranch_scc0 .LBB41_34366; VI-NEXT:  ; %bb.1: ; %cmp.false4367; VI-NEXT:    s_lshr_b32 s7, s16, 244368; VI-NEXT:    s_lshr_b32 s6, s16, 164369; VI-NEXT:    s_lshr_b32 s8, s16, 84370; VI-NEXT:    s_cbranch_execnz .LBB41_44371; VI-NEXT:  .LBB41_2: ; %cmp.true4372; VI-NEXT:    v_add_f32_e64 v0, s16, 1.04373; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v04374; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v04375; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v04376; VI-NEXT:    s_setpc_b64 s[30:31]4377; VI-NEXT:  .LBB41_3:4378; VI-NEXT:    ; implicit-def: $sgpr84379; VI-NEXT:    ; implicit-def: $sgpr64380; VI-NEXT:    ; implicit-def: $sgpr74381; VI-NEXT:    s_branch .LBB41_24382; VI-NEXT:  .LBB41_4:4383; VI-NEXT:    v_mov_b32_e32 v0, s164384; VI-NEXT:    v_mov_b32_e32 v1, s84385; VI-NEXT:    v_mov_b32_e32 v3, s74386; VI-NEXT:    v_mov_b32_e32 v2, s64387; VI-NEXT:    s_setpc_b64 s[30:31]4388;4389; GFX9-LABEL: bitcast_f32_to_v4i8_scalar:4390; GFX9:       ; %bb.0:4391; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4392; GFX9-NEXT:    s_cmp_lg_u32 s17, 04393; GFX9-NEXT:    s_cbranch_scc0 .LBB41_34394; GFX9-NEXT:  ; %bb.1: ; %cmp.false4395; GFX9-NEXT:    s_lshr_b32 s7, s16, 244396; GFX9-NEXT:    s_lshr_b32 s6, s16, 164397; GFX9-NEXT:    s_lshr_b32 s8, s16, 84398; GFX9-NEXT:    s_cbranch_execnz .LBB41_44399; GFX9-NEXT:  .LBB41_2: ; %cmp.true4400; GFX9-NEXT:    v_add_f32_e64 v0, s16, 1.04401; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v04402; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v04403; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v04404; GFX9-NEXT:    s_setpc_b64 s[30:31]4405; GFX9-NEXT:  .LBB41_3:4406; GFX9-NEXT:    ; implicit-def: $sgpr84407; GFX9-NEXT:    ; implicit-def: $sgpr64408; GFX9-NEXT:    ; implicit-def: $sgpr74409; GFX9-NEXT:    s_branch .LBB41_24410; GFX9-NEXT:  .LBB41_4:4411; GFX9-NEXT:    v_mov_b32_e32 v0, s164412; GFX9-NEXT:    v_mov_b32_e32 v1, s84413; GFX9-NEXT:    v_mov_b32_e32 v3, s74414; GFX9-NEXT:    v_mov_b32_e32 v2, s64415; GFX9-NEXT:    s_setpc_b64 s[30:31]4416;4417; GFX11-LABEL: bitcast_f32_to_v4i8_scalar:4418; GFX11:       ; %bb.0:4419; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4420; GFX11-NEXT:    s_cmp_lg_u32 s1, 04421; GFX11-NEXT:    s_mov_b32 s1, 04422; GFX11-NEXT:    s_cbranch_scc0 .LBB41_34423; GFX11-NEXT:  ; %bb.1: ; %cmp.false4424; GFX11-NEXT:    s_lshr_b32 s3, s0, 244425; GFX11-NEXT:    s_lshr_b32 s2, s0, 164426; GFX11-NEXT:    s_lshr_b32 s4, s0, 84427; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s14428; GFX11-NEXT:    s_cbranch_vccnz .LBB41_44429; GFX11-NEXT:  .LBB41_2: ; %cmp.true4430; GFX11-NEXT:    v_add_f32_e64 v0, s0, 1.04431; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)4432; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v04433; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v04434; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v04435; GFX11-NEXT:    s_setpc_b64 s[30:31]4436; GFX11-NEXT:  .LBB41_3:4437; GFX11-NEXT:    ; implicit-def: $sgpr44438; GFX11-NEXT:    ; implicit-def: $sgpr24439; GFX11-NEXT:    ; implicit-def: $sgpr34440; GFX11-NEXT:    s_branch .LBB41_24441; GFX11-NEXT:  .LBB41_4:4442; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s44443; GFX11-NEXT:    v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s24444; GFX11-NEXT:    s_setpc_b64 s[30:31]4445  %cmp = icmp eq i32 %b, 04446  br i1 %cmp, label %cmp.true, label %cmp.false4447 4448cmp.true:4449  %a1 = fadd float %a, 1.000000e+004450  %a2 = bitcast float %a1 to <4 x i8>4451  br label %end4452 4453cmp.false:4454  %a3 = bitcast float %a to <4 x i8>4455  br label %end4456 4457end:4458  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4459  ret <4 x i8> %phi4460}4461 4462define float @bitcast_v4i8_to_f32(<4 x i8> %a, i32 %b) {4463; SI-LABEL: bitcast_v4i8_to_f32:4464; SI:       ; %bb.0:4465; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4466; SI-NEXT:    v_mov_b32_e32 v5, v04467; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44468; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v14469; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v34470; SI-NEXT:    ; implicit-def: $vgpr04471; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4472; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4473; SI-NEXT:    s_cbranch_execnz .LBB42_34474; SI-NEXT:  ; %bb.1: ; %Flow4475; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4476; SI-NEXT:    s_cbranch_execnz .LBB42_44477; SI-NEXT:  .LBB42_2: ; %end4478; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4479; SI-NEXT:    s_setpc_b64 s[30:31]4480; SI-NEXT:  .LBB42_3: ; %cmp.false4481; SI-NEXT:    v_and_b32_e32 v0, 0xff, v54482; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24483; SI-NEXT:    v_or_b32_e32 v0, v0, v44484; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v24485; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v04486; SI-NEXT:    v_or_b32_e32 v1, v1, v24487; SI-NEXT:    v_or_b32_e32 v0, v0, v14488; SI-NEXT:    ; implicit-def: $vgpr54489; SI-NEXT:    ; implicit-def: $vgpr44490; SI-NEXT:    ; implicit-def: $vgpr24491; SI-NEXT:    ; implicit-def: $vgpr14492; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4493; SI-NEXT:    s_cbranch_execz .LBB42_24494; SI-NEXT:  .LBB42_4: ; %cmp.true4495; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v54496; SI-NEXT:    v_and_b32_e32 v0, 0xff, v04497; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v24498; SI-NEXT:    v_or_b32_e32 v0, v4, v04499; SI-NEXT:    v_and_b32_e32 v2, 0xff, v24500; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v04501; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v24502; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v04503; SI-NEXT:    v_or_b32_e32 v1, v1, v24504; SI-NEXT:    v_or_b32_e32 v0, v1, v04505; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v04506; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4507; SI-NEXT:    s_setpc_b64 s[30:31]4508;4509; VI-LABEL: bitcast_v4i8_to_f32:4510; VI:       ; %bb.0:4511; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4512; VI-NEXT:    v_mov_b32_e32 v5, v04513; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44514; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v14515; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v34516; VI-NEXT:    ; implicit-def: $vgpr04517; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4518; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4519; VI-NEXT:    s_cbranch_execnz .LBB42_34520; VI-NEXT:  ; %bb.1: ; %Flow4521; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4522; VI-NEXT:    s_cbranch_execnz .LBB42_44523; VI-NEXT:  .LBB42_2: ; %end4524; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4525; VI-NEXT:    s_setpc_b64 s[30:31]4526; VI-NEXT:  .LBB42_3: ; %cmp.false4527; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4528; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4529; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4530; VI-NEXT:    ; implicit-def: $vgpr54531; VI-NEXT:    ; implicit-def: $vgpr44532; VI-NEXT:    ; implicit-def: $vgpr24533; VI-NEXT:    ; implicit-def: $vgpr14534; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4535; VI-NEXT:    s_cbranch_execz .LBB42_24536; VI-NEXT:  .LBB42_4: ; %cmp.true4537; VI-NEXT:    v_add_u16_e32 v0, 3, v54538; VI-NEXT:    v_add_u16_e32 v2, 3, v24539; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_04540; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_04541; VI-NEXT:    v_mov_b32_e32 v2, 0x3004542; VI-NEXT:    v_add_u16_e32 v0, 0x300, v04543; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4544; VI-NEXT:    v_or_b32_e32 v0, v0, v14545; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4546; VI-NEXT:    s_setpc_b64 s[30:31]4547;4548; GFX9-LABEL: bitcast_v4i8_to_f32:4549; GFX9:       ; %bb.0:4550; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4551; GFX9-NEXT:    v_mov_b32_e32 v5, v04552; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v44553; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v14554; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v34555; GFX9-NEXT:    ; implicit-def: $vgpr04556; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4557; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4558; GFX9-NEXT:    s_cbranch_execnz .LBB42_34559; GFX9-NEXT:  ; %bb.1: ; %Flow4560; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4561; GFX9-NEXT:    s_cbranch_execnz .LBB42_44562; GFX9-NEXT:  .LBB42_2: ; %end4563; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4564; GFX9-NEXT:    s_setpc_b64 s[30:31]4565; GFX9-NEXT:  .LBB42_3: ; %cmp.false4566; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4567; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD4568; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD4569; GFX9-NEXT:    ; implicit-def: $vgpr54570; GFX9-NEXT:    ; implicit-def: $vgpr44571; GFX9-NEXT:    ; implicit-def: $vgpr24572; GFX9-NEXT:    ; implicit-def: $vgpr14573; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4574; GFX9-NEXT:    s_cbranch_execz .LBB42_24575; GFX9-NEXT:  .LBB42_4: ; %cmp.true4576; GFX9-NEXT:    v_add_u16_e32 v0, 3, v54577; GFX9-NEXT:    v_add_u16_e32 v2, 3, v24578; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_04579; GFX9-NEXT:    s_movk_i32 s6, 0x3004580; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_04581; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v04582; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD4583; GFX9-NEXT:    v_or_b32_e32 v0, v0, v14584; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4585; GFX9-NEXT:    s_setpc_b64 s[30:31]4586;4587; GFX11-TRUE16-LABEL: bitcast_v4i8_to_f32:4588; GFX11-TRUE16:       ; %bb.0:4589; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4590; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l4591; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l4592; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l4593; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo4594; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr04595; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v44596; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s04597; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB42_34598; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow4599; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s04600; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB42_44601; GFX11-TRUE16-NEXT:  .LBB42_2: ; %end4602; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04603; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]4604; GFX11-TRUE16-NEXT:  .LBB42_3: ; %cmp.false4605; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h4606; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l4607; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi164608; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo164609; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4610; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l4611; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h4612; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo164613; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi164614; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s04615; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB42_24616; GFX11-TRUE16-NEXT:  .LBB42_4: ; %cmp.true4617; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 34618; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 34619; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4620; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l4621; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h4622; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4623; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l4624; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h4625; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4626; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l4627; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h4628; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04629; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]4630;4631; GFX11-FAKE16-LABEL: bitcast_v4i8_to_f32:4632; GFX11-FAKE16:       ; %bb.0:4633; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4634; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v04635; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v14636; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v34637; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo4638; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr04639; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v44640; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s04641; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB42_34642; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow4643; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s04644; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB42_44645; GFX11-FAKE16-NEXT:  .LBB42_2: ; %end4646; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04647; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]4648; GFX11-FAKE16-NEXT:  .LBB42_3: ; %cmp.false4649; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v54650; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v24651; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr54652; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4653; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v14654; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v34655; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr24656; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr34657; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4658; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v04659; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v14660; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4661; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v14662; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr14663; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s04664; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB42_24665; GFX11-FAKE16-NEXT:  .LBB42_4: ; %cmp.true4666; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 34667; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 34668; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4669; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v04670; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v24671; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4672; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v04673; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v24674; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4675; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v04676; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v14677; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)4678; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v04679; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v14680; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)4681; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v14682; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s04683; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]4684  %cmp = icmp eq i32 %b, 04685  br i1 %cmp, label %cmp.true, label %cmp.false4686 4687cmp.true:4688  %a1 = add <4 x i8> %a, splat (i8 3)4689  %a2 = bitcast <4 x i8> %a1 to float4690  br label %end4691 4692cmp.false:4693  %a3 = bitcast <4 x i8> %a to float4694  br label %end4695 4696end:4697  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]4698  ret float %phi4699}4700 4701define inreg float @bitcast_v4i8_to_f32_scalar(<4 x i8> inreg %a, i32 inreg %b) {4702; SI-LABEL: bitcast_v4i8_to_f32_scalar:4703; SI:       ; %bb.0:4704; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4705; SI-NEXT:    s_cmp_lg_u32 s20, 04706; SI-NEXT:    s_cbranch_scc0 .LBB43_44707; SI-NEXT:  ; %bb.1: ; %cmp.false4708; SI-NEXT:    s_and_b32 s4, s16, 0xff4709; SI-NEXT:    s_lshl_b32 s5, s17, 84710; SI-NEXT:    s_or_b32 s4, s4, s54711; SI-NEXT:    s_and_b32 s5, s18, 0xff4712; SI-NEXT:    s_lshl_b32 s5, s5, 164713; SI-NEXT:    s_lshl_b32 s6, s19, 244714; SI-NEXT:    s_and_b32 s4, s4, 0xffff4715; SI-NEXT:    s_or_b32 s5, s6, s54716; SI-NEXT:    s_or_b32 s6, s4, s54717; SI-NEXT:    s_cbranch_execnz .LBB43_34718; SI-NEXT:  .LBB43_2: ; %cmp.true4719; SI-NEXT:    s_add_i32 s16, s16, 34720; SI-NEXT:    s_and_b32 s4, s16, 0xff4721; SI-NEXT:    s_lshl_b32 s5, s17, 84722; SI-NEXT:    s_add_i32 s18, s18, 34723; SI-NEXT:    s_or_b32 s4, s5, s44724; SI-NEXT:    s_and_b32 s6, s18, 0xff4725; SI-NEXT:    s_addk_i32 s4, 0x3004726; SI-NEXT:    s_lshl_b32 s5, s19, 244727; SI-NEXT:    s_lshl_b32 s6, s6, 164728; SI-NEXT:    s_and_b32 s4, s4, 0xffff4729; SI-NEXT:    s_or_b32 s5, s5, s64730; SI-NEXT:    s_or_b32 s4, s5, s44731; SI-NEXT:    s_add_i32 s6, s4, 0x30000004732; SI-NEXT:  .LBB43_3: ; %end4733; SI-NEXT:    v_mov_b32_e32 v0, s64734; SI-NEXT:    s_setpc_b64 s[30:31]4735; SI-NEXT:  .LBB43_4:4736; SI-NEXT:    ; implicit-def: $sgpr64737; SI-NEXT:    s_branch .LBB43_24738;4739; VI-LABEL: bitcast_v4i8_to_f32_scalar:4740; VI:       ; %bb.0:4741; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4742; VI-NEXT:    s_cmp_lg_u32 s20, 04743; VI-NEXT:    s_cbranch_scc0 .LBB43_44744; VI-NEXT:  ; %bb.1: ; %cmp.false4745; VI-NEXT:    s_and_b32 s4, s16, 0xff4746; VI-NEXT:    s_lshl_b32 s5, s17, 84747; VI-NEXT:    s_or_b32 s4, s4, s54748; VI-NEXT:    s_and_b32 s5, s18, 0xff4749; VI-NEXT:    s_lshl_b32 s6, s19, 84750; VI-NEXT:    s_or_b32 s5, s5, s64751; VI-NEXT:    s_and_b32 s4, s4, 0xffff4752; VI-NEXT:    s_lshl_b32 s5, s5, 164753; VI-NEXT:    s_or_b32 s6, s4, s54754; VI-NEXT:    s_cbranch_execnz .LBB43_34755; VI-NEXT:  .LBB43_2: ; %cmp.true4756; VI-NEXT:    s_add_i32 s16, s16, 34757; VI-NEXT:    s_and_b32 s4, s16, 0xff4758; VI-NEXT:    s_lshl_b32 s5, s17, 84759; VI-NEXT:    s_add_i32 s18, s18, 34760; VI-NEXT:    s_or_b32 s4, s5, s44761; VI-NEXT:    s_and_b32 s5, s18, 0xff4762; VI-NEXT:    s_lshl_b32 s6, s19, 84763; VI-NEXT:    s_addk_i32 s4, 0x3004764; VI-NEXT:    s_or_b32 s5, s6, s54765; VI-NEXT:    s_and_b32 s4, s4, 0xffff4766; VI-NEXT:    s_lshl_b32 s5, s5, 164767; VI-NEXT:    s_or_b32 s4, s5, s44768; VI-NEXT:    s_add_i32 s6, s4, 0x30000004769; VI-NEXT:  .LBB43_3: ; %end4770; VI-NEXT:    v_mov_b32_e32 v0, s64771; VI-NEXT:    s_setpc_b64 s[30:31]4772; VI-NEXT:  .LBB43_4:4773; VI-NEXT:    ; implicit-def: $sgpr64774; VI-NEXT:    s_branch .LBB43_24775;4776; GFX9-LABEL: bitcast_v4i8_to_f32_scalar:4777; GFX9:       ; %bb.0:4778; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4779; GFX9-NEXT:    s_cmp_lg_u32 s20, 04780; GFX9-NEXT:    s_cbranch_scc0 .LBB43_44781; GFX9-NEXT:  ; %bb.1: ; %cmp.false4782; GFX9-NEXT:    s_and_b32 s4, s16, 0xff4783; GFX9-NEXT:    s_lshl_b32 s5, s17, 84784; GFX9-NEXT:    s_or_b32 s4, s4, s54785; GFX9-NEXT:    s_and_b32 s5, s18, 0xff4786; GFX9-NEXT:    s_lshl_b32 s6, s19, 84787; GFX9-NEXT:    s_or_b32 s5, s5, s64788; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff4789; GFX9-NEXT:    s_lshl_b32 s5, s5, 164790; GFX9-NEXT:    s_or_b32 s6, s4, s54791; GFX9-NEXT:    s_cbranch_execnz .LBB43_34792; GFX9-NEXT:  .LBB43_2: ; %cmp.true4793; GFX9-NEXT:    s_add_i32 s16, s16, 34794; GFX9-NEXT:    s_and_b32 s4, s16, 0xff4795; GFX9-NEXT:    s_lshl_b32 s5, s17, 84796; GFX9-NEXT:    s_add_i32 s18, s18, 34797; GFX9-NEXT:    s_or_b32 s4, s5, s44798; GFX9-NEXT:    s_and_b32 s5, s18, 0xff4799; GFX9-NEXT:    s_lshl_b32 s6, s19, 84800; GFX9-NEXT:    s_or_b32 s5, s6, s54801; GFX9-NEXT:    s_addk_i32 s4, 0x3004802; GFX9-NEXT:    s_addk_i32 s5, 0x3004803; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff4804; GFX9-NEXT:    s_lshl_b32 s5, s5, 164805; GFX9-NEXT:    s_or_b32 s6, s4, s54806; GFX9-NEXT:  .LBB43_3: ; %end4807; GFX9-NEXT:    v_mov_b32_e32 v0, s64808; GFX9-NEXT:    s_setpc_b64 s[30:31]4809; GFX9-NEXT:  .LBB43_4:4810; GFX9-NEXT:    ; implicit-def: $sgpr64811; GFX9-NEXT:    s_branch .LBB43_24812;4813; GFX11-LABEL: bitcast_v4i8_to_f32_scalar:4814; GFX11:       ; %bb.0:4815; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4816; GFX11-NEXT:    s_cmp_lg_u32 s16, 04817; GFX11-NEXT:    s_mov_b32 s4, 04818; GFX11-NEXT:    s_cbranch_scc0 .LBB43_44819; GFX11-NEXT:  ; %bb.1: ; %cmp.false4820; GFX11-NEXT:    s_and_b32 s5, s0, 0xff4821; GFX11-NEXT:    s_lshl_b32 s6, s1, 84822; GFX11-NEXT:    s_and_b32 s7, s2, 0xff4823; GFX11-NEXT:    s_lshl_b32 s8, s3, 84824; GFX11-NEXT:    s_or_b32 s5, s5, s64825; GFX11-NEXT:    s_or_b32 s6, s7, s84826; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff4827; GFX11-NEXT:    s_lshl_b32 s6, s6, 164828; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4829; GFX11-NEXT:    s_or_b32 s5, s5, s64830; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s44831; GFX11-NEXT:    s_cbranch_vccnz .LBB43_34832; GFX11-NEXT:  .LBB43_2: ; %cmp.true4833; GFX11-NEXT:    s_add_i32 s0, s0, 34834; GFX11-NEXT:    s_add_i32 s2, s2, 34835; GFX11-NEXT:    s_and_b32 s0, s0, 0xff4836; GFX11-NEXT:    s_lshl_b32 s1, s1, 84837; GFX11-NEXT:    s_and_b32 s2, s2, 0xff4838; GFX11-NEXT:    s_lshl_b32 s3, s3, 84839; GFX11-NEXT:    s_or_b32 s0, s1, s04840; GFX11-NEXT:    s_or_b32 s1, s3, s24841; GFX11-NEXT:    s_addk_i32 s0, 0x3004842; GFX11-NEXT:    s_addk_i32 s1, 0x3004843; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff4844; GFX11-NEXT:    s_lshl_b32 s1, s1, 164845; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4846; GFX11-NEXT:    s_or_b32 s5, s0, s14847; GFX11-NEXT:  .LBB43_3: ; %end4848; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4849; GFX11-NEXT:    v_mov_b32_e32 v0, s54850; GFX11-NEXT:    s_setpc_b64 s[30:31]4851; GFX11-NEXT:  .LBB43_4:4852; GFX11-NEXT:    ; implicit-def: $sgpr54853; GFX11-NEXT:    s_branch .LBB43_24854  %cmp = icmp eq i32 %b, 04855  br i1 %cmp, label %cmp.true, label %cmp.false4856 4857cmp.true:4858  %a1 = add <4 x i8> %a, splat (i8 3)4859  %a2 = bitcast <4 x i8> %a1 to float4860  br label %end4861 4862cmp.false:4863  %a3 = bitcast <4 x i8> %a to float4864  br label %end4865 4866end:4867  %phi = phi float [ %a2, %cmp.true ], [ %a3, %cmp.false ]4868  ret float %phi4869}4870 4871define <2 x half> @bitcast_v2i16_to_v2f16(<2 x i16> %a, i32 %b) {4872; SI-LABEL: bitcast_v2i16_to_v2f16:4873; SI:       ; %bb.0:4874; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4875; SI-NEXT:    v_mov_b32_e32 v4, v14876; SI-NEXT:    v_mov_b32_e32 v3, v04877; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v24878; SI-NEXT:    ; implicit-def: $vgpr04879; SI-NEXT:    ; implicit-def: $vgpr14880; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4881; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4882; SI-NEXT:    s_cbranch_execnz .LBB44_34883; SI-NEXT:  ; %bb.1: ; %Flow4884; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4885; SI-NEXT:    s_cbranch_execnz .LBB44_44886; SI-NEXT:  .LBB44_2: ; %end4887; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4888; SI-NEXT:    s_setpc_b64 s[30:31]4889; SI-NEXT:  .LBB44_3: ; %cmp.false4890; SI-NEXT:    v_cvt_f32_f16_e32 v0, v34891; SI-NEXT:    v_cvt_f32_f16_e32 v1, v44892; SI-NEXT:    ; implicit-def: $vgpr44893; SI-NEXT:    ; implicit-def: $vgpr34894; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4895; SI-NEXT:    s_cbranch_execz .LBB44_24896; SI-NEXT:  .LBB44_4: ; %cmp.true4897; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v44898; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v34899; SI-NEXT:    v_cvt_f32_f16_e32 v0, v04900; SI-NEXT:    v_cvt_f32_f16_e32 v1, v14901; SI-NEXT:    s_or_b64 exec, exec, s[4:5]4902; SI-NEXT:    s_setpc_b64 s[30:31]4903;4904; VI-LABEL: bitcast_v2i16_to_v2f16:4905; VI:       ; %bb.0:4906; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4907; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14908; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc4909; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4910; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4911; VI-NEXT:  ; %bb.1: ; %cmp.true4912; VI-NEXT:    v_mov_b32_e32 v1, 34913; VI-NEXT:    v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD4914; VI-NEXT:    v_add_u16_e32 v0, 3, v04915; VI-NEXT:    v_or_b32_e32 v0, v0, v14916; VI-NEXT:  ; %bb.2: ; %end4917; VI-NEXT:    s_or_b64 exec, exec, s[4:5]4918; VI-NEXT:    s_setpc_b64 s[30:31]4919;4920; GFX9-LABEL: bitcast_v2i16_to_v2f16:4921; GFX9:       ; %bb.0:4922; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4923; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v14924; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc4925; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]4926; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]4927; GFX9-NEXT:  ; %bb.1: ; %cmp.true4928; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4929; GFX9-NEXT:  ; %bb.2: ; %end4930; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]4931; GFX9-NEXT:    s_setpc_b64 s[30:31]4932;4933; GFX11-LABEL: bitcast_v2i16_to_v2f16:4934; GFX11:       ; %bb.0:4935; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4936; GFX11-NEXT:    s_mov_b32 s0, exec_lo4937; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v14938; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s04939; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)4940; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s04941; GFX11-NEXT:  ; %bb.1: ; %cmp.true4942; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]4943; GFX11-NEXT:  ; %bb.2: ; %end4944; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s04945; GFX11-NEXT:    s_setpc_b64 s[30:31]4946  %cmp = icmp eq i32 %b, 04947  br i1 %cmp, label %cmp.true, label %cmp.false4948 4949cmp.true:4950  %a1 = add <2 x i16> %a, splat (i16 3)4951  %a2 = bitcast <2 x i16> %a1 to <2 x half>4952  br label %end4953 4954cmp.false:4955  %a3 = bitcast <2 x i16> %a to <2 x half>4956  br label %end4957 4958end:4959  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]4960  ret <2 x half> %phi4961}4962 4963define inreg <2 x half> @bitcast_v2i16_to_v2f16_scalar(<2 x i16> inreg %a, i32 inreg %b) {4964; SI-LABEL: bitcast_v2i16_to_v2f16_scalar:4965; SI:       ; %bb.0:4966; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4967; SI-NEXT:    s_cmp_lg_u32 s18, 04968; SI-NEXT:    s_cbranch_scc0 .LBB45_44969; SI-NEXT:  ; %bb.1: ; %cmp.false4970; SI-NEXT:    v_cvt_f32_f16_e32 v0, s164971; SI-NEXT:    v_cvt_f32_f16_e32 v1, s174972; SI-NEXT:    s_cbranch_execnz .LBB45_34973; SI-NEXT:  .LBB45_2: ; %cmp.true4974; SI-NEXT:    s_add_i32 s17, s17, 34975; SI-NEXT:    s_add_i32 s16, s16, 34976; SI-NEXT:    v_cvt_f32_f16_e32 v0, s164977; SI-NEXT:    v_cvt_f32_f16_e32 v1, s174978; SI-NEXT:  .LBB45_3: ; %end4979; SI-NEXT:    s_setpc_b64 s[30:31]4980; SI-NEXT:  .LBB45_4:4981; SI-NEXT:    ; implicit-def: $vgpr04982; SI-NEXT:    ; implicit-def: $vgpr14983; SI-NEXT:    s_branch .LBB45_24984;4985; VI-LABEL: bitcast_v2i16_to_v2f16_scalar:4986; VI:       ; %bb.0:4987; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)4988; VI-NEXT:    s_cmp_lg_u32 s17, 04989; VI-NEXT:    s_cbranch_scc0 .LBB45_44990; VI-NEXT:  ; %bb.1: ; %cmp.false4991; VI-NEXT:    s_cbranch_execnz .LBB45_34992; VI-NEXT:  .LBB45_2: ; %cmp.true4993; VI-NEXT:    s_add_i32 s5, s16, 34994; VI-NEXT:    s_and_b32 s4, s16, 0xffff00004995; VI-NEXT:    s_and_b32 s5, s5, 0xffff4996; VI-NEXT:    s_or_b32 s4, s4, s54997; VI-NEXT:    s_add_i32 s16, s4, 0x300004998; VI-NEXT:  .LBB45_3: ; %end4999; VI-NEXT:    v_mov_b32_e32 v0, s165000; VI-NEXT:    s_setpc_b64 s[30:31]5001; VI-NEXT:  .LBB45_4:5002; VI-NEXT:    s_branch .LBB45_25003;5004; GFX9-LABEL: bitcast_v2i16_to_v2f16_scalar:5005; GFX9:       ; %bb.0:5006; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5007; GFX9-NEXT:    s_cmp_lg_u32 s17, 05008; GFX9-NEXT:    s_cbranch_scc0 .LBB45_35009; GFX9-NEXT:  ; %bb.1: ; %cmp.false5010; GFX9-NEXT:    s_cbranch_execnz .LBB45_45011; GFX9-NEXT:  .LBB45_2: ; %cmp.true5012; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]5013; GFX9-NEXT:    s_setpc_b64 s[30:31]5014; GFX9-NEXT:  .LBB45_3:5015; GFX9-NEXT:    s_branch .LBB45_25016; GFX9-NEXT:  .LBB45_4:5017; GFX9-NEXT:    v_mov_b32_e32 v0, s165018; GFX9-NEXT:    s_setpc_b64 s[30:31]5019;5020; GFX11-LABEL: bitcast_v2i16_to_v2f16_scalar:5021; GFX11:       ; %bb.0:5022; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5023; GFX11-NEXT:    s_cmp_lg_u32 s1, 05024; GFX11-NEXT:    s_mov_b32 s1, 05025; GFX11-NEXT:    s_cbranch_scc0 .LBB45_35026; GFX11-NEXT:  ; %bb.1: ; %Flow5027; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15028; GFX11-NEXT:    s_cbranch_vccnz .LBB45_45029; GFX11-NEXT:  .LBB45_2: ; %cmp.true5030; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]5031; GFX11-NEXT:    s_setpc_b64 s[30:31]5032; GFX11-NEXT:  .LBB45_3:5033; GFX11-NEXT:    s_branch .LBB45_25034; GFX11-NEXT:  .LBB45_4:5035; GFX11-NEXT:    v_mov_b32_e32 v0, s05036; GFX11-NEXT:    s_setpc_b64 s[30:31]5037  %cmp = icmp eq i32 %b, 05038  br i1 %cmp, label %cmp.true, label %cmp.false5039 5040cmp.true:5041  %a1 = add <2 x i16> %a, splat (i16 3)5042  %a2 = bitcast <2 x i16> %a1 to <2 x half>5043  br label %end5044 5045cmp.false:5046  %a3 = bitcast <2 x i16> %a to <2 x half>5047  br label %end5048 5049end:5050  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5051  ret <2 x half> %phi5052}5053 5054define <2 x i16> @bitcast_v2f16_to_v2i16(<2 x half> %a, i32 %b) {5055; SI-LABEL: bitcast_v2f16_to_v2i16:5056; SI:       ; %bb.0:5057; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5058; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05059; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15060; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25061; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5062; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5063; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5064; SI-NEXT:    s_cbranch_execz .LBB46_25065; SI-NEXT:  ; %bb.1: ; %cmp.true5066; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15067; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05068; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v15069; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15070; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v05071; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05072; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15073; SI-NEXT:    v_or_b32_e32 v0, v0, v25074; SI-NEXT:  .LBB46_2: ; %end5075; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5076; SI-NEXT:    s_setpc_b64 s[30:31]5077;5078; VI-LABEL: bitcast_v2f16_to_v2i16:5079; VI:       ; %bb.0:5080; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5081; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15082; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5083; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5084; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5085; VI-NEXT:  ; %bb.1: ; %cmp.true5086; VI-NEXT:    v_mov_b32_e32 v2, 0x2005087; VI-NEXT:    v_add_f16_e32 v1, 0x200, v05088; VI-NEXT:    v_add_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5089; VI-NEXT:    v_or_b32_e32 v0, v1, v05090; VI-NEXT:  ; %bb.2: ; %end5091; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5092; VI-NEXT:    s_setpc_b64 s[30:31]5093;5094; GFX9-LABEL: bitcast_v2f16_to_v2i16:5095; GFX9:       ; %bb.0:5096; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5097; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15098; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5099; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5100; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5101; GFX9-NEXT:  ; %bb.1: ; %cmp.true5102; GFX9-NEXT:    s_movk_i32 s6, 0x2005103; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]5104; GFX9-NEXT:  ; %bb.2: ; %end5105; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5106; GFX9-NEXT:    s_setpc_b64 s[30:31]5107;5108; GFX11-LABEL: bitcast_v2f16_to_v2i16:5109; GFX11:       ; %bb.0:5110; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5111; GFX11-NEXT:    s_mov_b32 s0, exec_lo5112; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v15113; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s05114; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5115; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s05116; GFX11-NEXT:  ; %bb.1: ; %cmp.true5117; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]5118; GFX11-NEXT:  ; %bb.2: ; %end5119; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05120; GFX11-NEXT:    s_setpc_b64 s[30:31]5121  %cmp = icmp eq i32 %b, 05122  br i1 %cmp, label %cmp.true, label %cmp.false5123 5124cmp.true:5125  %a1 = fadd <2 x half> %a, splat (half 0xH0200)5126  %a2 = bitcast <2 x half> %a1 to <2 x i16>5127  br label %end5128 5129cmp.false:5130  %a3 = bitcast <2 x half> %a to <2 x i16>5131  br label %end5132 5133end:5134  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5135  ret <2 x i16> %phi5136}5137 5138define inreg <2 x i16> @bitcast_v2f16_to_v2i16_scalar(<2 x half> inreg %a, i32 inreg %b) {5139; SI-LABEL: bitcast_v2f16_to_v2i16_scalar:5140; SI:       ; %bb.0:5141; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5142; SI-NEXT:    v_cvt_f16_f32_e32 v0, s165143; SI-NEXT:    v_cvt_f16_f32_e32 v1, s175144; SI-NEXT:    s_cmp_lg_u32 s18, 05145; SI-NEXT:    s_cbranch_scc0 .LBB47_45146; SI-NEXT:  ; %bb.1: ; %cmp.false5147; SI-NEXT:    s_cbranch_execnz .LBB47_35148; SI-NEXT:  .LBB47_2: ; %cmp.true5149; SI-NEXT:    v_cvt_f32_f16_e32 v1, v15150; SI-NEXT:    v_cvt_f32_f16_e32 v0, v05151; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v15152; SI-NEXT:    v_cvt_f16_f32_e32 v1, v15153; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v05154; SI-NEXT:    v_cvt_f16_f32_e32 v0, v05155; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v15156; SI-NEXT:    v_or_b32_e32 v0, v0, v25157; SI-NEXT:  .LBB47_3: ; %end5158; SI-NEXT:    s_setpc_b64 s[30:31]5159; SI-NEXT:  .LBB47_4:5160; SI-NEXT:    s_branch .LBB47_25161;5162; VI-LABEL: bitcast_v2f16_to_v2i16_scalar:5163; VI:       ; %bb.0:5164; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5165; VI-NEXT:    s_cmp_lg_u32 s17, 05166; VI-NEXT:    s_cbranch_scc0 .LBB47_35167; VI-NEXT:  ; %bb.1: ; %cmp.false5168; VI-NEXT:    s_cbranch_execnz .LBB47_45169; VI-NEXT:  .LBB47_2: ; %cmp.true5170; VI-NEXT:    s_lshr_b32 s4, s16, 165171; VI-NEXT:    v_mov_b32_e32 v0, 0x2005172; VI-NEXT:    v_mov_b32_e32 v2, s45173; VI-NEXT:    v_add_f16_e32 v1, s16, v05174; VI-NEXT:    v_add_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD5175; VI-NEXT:    v_or_b32_e32 v0, v1, v05176; VI-NEXT:    s_setpc_b64 s[30:31]5177; VI-NEXT:  .LBB47_3:5178; VI-NEXT:    s_branch .LBB47_25179; VI-NEXT:  .LBB47_4:5180; VI-NEXT:    v_mov_b32_e32 v0, s165181; VI-NEXT:    s_setpc_b64 s[30:31]5182;5183; GFX9-LABEL: bitcast_v2f16_to_v2i16_scalar:5184; GFX9:       ; %bb.0:5185; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5186; GFX9-NEXT:    s_cmp_lg_u32 s17, 05187; GFX9-NEXT:    s_cbranch_scc0 .LBB47_35188; GFX9-NEXT:  ; %bb.1: ; %cmp.false5189; GFX9-NEXT:    s_cbranch_execnz .LBB47_45190; GFX9-NEXT:  .LBB47_2: ; %cmp.true5191; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2005192; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]5193; GFX9-NEXT:    s_setpc_b64 s[30:31]5194; GFX9-NEXT:  .LBB47_3:5195; GFX9-NEXT:    s_branch .LBB47_25196; GFX9-NEXT:  .LBB47_4:5197; GFX9-NEXT:    v_mov_b32_e32 v0, s165198; GFX9-NEXT:    s_setpc_b64 s[30:31]5199;5200; GFX11-LABEL: bitcast_v2f16_to_v2i16_scalar:5201; GFX11:       ; %bb.0:5202; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5203; GFX11-NEXT:    s_cmp_lg_u32 s1, 05204; GFX11-NEXT:    s_mov_b32 s1, 05205; GFX11-NEXT:    s_cbranch_scc0 .LBB47_35206; GFX11-NEXT:  ; %bb.1: ; %Flow5207; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15208; GFX11-NEXT:    s_cbranch_vccnz .LBB47_45209; GFX11-NEXT:  .LBB47_2: ; %cmp.true5210; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]5211; GFX11-NEXT:    s_setpc_b64 s[30:31]5212; GFX11-NEXT:  .LBB47_3:5213; GFX11-NEXT:    s_branch .LBB47_25214; GFX11-NEXT:  .LBB47_4:5215; GFX11-NEXT:    v_mov_b32_e32 v0, s05216; GFX11-NEXT:    s_setpc_b64 s[30:31]5217  %cmp = icmp eq i32 %b, 05218  br i1 %cmp, label %cmp.true, label %cmp.false5219 5220cmp.true:5221  %a1 = fadd <2 x half> %a, splat (half 0xH0200)5222  %a2 = bitcast <2 x half> %a1 to <2 x i16>5223  br label %end5224 5225cmp.false:5226  %a3 = bitcast <2 x half> %a to <2 x i16>5227  br label %end5228 5229end:5230  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5231  ret <2 x i16> %phi5232}5233 5234define <2 x bfloat> @bitcast_v2i16_to_v2bf16(<2 x i16> %a, i32 %b) {5235; SI-LABEL: bitcast_v2i16_to_v2bf16:5236; SI:       ; %bb.0:5237; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5238; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25239; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v05240; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v15241; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5242; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5243; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5244; SI-NEXT:  ; %bb.1: ; %cmp.true5245; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v05246; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x30000, v15247; SI-NEXT:  ; %bb.2: ; %end5248; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5249; SI-NEXT:    s_setpc_b64 s[30:31]5250;5251; VI-LABEL: bitcast_v2i16_to_v2bf16:5252; VI:       ; %bb.0:5253; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5254; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15255; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5256; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5257; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5258; VI-NEXT:  ; %bb.1: ; %cmp.true5259; VI-NEXT:    v_mov_b32_e32 v1, 35260; VI-NEXT:    v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5261; VI-NEXT:    v_add_u16_e32 v0, 3, v05262; VI-NEXT:    v_or_b32_e32 v0, v0, v15263; VI-NEXT:  ; %bb.2: ; %end5264; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5265; VI-NEXT:    s_setpc_b64 s[30:31]5266;5267; GFX9-LABEL: bitcast_v2i16_to_v2bf16:5268; GFX9:       ; %bb.0:5269; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5270; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15271; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5272; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5273; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5274; GFX9-NEXT:  ; %bb.1: ; %cmp.true5275; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5276; GFX9-NEXT:  ; %bb.2: ; %end5277; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5278; GFX9-NEXT:    s_setpc_b64 s[30:31]5279;5280; GFX11-LABEL: bitcast_v2i16_to_v2bf16:5281; GFX11:       ; %bb.0:5282; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5283; GFX11-NEXT:    s_mov_b32 s0, exec_lo5284; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v15285; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s05286; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5287; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s05288; GFX11-NEXT:  ; %bb.1: ; %cmp.true5289; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5290; GFX11-NEXT:  ; %bb.2: ; %end5291; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05292; GFX11-NEXT:    s_setpc_b64 s[30:31]5293  %cmp = icmp eq i32 %b, 05294  br i1 %cmp, label %cmp.true, label %cmp.false5295 5296cmp.true:5297  %a1 = add <2 x i16> %a, splat (i16 3)5298  %a2 = bitcast <2 x i16> %a1 to <2 x bfloat>5299  br label %end5300 5301cmp.false:5302  %a3 = bitcast <2 x i16> %a to <2 x bfloat>5303  br label %end5304 5305end:5306  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5307  ret <2 x bfloat> %phi5308}5309 5310define inreg <2 x bfloat> @bitcast_v2i16_to_v2bf16_scalar(<2 x i16> inreg %a, i32 inreg %b) {5311; SI-LABEL: bitcast_v2i16_to_v2bf16_scalar:5312; SI:       ; %bb.0:5313; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5314; SI-NEXT:    s_cmp_lg_u32 s18, 05315; SI-NEXT:    s_cbranch_scc0 .LBB49_45316; SI-NEXT:  ; %bb.1: ; %cmp.false5317; SI-NEXT:    s_lshl_b32 s6, s16, 165318; SI-NEXT:    s_lshl_b32 s7, s17, 165319; SI-NEXT:    s_cbranch_execnz .LBB49_35320; SI-NEXT:  .LBB49_2: ; %cmp.true5321; SI-NEXT:    s_lshl_b32 s4, s17, 165322; SI-NEXT:    s_lshl_b32 s5, s16, 165323; SI-NEXT:    s_add_i32 s6, s5, 0x300005324; SI-NEXT:    s_add_i32 s7, s4, 0x300005325; SI-NEXT:  .LBB49_3: ; %end5326; SI-NEXT:    v_mov_b32_e32 v0, s65327; SI-NEXT:    v_mov_b32_e32 v1, s75328; SI-NEXT:    s_setpc_b64 s[30:31]5329; SI-NEXT:  .LBB49_4:5330; SI-NEXT:    ; implicit-def: $sgpr65331; SI-NEXT:    ; implicit-def: $sgpr75332; SI-NEXT:    s_branch .LBB49_25333;5334; VI-LABEL: bitcast_v2i16_to_v2bf16_scalar:5335; VI:       ; %bb.0:5336; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5337; VI-NEXT:    s_cmp_lg_u32 s17, 05338; VI-NEXT:    s_cbranch_scc0 .LBB49_45339; VI-NEXT:  ; %bb.1: ; %cmp.false5340; VI-NEXT:    s_cbranch_execnz .LBB49_35341; VI-NEXT:  .LBB49_2: ; %cmp.true5342; VI-NEXT:    s_add_i32 s5, s16, 35343; VI-NEXT:    s_and_b32 s4, s16, 0xffff00005344; VI-NEXT:    s_and_b32 s5, s5, 0xffff5345; VI-NEXT:    s_or_b32 s4, s4, s55346; VI-NEXT:    s_add_i32 s16, s4, 0x300005347; VI-NEXT:  .LBB49_3: ; %end5348; VI-NEXT:    v_mov_b32_e32 v0, s165349; VI-NEXT:    s_setpc_b64 s[30:31]5350; VI-NEXT:  .LBB49_4:5351; VI-NEXT:    s_branch .LBB49_25352;5353; GFX9-LABEL: bitcast_v2i16_to_v2bf16_scalar:5354; GFX9:       ; %bb.0:5355; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5356; GFX9-NEXT:    s_cmp_lg_u32 s17, 05357; GFX9-NEXT:    s_cbranch_scc0 .LBB49_35358; GFX9-NEXT:  ; %bb.1: ; %cmp.false5359; GFX9-NEXT:    s_cbranch_execnz .LBB49_45360; GFX9-NEXT:  .LBB49_2: ; %cmp.true5361; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]5362; GFX9-NEXT:    s_setpc_b64 s[30:31]5363; GFX9-NEXT:  .LBB49_3:5364; GFX9-NEXT:    s_branch .LBB49_25365; GFX9-NEXT:  .LBB49_4:5366; GFX9-NEXT:    v_mov_b32_e32 v0, s165367; GFX9-NEXT:    s_setpc_b64 s[30:31]5368;5369; GFX11-LABEL: bitcast_v2i16_to_v2bf16_scalar:5370; GFX11:       ; %bb.0:5371; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5372; GFX11-NEXT:    s_cmp_lg_u32 s1, 05373; GFX11-NEXT:    s_mov_b32 s1, 05374; GFX11-NEXT:    s_cbranch_scc0 .LBB49_35375; GFX11-NEXT:  ; %bb.1: ; %Flow5376; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15377; GFX11-NEXT:    s_cbranch_vccnz .LBB49_45378; GFX11-NEXT:  .LBB49_2: ; %cmp.true5379; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]5380; GFX11-NEXT:    s_setpc_b64 s[30:31]5381; GFX11-NEXT:  .LBB49_3:5382; GFX11-NEXT:    s_branch .LBB49_25383; GFX11-NEXT:  .LBB49_4:5384; GFX11-NEXT:    v_mov_b32_e32 v0, s05385; GFX11-NEXT:    s_setpc_b64 s[30:31]5386  %cmp = icmp eq i32 %b, 05387  br i1 %cmp, label %cmp.true, label %cmp.false5388 5389cmp.true:5390  %a1 = add <2 x i16> %a, splat (i16 3)5391  %a2 = bitcast <2 x i16> %a1 to <2 x bfloat>5392  br label %end5393 5394cmp.false:5395  %a3 = bitcast <2 x i16> %a to <2 x bfloat>5396  br label %end5397 5398end:5399  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5400  ret <2 x bfloat> %phi5401}5402 5403define <2 x i16> @bitcast_v2bf16_to_v2i16(<2 x bfloat> %a, i32 %b) {5404; SI-LABEL: bitcast_v2bf16_to_v2i16:5405; SI:       ; %bb.0:5406; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5407; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25408; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v05409; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v15410; SI-NEXT:    ; implicit-def: $vgpr05411; SI-NEXT:    ; implicit-def: $vgpr15412; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5413; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5414; SI-NEXT:    s_cbranch_execnz .LBB50_35415; SI-NEXT:  ; %bb.1: ; %Flow5416; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5417; SI-NEXT:    s_cbranch_execnz .LBB50_45418; SI-NEXT:  .LBB50_2: ; %end5419; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5420; SI-NEXT:    s_setpc_b64 s[30:31]5421; SI-NEXT:  .LBB50_3: ; %cmp.false5422; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v35423; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v25424; SI-NEXT:    ; implicit-def: $vgpr35425; SI-NEXT:    ; implicit-def: $vgpr25426; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5427; SI-NEXT:    s_cbranch_execz .LBB50_25428; SI-NEXT:  .LBB50_4: ; %cmp.true5429; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v25430; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v35431; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15432; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05433; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15434; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 165435; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5436; SI-NEXT:    s_setpc_b64 s[30:31]5437;5438; VI-LABEL: bitcast_v2bf16_to_v2i16:5439; VI:       ; %bb.0:5440; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5441; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15442; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5443; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5444; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5445; VI-NEXT:    s_cbranch_execz .LBB50_25446; VI-NEXT:  ; %bb.1: ; %cmp.true5447; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v05448; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15449; VI-NEXT:    v_bfe_u32 v2, v1, 16, 15450; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v15451; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v25452; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05453; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v15454; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15455; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05456; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc5457; VI-NEXT:    v_bfe_u32 v2, v0, 16, 15458; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v05459; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v25460; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v05461; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05462; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc5463; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v05464; VI-NEXT:    v_alignbit_b32 v0, v0, v1, 165465; VI-NEXT:  .LBB50_2: ; %end5466; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5467; VI-NEXT:    s_setpc_b64 s[30:31]5468;5469; GFX9-LABEL: bitcast_v2bf16_to_v2i16:5470; GFX9:       ; %bb.0:5471; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5472; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15473; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5474; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5475; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5476; GFX9-NEXT:    s_cbranch_execz .LBB50_25477; GFX9-NEXT:  ; %bb.1: ; %cmp.true5478; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v05479; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15480; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 15481; GFX9-NEXT:    s_movk_i32 s6, 0x7fff5482; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05483; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s65484; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v15485; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15486; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05487; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc5488; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 15489; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s65490; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v05491; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05492; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc5493; GFX9-NEXT:    s_mov_b32 s6, 0x70603025494; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s65495; GFX9-NEXT:  .LBB50_2: ; %end5496; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5497; GFX9-NEXT:    s_setpc_b64 s[30:31]5498;5499; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2i16:5500; GFX11-TRUE16:       ; %bb.0:5501; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5502; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo5503; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v15504; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s05505; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5506; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s05507; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB50_25508; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.true5509; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v05510; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05511; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5512; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v05513; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 15514; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5515; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 15516; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v15517; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15518; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v05519; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff5520; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff5521; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5522; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo5523; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05524; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo5525; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)5526; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v1.h5527; GFX11-TRUE16-NEXT:  .LBB50_2: ; %end5528; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05529; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5530;5531; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2i16:5532; GFX11-FAKE16:       ; %bb.0:5533; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5534; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo5535; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v15536; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s05537; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5538; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s05539; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB50_25540; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true5541; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v05542; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05543; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5544; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v05545; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 15546; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)5547; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 15548; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v15549; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15550; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v05551; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff5552; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff5553; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)5554; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo5555; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05556; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo5557; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)5558; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x70603025559; GFX11-FAKE16-NEXT:  .LBB50_2: ; %end5560; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s05561; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5562  %cmp = icmp eq i32 %b, 05563  br i1 %cmp, label %cmp.true, label %cmp.false5564 5565cmp.true:5566  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)5567  %a2 = bitcast <2 x bfloat> %a1 to <2 x i16>5568  br label %end5569 5570cmp.false:5571  %a3 = bitcast <2 x bfloat> %a to <2 x i16>5572  br label %end5573 5574end:5575  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5576  ret <2 x i16> %phi5577}5578 5579define inreg <2 x i16> @bitcast_v2bf16_to_v2i16_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {5580; SI-LABEL: bitcast_v2bf16_to_v2i16_scalar:5581; SI:       ; %bb.0:5582; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5583; SI-NEXT:    s_cmp_lg_u32 s18, 05584; SI-NEXT:    v_mul_f32_e64 v0, 1.0, s165585; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s175586; SI-NEXT:    s_cbranch_scc0 .LBB51_45587; SI-NEXT:  ; %bb.1: ; %cmp.false5588; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v05589; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v35590; SI-NEXT:    s_cbranch_execnz .LBB51_35591; SI-NEXT:  .LBB51_2: ; %cmp.true5592; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v35593; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v05594; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v15595; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v05596; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15597; SI-NEXT:    v_lshr_b64 v[2:3], v[0:1], 165598; SI-NEXT:  .LBB51_3: ; %end5599; SI-NEXT:    v_mov_b32_e32 v0, v25600; SI-NEXT:    s_setpc_b64 s[30:31]5601; SI-NEXT:  .LBB51_4:5602; SI-NEXT:    ; implicit-def: $vgpr25603; SI-NEXT:    ; implicit-def: $vgpr15604; SI-NEXT:    s_branch .LBB51_25605;5606; VI-LABEL: bitcast_v2bf16_to_v2i16_scalar:5607; VI:       ; %bb.0:5608; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5609; VI-NEXT:    s_cmp_lg_u32 s17, 05610; VI-NEXT:    s_cbranch_scc0 .LBB51_35611; VI-NEXT:  ; %bb.1: ; %cmp.false5612; VI-NEXT:    s_cbranch_execnz .LBB51_45613; VI-NEXT:  .LBB51_2: ; %cmp.true5614; VI-NEXT:    s_lshl_b32 s4, s16, 165615; VI-NEXT:    v_mov_b32_e32 v1, 0x40c000005616; VI-NEXT:    v_add_f32_e32 v0, s4, v15617; VI-NEXT:    v_bfe_u32 v2, v0, 16, 15618; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v05619; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v25620; VI-NEXT:    s_and_b32 s4, s16, 0xffff00005621; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v05622; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05623; VI-NEXT:    v_add_f32_e32 v1, s4, v15624; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc5625; VI-NEXT:    v_bfe_u32 v2, v1, 16, 15626; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v15627; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v25628; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v15629; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15630; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc5631; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v15632; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]5633; VI-NEXT:    s_setpc_b64 s[30:31]5634; VI-NEXT:  .LBB51_3:5635; VI-NEXT:    s_branch .LBB51_25636; VI-NEXT:  .LBB51_4:5637; VI-NEXT:    v_mov_b32_e32 v0, s165638; VI-NEXT:    s_setpc_b64 s[30:31]5639;5640; GFX9-LABEL: bitcast_v2bf16_to_v2i16_scalar:5641; GFX9:       ; %bb.0:5642; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5643; GFX9-NEXT:    s_cmp_lg_u32 s17, 05644; GFX9-NEXT:    s_cbranch_scc0 .LBB51_35645; GFX9-NEXT:  ; %bb.1: ; %cmp.false5646; GFX9-NEXT:    s_cbranch_execnz .LBB51_45647; GFX9-NEXT:  .LBB51_2: ; %cmp.true5648; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00005649; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000005650; GFX9-NEXT:    v_add_f32_e32 v1, s4, v05651; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 15652; GFX9-NEXT:    v_add_u32_e32 v2, v2, v15653; GFX9-NEXT:    s_lshl_b32 s4, s16, 165654; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v25655; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v15656; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v15657; GFX9-NEXT:    v_add_f32_e32 v0, s4, v05658; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc5659; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 15660; GFX9-NEXT:    v_add_u32_e32 v2, v2, v05661; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v25662; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v05663; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v05664; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc5665; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v05666; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff00005667; GFX9-NEXT:    v_and_or_b32 v0, v1, v2, v05668; GFX9-NEXT:    s_setpc_b64 s[30:31]5669; GFX9-NEXT:  .LBB51_3:5670; GFX9-NEXT:    s_branch .LBB51_25671; GFX9-NEXT:  .LBB51_4:5672; GFX9-NEXT:    v_mov_b32_e32 v0, s165673; GFX9-NEXT:    s_setpc_b64 s[30:31]5674;5675; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2i16_scalar:5676; GFX11-TRUE16:       ; %bb.0:5677; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5678; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 05679; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 05680; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB51_35681; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow5682; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15683; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB51_45684; GFX11-TRUE16-NEXT:  .LBB51_2: ; %cmp.true5685; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s0, 165686; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, 0xffff00005687; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s15688; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s05689; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5690; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 15691; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 15692; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v05693; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05694; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v15695; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v05696; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5697; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v25698; GFX11-TRUE16-NEXT:    v_dual_cndmask_b32 v2, v2, v4 :: v_dual_add_nc_u32 v3, v3, v15699; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)5700; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v35701; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15702; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo5703; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4)5704; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.h5705; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5706; GFX11-TRUE16-NEXT:  .LBB51_3:5707; GFX11-TRUE16-NEXT:    s_branch .LBB51_25708; GFX11-TRUE16-NEXT:  .LBB51_4:5709; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s05710; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]5711;5712; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2i16_scalar:5713; GFX11-FAKE16:       ; %bb.0:5714; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5715; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 05716; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 05717; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB51_35718; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow5719; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15720; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB51_45721; GFX11-FAKE16-NEXT:  .LBB51_2: ; %cmp.true5722; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 165723; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00005724; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s15725; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s05726; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)5727; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 15728; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 15729; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v05730; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v05731; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v15732; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)5733; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v15734; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v35735; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v05736; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)5737; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v25738; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo5739; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v15740; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)5741; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v05742; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo5743; GFX11-FAKE16-NEXT:    v_and_or_b32 v0, 0xffff0000, v1, v05744; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5745; GFX11-FAKE16-NEXT:  .LBB51_3:5746; GFX11-FAKE16-NEXT:    s_branch .LBB51_25747; GFX11-FAKE16-NEXT:  .LBB51_4:5748; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s05749; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]5750  %cmp = icmp eq i32 %b, 05751  br i1 %cmp, label %cmp.true, label %cmp.false5752 5753cmp.true:5754  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)5755  %a2 = bitcast <2 x bfloat> %a1 to <2 x i16>5756  br label %end5757 5758cmp.false:5759  %a3 = bitcast <2 x bfloat> %a to <2 x i16>5760  br label %end5761 5762end:5763  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5764  ret <2 x i16> %phi5765}5766 5767define <1 x i32> @bitcast_v2i16_to_v1i32(<2 x i16> %a, i32 %b) {5768; SI-LABEL: bitcast_v2i16_to_v1i32:5769; SI:       ; %bb.0:5770; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5771; SI-NEXT:    v_mov_b32_e32 v3, v05772; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v25773; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v15774; SI-NEXT:    ; implicit-def: $vgpr05775; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5776; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5777; SI-NEXT:    s_cbranch_execnz .LBB52_35778; SI-NEXT:  ; %bb.1: ; %Flow5779; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5780; SI-NEXT:    s_cbranch_execnz .LBB52_45781; SI-NEXT:  .LBB52_2: ; %end5782; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5783; SI-NEXT:    s_setpc_b64 s[30:31]5784; SI-NEXT:  .LBB52_3: ; %cmp.false5785; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v35786; SI-NEXT:    v_or_b32_e32 v0, v0, v15787; SI-NEXT:    ; implicit-def: $vgpr35788; SI-NEXT:    ; implicit-def: $vgpr15789; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5790; SI-NEXT:    s_cbranch_execz .LBB52_25791; SI-NEXT:  .LBB52_4: ; %cmp.true5792; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v35793; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v05794; SI-NEXT:    v_or_b32_e32 v0, v1, v05795; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x30000, v05796; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5797; SI-NEXT:    s_setpc_b64 s[30:31]5798;5799; VI-LABEL: bitcast_v2i16_to_v1i32:5800; VI:       ; %bb.0:5801; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5802; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15803; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5804; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5805; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5806; VI-NEXT:  ; %bb.1: ; %cmp.true5807; VI-NEXT:    v_mov_b32_e32 v2, 35808; VI-NEXT:    v_add_u16_e32 v1, 3, v05809; VI-NEXT:    v_add_u16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD5810; VI-NEXT:    v_or_b32_e32 v0, v1, v05811; VI-NEXT:  ; %bb.2: ; %end5812; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5813; VI-NEXT:    s_setpc_b64 s[30:31]5814;5815; GFX9-LABEL: bitcast_v2i16_to_v1i32:5816; GFX9:       ; %bb.0:5817; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5818; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15819; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5820; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5821; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5822; GFX9-NEXT:  ; %bb.1: ; %cmp.true5823; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5824; GFX9-NEXT:  ; %bb.2: ; %end5825; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]5826; GFX9-NEXT:    s_setpc_b64 s[30:31]5827;5828; GFX11-LABEL: bitcast_v2i16_to_v1i32:5829; GFX11:       ; %bb.0:5830; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5831; GFX11-NEXT:    s_mov_b32 s0, exec_lo5832; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v15833; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s05834; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)5835; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s05836; GFX11-NEXT:  ; %bb.1: ; %cmp.true5837; GFX11-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]5838; GFX11-NEXT:  ; %bb.2: ; %end5839; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s05840; GFX11-NEXT:    s_setpc_b64 s[30:31]5841  %cmp = icmp eq i32 %b, 05842  br i1 %cmp, label %cmp.true, label %cmp.false5843 5844cmp.true:5845  %a1 = add <2 x i16> %a, splat (i16 3)5846  %a2 = bitcast <2 x i16> %a1 to <1 x i32>5847  br label %end5848 5849cmp.false:5850  %a3 = bitcast <2 x i16> %a to <1 x i32>5851  br label %end5852 5853end:5854  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5855  ret <1 x i32> %phi5856}5857 5858define inreg <1 x i32> @bitcast_v2i16_to_v1i32_scalar(<2 x i16> inreg %a, i32 inreg %b) {5859; SI-LABEL: bitcast_v2i16_to_v1i32_scalar:5860; SI:       ; %bb.0:5861; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5862; SI-NEXT:    s_cmp_lg_u32 s18, 05863; SI-NEXT:    s_cbranch_scc0 .LBB53_45864; SI-NEXT:  ; %bb.1: ; %cmp.false5865; SI-NEXT:    s_and_b32 s4, s16, 0xffff5866; SI-NEXT:    s_lshl_b32 s5, s17, 165867; SI-NEXT:    s_or_b32 s6, s4, s55868; SI-NEXT:    s_cbranch_execnz .LBB53_35869; SI-NEXT:  .LBB53_2: ; %cmp.true5870; SI-NEXT:    s_add_i32 s16, s16, 35871; SI-NEXT:    s_and_b32 s4, s16, 0xffff5872; SI-NEXT:    s_lshl_b32 s5, s17, 165873; SI-NEXT:    s_or_b32 s4, s5, s45874; SI-NEXT:    s_add_i32 s6, s4, 0x300005875; SI-NEXT:  .LBB53_3: ; %end5876; SI-NEXT:    v_mov_b32_e32 v0, s65877; SI-NEXT:    s_setpc_b64 s[30:31]5878; SI-NEXT:  .LBB53_4:5879; SI-NEXT:    ; implicit-def: $sgpr65880; SI-NEXT:    s_branch .LBB53_25881;5882; VI-LABEL: bitcast_v2i16_to_v1i32_scalar:5883; VI:       ; %bb.0:5884; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5885; VI-NEXT:    s_cmp_lg_u32 s17, 05886; VI-NEXT:    s_cbranch_scc0 .LBB53_45887; VI-NEXT:  ; %bb.1: ; %cmp.false5888; VI-NEXT:    s_cbranch_execnz .LBB53_35889; VI-NEXT:  .LBB53_2: ; %cmp.true5890; VI-NEXT:    s_add_i32 s5, s16, 35891; VI-NEXT:    s_and_b32 s4, s16, 0xffff00005892; VI-NEXT:    s_and_b32 s5, s5, 0xffff5893; VI-NEXT:    s_or_b32 s4, s4, s55894; VI-NEXT:    s_add_i32 s16, s4, 0x300005895; VI-NEXT:  .LBB53_3: ; %end5896; VI-NEXT:    v_mov_b32_e32 v0, s165897; VI-NEXT:    s_setpc_b64 s[30:31]5898; VI-NEXT:  .LBB53_4:5899; VI-NEXT:    s_branch .LBB53_25900;5901; GFX9-LABEL: bitcast_v2i16_to_v1i32_scalar:5902; GFX9:       ; %bb.0:5903; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5904; GFX9-NEXT:    s_cmp_lg_u32 s17, 05905; GFX9-NEXT:    s_cbranch_scc0 .LBB53_35906; GFX9-NEXT:  ; %bb.1: ; %cmp.false5907; GFX9-NEXT:    s_cbranch_execnz .LBB53_45908; GFX9-NEXT:  .LBB53_2: ; %cmp.true5909; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]5910; GFX9-NEXT:    s_setpc_b64 s[30:31]5911; GFX9-NEXT:  .LBB53_3:5912; GFX9-NEXT:    s_branch .LBB53_25913; GFX9-NEXT:  .LBB53_4:5914; GFX9-NEXT:    v_mov_b32_e32 v0, s165915; GFX9-NEXT:    s_setpc_b64 s[30:31]5916;5917; GFX11-LABEL: bitcast_v2i16_to_v1i32_scalar:5918; GFX11:       ; %bb.0:5919; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5920; GFX11-NEXT:    s_cmp_lg_u32 s1, 05921; GFX11-NEXT:    s_mov_b32 s1, 05922; GFX11-NEXT:    s_cbranch_scc0 .LBB53_35923; GFX11-NEXT:  ; %bb.1: ; %Flow5924; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s15925; GFX11-NEXT:    s_cbranch_vccnz .LBB53_45926; GFX11-NEXT:  .LBB53_2: ; %cmp.true5927; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]5928; GFX11-NEXT:    s_setpc_b64 s[30:31]5929; GFX11-NEXT:  .LBB53_3:5930; GFX11-NEXT:    s_branch .LBB53_25931; GFX11-NEXT:  .LBB53_4:5932; GFX11-NEXT:    v_mov_b32_e32 v0, s05933; GFX11-NEXT:    s_setpc_b64 s[30:31]5934  %cmp = icmp eq i32 %b, 05935  br i1 %cmp, label %cmp.true, label %cmp.false5936 5937cmp.true:5938  %a1 = add <2 x i16> %a, splat (i16 3)5939  %a2 = bitcast <2 x i16> %a1 to <1 x i32>5940  br label %end5941 5942cmp.false:5943  %a3 = bitcast <2 x i16> %a to <1 x i32>5944  br label %end5945 5946end:5947  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]5948  ret <1 x i32> %phi5949}5950 5951define <2 x i16> @bitcast_v1i32_to_v2i16(<1 x i32> %a, i32 %b) {5952; SI-LABEL: bitcast_v1i32_to_v2i16:5953; SI:       ; %bb.0:5954; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5955; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15956; SI-NEXT:    ; implicit-def: $vgpr15957; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5958; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5959; SI-NEXT:    s_cbranch_execnz .LBB54_35960; SI-NEXT:  ; %bb.1: ; %Flow5961; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5962; SI-NEXT:    s_cbranch_execnz .LBB54_45963; SI-NEXT:  .LBB54_2: ; %end5964; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5965; SI-NEXT:    s_setpc_b64 s[30:31]5966; SI-NEXT:  .LBB54_3: ; %cmp.false5967; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v05968; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5969; SI-NEXT:    s_cbranch_execz .LBB54_25970; SI-NEXT:  .LBB54_4: ; %cmp.true5971; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v05972; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v05973; SI-NEXT:    s_or_b64 exec, exec, s[4:5]5974; SI-NEXT:    s_setpc_b64 s[30:31]5975;5976; VI-LABEL: bitcast_v1i32_to_v2i16:5977; VI:       ; %bb.0:5978; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5979; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15980; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc5981; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5982; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5983; VI-NEXT:  ; %bb.1: ; %cmp.true5984; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v05985; VI-NEXT:  ; %bb.2: ; %end5986; VI-NEXT:    s_or_b64 exec, exec, s[4:5]5987; VI-NEXT:    s_setpc_b64 s[30:31]5988;5989; GFX9-LABEL: bitcast_v1i32_to_v2i16:5990; GFX9:       ; %bb.0:5991; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)5992; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v15993; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc5994; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]5995; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]5996; GFX9-NEXT:  ; %bb.1: ; %cmp.true5997; GFX9-NEXT:    v_add_u32_e32 v0, 3, v05998; GFX9-NEXT:  ; %bb.2: ; %end5999; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6000; GFX9-NEXT:    s_setpc_b64 s[30:31]6001;6002; GFX11-LABEL: bitcast_v1i32_to_v2i16:6003; GFX11:       ; %bb.0:6004; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6005; GFX11-NEXT:    s_mov_b32 s0, exec_lo6006; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16007; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s06008; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6009; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s06010; GFX11-NEXT:  ; %bb.1: ; %cmp.true6011; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v06012; GFX11-NEXT:  ; %bb.2: ; %end6013; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s06014; GFX11-NEXT:    s_setpc_b64 s[30:31]6015  %cmp = icmp eq i32 %b, 06016  br i1 %cmp, label %cmp.true, label %cmp.false6017 6018cmp.true:6019  %a1 = add <1 x i32> %a, splat (i32 3)6020  %a2 = bitcast <1 x i32> %a1 to <2 x i16>6021  br label %end6022 6023cmp.false:6024  %a3 = bitcast <1 x i32> %a to <2 x i16>6025  br label %end6026 6027end:6028  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6029  ret <2 x i16> %phi6030}6031 6032define inreg <2 x i16> @bitcast_v1i32_to_v2i16_scalar(<1 x i32> inreg %a, i32 inreg %b) {6033; SI-LABEL: bitcast_v1i32_to_v2i16_scalar:6034; SI:       ; %bb.0:6035; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6036; SI-NEXT:    s_cmp_lg_u32 s17, 06037; SI-NEXT:    s_cbranch_scc0 .LBB55_46038; SI-NEXT:  ; %bb.1: ; %cmp.false6039; SI-NEXT:    s_lshr_b32 s6, s16, 166040; SI-NEXT:    s_cbranch_execnz .LBB55_36041; SI-NEXT:  .LBB55_2: ; %cmp.true6042; SI-NEXT:    s_add_i32 s16, s16, 36043; SI-NEXT:    s_lshr_b32 s6, s16, 166044; SI-NEXT:  .LBB55_3: ; %end6045; SI-NEXT:    v_mov_b32_e32 v0, s166046; SI-NEXT:    v_mov_b32_e32 v1, s66047; SI-NEXT:    s_setpc_b64 s[30:31]6048; SI-NEXT:  .LBB55_4:6049; SI-NEXT:    ; implicit-def: $sgpr66050; SI-NEXT:    s_branch .LBB55_26051;6052; VI-LABEL: bitcast_v1i32_to_v2i16_scalar:6053; VI:       ; %bb.0:6054; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6055; VI-NEXT:    s_cmp_lg_u32 s17, 06056; VI-NEXT:    s_cbranch_scc0 .LBB55_46057; VI-NEXT:  ; %bb.1: ; %cmp.false6058; VI-NEXT:    s_cbranch_execnz .LBB55_36059; VI-NEXT:  .LBB55_2: ; %cmp.true6060; VI-NEXT:    s_add_i32 s16, s16, 36061; VI-NEXT:  .LBB55_3: ; %end6062; VI-NEXT:    v_mov_b32_e32 v0, s166063; VI-NEXT:    s_setpc_b64 s[30:31]6064; VI-NEXT:  .LBB55_4:6065; VI-NEXT:    s_branch .LBB55_26066;6067; GFX9-LABEL: bitcast_v1i32_to_v2i16_scalar:6068; GFX9:       ; %bb.0:6069; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6070; GFX9-NEXT:    s_cmp_lg_u32 s17, 06071; GFX9-NEXT:    s_cbranch_scc0 .LBB55_46072; GFX9-NEXT:  ; %bb.1: ; %cmp.false6073; GFX9-NEXT:    s_cbranch_execnz .LBB55_36074; GFX9-NEXT:  .LBB55_2: ; %cmp.true6075; GFX9-NEXT:    s_add_i32 s16, s16, 36076; GFX9-NEXT:  .LBB55_3: ; %end6077; GFX9-NEXT:    v_mov_b32_e32 v0, s166078; GFX9-NEXT:    s_setpc_b64 s[30:31]6079; GFX9-NEXT:  .LBB55_4:6080; GFX9-NEXT:    s_branch .LBB55_26081;6082; GFX11-LABEL: bitcast_v1i32_to_v2i16_scalar:6083; GFX11:       ; %bb.0:6084; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6085; GFX11-NEXT:    s_cmp_lg_u32 s1, 06086; GFX11-NEXT:    s_mov_b32 s1, 06087; GFX11-NEXT:    s_cbranch_scc0 .LBB55_36088; GFX11-NEXT:  ; %bb.1: ; %Flow6089; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s16090; GFX11-NEXT:    s_cbranch_vccz .LBB55_46091; GFX11-NEXT:  ; %bb.2: ; %end6092; GFX11-NEXT:    v_mov_b32_e32 v0, s06093; GFX11-NEXT:    s_setpc_b64 s[30:31]6094; GFX11-NEXT:  .LBB55_3:6095; GFX11-NEXT:  .LBB55_4: ; %cmp.true6096; GFX11-NEXT:    s_add_i32 s0, s0, 36097; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6098; GFX11-NEXT:    v_mov_b32_e32 v0, s06099; GFX11-NEXT:    s_setpc_b64 s[30:31]6100  %cmp = icmp eq i32 %b, 06101  br i1 %cmp, label %cmp.true, label %cmp.false6102 6103cmp.true:6104  %a1 = add <1 x i32> %a, splat (i32 3)6105  %a2 = bitcast <1 x i32> %a1 to <2 x i16>6106  br label %end6107 6108cmp.false:6109  %a3 = bitcast <1 x i32> %a to <2 x i16>6110  br label %end6111 6112end:6113  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6114  ret <2 x i16> %phi6115}6116 6117define <4 x i8> @bitcast_v2i16_to_v4i8(<2 x i16> %a, i32 %b) {6118; SI-LABEL: bitcast_v2i16_to_v4i8:6119; SI:       ; %bb.0:6120; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6121; SI-NEXT:    v_mov_b32_e32 v4, v16122; SI-NEXT:    v_mov_b32_e32 v5, v06123; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26124; SI-NEXT:    ; implicit-def: $vgpr06125; SI-NEXT:    ; implicit-def: $vgpr16126; SI-NEXT:    ; implicit-def: $vgpr26127; SI-NEXT:    ; implicit-def: $vgpr36128; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6129; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6130; SI-NEXT:    s_cbranch_execnz .LBB56_36131; SI-NEXT:  ; %bb.1: ; %Flow6132; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6133; SI-NEXT:    s_cbranch_execnz .LBB56_46134; SI-NEXT:  .LBB56_2: ; %end6135; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6136; SI-NEXT:    s_setpc_b64 s[30:31]6137; SI-NEXT:  .LBB56_3: ; %cmp.false6138; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v56139; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v46140; SI-NEXT:    v_or_b32_e32 v0, v0, v16141; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v06142; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v46143; SI-NEXT:    v_bfe_u32 v3, v4, 8, 86144; SI-NEXT:    ; implicit-def: $vgpr56145; SI-NEXT:    ; implicit-def: $vgpr46146; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6147; SI-NEXT:    s_cbranch_execz .LBB56_26148; SI-NEXT:  .LBB56_4: ; %cmp.true6149; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v56150; SI-NEXT:    v_add_i32_e32 v3, vcc, 3, v46151; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v06152; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v36153; SI-NEXT:    v_or_b32_e32 v0, v0, v16154; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v06155; SI-NEXT:    v_and_b32_e32 v2, 0xffff, v36156; SI-NEXT:    v_bfe_u32 v3, v3, 8, 86157; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6158; SI-NEXT:    s_setpc_b64 s[30:31]6159;6160; VI-LABEL: bitcast_v2i16_to_v4i8:6161; VI:       ; %bb.0:6162; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6163; VI-NEXT:    v_mov_b32_e32 v4, v06164; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16165; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v46166; VI-NEXT:    ; implicit-def: $vgpr06167; VI-NEXT:    ; implicit-def: $vgpr16168; VI-NEXT:    ; implicit-def: $vgpr36169; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6170; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6171; VI-NEXT:    s_cbranch_execnz .LBB56_36172; VI-NEXT:  ; %bb.1: ; %Flow6173; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6174; VI-NEXT:    s_cbranch_execnz .LBB56_46175; VI-NEXT:  .LBB56_2: ; %end6176; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6177; VI-NEXT:    s_setpc_b64 s[30:31]6178; VI-NEXT:  .LBB56_3: ; %cmp.false6179; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v46180; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v46181; VI-NEXT:    v_mov_b32_e32 v0, v46182; VI-NEXT:    ; implicit-def: $vgpr46183; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6184; VI-NEXT:    s_cbranch_execz .LBB56_26185; VI-NEXT:  .LBB56_4: ; %cmp.true6186; VI-NEXT:    v_mov_b32_e32 v1, 36187; VI-NEXT:    v_add_u16_sdwa v2, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6188; VI-NEXT:    v_add_u16_e32 v0, 3, v46189; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v26190; VI-NEXT:    v_or_b32_e32 v1, v0, v16191; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v16192; VI-NEXT:    v_bfe_u32 v3, v2, 8, 86193; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6194; VI-NEXT:    s_setpc_b64 s[30:31]6195;6196; GFX9-LABEL: bitcast_v2i16_to_v4i8:6197; GFX9:       ; %bb.0:6198; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6199; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16200; GFX9-NEXT:    ; implicit-def: $vgpr16201; GFX9-NEXT:    ; implicit-def: $vgpr26202; GFX9-NEXT:    ; implicit-def: $vgpr36203; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6204; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6205; GFX9-NEXT:    s_cbranch_execnz .LBB56_36206; GFX9-NEXT:  ; %bb.1: ; %Flow6207; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6208; GFX9-NEXT:    s_cbranch_execnz .LBB56_46209; GFX9-NEXT:  .LBB56_2: ; %end6210; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6211; GFX9-NEXT:    s_setpc_b64 s[30:31]6212; GFX9-NEXT:  .LBB56_3: ; %cmp.false6213; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v06214; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v06215; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v06216; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6217; GFX9-NEXT:    s_cbranch_execz .LBB56_26218; GFX9-NEXT:  .LBB56_4: ; %cmp.true6219; GFX9-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6220; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v06221; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v06222; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v06223; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6224; GFX9-NEXT:    s_setpc_b64 s[30:31]6225;6226; GFX11-TRUE16-LABEL: bitcast_v2i16_to_v4i8:6227; GFX11-TRUE16:       ; %bb.0:6228; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6229; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v06230; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16231; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo166232; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo166233; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo6234; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6235; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s06236; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false6237; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)6238; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v26239; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v26240; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow6241; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s06242; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true6243; GFX11-TRUE16-NEXT:    v_pk_add_u16 v2, v2, 3 op_sel_hi:[1,0]6244; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6245; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v26246; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v26247; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end6248; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06249; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l6250; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h6251; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]6252;6253; GFX11-FAKE16-LABEL: bitcast_v2i16_to_v4i8:6254; GFX11-FAKE16:       ; %bb.0:6255; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6256; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v16257; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16258; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26259; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36260; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo6261; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6262; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s06263; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB56_36264; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow6265; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06266; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB56_46267; GFX11-FAKE16-NEXT:  .LBB56_2: ; %end6268; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06269; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6270; GFX11-FAKE16-NEXT:  .LBB56_3: ; %cmp.false6271; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v06272; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v06273; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v06274; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06275; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB56_26276; GFX11-FAKE16-NEXT:  .LBB56_4: ; %cmp.true6277; GFX11-FAKE16-NEXT:    v_pk_add_u16 v0, v0, 3 op_sel_hi:[1,0]6278; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6279; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v06280; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v06281; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v06282; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06283; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6284  %cmp = icmp eq i32 %b, 06285  br i1 %cmp, label %cmp.true, label %cmp.false6286 6287cmp.true:6288  %a1 = add <2 x i16> %a, splat (i16 3)6289  %a2 = bitcast <2 x i16> %a1 to <4 x i8>6290  br label %end6291 6292cmp.false:6293  %a3 = bitcast <2 x i16> %a to <4 x i8>6294  br label %end6295 6296end:6297  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6298  ret <4 x i8> %phi6299}6300 6301define inreg <4 x i8> @bitcast_v2i16_to_v4i8_scalar(<2 x i16> inreg %a, i32 inreg %b) {6302; SI-LABEL: bitcast_v2i16_to_v4i8_scalar:6303; SI:       ; %bb.0:6304; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6305; SI-NEXT:    s_cmp_lg_u32 s18, 06306; SI-NEXT:    s_cbranch_scc0 .LBB57_46307; SI-NEXT:  ; %bb.1: ; %cmp.false6308; SI-NEXT:    s_and_b32 s4, s16, 0xffff6309; SI-NEXT:    s_lshl_b32 s5, s17, 166310; SI-NEXT:    s_or_b32 s6, s4, s56311; SI-NEXT:    s_lshr_b32 s7, s6, 86312; SI-NEXT:    s_and_b32 s8, s17, 0xffff6313; SI-NEXT:    s_bfe_u32 s9, s17, 0x800086314; SI-NEXT:    s_cbranch_execnz .LBB57_36315; SI-NEXT:  .LBB57_2: ; %cmp.true6316; SI-NEXT:    s_add_i32 s16, s16, 36317; SI-NEXT:    s_add_i32 s17, s17, 36318; SI-NEXT:    s_and_b32 s4, s16, 0xffff6319; SI-NEXT:    s_lshl_b32 s5, s17, 166320; SI-NEXT:    s_or_b32 s6, s4, s56321; SI-NEXT:    s_lshr_b32 s7, s6, 86322; SI-NEXT:    s_and_b32 s8, s17, 0xffff6323; SI-NEXT:    s_bfe_u32 s9, s17, 0x800086324; SI-NEXT:  .LBB57_3: ; %end6325; SI-NEXT:    v_mov_b32_e32 v0, s66326; SI-NEXT:    v_mov_b32_e32 v1, s76327; SI-NEXT:    v_mov_b32_e32 v2, s86328; SI-NEXT:    v_mov_b32_e32 v3, s96329; SI-NEXT:    s_setpc_b64 s[30:31]6330; SI-NEXT:  .LBB57_4:6331; SI-NEXT:    ; implicit-def: $sgpr66332; SI-NEXT:    ; implicit-def: $sgpr76333; SI-NEXT:    ; implicit-def: $sgpr86334; SI-NEXT:    ; implicit-def: $sgpr96335; SI-NEXT:    s_branch .LBB57_26336;6337; VI-LABEL: bitcast_v2i16_to_v4i8_scalar:6338; VI:       ; %bb.0:6339; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6340; VI-NEXT:    s_cmp_lg_u32 s17, 06341; VI-NEXT:    s_cbranch_scc0 .LBB57_46342; VI-NEXT:  ; %bb.1: ; %cmp.false6343; VI-NEXT:    s_lshr_b32 s8, s16, 246344; VI-NEXT:    s_lshr_b32 s6, s16, 166345; VI-NEXT:    s_lshr_b32 s9, s16, 86346; VI-NEXT:    s_mov_b32 s7, s166347; VI-NEXT:    s_cbranch_execnz .LBB57_36348; VI-NEXT:  .LBB57_2: ; %cmp.true6349; VI-NEXT:    s_lshr_b32 s5, s16, 166350; VI-NEXT:    s_add_i32 s7, s16, 36351; VI-NEXT:    s_add_i32 s6, s5, 36352; VI-NEXT:    s_and_b32 s4, s7, 0xffff6353; VI-NEXT:    s_lshl_b32 s5, s6, 166354; VI-NEXT:    s_or_b32 s4, s4, s56355; VI-NEXT:    s_lshr_b32 s9, s4, 86356; VI-NEXT:    s_bfe_u32 s8, s6, 0x800086357; VI-NEXT:  .LBB57_3: ; %end6358; VI-NEXT:    v_mov_b32_e32 v0, s76359; VI-NEXT:    v_mov_b32_e32 v1, s96360; VI-NEXT:    v_mov_b32_e32 v2, s66361; VI-NEXT:    v_mov_b32_e32 v3, s86362; VI-NEXT:    s_setpc_b64 s[30:31]6363; VI-NEXT:  .LBB57_4:6364; VI-NEXT:    ; implicit-def: $sgpr76365; VI-NEXT:    ; implicit-def: $sgpr96366; VI-NEXT:    ; implicit-def: $sgpr66367; VI-NEXT:    ; implicit-def: $sgpr86368; VI-NEXT:    s_branch .LBB57_26369;6370; GFX9-LABEL: bitcast_v2i16_to_v4i8_scalar:6371; GFX9:       ; %bb.0:6372; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6373; GFX9-NEXT:    s_cmp_lg_u32 s17, 06374; GFX9-NEXT:    s_cbranch_scc0 .LBB57_36375; GFX9-NEXT:  ; %bb.1: ; %cmp.false6376; GFX9-NEXT:    s_lshr_b32 s7, s16, 246377; GFX9-NEXT:    s_lshr_b32 s6, s16, 166378; GFX9-NEXT:    s_lshr_b32 s8, s16, 86379; GFX9-NEXT:    s_cbranch_execnz .LBB57_46380; GFX9-NEXT:  .LBB57_2: ; %cmp.true6381; GFX9-NEXT:    v_pk_add_u16 v0, s16, 3 op_sel_hi:[1,0]6382; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v06383; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v06384; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v06385; GFX9-NEXT:    s_setpc_b64 s[30:31]6386; GFX9-NEXT:  .LBB57_3:6387; GFX9-NEXT:    ; implicit-def: $sgpr86388; GFX9-NEXT:    ; implicit-def: $sgpr66389; GFX9-NEXT:    ; implicit-def: $sgpr76390; GFX9-NEXT:    s_branch .LBB57_26391; GFX9-NEXT:  .LBB57_4:6392; GFX9-NEXT:    v_mov_b32_e32 v0, s166393; GFX9-NEXT:    v_mov_b32_e32 v1, s86394; GFX9-NEXT:    v_mov_b32_e32 v3, s76395; GFX9-NEXT:    v_mov_b32_e32 v2, s66396; GFX9-NEXT:    s_setpc_b64 s[30:31]6397;6398; GFX11-LABEL: bitcast_v2i16_to_v4i8_scalar:6399; GFX11:       ; %bb.0:6400; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6401; GFX11-NEXT:    s_cmp_lg_u32 s1, 06402; GFX11-NEXT:    s_mov_b32 s1, 06403; GFX11-NEXT:    s_cbranch_scc0 .LBB57_36404; GFX11-NEXT:  ; %bb.1: ; %cmp.false6405; GFX11-NEXT:    s_lshr_b32 s3, s0, 246406; GFX11-NEXT:    s_lshr_b32 s2, s0, 166407; GFX11-NEXT:    s_lshr_b32 s4, s0, 86408; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s16409; GFX11-NEXT:    s_cbranch_vccnz .LBB57_46410; GFX11-NEXT:  .LBB57_2: ; %cmp.true6411; GFX11-NEXT:    v_pk_add_u16 v0, s0, 3 op_sel_hi:[1,0]6412; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)6413; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v06414; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v06415; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v06416; GFX11-NEXT:    s_setpc_b64 s[30:31]6417; GFX11-NEXT:  .LBB57_3:6418; GFX11-NEXT:    ; implicit-def: $sgpr46419; GFX11-NEXT:    ; implicit-def: $sgpr26420; GFX11-NEXT:    ; implicit-def: $sgpr36421; GFX11-NEXT:    s_branch .LBB57_26422; GFX11-NEXT:  .LBB57_4:6423; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s46424; GFX11-NEXT:    v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s26425; GFX11-NEXT:    s_setpc_b64 s[30:31]6426  %cmp = icmp eq i32 %b, 06427  br i1 %cmp, label %cmp.true, label %cmp.false6428 6429cmp.true:6430  %a1 = add <2 x i16> %a, splat (i16 3)6431  %a2 = bitcast <2 x i16> %a1 to <4 x i8>6432  br label %end6433 6434cmp.false:6435  %a3 = bitcast <2 x i16> %a to <4 x i8>6436  br label %end6437 6438end:6439  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6440  ret <4 x i8> %phi6441}6442 6443define <2 x i16> @bitcast_v4i8_to_v2i16(<4 x i8> %a, i32 %b) {6444; SI-LABEL: bitcast_v4i8_to_v2i16:6445; SI:       ; %bb.0:6446; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6447; SI-NEXT:    v_mov_b32_e32 v5, v06448; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v46449; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v16450; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v36451; SI-NEXT:    ; implicit-def: $vgpr06452; SI-NEXT:    ; implicit-def: $vgpr16453; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6454; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6455; SI-NEXT:    s_cbranch_execnz .LBB58_36456; SI-NEXT:  ; %bb.1: ; %Flow6457; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6458; SI-NEXT:    s_cbranch_execnz .LBB58_46459; SI-NEXT:  .LBB58_2: ; %end6460; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6461; SI-NEXT:    s_setpc_b64 s[30:31]6462; SI-NEXT:  .LBB58_3: ; %cmp.false6463; SI-NEXT:    v_and_b32_e32 v0, 0xff, v56464; SI-NEXT:    v_and_b32_e32 v1, 0xff, v26465; SI-NEXT:    v_or_b32_e32 v0, v0, v46466; SI-NEXT:    v_or_b32_e32 v1, v1, v36467; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v06468; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v16469; SI-NEXT:    v_or_b32_e32 v0, v0, v26470; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v16471; SI-NEXT:    ; implicit-def: $vgpr56472; SI-NEXT:    ; implicit-def: $vgpr46473; SI-NEXT:    ; implicit-def: $vgpr26474; SI-NEXT:    ; implicit-def: $vgpr36475; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6476; SI-NEXT:    s_cbranch_execz .LBB58_26477; SI-NEXT:  .LBB58_4: ; %cmp.true6478; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v56479; SI-NEXT:    v_add_i32_e32 v1, vcc, 3, v26480; SI-NEXT:    v_and_b32_e32 v0, 0xff, v06481; SI-NEXT:    v_and_b32_e32 v1, 0xff, v16482; SI-NEXT:    v_or_b32_e32 v0, v4, v06483; SI-NEXT:    v_or_b32_e32 v1, v3, v16484; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v06485; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v16486; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v06487; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v16488; SI-NEXT:    v_or_b32_e32 v0, v0, v26489; SI-NEXT:    v_and_b32_e32 v1, 0xffff, v16490; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6491; SI-NEXT:    s_setpc_b64 s[30:31]6492;6493; VI-LABEL: bitcast_v4i8_to_v2i16:6494; VI:       ; %bb.0:6495; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6496; VI-NEXT:    v_mov_b32_e32 v5, v06497; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v46498; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v16499; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v36500; VI-NEXT:    ; implicit-def: $vgpr06501; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6502; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6503; VI-NEXT:    s_cbranch_execnz .LBB58_36504; VI-NEXT:  ; %bb.1: ; %Flow6505; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6506; VI-NEXT:    s_cbranch_execnz .LBB58_46507; VI-NEXT:  .LBB58_2: ; %end6508; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6509; VI-NEXT:    s_setpc_b64 s[30:31]6510; VI-NEXT:  .LBB58_3: ; %cmp.false6511; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6512; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6513; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6514; VI-NEXT:    ; implicit-def: $vgpr56515; VI-NEXT:    ; implicit-def: $vgpr46516; VI-NEXT:    ; implicit-def: $vgpr26517; VI-NEXT:    ; implicit-def: $vgpr16518; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6519; VI-NEXT:    s_cbranch_execz .LBB58_26520; VI-NEXT:  .LBB58_4: ; %cmp.true6521; VI-NEXT:    v_add_u16_e32 v0, 3, v56522; VI-NEXT:    v_add_u16_e32 v2, 3, v26523; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06524; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06525; VI-NEXT:    v_mov_b32_e32 v2, 0x3006526; VI-NEXT:    v_add_u16_e32 v0, 0x300, v06527; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6528; VI-NEXT:    v_or_b32_e32 v0, v0, v16529; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6530; VI-NEXT:    s_setpc_b64 s[30:31]6531;6532; GFX9-LABEL: bitcast_v4i8_to_v2i16:6533; GFX9:       ; %bb.0:6534; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6535; GFX9-NEXT:    v_mov_b32_e32 v5, v06536; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v46537; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v16538; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v36539; GFX9-NEXT:    ; implicit-def: $vgpr06540; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6541; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6542; GFX9-NEXT:    s_cbranch_execnz .LBB58_36543; GFX9-NEXT:  ; %bb.1: ; %Flow6544; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6545; GFX9-NEXT:    s_cbranch_execnz .LBB58_46546; GFX9-NEXT:  .LBB58_2: ; %end6547; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6548; GFX9-NEXT:    s_setpc_b64 s[30:31]6549; GFX9-NEXT:  .LBB58_3: ; %cmp.false6550; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6551; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD6552; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD6553; GFX9-NEXT:    ; implicit-def: $vgpr56554; GFX9-NEXT:    ; implicit-def: $vgpr46555; GFX9-NEXT:    ; implicit-def: $vgpr26556; GFX9-NEXT:    ; implicit-def: $vgpr16557; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6558; GFX9-NEXT:    s_cbranch_execz .LBB58_26559; GFX9-NEXT:  .LBB58_4: ; %cmp.true6560; GFX9-NEXT:    v_add_u16_e32 v0, 3, v56561; GFX9-NEXT:    v_add_u16_e32 v2, 3, v26562; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06563; GFX9-NEXT:    s_movk_i32 s6, 0x3006564; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_06565; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v06566; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6567; GFX9-NEXT:    v_or_b32_e32 v0, v0, v16568; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6569; GFX9-NEXT:    s_setpc_b64 s[30:31]6570;6571; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2i16:6572; GFX11-TRUE16:       ; %bb.0:6573; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6574; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l6575; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l6576; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l6577; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo6578; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr06579; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v46580; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s06581; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB58_36582; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow6583; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s06584; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB58_46585; GFX11-TRUE16-NEXT:  .LBB58_2: ; %end6586; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06587; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]6588; GFX11-TRUE16-NEXT:  .LBB58_3: ; %cmp.false6589; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h6590; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l6591; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi166592; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo166593; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6594; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l6595; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h6596; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo166597; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi166598; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s06599; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB58_26600; GFX11-TRUE16-NEXT:  .LBB58_4: ; %cmp.true6601; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 36602; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 36603; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6604; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l6605; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h6606; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6607; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l6608; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h6609; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6610; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l6611; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h6612; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06613; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]6614;6615; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2i16:6616; GFX11-FAKE16:       ; %bb.0:6617; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6618; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v06619; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v16620; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v36621; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo6622; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr06623; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v46624; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s06625; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB58_36626; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow6627; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06628; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB58_46629; GFX11-FAKE16-NEXT:  .LBB58_2: ; %end6630; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06631; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6632; GFX11-FAKE16-NEXT:  .LBB58_3: ; %cmp.false6633; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v56634; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v26635; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr56636; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6637; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16638; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v36639; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr26640; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr36641; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6642; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v06643; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v16644; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6645; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16646; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr16647; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s06648; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB58_26649; GFX11-FAKE16-NEXT:  .LBB58_4: ; %cmp.true6650; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 36651; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 36652; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6653; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v06654; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v26655; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6656; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v06657; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v26658; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6659; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v06660; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v16661; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)6662; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v06663; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v16664; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)6665; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v16666; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s06667; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]6668  %cmp = icmp eq i32 %b, 06669  br i1 %cmp, label %cmp.true, label %cmp.false6670 6671cmp.true:6672  %a1 = add <4 x i8> %a, splat (i8 3)6673  %a2 = bitcast <4 x i8> %a1 to <2 x i16>6674  br label %end6675 6676cmp.false:6677  %a3 = bitcast <4 x i8> %a to <2 x i16>6678  br label %end6679 6680end:6681  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6682  ret <2 x i16> %phi6683}6684 6685define inreg <2 x i16> @bitcast_v4i8_to_v2i16_scalar(<4 x i8> inreg %a, i32 inreg %b) {6686; SI-LABEL: bitcast_v4i8_to_v2i16_scalar:6687; SI:       ; %bb.0:6688; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6689; SI-NEXT:    s_cmp_lg_u32 s20, 06690; SI-NEXT:    s_cbranch_scc0 .LBB59_46691; SI-NEXT:  ; %bb.1: ; %cmp.false6692; SI-NEXT:    s_and_b32 s4, s16, 0xff6693; SI-NEXT:    s_lshl_b32 s5, s17, 86694; SI-NEXT:    s_or_b32 s4, s4, s56695; SI-NEXT:    s_and_b32 s5, s18, 0xff6696; SI-NEXT:    s_lshl_b32 s6, s19, 86697; SI-NEXT:    s_or_b32 s5, s5, s66698; SI-NEXT:    s_and_b32 s4, s4, 0xffff6699; SI-NEXT:    s_lshl_b32 s6, s5, 166700; SI-NEXT:    s_or_b32 s6, s4, s66701; SI-NEXT:    s_and_b32 s7, s5, 0xffff6702; SI-NEXT:    s_cbranch_execnz .LBB59_36703; SI-NEXT:  .LBB59_2: ; %cmp.true6704; SI-NEXT:    s_add_i32 s16, s16, 36705; SI-NEXT:    s_and_b32 s4, s16, 0xff6706; SI-NEXT:    s_lshl_b32 s5, s17, 86707; SI-NEXT:    s_add_i32 s18, s18, 36708; SI-NEXT:    s_or_b32 s4, s5, s46709; SI-NEXT:    s_and_b32 s5, s18, 0xff6710; SI-NEXT:    s_lshl_b32 s6, s19, 86711; SI-NEXT:    s_or_b32 s5, s6, s56712; SI-NEXT:    s_addk_i32 s4, 0x3006713; SI-NEXT:    s_addk_i32 s5, 0x3006714; SI-NEXT:    s_and_b32 s4, s4, 0xffff6715; SI-NEXT:    s_lshl_b32 s6, s5, 166716; SI-NEXT:    s_or_b32 s6, s4, s66717; SI-NEXT:    s_and_b32 s7, s5, 0xffff6718; SI-NEXT:  .LBB59_3: ; %end6719; SI-NEXT:    v_mov_b32_e32 v0, s66720; SI-NEXT:    v_mov_b32_e32 v1, s76721; SI-NEXT:    s_setpc_b64 s[30:31]6722; SI-NEXT:  .LBB59_4:6723; SI-NEXT:    ; implicit-def: $sgpr66724; SI-NEXT:    ; implicit-def: $sgpr76725; SI-NEXT:    s_branch .LBB59_26726;6727; VI-LABEL: bitcast_v4i8_to_v2i16_scalar:6728; VI:       ; %bb.0:6729; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6730; VI-NEXT:    s_cmp_lg_u32 s20, 06731; VI-NEXT:    s_cbranch_scc0 .LBB59_46732; VI-NEXT:  ; %bb.1: ; %cmp.false6733; VI-NEXT:    s_and_b32 s4, s16, 0xff6734; VI-NEXT:    s_lshl_b32 s5, s17, 86735; VI-NEXT:    s_or_b32 s4, s4, s56736; VI-NEXT:    s_and_b32 s5, s18, 0xff6737; VI-NEXT:    s_lshl_b32 s6, s19, 86738; VI-NEXT:    s_or_b32 s5, s5, s66739; VI-NEXT:    s_and_b32 s4, s4, 0xffff6740; VI-NEXT:    s_lshl_b32 s5, s5, 166741; VI-NEXT:    s_or_b32 s6, s4, s56742; VI-NEXT:    s_cbranch_execnz .LBB59_36743; VI-NEXT:  .LBB59_2: ; %cmp.true6744; VI-NEXT:    s_add_i32 s16, s16, 36745; VI-NEXT:    s_and_b32 s4, s16, 0xff6746; VI-NEXT:    s_lshl_b32 s5, s17, 86747; VI-NEXT:    s_add_i32 s18, s18, 36748; VI-NEXT:    s_or_b32 s4, s5, s46749; VI-NEXT:    s_and_b32 s5, s18, 0xff6750; VI-NEXT:    s_lshl_b32 s6, s19, 86751; VI-NEXT:    s_addk_i32 s4, 0x3006752; VI-NEXT:    s_or_b32 s5, s6, s56753; VI-NEXT:    s_and_b32 s4, s4, 0xffff6754; VI-NEXT:    s_lshl_b32 s5, s5, 166755; VI-NEXT:    s_or_b32 s4, s5, s46756; VI-NEXT:    s_add_i32 s6, s4, 0x30000006757; VI-NEXT:  .LBB59_3: ; %end6758; VI-NEXT:    v_mov_b32_e32 v0, s66759; VI-NEXT:    s_setpc_b64 s[30:31]6760; VI-NEXT:  .LBB59_4:6761; VI-NEXT:    ; implicit-def: $sgpr66762; VI-NEXT:    s_branch .LBB59_26763;6764; GFX9-LABEL: bitcast_v4i8_to_v2i16_scalar:6765; GFX9:       ; %bb.0:6766; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6767; GFX9-NEXT:    s_cmp_lg_u32 s20, 06768; GFX9-NEXT:    s_cbranch_scc0 .LBB59_46769; GFX9-NEXT:  ; %bb.1: ; %cmp.false6770; GFX9-NEXT:    s_and_b32 s4, s16, 0xff6771; GFX9-NEXT:    s_lshl_b32 s5, s17, 86772; GFX9-NEXT:    s_or_b32 s4, s4, s56773; GFX9-NEXT:    s_and_b32 s5, s18, 0xff6774; GFX9-NEXT:    s_lshl_b32 s6, s19, 86775; GFX9-NEXT:    s_or_b32 s5, s5, s66776; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff6777; GFX9-NEXT:    s_lshl_b32 s5, s5, 166778; GFX9-NEXT:    s_or_b32 s6, s4, s56779; GFX9-NEXT:    s_cbranch_execnz .LBB59_36780; GFX9-NEXT:  .LBB59_2: ; %cmp.true6781; GFX9-NEXT:    s_add_i32 s16, s16, 36782; GFX9-NEXT:    s_and_b32 s4, s16, 0xff6783; GFX9-NEXT:    s_lshl_b32 s5, s17, 86784; GFX9-NEXT:    s_add_i32 s18, s18, 36785; GFX9-NEXT:    s_or_b32 s4, s5, s46786; GFX9-NEXT:    s_and_b32 s5, s18, 0xff6787; GFX9-NEXT:    s_lshl_b32 s6, s19, 86788; GFX9-NEXT:    s_or_b32 s5, s6, s56789; GFX9-NEXT:    s_addk_i32 s4, 0x3006790; GFX9-NEXT:    s_addk_i32 s5, 0x3006791; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff6792; GFX9-NEXT:    s_lshl_b32 s5, s5, 166793; GFX9-NEXT:    s_or_b32 s6, s4, s56794; GFX9-NEXT:  .LBB59_3: ; %end6795; GFX9-NEXT:    v_mov_b32_e32 v0, s66796; GFX9-NEXT:    s_setpc_b64 s[30:31]6797; GFX9-NEXT:  .LBB59_4:6798; GFX9-NEXT:    ; implicit-def: $sgpr66799; GFX9-NEXT:    s_branch .LBB59_26800;6801; GFX11-LABEL: bitcast_v4i8_to_v2i16_scalar:6802; GFX11:       ; %bb.0:6803; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6804; GFX11-NEXT:    s_cmp_lg_u32 s16, 06805; GFX11-NEXT:    s_mov_b32 s4, 06806; GFX11-NEXT:    s_cbranch_scc0 .LBB59_46807; GFX11-NEXT:  ; %bb.1: ; %cmp.false6808; GFX11-NEXT:    s_and_b32 s5, s0, 0xff6809; GFX11-NEXT:    s_lshl_b32 s6, s1, 86810; GFX11-NEXT:    s_and_b32 s7, s2, 0xff6811; GFX11-NEXT:    s_lshl_b32 s8, s3, 86812; GFX11-NEXT:    s_or_b32 s5, s5, s66813; GFX11-NEXT:    s_or_b32 s6, s7, s86814; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff6815; GFX11-NEXT:    s_lshl_b32 s6, s6, 166816; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6817; GFX11-NEXT:    s_or_b32 s5, s5, s66818; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s46819; GFX11-NEXT:    s_cbranch_vccnz .LBB59_36820; GFX11-NEXT:  .LBB59_2: ; %cmp.true6821; GFX11-NEXT:    s_add_i32 s0, s0, 36822; GFX11-NEXT:    s_add_i32 s2, s2, 36823; GFX11-NEXT:    s_and_b32 s0, s0, 0xff6824; GFX11-NEXT:    s_lshl_b32 s1, s1, 86825; GFX11-NEXT:    s_and_b32 s2, s2, 0xff6826; GFX11-NEXT:    s_lshl_b32 s3, s3, 86827; GFX11-NEXT:    s_or_b32 s0, s1, s06828; GFX11-NEXT:    s_or_b32 s1, s3, s26829; GFX11-NEXT:    s_addk_i32 s0, 0x3006830; GFX11-NEXT:    s_addk_i32 s1, 0x3006831; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff6832; GFX11-NEXT:    s_lshl_b32 s1, s1, 166833; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6834; GFX11-NEXT:    s_or_b32 s5, s0, s16835; GFX11-NEXT:  .LBB59_3: ; %end6836; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6837; GFX11-NEXT:    v_mov_b32_e32 v0, s56838; GFX11-NEXT:    s_setpc_b64 s[30:31]6839; GFX11-NEXT:  .LBB59_4:6840; GFX11-NEXT:    ; implicit-def: $sgpr56841; GFX11-NEXT:    s_branch .LBB59_26842  %cmp = icmp eq i32 %b, 06843  br i1 %cmp, label %cmp.true, label %cmp.false6844 6845cmp.true:6846  %a1 = add <4 x i8> %a, splat (i8 3)6847  %a2 = bitcast <4 x i8> %a1 to <2 x i16>6848  br label %end6849 6850cmp.false:6851  %a3 = bitcast <4 x i8> %a to <2 x i16>6852  br label %end6853 6854end:6855  %phi = phi <2 x i16> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6856  ret <2 x i16> %phi6857}6858 6859define <2 x bfloat> @bitcast_v2f16_to_v2bf16(<2 x half> %a, i32 %b) {6860; SI-LABEL: bitcast_v2f16_to_v2bf16:6861; SI:       ; %bb.0:6862; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6863; SI-NEXT:    v_cvt_f16_f32_e32 v3, v06864; SI-NEXT:    v_cvt_f16_f32_e32 v4, v16865; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v26866; SI-NEXT:    ; implicit-def: $vgpr06867; SI-NEXT:    ; implicit-def: $vgpr16868; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6869; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6870; SI-NEXT:    s_cbranch_execnz .LBB60_36871; SI-NEXT:  ; %bb.1: ; %Flow6872; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6873; SI-NEXT:    s_cbranch_execnz .LBB60_46874; SI-NEXT:  .LBB60_2: ; %end6875; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6876; SI-NEXT:    s_setpc_b64 s[30:31]6877; SI-NEXT:  .LBB60_3: ; %cmp.false6878; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v36879; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v46880; SI-NEXT:    ; implicit-def: $vgpr46881; SI-NEXT:    ; implicit-def: $vgpr36882; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6883; SI-NEXT:    s_cbranch_execz .LBB60_26884; SI-NEXT:  .LBB60_4: ; %cmp.true6885; SI-NEXT:    v_cvt_f32_f16_e32 v0, v46886; SI-NEXT:    v_cvt_f32_f16_e32 v1, v36887; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v06888; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v16889; SI-NEXT:    v_cvt_f16_f32_e32 v1, v16890; SI-NEXT:    v_cvt_f16_f32_e32 v2, v06891; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v16892; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v26893; SI-NEXT:    s_or_b64 exec, exec, s[4:5]6894; SI-NEXT:    s_setpc_b64 s[30:31]6895;6896; VI-LABEL: bitcast_v2f16_to_v2bf16:6897; VI:       ; %bb.0:6898; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6899; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16900; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc6901; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6902; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6903; VI-NEXT:  ; %bb.1: ; %cmp.true6904; VI-NEXT:    v_mov_b32_e32 v2, 0x2006905; VI-NEXT:    v_add_f16_e32 v1, 0x200, v06906; VI-NEXT:    v_add_f16_sdwa v0, v0, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD6907; VI-NEXT:    v_or_b32_e32 v0, v1, v06908; VI-NEXT:  ; %bb.2: ; %end6909; VI-NEXT:    s_or_b64 exec, exec, s[4:5]6910; VI-NEXT:    s_setpc_b64 s[30:31]6911;6912; GFX9-LABEL: bitcast_v2f16_to_v2bf16:6913; GFX9:       ; %bb.0:6914; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6915; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v16916; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc6917; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]6918; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]6919; GFX9-NEXT:  ; %bb.1: ; %cmp.true6920; GFX9-NEXT:    s_movk_i32 s6, 0x2006921; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]6922; GFX9-NEXT:  ; %bb.2: ; %end6923; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]6924; GFX9-NEXT:    s_setpc_b64 s[30:31]6925;6926; GFX11-LABEL: bitcast_v2f16_to_v2bf16:6927; GFX11:       ; %bb.0:6928; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6929; GFX11-NEXT:    s_mov_b32 s0, exec_lo6930; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v16931; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s06932; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)6933; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s06934; GFX11-NEXT:  ; %bb.1: ; %cmp.true6935; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]6936; GFX11-NEXT:  ; %bb.2: ; %end6937; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s06938; GFX11-NEXT:    s_setpc_b64 s[30:31]6939  %cmp = icmp eq i32 %b, 06940  br i1 %cmp, label %cmp.true, label %cmp.false6941 6942cmp.true:6943  %a1 = fadd <2 x half> %a, splat (half 0xH0200)6944  %a2 = bitcast <2 x half> %a1 to <2 x bfloat>6945  br label %end6946 6947cmp.false:6948  %a3 = bitcast <2 x half> %a to <2 x bfloat>6949  br label %end6950 6951end:6952  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]6953  ret <2 x bfloat> %phi6954}6955 6956define inreg <2 x bfloat> @bitcast_v2f16_to_v2bf16_scalar(<2 x half> inreg %a, i32 inreg %b) {6957; SI-LABEL: bitcast_v2f16_to_v2bf16_scalar:6958; SI:       ; %bb.0:6959; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6960; SI-NEXT:    v_cvt_f16_f32_e32 v2, s166961; SI-NEXT:    v_cvt_f16_f32_e32 v3, s176962; SI-NEXT:    s_cmp_lg_u32 s18, 06963; SI-NEXT:    s_cbranch_scc0 .LBB61_46964; SI-NEXT:  ; %bb.1: ; %cmp.false6965; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v26966; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v36967; SI-NEXT:    s_cbranch_execnz .LBB61_36968; SI-NEXT:  .LBB61_2: ; %cmp.true6969; SI-NEXT:    v_cvt_f32_f16_e32 v0, v36970; SI-NEXT:    v_cvt_f32_f16_e32 v1, v26971; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v06972; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v16973; SI-NEXT:    v_cvt_f16_f32_e32 v1, v16974; SI-NEXT:    v_cvt_f16_f32_e32 v2, v06975; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v16976; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v26977; SI-NEXT:  .LBB61_3: ; %end6978; SI-NEXT:    s_setpc_b64 s[30:31]6979; SI-NEXT:  .LBB61_4:6980; SI-NEXT:    ; implicit-def: $vgpr06981; SI-NEXT:    ; implicit-def: $vgpr16982; SI-NEXT:    s_branch .LBB61_26983;6984; VI-LABEL: bitcast_v2f16_to_v2bf16_scalar:6985; VI:       ; %bb.0:6986; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)6987; VI-NEXT:    s_cmp_lg_u32 s17, 06988; VI-NEXT:    s_cbranch_scc0 .LBB61_36989; VI-NEXT:  ; %bb.1: ; %cmp.false6990; VI-NEXT:    s_cbranch_execnz .LBB61_46991; VI-NEXT:  .LBB61_2: ; %cmp.true6992; VI-NEXT:    s_lshr_b32 s4, s16, 166993; VI-NEXT:    v_mov_b32_e32 v0, 0x2006994; VI-NEXT:    v_mov_b32_e32 v2, s46995; VI-NEXT:    v_add_f16_e32 v1, s16, v06996; VI-NEXT:    v_add_f16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD6997; VI-NEXT:    v_or_b32_e32 v0, v1, v06998; VI-NEXT:    s_setpc_b64 s[30:31]6999; VI-NEXT:  .LBB61_3:7000; VI-NEXT:    s_branch .LBB61_27001; VI-NEXT:  .LBB61_4:7002; VI-NEXT:    v_mov_b32_e32 v0, s167003; VI-NEXT:    s_setpc_b64 s[30:31]7004;7005; GFX9-LABEL: bitcast_v2f16_to_v2bf16_scalar:7006; GFX9:       ; %bb.0:7007; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7008; GFX9-NEXT:    s_cmp_lg_u32 s17, 07009; GFX9-NEXT:    s_cbranch_scc0 .LBB61_37010; GFX9-NEXT:  ; %bb.1: ; %cmp.false7011; GFX9-NEXT:    s_cbranch_execnz .LBB61_47012; GFX9-NEXT:  .LBB61_2: ; %cmp.true7013; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2007014; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]7015; GFX9-NEXT:    s_setpc_b64 s[30:31]7016; GFX9-NEXT:  .LBB61_3:7017; GFX9-NEXT:    s_branch .LBB61_27018; GFX9-NEXT:  .LBB61_4:7019; GFX9-NEXT:    v_mov_b32_e32 v0, s167020; GFX9-NEXT:    s_setpc_b64 s[30:31]7021;7022; GFX11-LABEL: bitcast_v2f16_to_v2bf16_scalar:7023; GFX11:       ; %bb.0:7024; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7025; GFX11-NEXT:    s_cmp_lg_u32 s1, 07026; GFX11-NEXT:    s_mov_b32 s1, 07027; GFX11-NEXT:    s_cbranch_scc0 .LBB61_37028; GFX11-NEXT:  ; %bb.1: ; %Flow7029; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s17030; GFX11-NEXT:    s_cbranch_vccnz .LBB61_47031; GFX11-NEXT:  .LBB61_2: ; %cmp.true7032; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]7033; GFX11-NEXT:    s_setpc_b64 s[30:31]7034; GFX11-NEXT:  .LBB61_3:7035; GFX11-NEXT:    s_branch .LBB61_27036; GFX11-NEXT:  .LBB61_4:7037; GFX11-NEXT:    v_mov_b32_e32 v0, s07038; GFX11-NEXT:    s_setpc_b64 s[30:31]7039  %cmp = icmp eq i32 %b, 07040  br i1 %cmp, label %cmp.true, label %cmp.false7041 7042cmp.true:7043  %a1 = fadd <2 x half> %a, splat (half 0xH0200)7044  %a2 = bitcast <2 x half> %a1 to <2 x bfloat>7045  br label %end7046 7047cmp.false:7048  %a3 = bitcast <2 x half> %a to <2 x bfloat>7049  br label %end7050 7051end:7052  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7053  ret <2 x bfloat> %phi7054}7055 7056define <2 x half> @bitcast_v2bf16_to_v2f16(<2 x bfloat> %a, i32 %b) {7057; SI-LABEL: bitcast_v2bf16_to_v2f16:7058; SI:       ; %bb.0:7059; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7060; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27061; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v07062; SI-NEXT:    v_mul_f32_e32 v3, 1.0, v17063; SI-NEXT:    ; implicit-def: $vgpr07064; SI-NEXT:    ; implicit-def: $vgpr17065; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7066; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7067; SI-NEXT:    s_cbranch_execnz .LBB62_37068; SI-NEXT:  ; %bb.1: ; %Flow7069; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7070; SI-NEXT:    s_cbranch_execnz .LBB62_47071; SI-NEXT:  .LBB62_2: ; %end7072; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7073; SI-NEXT:    s_setpc_b64 s[30:31]7074; SI-NEXT:  .LBB62_3: ; %cmp.false7075; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v27076; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v37077; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07078; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17079; SI-NEXT:    ; implicit-def: $vgpr37080; SI-NEXT:    ; implicit-def: $vgpr27081; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7082; SI-NEXT:    s_cbranch_execz .LBB62_27083; SI-NEXT:  .LBB62_4: ; %cmp.true7084; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v37085; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07086; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v07087; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v27088; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07089; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v07090; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07091; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17092; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7093; SI-NEXT:    s_setpc_b64 s[30:31]7094;7095; VI-LABEL: bitcast_v2bf16_to_v2f16:7096; VI:       ; %bb.0:7097; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7098; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17099; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7100; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7101; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7102; VI-NEXT:    s_cbranch_execz .LBB62_27103; VI-NEXT:  ; %bb.1: ; %cmp.true7104; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v07105; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v17106; VI-NEXT:    v_bfe_u32 v2, v1, 16, 17107; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v17108; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v27109; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v07110; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v17111; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v17112; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07113; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc7114; VI-NEXT:    v_bfe_u32 v2, v0, 16, 17115; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v07116; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v27117; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v07118; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v07119; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc7120; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v07121; VI-NEXT:    v_alignbit_b32 v0, v0, v1, 167122; VI-NEXT:  .LBB62_2: ; %end7123; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7124; VI-NEXT:    s_setpc_b64 s[30:31]7125;7126; GFX9-LABEL: bitcast_v2bf16_to_v2f16:7127; GFX9:       ; %bb.0:7128; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7129; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17130; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7131; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7132; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7133; GFX9-NEXT:    s_cbranch_execz .LBB62_27134; GFX9-NEXT:  ; %bb.1: ; %cmp.true7135; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v07136; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v17137; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 17138; GFX9-NEXT:    s_movk_i32 s6, 0x7fff7139; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v07140; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s67141; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v17142; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v17143; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07144; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc7145; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 17146; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s67147; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v07148; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v07149; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc7150; GFX9-NEXT:    s_mov_b32 s6, 0x70603027151; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s67152; GFX9-NEXT:  .LBB62_2: ; %end7153; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7154; GFX9-NEXT:    s_setpc_b64 s[30:31]7155;7156; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2f16:7157; GFX11-TRUE16:       ; %bb.0:7158; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7159; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17160; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr17161; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo7162; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7163; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s07164; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false7165; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v07166; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr07167; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow7168; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s07169; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB62_47170; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true7171; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v07172; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v07173; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7174; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v07175; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 17176; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)7177; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 17178; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v17179; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v17180; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v07181; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff7182; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff7183; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)7184; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo7185; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v07186; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo7187; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)7188; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h7189; GFX11-TRUE16-NEXT:  .LBB62_4: ; %end7190; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s07191; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)7192; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v17193; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]7194;7195; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2f16:7196; GFX11-FAKE16:       ; %bb.0:7197; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7198; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo7199; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v17200; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s07201; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7202; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s07203; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB62_27204; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true7205; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v07206; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v07207; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7208; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v07209; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 17210; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)7211; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 17212; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v17213; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v17214; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v07215; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff7216; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff7217; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)7218; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo7219; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v07220; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo7221; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)7222; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x70603027223; GFX11-FAKE16-NEXT:  .LBB62_2: ; %end7224; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s07225; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7226  %cmp = icmp eq i32 %b, 07227  br i1 %cmp, label %cmp.true, label %cmp.false7228 7229cmp.true:7230  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)7231  %a2 = bitcast <2 x bfloat> %a1 to <2 x half>7232  br label %end7233 7234cmp.false:7235  %a3 = bitcast <2 x bfloat> %a to <2 x half>7236  br label %end7237 7238end:7239  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7240  ret <2 x half> %phi7241}7242 7243define inreg <2 x half> @bitcast_v2bf16_to_v2f16_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {7244; SI-LABEL: bitcast_v2bf16_to_v2f16_scalar:7245; SI:       ; %bb.0:7246; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7247; SI-NEXT:    s_cmp_lg_u32 s18, 07248; SI-NEXT:    v_mul_f32_e64 v2, 1.0, s167249; SI-NEXT:    v_mul_f32_e64 v3, 1.0, s177250; SI-NEXT:    s_cbranch_scc0 .LBB63_47251; SI-NEXT:  ; %bb.1: ; %cmp.false7252; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v27253; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v37254; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07255; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17256; SI-NEXT:    s_cbranch_execnz .LBB63_37257; SI-NEXT:  .LBB63_2: ; %cmp.true7258; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v37259; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07260; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v07261; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v27262; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v07263; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v07264; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07265; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17266; SI-NEXT:  .LBB63_3: ; %end7267; SI-NEXT:    s_setpc_b64 s[30:31]7268; SI-NEXT:  .LBB63_4:7269; SI-NEXT:    ; implicit-def: $vgpr07270; SI-NEXT:    ; implicit-def: $vgpr17271; SI-NEXT:    s_branch .LBB63_27272;7273; VI-LABEL: bitcast_v2bf16_to_v2f16_scalar:7274; VI:       ; %bb.0:7275; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7276; VI-NEXT:    s_cmp_lg_u32 s17, 07277; VI-NEXT:    s_cbranch_scc0 .LBB63_37278; VI-NEXT:  ; %bb.1: ; %cmp.false7279; VI-NEXT:    s_cbranch_execnz .LBB63_47280; VI-NEXT:  .LBB63_2: ; %cmp.true7281; VI-NEXT:    s_lshl_b32 s4, s16, 167282; VI-NEXT:    v_mov_b32_e32 v1, 0x40c000007283; VI-NEXT:    v_add_f32_e32 v0, s4, v17284; VI-NEXT:    v_bfe_u32 v2, v0, 16, 17285; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v07286; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v27287; VI-NEXT:    s_and_b32 s4, s16, 0xffff00007288; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v07289; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v07290; VI-NEXT:    v_add_f32_e32 v1, s4, v17291; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc7292; VI-NEXT:    v_bfe_u32 v2, v1, 16, 17293; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v17294; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v27295; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v17296; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v17297; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc7298; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v17299; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]7300; VI-NEXT:    s_setpc_b64 s[30:31]7301; VI-NEXT:  .LBB63_3:7302; VI-NEXT:    s_branch .LBB63_27303; VI-NEXT:  .LBB63_4:7304; VI-NEXT:    v_mov_b32_e32 v0, s167305; VI-NEXT:    s_setpc_b64 s[30:31]7306;7307; GFX9-LABEL: bitcast_v2bf16_to_v2f16_scalar:7308; GFX9:       ; %bb.0:7309; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7310; GFX9-NEXT:    s_cmp_lg_u32 s17, 07311; GFX9-NEXT:    s_cbranch_scc0 .LBB63_37312; GFX9-NEXT:  ; %bb.1: ; %cmp.false7313; GFX9-NEXT:    s_cbranch_execnz .LBB63_47314; GFX9-NEXT:  .LBB63_2: ; %cmp.true7315; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00007316; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000007317; GFX9-NEXT:    v_add_f32_e32 v1, s4, v07318; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 17319; GFX9-NEXT:    v_add_u32_e32 v2, v2, v17320; GFX9-NEXT:    s_lshl_b32 s4, s16, 167321; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v27322; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v17323; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v17324; GFX9-NEXT:    v_add_f32_e32 v0, s4, v07325; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc7326; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 17327; GFX9-NEXT:    v_add_u32_e32 v2, v2, v07328; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v27329; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v07330; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v07331; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc7332; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff7333; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v17334; GFX9-NEXT:    v_and_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_17335; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v07336; GFX9-NEXT:    s_setpc_b64 s[30:31]7337; GFX9-NEXT:  .LBB63_3:7338; GFX9-NEXT:    s_branch .LBB63_27339; GFX9-NEXT:  .LBB63_4:7340; GFX9-NEXT:    v_mov_b32_e32 v0, s167341; GFX9-NEXT:    s_setpc_b64 s[30:31]7342;7343; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v2f16_scalar:7344; GFX11-TRUE16:       ; %bb.0:7345; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7346; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 07347; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 07348; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB63_37349; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow7350; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s17351; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB63_47352; GFX11-TRUE16-NEXT:  .LBB63_2: ; %cmp.true7353; GFX11-TRUE16-NEXT:    s_and_b32 s1, s0, 0xffff00007354; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 167355; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s17356; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s07357; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7358; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 17359; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 17360; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v07361; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v07362; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v17363; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)7364; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v17365; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v37366; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v07367; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7368; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v27369; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo7370; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v17371; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)7372; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v07373; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo7374; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v17375; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)7376; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l7377; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]7378; GFX11-TRUE16-NEXT:  .LBB63_3:7379; GFX11-TRUE16-NEXT:    s_branch .LBB63_27380; GFX11-TRUE16-NEXT:  .LBB63_4:7381; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s07382; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]7383;7384; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v2f16_scalar:7385; GFX11-FAKE16:       ; %bb.0:7386; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7387; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 07388; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 07389; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB63_37390; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow7391; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s17392; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB63_47393; GFX11-FAKE16-NEXT:  .LBB63_2: ; %cmp.true7394; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 167395; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00007396; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s17397; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s07398; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)7399; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 17400; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 17401; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v07402; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v07403; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v17404; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)7405; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v17406; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v37407; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v07408; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7409; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v27410; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo7411; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v17412; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)7413; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v07414; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_and_b32 v0, 0xffff, v07415; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)7416; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v17417; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v07418; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7419; GFX11-FAKE16-NEXT:  .LBB63_3:7420; GFX11-FAKE16-NEXT:    s_branch .LBB63_27421; GFX11-FAKE16-NEXT:  .LBB63_4:7422; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s07423; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7424  %cmp = icmp eq i32 %b, 07425  br i1 %cmp, label %cmp.true, label %cmp.false7426 7427cmp.true:7428  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)7429  %a2 = bitcast <2 x bfloat> %a1 to <2 x half>7430  br label %end7431 7432cmp.false:7433  %a3 = bitcast <2 x bfloat> %a to <2 x half>7434  br label %end7435 7436end:7437  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7438  ret <2 x half> %phi7439}7440 7441define <1 x i32> @bitcast_v2f16_to_v1i32(<2 x half> %a, i32 %b) {7442; SI-LABEL: bitcast_v2f16_to_v1i32:7443; SI:       ; %bb.0:7444; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7445; SI-NEXT:    v_cvt_f16_f32_e32 v3, v17446; SI-NEXT:    v_cvt_f16_f32_e32 v1, v07447; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v27448; SI-NEXT:    ; implicit-def: $vgpr07449; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7450; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7451; SI-NEXT:    s_cbranch_execnz .LBB64_37452; SI-NEXT:  ; %bb.1: ; %Flow7453; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7454; SI-NEXT:    s_cbranch_execnz .LBB64_47455; SI-NEXT:  .LBB64_2: ; %end7456; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7457; SI-NEXT:    s_setpc_b64 s[30:31]7458; SI-NEXT:  .LBB64_3: ; %cmp.false7459; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v37460; SI-NEXT:    v_or_b32_e32 v0, v1, v07461; SI-NEXT:    ; implicit-def: $vgpr37462; SI-NEXT:    ; implicit-def: $vgpr17463; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7464; SI-NEXT:    s_cbranch_execz .LBB64_27465; SI-NEXT:  .LBB64_4: ; %cmp.true7466; SI-NEXT:    v_cvt_f32_f16_e32 v0, v37467; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17468; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v07469; SI-NEXT:    v_cvt_f16_f32_e32 v0, v07470; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v17471; SI-NEXT:    v_cvt_f16_f32_e32 v1, v17472; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v07473; SI-NEXT:    v_or_b32_e32 v0, v1, v07474; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7475; SI-NEXT:    s_setpc_b64 s[30:31]7476;7477; VI-LABEL: bitcast_v2f16_to_v1i32:7478; VI:       ; %bb.0:7479; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7480; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17481; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7482; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7483; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7484; VI-NEXT:  ; %bb.1: ; %cmp.true7485; VI-NEXT:    v_mov_b32_e32 v1, 0x2007486; VI-NEXT:    v_add_f16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7487; VI-NEXT:    v_add_f16_e32 v0, 0x200, v07488; VI-NEXT:    v_or_b32_e32 v0, v0, v17489; VI-NEXT:  ; %bb.2: ; %end7490; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7491; VI-NEXT:    s_setpc_b64 s[30:31]7492;7493; GFX9-LABEL: bitcast_v2f16_to_v1i32:7494; GFX9:       ; %bb.0:7495; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7496; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17497; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7498; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7499; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7500; GFX9-NEXT:  ; %bb.1: ; %cmp.true7501; GFX9-NEXT:    s_movk_i32 s6, 0x2007502; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]7503; GFX9-NEXT:  ; %bb.2: ; %end7504; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7505; GFX9-NEXT:    s_setpc_b64 s[30:31]7506;7507; GFX11-LABEL: bitcast_v2f16_to_v1i32:7508; GFX11:       ; %bb.0:7509; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7510; GFX11-NEXT:    s_mov_b32 s0, exec_lo7511; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v17512; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07513; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7514; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07515; GFX11-NEXT:  ; %bb.1: ; %cmp.true7516; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]7517; GFX11-NEXT:  ; %bb.2: ; %end7518; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07519; GFX11-NEXT:    s_setpc_b64 s[30:31]7520  %cmp = icmp eq i32 %b, 07521  br i1 %cmp, label %cmp.true, label %cmp.false7522 7523cmp.true:7524  %a1 = fadd <2 x half> %a, splat (half 0xH0200)7525  %a2 = bitcast <2 x half> %a1 to <1 x i32>7526  br label %end7527 7528cmp.false:7529  %a3 = bitcast <2 x half> %a to <1 x i32>7530  br label %end7531 7532end:7533  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7534  ret <1 x i32> %phi7535}7536 7537define inreg <1 x i32> @bitcast_v2f16_to_v1i32_scalar(<2 x half> inreg %a, i32 inreg %b) {7538; SI-LABEL: bitcast_v2f16_to_v1i32_scalar:7539; SI:       ; %bb.0:7540; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7541; SI-NEXT:    v_cvt_f16_f32_e32 v2, s177542; SI-NEXT:    v_cvt_f16_f32_e32 v1, s167543; SI-NEXT:    s_cmp_lg_u32 s18, 07544; SI-NEXT:    s_cbranch_scc0 .LBB65_47545; SI-NEXT:  ; %bb.1: ; %cmp.false7546; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v27547; SI-NEXT:    v_or_b32_e32 v0, v1, v07548; SI-NEXT:    s_cbranch_execnz .LBB65_37549; SI-NEXT:  .LBB65_2: ; %cmp.true7550; SI-NEXT:    v_cvt_f32_f16_e32 v0, v27551; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17552; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v07553; SI-NEXT:    v_cvt_f16_f32_e32 v0, v07554; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v17555; SI-NEXT:    v_cvt_f16_f32_e32 v1, v17556; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v07557; SI-NEXT:    v_or_b32_e32 v0, v1, v07558; SI-NEXT:  .LBB65_3: ; %end7559; SI-NEXT:    s_setpc_b64 s[30:31]7560; SI-NEXT:  .LBB65_4:7561; SI-NEXT:    ; implicit-def: $vgpr07562; SI-NEXT:    s_branch .LBB65_27563;7564; VI-LABEL: bitcast_v2f16_to_v1i32_scalar:7565; VI:       ; %bb.0:7566; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7567; VI-NEXT:    s_cmp_lg_u32 s17, 07568; VI-NEXT:    s_cbranch_scc0 .LBB65_37569; VI-NEXT:  ; %bb.1: ; %cmp.false7570; VI-NEXT:    s_cbranch_execnz .LBB65_47571; VI-NEXT:  .LBB65_2: ; %cmp.true7572; VI-NEXT:    s_lshr_b32 s4, s16, 167573; VI-NEXT:    v_mov_b32_e32 v0, 0x2007574; VI-NEXT:    v_mov_b32_e32 v1, s47575; VI-NEXT:    v_add_f16_sdwa v1, v1, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD7576; VI-NEXT:    v_add_f16_e32 v0, s16, v07577; VI-NEXT:    v_or_b32_e32 v0, v0, v17578; VI-NEXT:    s_setpc_b64 s[30:31]7579; VI-NEXT:  .LBB65_3:7580; VI-NEXT:    s_branch .LBB65_27581; VI-NEXT:  .LBB65_4:7582; VI-NEXT:    v_mov_b32_e32 v0, s167583; VI-NEXT:    s_setpc_b64 s[30:31]7584;7585; GFX9-LABEL: bitcast_v2f16_to_v1i32_scalar:7586; GFX9:       ; %bb.0:7587; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7588; GFX9-NEXT:    s_cmp_lg_u32 s17, 07589; GFX9-NEXT:    s_cbranch_scc0 .LBB65_37590; GFX9-NEXT:  ; %bb.1: ; %cmp.false7591; GFX9-NEXT:    s_cbranch_execnz .LBB65_47592; GFX9-NEXT:  .LBB65_2: ; %cmp.true7593; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2007594; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]7595; GFX9-NEXT:    s_setpc_b64 s[30:31]7596; GFX9-NEXT:  .LBB65_3:7597; GFX9-NEXT:    s_branch .LBB65_27598; GFX9-NEXT:  .LBB65_4:7599; GFX9-NEXT:    v_mov_b32_e32 v0, s167600; GFX9-NEXT:    s_setpc_b64 s[30:31]7601;7602; GFX11-LABEL: bitcast_v2f16_to_v1i32_scalar:7603; GFX11:       ; %bb.0:7604; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7605; GFX11-NEXT:    s_cmp_lg_u32 s1, 07606; GFX11-NEXT:    s_mov_b32 s1, 07607; GFX11-NEXT:    s_cbranch_scc0 .LBB65_37608; GFX11-NEXT:  ; %bb.1: ; %Flow7609; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s17610; GFX11-NEXT:    s_cbranch_vccnz .LBB65_47611; GFX11-NEXT:  .LBB65_2: ; %cmp.true7612; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]7613; GFX11-NEXT:    s_setpc_b64 s[30:31]7614; GFX11-NEXT:  .LBB65_3:7615; GFX11-NEXT:    s_branch .LBB65_27616; GFX11-NEXT:  .LBB65_4:7617; GFX11-NEXT:    v_mov_b32_e32 v0, s07618; GFX11-NEXT:    s_setpc_b64 s[30:31]7619  %cmp = icmp eq i32 %b, 07620  br i1 %cmp, label %cmp.true, label %cmp.false7621 7622cmp.true:7623  %a1 = fadd <2 x half> %a, splat (half 0xH0200)7624  %a2 = bitcast <2 x half> %a1 to <1 x i32>7625  br label %end7626 7627cmp.false:7628  %a3 = bitcast <2 x half> %a to <1 x i32>7629  br label %end7630 7631end:7632  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7633  ret <1 x i32> %phi7634}7635 7636define <2 x half> @bitcast_v1i32_to_v2f16(<1 x i32> %a, i32 %b) {7637; SI-LABEL: bitcast_v1i32_to_v2f16:7638; SI:       ; %bb.0:7639; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7640; SI-NEXT:    v_mov_b32_e32 v2, v07641; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17642; SI-NEXT:    ; implicit-def: $vgpr07643; SI-NEXT:    ; implicit-def: $vgpr17644; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7645; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7646; SI-NEXT:    s_cbranch_execnz .LBB66_37647; SI-NEXT:  ; %bb.1: ; %Flow7648; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7649; SI-NEXT:    s_cbranch_execnz .LBB66_47650; SI-NEXT:  .LBB66_2: ; %end7651; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7652; SI-NEXT:    s_setpc_b64 s[30:31]7653; SI-NEXT:  .LBB66_3: ; %cmp.false7654; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v27655; SI-NEXT:    v_cvt_f32_f16_e32 v1, v07656; SI-NEXT:    v_cvt_f32_f16_e32 v0, v27657; SI-NEXT:    ; implicit-def: $vgpr27658; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7659; SI-NEXT:    s_cbranch_execz .LBB66_27660; SI-NEXT:  .LBB66_4: ; %cmp.true7661; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v27662; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v07663; SI-NEXT:    v_cvt_f32_f16_e32 v0, v07664; SI-NEXT:    v_cvt_f32_f16_e32 v1, v17665; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7666; SI-NEXT:    s_setpc_b64 s[30:31]7667;7668; VI-LABEL: bitcast_v1i32_to_v2f16:7669; VI:       ; %bb.0:7670; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7671; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17672; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7673; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7674; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7675; VI-NEXT:  ; %bb.1: ; %cmp.true7676; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v07677; VI-NEXT:  ; %bb.2: ; %end7678; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7679; VI-NEXT:    s_setpc_b64 s[30:31]7680;7681; GFX9-LABEL: bitcast_v1i32_to_v2f16:7682; GFX9:       ; %bb.0:7683; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7684; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17685; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7686; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7687; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7688; GFX9-NEXT:  ; %bb.1: ; %cmp.true7689; GFX9-NEXT:    v_add_u32_e32 v0, 3, v07690; GFX9-NEXT:  ; %bb.2: ; %end7691; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7692; GFX9-NEXT:    s_setpc_b64 s[30:31]7693;7694; GFX11-LABEL: bitcast_v1i32_to_v2f16:7695; GFX11:       ; %bb.0:7696; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7697; GFX11-NEXT:    s_mov_b32 s0, exec_lo7698; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v17699; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s07700; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7701; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s07702; GFX11-NEXT:  ; %bb.1: ; %cmp.true7703; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v07704; GFX11-NEXT:  ; %bb.2: ; %end7705; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s07706; GFX11-NEXT:    s_setpc_b64 s[30:31]7707  %cmp = icmp eq i32 %b, 07708  br i1 %cmp, label %cmp.true, label %cmp.false7709 7710cmp.true:7711  %a1 = add <1 x i32> %a, splat (i32 3)7712  %a2 = bitcast <1 x i32> %a1 to <2 x half>7713  br label %end7714 7715cmp.false:7716  %a3 = bitcast <1 x i32> %a to <2 x half>7717  br label %end7718 7719end:7720  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7721  ret <2 x half> %phi7722}7723 7724define inreg <2 x half> @bitcast_v1i32_to_v2f16_scalar(<1 x i32> inreg %a, i32 inreg %b) {7725; SI-LABEL: bitcast_v1i32_to_v2f16_scalar:7726; SI:       ; %bb.0:7727; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7728; SI-NEXT:    s_cmp_lg_u32 s17, 07729; SI-NEXT:    s_cbranch_scc0 .LBB67_47730; SI-NEXT:  ; %bb.1: ; %cmp.false7731; SI-NEXT:    s_lshr_b32 s4, s16, 167732; SI-NEXT:    v_cvt_f32_f16_e32 v1, s47733; SI-NEXT:    v_cvt_f32_f16_e32 v0, s167734; SI-NEXT:    s_cbranch_execnz .LBB67_37735; SI-NEXT:  .LBB67_2: ; %cmp.true7736; SI-NEXT:    s_add_i32 s16, s16, 37737; SI-NEXT:    s_lshr_b32 s4, s16, 167738; SI-NEXT:    v_cvt_f32_f16_e32 v0, s167739; SI-NEXT:    v_cvt_f32_f16_e32 v1, s47740; SI-NEXT:  .LBB67_3: ; %end7741; SI-NEXT:    s_setpc_b64 s[30:31]7742; SI-NEXT:  .LBB67_4:7743; SI-NEXT:    ; implicit-def: $vgpr07744; SI-NEXT:    ; implicit-def: $vgpr17745; SI-NEXT:    s_branch .LBB67_27746;7747; VI-LABEL: bitcast_v1i32_to_v2f16_scalar:7748; VI:       ; %bb.0:7749; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7750; VI-NEXT:    s_cmp_lg_u32 s17, 07751; VI-NEXT:    s_cbranch_scc0 .LBB67_47752; VI-NEXT:  ; %bb.1: ; %cmp.false7753; VI-NEXT:    s_cbranch_execnz .LBB67_37754; VI-NEXT:  .LBB67_2: ; %cmp.true7755; VI-NEXT:    s_add_i32 s16, s16, 37756; VI-NEXT:  .LBB67_3: ; %end7757; VI-NEXT:    v_mov_b32_e32 v0, s167758; VI-NEXT:    s_setpc_b64 s[30:31]7759; VI-NEXT:  .LBB67_4:7760; VI-NEXT:    s_branch .LBB67_27761;7762; GFX9-LABEL: bitcast_v1i32_to_v2f16_scalar:7763; GFX9:       ; %bb.0:7764; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7765; GFX9-NEXT:    s_cmp_lg_u32 s17, 07766; GFX9-NEXT:    s_cbranch_scc0 .LBB67_47767; GFX9-NEXT:  ; %bb.1: ; %cmp.false7768; GFX9-NEXT:    s_cbranch_execnz .LBB67_37769; GFX9-NEXT:  .LBB67_2: ; %cmp.true7770; GFX9-NEXT:    s_add_i32 s16, s16, 37771; GFX9-NEXT:  .LBB67_3: ; %end7772; GFX9-NEXT:    v_mov_b32_e32 v0, s167773; GFX9-NEXT:    s_setpc_b64 s[30:31]7774; GFX9-NEXT:  .LBB67_4:7775; GFX9-NEXT:    s_branch .LBB67_27776;7777; GFX11-LABEL: bitcast_v1i32_to_v2f16_scalar:7778; GFX11:       ; %bb.0:7779; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7780; GFX11-NEXT:    s_cmp_lg_u32 s1, 07781; GFX11-NEXT:    s_mov_b32 s1, 07782; GFX11-NEXT:    s_cbranch_scc0 .LBB67_37783; GFX11-NEXT:  ; %bb.1: ; %Flow7784; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s17785; GFX11-NEXT:    s_cbranch_vccz .LBB67_47786; GFX11-NEXT:  ; %bb.2: ; %end7787; GFX11-NEXT:    v_mov_b32_e32 v0, s07788; GFX11-NEXT:    s_setpc_b64 s[30:31]7789; GFX11-NEXT:  .LBB67_3:7790; GFX11-NEXT:  .LBB67_4: ; %cmp.true7791; GFX11-NEXT:    s_add_i32 s0, s0, 37792; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7793; GFX11-NEXT:    v_mov_b32_e32 v0, s07794; GFX11-NEXT:    s_setpc_b64 s[30:31]7795  %cmp = icmp eq i32 %b, 07796  br i1 %cmp, label %cmp.true, label %cmp.false7797 7798cmp.true:7799  %a1 = add <1 x i32> %a, splat (i32 3)7800  %a2 = bitcast <1 x i32> %a1 to <2 x half>7801  br label %end7802 7803cmp.false:7804  %a3 = bitcast <1 x i32> %a to <2 x half>7805  br label %end7806 7807end:7808  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7809  ret <2 x half> %phi7810}7811 7812define <4 x i8> @bitcast_v2f16_to_v4i8(<2 x half> %a, i32 %b) {7813; SI-LABEL: bitcast_v2f16_to_v4i8:7814; SI:       ; %bb.0:7815; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7816; SI-NEXT:    v_mov_b32_e32 v3, v27817; SI-NEXT:    v_cvt_f16_f32_e32 v2, v17818; SI-NEXT:    v_cvt_f16_f32_e32 v4, v07819; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v37820; SI-NEXT:    ; implicit-def: $vgpr07821; SI-NEXT:    ; implicit-def: $vgpr17822; SI-NEXT:    ; implicit-def: $vgpr37823; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7824; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7825; SI-NEXT:    s_cbranch_execnz .LBB68_37826; SI-NEXT:  ; %bb.1: ; %Flow7827; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7828; SI-NEXT:    s_cbranch_execnz .LBB68_47829; SI-NEXT:  .LBB68_2: ; %end7830; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7831; SI-NEXT:    s_setpc_b64 s[30:31]7832; SI-NEXT:  .LBB68_3: ; %cmp.false7833; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v27834; SI-NEXT:    v_or_b32_e32 v0, v4, v07835; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v07836; SI-NEXT:    v_bfe_u32 v3, v2, 8, 87837; SI-NEXT:    ; implicit-def: $vgpr47838; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7839; SI-NEXT:    s_cbranch_execz .LBB68_27840; SI-NEXT:  .LBB68_4: ; %cmp.true7841; SI-NEXT:    v_cvt_f32_f16_e32 v0, v27842; SI-NEXT:    v_cvt_f32_f16_e32 v1, v47843; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v07844; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v17845; SI-NEXT:    v_cvt_f16_f32_e32 v2, v07846; SI-NEXT:    v_cvt_f16_f32_e32 v0, v17847; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v27848; SI-NEXT:    v_or_b32_e32 v0, v0, v17849; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v07850; SI-NEXT:    v_bfe_u32 v3, v2, 8, 87851; SI-NEXT:    s_or_b64 exec, exec, s[4:5]7852; SI-NEXT:    s_setpc_b64 s[30:31]7853;7854; VI-LABEL: bitcast_v2f16_to_v4i8:7855; VI:       ; %bb.0:7856; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7857; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17858; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v07859; VI-NEXT:    ; implicit-def: $vgpr17860; VI-NEXT:    ; implicit-def: $vgpr37861; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc7862; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7863; VI-NEXT:    s_cbranch_execnz .LBB68_37864; VI-NEXT:  ; %bb.1: ; %Flow7865; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7866; VI-NEXT:    s_cbranch_execnz .LBB68_47867; VI-NEXT:  .LBB68_2: ; %end7868; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7869; VI-NEXT:    s_setpc_b64 s[30:31]7870; VI-NEXT:  .LBB68_3: ; %cmp.false7871; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v07872; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v07873; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7874; VI-NEXT:    s_cbranch_execz .LBB68_27875; VI-NEXT:  .LBB68_4: ; %cmp.true7876; VI-NEXT:    v_mov_b32_e32 v1, 0x2007877; VI-NEXT:    v_add_f16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD7878; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v27879; VI-NEXT:    v_add_f16_e32 v0, 0x200, v07880; VI-NEXT:    v_or_b32_e32 v1, v0, v17881; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v17882; VI-NEXT:    v_bfe_u32 v3, v2, 8, 87883; VI-NEXT:    s_or_b64 exec, exec, s[4:5]7884; VI-NEXT:    s_setpc_b64 s[30:31]7885;7886; GFX9-LABEL: bitcast_v2f16_to_v4i8:7887; GFX9:       ; %bb.0:7888; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7889; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v17890; GFX9-NEXT:    ; implicit-def: $vgpr17891; GFX9-NEXT:    ; implicit-def: $vgpr27892; GFX9-NEXT:    ; implicit-def: $vgpr37893; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc7894; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]7895; GFX9-NEXT:    s_cbranch_execnz .LBB68_37896; GFX9-NEXT:  ; %bb.1: ; %Flow7897; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7898; GFX9-NEXT:    s_cbranch_execnz .LBB68_47899; GFX9-NEXT:  .LBB68_2: ; %end7900; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7901; GFX9-NEXT:    s_setpc_b64 s[30:31]7902; GFX9-NEXT:  .LBB68_3: ; %cmp.false7903; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v07904; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v07905; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v07906; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]7907; GFX9-NEXT:    s_cbranch_execz .LBB68_27908; GFX9-NEXT:  .LBB68_4: ; %cmp.true7909; GFX9-NEXT:    s_movk_i32 s6, 0x2007910; GFX9-NEXT:    v_pk_add_f16 v0, v0, s6 op_sel_hi:[1,0]7911; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v07912; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v07913; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v07914; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]7915; GFX9-NEXT:    s_setpc_b64 s[30:31]7916;7917; GFX11-TRUE16-LABEL: bitcast_v2f16_to_v4i8:7918; GFX11-TRUE16:       ; %bb.0:7919; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7920; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v07921; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17922; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo167923; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo167924; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo7925; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7926; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s07927; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false7928; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)7929; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v27930; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v27931; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow7932; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s07933; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true7934; GFX11-TRUE16-NEXT:    v_pk_add_f16 v2, 0x200, v2 op_sel_hi:[0,1]7935; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)7936; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v27937; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v27938; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end7939; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s07940; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l7941; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h7942; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]7943;7944; GFX11-FAKE16-LABEL: bitcast_v2f16_to_v4i8:7945; GFX11-FAKE16:       ; %bb.0:7946; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7947; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v17948; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr17949; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr27950; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr37951; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo7952; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)7953; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s07954; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB68_37955; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow7956; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s07957; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB68_47958; GFX11-FAKE16-NEXT:  .LBB68_2: ; %end7959; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s07960; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7961; GFX11-FAKE16-NEXT:  .LBB68_3: ; %cmp.false7962; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v07963; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v07964; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v07965; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s07966; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB68_27967; GFX11-FAKE16-NEXT:  .LBB68_4: ; %cmp.true7968; GFX11-FAKE16-NEXT:    v_pk_add_f16 v0, 0x200, v0 op_sel_hi:[0,1]7969; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)7970; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v07971; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v07972; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v07973; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s07974; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]7975  %cmp = icmp eq i32 %b, 07976  br i1 %cmp, label %cmp.true, label %cmp.false7977 7978cmp.true:7979  %a1 = fadd <2 x half> %a, splat (half 0xH0200)7980  %a2 = bitcast <2 x half> %a1 to <4 x i8>7981  br label %end7982 7983cmp.false:7984  %a3 = bitcast <2 x half> %a to <4 x i8>7985  br label %end7986 7987end:7988  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]7989  ret <4 x i8> %phi7990}7991 7992define inreg <4 x i8> @bitcast_v2f16_to_v4i8_scalar(<2 x half> inreg %a, i32 inreg %b) {7993; SI-LABEL: bitcast_v2f16_to_v4i8_scalar:7994; SI:       ; %bb.0:7995; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)7996; SI-NEXT:    v_cvt_f16_f32_e32 v2, s177997; SI-NEXT:    v_cvt_f16_f32_e32 v4, s167998; SI-NEXT:    s_cmp_lg_u32 s18, 07999; SI-NEXT:    s_cbranch_scc0 .LBB69_48000; SI-NEXT:  ; %bb.1: ; %cmp.false8001; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v28002; SI-NEXT:    v_or_b32_e32 v0, v4, v08003; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v08004; SI-NEXT:    v_bfe_u32 v3, v2, 8, 88005; SI-NEXT:    s_cbranch_execnz .LBB69_38006; SI-NEXT:  .LBB69_2: ; %cmp.true8007; SI-NEXT:    v_cvt_f32_f16_e32 v0, v28008; SI-NEXT:    v_cvt_f32_f16_e32 v1, v48009; SI-NEXT:    v_add_f32_e32 v0, 0x38000000, v08010; SI-NEXT:    v_add_f32_e32 v1, 0x38000000, v18011; SI-NEXT:    v_cvt_f16_f32_e32 v2, v08012; SI-NEXT:    v_cvt_f16_f32_e32 v0, v18013; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v28014; SI-NEXT:    v_or_b32_e32 v0, v0, v18015; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v08016; SI-NEXT:    v_bfe_u32 v3, v2, 8, 88017; SI-NEXT:  .LBB69_3: ; %end8018; SI-NEXT:    s_setpc_b64 s[30:31]8019; SI-NEXT:  .LBB69_4:8020; SI-NEXT:    ; implicit-def: $vgpr08021; SI-NEXT:    ; implicit-def: $vgpr18022; SI-NEXT:    ; implicit-def: $vgpr38023; SI-NEXT:    s_branch .LBB69_28024;8025; VI-LABEL: bitcast_v2f16_to_v4i8_scalar:8026; VI:       ; %bb.0:8027; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8028; VI-NEXT:    s_cmp_lg_u32 s17, 08029; VI-NEXT:    s_cbranch_scc0 .LBB69_38030; VI-NEXT:  ; %bb.1: ; %cmp.false8031; VI-NEXT:    s_lshr_b32 s6, s16, 248032; VI-NEXT:    s_lshr_b32 s8, s16, 168033; VI-NEXT:    s_lshr_b32 s7, s16, 88034; VI-NEXT:    s_cbranch_execnz .LBB69_48035; VI-NEXT:  .LBB69_2: ; %cmp.true8036; VI-NEXT:    s_lshr_b32 s4, s16, 168037; VI-NEXT:    v_mov_b32_e32 v0, 0x2008038; VI-NEXT:    v_add_f16_e32 v2, s4, v08039; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v28040; VI-NEXT:    v_add_f16_e32 v0, s16, v08041; VI-NEXT:    v_or_b32_e32 v1, v0, v18042; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v18043; VI-NEXT:    v_bfe_u32 v3, v2, 8, 88044; VI-NEXT:    s_setpc_b64 s[30:31]8045; VI-NEXT:  .LBB69_3:8046; VI-NEXT:    ; implicit-def: $sgpr78047; VI-NEXT:    ; implicit-def: $sgpr88048; VI-NEXT:    ; implicit-def: $sgpr68049; VI-NEXT:    s_branch .LBB69_28050; VI-NEXT:  .LBB69_4:8051; VI-NEXT:    v_mov_b32_e32 v2, s88052; VI-NEXT:    v_mov_b32_e32 v0, s168053; VI-NEXT:    v_mov_b32_e32 v3, s68054; VI-NEXT:    v_mov_b32_e32 v1, s78055; VI-NEXT:    s_setpc_b64 s[30:31]8056;8057; GFX9-LABEL: bitcast_v2f16_to_v4i8_scalar:8058; GFX9:       ; %bb.0:8059; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8060; GFX9-NEXT:    s_cmp_lg_u32 s17, 08061; GFX9-NEXT:    s_cbranch_scc0 .LBB69_38062; GFX9-NEXT:  ; %bb.1: ; %cmp.false8063; GFX9-NEXT:    s_lshr_b32 s7, s16, 248064; GFX9-NEXT:    s_lshr_b32 s6, s16, 168065; GFX9-NEXT:    s_lshr_b32 s8, s16, 88066; GFX9-NEXT:    s_cbranch_execnz .LBB69_48067; GFX9-NEXT:  .LBB69_2: ; %cmp.true8068; GFX9-NEXT:    v_mov_b32_e32 v0, 0x2008069; GFX9-NEXT:    v_pk_add_f16 v0, s16, v0 op_sel_hi:[1,0]8070; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v08071; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v08072; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v08073; GFX9-NEXT:    s_setpc_b64 s[30:31]8074; GFX9-NEXT:  .LBB69_3:8075; GFX9-NEXT:    ; implicit-def: $sgpr88076; GFX9-NEXT:    ; implicit-def: $sgpr68077; GFX9-NEXT:    ; implicit-def: $sgpr78078; GFX9-NEXT:    s_branch .LBB69_28079; GFX9-NEXT:  .LBB69_4:8080; GFX9-NEXT:    v_mov_b32_e32 v0, s168081; GFX9-NEXT:    v_mov_b32_e32 v1, s88082; GFX9-NEXT:    v_mov_b32_e32 v3, s78083; GFX9-NEXT:    v_mov_b32_e32 v2, s68084; GFX9-NEXT:    s_setpc_b64 s[30:31]8085;8086; GFX11-LABEL: bitcast_v2f16_to_v4i8_scalar:8087; GFX11:       ; %bb.0:8088; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8089; GFX11-NEXT:    s_cmp_lg_u32 s1, 08090; GFX11-NEXT:    s_mov_b32 s1, 08091; GFX11-NEXT:    s_cbranch_scc0 .LBB69_38092; GFX11-NEXT:  ; %bb.1: ; %cmp.false8093; GFX11-NEXT:    s_lshr_b32 s3, s0, 248094; GFX11-NEXT:    s_lshr_b32 s2, s0, 168095; GFX11-NEXT:    s_lshr_b32 s4, s0, 88096; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s18097; GFX11-NEXT:    s_cbranch_vccnz .LBB69_48098; GFX11-NEXT:  .LBB69_2: ; %cmp.true8099; GFX11-NEXT:    v_pk_add_f16 v0, 0x200, s0 op_sel_hi:[0,1]8100; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1)8101; GFX11-NEXT:    v_lshrrev_b32_e32 v2, 16, v08102; GFX11-NEXT:    v_lshrrev_b32_e32 v3, 24, v08103; GFX11-NEXT:    v_lshrrev_b32_e32 v1, 8, v08104; GFX11-NEXT:    s_setpc_b64 s[30:31]8105; GFX11-NEXT:  .LBB69_3:8106; GFX11-NEXT:    ; implicit-def: $sgpr48107; GFX11-NEXT:    ; implicit-def: $sgpr28108; GFX11-NEXT:    ; implicit-def: $sgpr38109; GFX11-NEXT:    s_branch .LBB69_28110; GFX11-NEXT:  .LBB69_4:8111; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s48112; GFX11-NEXT:    v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v2, s28113; GFX11-NEXT:    s_setpc_b64 s[30:31]8114  %cmp = icmp eq i32 %b, 08115  br i1 %cmp, label %cmp.true, label %cmp.false8116 8117cmp.true:8118  %a1 = fadd <2 x half> %a, splat (half 0xH0200)8119  %a2 = bitcast <2 x half> %a1 to <4 x i8>8120  br label %end8121 8122cmp.false:8123  %a3 = bitcast <2 x half> %a to <4 x i8>8124  br label %end8125 8126end:8127  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8128  ret <4 x i8> %phi8129}8130 8131define <2 x half> @bitcast_v4i8_to_v2f16(<4 x i8> %a, i32 %b) {8132; SI-LABEL: bitcast_v4i8_to_v2f16:8133; SI:       ; %bb.0:8134; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8135; SI-NEXT:    v_mov_b32_e32 v5, v08136; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v48137; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v18138; SI-NEXT:    v_lshlrev_b32_e32 v3, 8, v38139; SI-NEXT:    ; implicit-def: $vgpr08140; SI-NEXT:    ; implicit-def: $vgpr18141; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8142; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8143; SI-NEXT:    s_cbranch_execnz .LBB70_38144; SI-NEXT:  ; %bb.1: ; %Flow8145; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8146; SI-NEXT:    s_cbranch_execnz .LBB70_48147; SI-NEXT:  .LBB70_2: ; %end8148; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8149; SI-NEXT:    s_setpc_b64 s[30:31]8150; SI-NEXT:  .LBB70_3: ; %cmp.false8151; SI-NEXT:    v_and_b32_e32 v0, 0xff, v58152; SI-NEXT:    v_and_b32_e32 v1, 0xff, v28153; SI-NEXT:    v_or_b32_e32 v0, v0, v48154; SI-NEXT:    v_or_b32_e32 v1, v1, v38155; SI-NEXT:    v_cvt_f32_f16_e32 v0, v08156; SI-NEXT:    v_cvt_f32_f16_e32 v1, v18157; SI-NEXT:    ; implicit-def: $vgpr28158; SI-NEXT:    ; implicit-def: $vgpr38159; SI-NEXT:    ; implicit-def: $vgpr58160; SI-NEXT:    ; implicit-def: $vgpr48161; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8162; SI-NEXT:    s_cbranch_execz .LBB70_28163; SI-NEXT:  .LBB70_4: ; %cmp.true8164; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v28165; SI-NEXT:    v_and_b32_e32 v0, 0xff, v08166; SI-NEXT:    v_or_b32_e32 v0, v3, v08167; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x300, v08168; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v58169; SI-NEXT:    v_and_b32_e32 v0, 0xff, v08170; SI-NEXT:    v_or_b32_e32 v0, v4, v08171; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v08172; SI-NEXT:    v_cvt_f32_f16_e32 v0, v08173; SI-NEXT:    v_cvt_f32_f16_e32 v1, v18174; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8175; SI-NEXT:    s_setpc_b64 s[30:31]8176;8177; VI-LABEL: bitcast_v4i8_to_v2f16:8178; VI:       ; %bb.0:8179; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8180; VI-NEXT:    v_mov_b32_e32 v5, v08181; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v48182; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v18183; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v38184; VI-NEXT:    ; implicit-def: $vgpr08185; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8186; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8187; VI-NEXT:    s_cbranch_execnz .LBB70_38188; VI-NEXT:  ; %bb.1: ; %Flow8189; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8190; VI-NEXT:    s_cbranch_execnz .LBB70_48191; VI-NEXT:  .LBB70_2: ; %end8192; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8193; VI-NEXT:    s_setpc_b64 s[30:31]8194; VI-NEXT:  .LBB70_3: ; %cmp.false8195; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD8196; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD8197; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD8198; VI-NEXT:    ; implicit-def: $vgpr58199; VI-NEXT:    ; implicit-def: $vgpr48200; VI-NEXT:    ; implicit-def: $vgpr28201; VI-NEXT:    ; implicit-def: $vgpr18202; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8203; VI-NEXT:    s_cbranch_execz .LBB70_28204; VI-NEXT:  .LBB70_4: ; %cmp.true8205; VI-NEXT:    v_add_u16_e32 v0, 3, v58206; VI-NEXT:    v_add_u16_e32 v2, 3, v28207; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_08208; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_08209; VI-NEXT:    v_mov_b32_e32 v2, 0x3008210; VI-NEXT:    v_add_u16_e32 v0, 0x300, v08211; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8212; VI-NEXT:    v_or_b32_e32 v0, v0, v18213; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8214; VI-NEXT:    s_setpc_b64 s[30:31]8215;8216; GFX9-LABEL: bitcast_v4i8_to_v2f16:8217; GFX9:       ; %bb.0:8218; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8219; GFX9-NEXT:    v_mov_b32_e32 v5, v08220; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v48221; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v18222; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v38223; GFX9-NEXT:    ; implicit-def: $vgpr08224; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc8225; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8226; GFX9-NEXT:    s_cbranch_execnz .LBB70_38227; GFX9-NEXT:  ; %bb.1: ; %Flow8228; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8229; GFX9-NEXT:    s_cbranch_execnz .LBB70_48230; GFX9-NEXT:  .LBB70_2: ; %end8231; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8232; GFX9-NEXT:    s_setpc_b64 s[30:31]8233; GFX9-NEXT:  .LBB70_3: ; %cmp.false8234; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD8235; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD8236; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD8237; GFX9-NEXT:    ; implicit-def: $vgpr58238; GFX9-NEXT:    ; implicit-def: $vgpr48239; GFX9-NEXT:    ; implicit-def: $vgpr28240; GFX9-NEXT:    ; implicit-def: $vgpr18241; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8242; GFX9-NEXT:    s_cbranch_execz .LBB70_28243; GFX9-NEXT:  .LBB70_4: ; %cmp.true8244; GFX9-NEXT:    v_add_u16_e32 v0, 3, v58245; GFX9-NEXT:    v_add_u16_e32 v2, 3, v28246; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_08247; GFX9-NEXT:    s_movk_i32 s6, 0x3008248; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_08249; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v08250; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD8251; GFX9-NEXT:    v_or_b32_e32 v0, v0, v18252; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8253; GFX9-NEXT:    s_setpc_b64 s[30:31]8254;8255; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2f16:8256; GFX11-TRUE16:       ; %bb.0:8257; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8258; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l8259; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l8260; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l8261; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo8262; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr08263; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v48264; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s08265; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB70_38266; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow8267; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s08268; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB70_48269; GFX11-TRUE16-NEXT:  .LBB70_2: ; %end8270; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08271; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8272; GFX11-TRUE16-NEXT:  .LBB70_3: ; %cmp.false8273; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h8274; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l8275; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi168276; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo168277; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8278; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l8279; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h8280; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo168281; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi168282; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s08283; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB70_28284; GFX11-TRUE16-NEXT:  .LBB70_4: ; %cmp.true8285; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 38286; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 38287; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8288; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l8289; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h8290; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8291; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l8292; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h8293; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8294; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l8295; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h8296; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08297; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8298;8299; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2f16:8300; GFX11-FAKE16:       ; %bb.0:8301; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8302; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v08303; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v18304; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v38305; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo8306; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr08307; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v48308; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s08309; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB70_38310; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow8311; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s08312; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB70_48313; GFX11-FAKE16-NEXT:  .LBB70_2: ; %end8314; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08315; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8316; GFX11-FAKE16-NEXT:  .LBB70_3: ; %cmp.false8317; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v58318; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v28319; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr58320; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8321; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v18322; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v38323; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr28324; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr38325; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8326; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v08327; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v18328; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8329; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v18330; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr18331; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s08332; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB70_28333; GFX11-FAKE16-NEXT:  .LBB70_4: ; %cmp.true8334; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 38335; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 38336; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8337; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v08338; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v28339; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8340; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v08341; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v28342; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8343; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v08344; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v18345; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8346; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v08347; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v18348; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8349; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v18350; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08351; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8352  %cmp = icmp eq i32 %b, 08353  br i1 %cmp, label %cmp.true, label %cmp.false8354 8355cmp.true:8356  %a1 = add <4 x i8> %a, splat (i8 3)8357  %a2 = bitcast <4 x i8> %a1 to <2 x half>8358  br label %end8359 8360cmp.false:8361  %a3 = bitcast <4 x i8> %a to <2 x half>8362  br label %end8363 8364end:8365  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8366  ret <2 x half> %phi8367}8368 8369define inreg <2 x half> @bitcast_v4i8_to_v2f16_scalar(<4 x i8> inreg %a, i32 inreg %b) {8370; SI-LABEL: bitcast_v4i8_to_v2f16_scalar:8371; SI:       ; %bb.0:8372; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8373; SI-NEXT:    s_cmp_lg_u32 s20, 08374; SI-NEXT:    s_cbranch_scc0 .LBB71_48375; SI-NEXT:  ; %bb.1: ; %cmp.false8376; SI-NEXT:    s_and_b32 s4, s16, 0xff8377; SI-NEXT:    s_lshl_b32 s5, s17, 88378; SI-NEXT:    s_or_b32 s4, s4, s58379; SI-NEXT:    v_cvt_f32_f16_e32 v0, s48380; SI-NEXT:    s_and_b32 s4, s18, 0xff8381; SI-NEXT:    s_lshl_b32 s5, s19, 88382; SI-NEXT:    s_or_b32 s4, s4, s58383; SI-NEXT:    v_cvt_f32_f16_e32 v1, s48384; SI-NEXT:    s_cbranch_execnz .LBB71_38385; SI-NEXT:  .LBB71_2: ; %cmp.true8386; SI-NEXT:    s_add_i32 s18, s18, 38387; SI-NEXT:    s_and_b32 s4, s18, 0xff8388; SI-NEXT:    s_lshl_b32 s5, s19, 88389; SI-NEXT:    s_add_i32 s16, s16, 38390; SI-NEXT:    s_or_b32 s4, s5, s48391; SI-NEXT:    s_and_b32 s5, s16, 0xff8392; SI-NEXT:    s_lshl_b32 s6, s17, 88393; SI-NEXT:    s_or_b32 s5, s6, s58394; SI-NEXT:    s_addk_i32 s4, 0x3008395; SI-NEXT:    s_addk_i32 s5, 0x3008396; SI-NEXT:    v_cvt_f32_f16_e32 v0, s58397; SI-NEXT:    v_cvt_f32_f16_e32 v1, s48398; SI-NEXT:  .LBB71_3: ; %end8399; SI-NEXT:    s_setpc_b64 s[30:31]8400; SI-NEXT:  .LBB71_4:8401; SI-NEXT:    ; implicit-def: $vgpr08402; SI-NEXT:    ; implicit-def: $vgpr18403; SI-NEXT:    s_branch .LBB71_28404;8405; VI-LABEL: bitcast_v4i8_to_v2f16_scalar:8406; VI:       ; %bb.0:8407; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8408; VI-NEXT:    s_cmp_lg_u32 s20, 08409; VI-NEXT:    s_cbranch_scc0 .LBB71_48410; VI-NEXT:  ; %bb.1: ; %cmp.false8411; VI-NEXT:    s_and_b32 s4, s16, 0xff8412; VI-NEXT:    s_lshl_b32 s5, s17, 88413; VI-NEXT:    s_or_b32 s4, s4, s58414; VI-NEXT:    s_and_b32 s5, s18, 0xff8415; VI-NEXT:    s_lshl_b32 s6, s19, 88416; VI-NEXT:    s_or_b32 s5, s5, s68417; VI-NEXT:    s_and_b32 s4, s4, 0xffff8418; VI-NEXT:    s_lshl_b32 s5, s5, 168419; VI-NEXT:    s_or_b32 s6, s4, s58420; VI-NEXT:    s_cbranch_execnz .LBB71_38421; VI-NEXT:  .LBB71_2: ; %cmp.true8422; VI-NEXT:    s_add_i32 s16, s16, 38423; VI-NEXT:    s_and_b32 s4, s16, 0xff8424; VI-NEXT:    s_lshl_b32 s5, s17, 88425; VI-NEXT:    s_add_i32 s18, s18, 38426; VI-NEXT:    s_or_b32 s4, s5, s48427; VI-NEXT:    s_and_b32 s5, s18, 0xff8428; VI-NEXT:    s_lshl_b32 s6, s19, 88429; VI-NEXT:    s_addk_i32 s4, 0x3008430; VI-NEXT:    s_or_b32 s5, s6, s58431; VI-NEXT:    s_and_b32 s4, s4, 0xffff8432; VI-NEXT:    s_lshl_b32 s5, s5, 168433; VI-NEXT:    s_or_b32 s4, s5, s48434; VI-NEXT:    s_add_i32 s6, s4, 0x30000008435; VI-NEXT:  .LBB71_3: ; %end8436; VI-NEXT:    v_mov_b32_e32 v0, s68437; VI-NEXT:    s_setpc_b64 s[30:31]8438; VI-NEXT:  .LBB71_4:8439; VI-NEXT:    ; implicit-def: $sgpr68440; VI-NEXT:    s_branch .LBB71_28441;8442; GFX9-LABEL: bitcast_v4i8_to_v2f16_scalar:8443; GFX9:       ; %bb.0:8444; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8445; GFX9-NEXT:    s_cmp_lg_u32 s20, 08446; GFX9-NEXT:    s_cbranch_scc0 .LBB71_48447; GFX9-NEXT:  ; %bb.1: ; %cmp.false8448; GFX9-NEXT:    s_and_b32 s4, s16, 0xff8449; GFX9-NEXT:    s_lshl_b32 s5, s17, 88450; GFX9-NEXT:    s_or_b32 s4, s4, s58451; GFX9-NEXT:    s_and_b32 s5, s18, 0xff8452; GFX9-NEXT:    s_lshl_b32 s6, s19, 88453; GFX9-NEXT:    s_or_b32 s5, s5, s68454; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff8455; GFX9-NEXT:    s_lshl_b32 s5, s5, 168456; GFX9-NEXT:    s_or_b32 s6, s4, s58457; GFX9-NEXT:    s_cbranch_execnz .LBB71_38458; GFX9-NEXT:  .LBB71_2: ; %cmp.true8459; GFX9-NEXT:    s_add_i32 s16, s16, 38460; GFX9-NEXT:    s_and_b32 s4, s16, 0xff8461; GFX9-NEXT:    s_lshl_b32 s5, s17, 88462; GFX9-NEXT:    s_add_i32 s18, s18, 38463; GFX9-NEXT:    s_or_b32 s4, s5, s48464; GFX9-NEXT:    s_and_b32 s5, s18, 0xff8465; GFX9-NEXT:    s_lshl_b32 s6, s19, 88466; GFX9-NEXT:    s_or_b32 s5, s6, s58467; GFX9-NEXT:    s_addk_i32 s4, 0x3008468; GFX9-NEXT:    s_addk_i32 s5, 0x3008469; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff8470; GFX9-NEXT:    s_lshl_b32 s5, s5, 168471; GFX9-NEXT:    s_or_b32 s6, s4, s58472; GFX9-NEXT:  .LBB71_3: ; %end8473; GFX9-NEXT:    v_mov_b32_e32 v0, s68474; GFX9-NEXT:    s_setpc_b64 s[30:31]8475; GFX9-NEXT:  .LBB71_4:8476; GFX9-NEXT:    ; implicit-def: $sgpr68477; GFX9-NEXT:    s_branch .LBB71_28478;8479; GFX11-LABEL: bitcast_v4i8_to_v2f16_scalar:8480; GFX11:       ; %bb.0:8481; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8482; GFX11-NEXT:    s_cmp_lg_u32 s16, 08483; GFX11-NEXT:    s_mov_b32 s4, 08484; GFX11-NEXT:    s_cbranch_scc0 .LBB71_48485; GFX11-NEXT:  ; %bb.1: ; %cmp.false8486; GFX11-NEXT:    s_and_b32 s5, s0, 0xff8487; GFX11-NEXT:    s_lshl_b32 s6, s1, 88488; GFX11-NEXT:    s_and_b32 s7, s2, 0xff8489; GFX11-NEXT:    s_lshl_b32 s8, s3, 88490; GFX11-NEXT:    s_or_b32 s5, s5, s68491; GFX11-NEXT:    s_or_b32 s6, s7, s88492; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff8493; GFX11-NEXT:    s_lshl_b32 s6, s6, 168494; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8495; GFX11-NEXT:    s_or_b32 s5, s5, s68496; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s48497; GFX11-NEXT:    s_cbranch_vccnz .LBB71_38498; GFX11-NEXT:  .LBB71_2: ; %cmp.true8499; GFX11-NEXT:    s_add_i32 s0, s0, 38500; GFX11-NEXT:    s_add_i32 s2, s2, 38501; GFX11-NEXT:    s_and_b32 s0, s0, 0xff8502; GFX11-NEXT:    s_lshl_b32 s1, s1, 88503; GFX11-NEXT:    s_and_b32 s2, s2, 0xff8504; GFX11-NEXT:    s_lshl_b32 s3, s3, 88505; GFX11-NEXT:    s_or_b32 s0, s1, s08506; GFX11-NEXT:    s_or_b32 s1, s3, s28507; GFX11-NEXT:    s_addk_i32 s0, 0x3008508; GFX11-NEXT:    s_addk_i32 s1, 0x3008509; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff8510; GFX11-NEXT:    s_lshl_b32 s1, s1, 168511; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8512; GFX11-NEXT:    s_or_b32 s5, s0, s18513; GFX11-NEXT:  .LBB71_3: ; %end8514; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8515; GFX11-NEXT:    v_mov_b32_e32 v0, s58516; GFX11-NEXT:    s_setpc_b64 s[30:31]8517; GFX11-NEXT:  .LBB71_4:8518; GFX11-NEXT:    ; implicit-def: $sgpr58519; GFX11-NEXT:    s_branch .LBB71_28520  %cmp = icmp eq i32 %b, 08521  br i1 %cmp, label %cmp.true, label %cmp.false8522 8523cmp.true:8524  %a1 = add <4 x i8> %a, splat (i8 3)8525  %a2 = bitcast <4 x i8> %a1 to <2 x half>8526  br label %end8527 8528cmp.false:8529  %a3 = bitcast <4 x i8> %a to <2 x half>8530  br label %end8531 8532end:8533  %phi = phi <2 x half> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8534  ret <2 x half> %phi8535}8536 8537define <1 x i32> @bitcast_v2bf16_to_v1i32(<2 x bfloat> %a, i32 %b) {8538; SI-LABEL: bitcast_v2bf16_to_v1i32:8539; SI:       ; %bb.0:8540; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8541; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v28542; SI-NEXT:    v_mul_f32_e32 v1, 1.0, v18543; SI-NEXT:    v_mul_f32_e32 v2, 1.0, v08544; SI-NEXT:    ; implicit-def: $vgpr08545; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8546; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8547; SI-NEXT:    s_cbranch_execnz .LBB72_38548; SI-NEXT:  ; %bb.1: ; %Flow8549; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8550; SI-NEXT:    s_cbranch_execnz .LBB72_48551; SI-NEXT:  .LBB72_2: ; %end8552; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8553; SI-NEXT:    s_setpc_b64 s[30:31]8554; SI-NEXT:  .LBB72_3: ; %cmp.false8555; SI-NEXT:    v_lshrrev_b32_e32 v0, 16, v18556; SI-NEXT:    v_alignbit_b32 v0, v0, v2, 168557; SI-NEXT:    ; implicit-def: $vgpr28558; SI-NEXT:    ; implicit-def: $vgpr18559; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8560; SI-NEXT:    s_cbranch_execz .LBB72_28561; SI-NEXT:  .LBB72_4: ; %cmp.true8562; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v18563; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v28564; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18565; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08566; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18567; SI-NEXT:    v_alignbit_b32 v0, v1, v0, 168568; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8569; SI-NEXT:    s_setpc_b64 s[30:31]8570;8571; VI-LABEL: bitcast_v2bf16_to_v1i32:8572; VI:       ; %bb.0:8573; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8574; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18575; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8576; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8577; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8578; VI-NEXT:    s_cbranch_execz .LBB72_28579; VI-NEXT:  ; %bb.1: ; %cmp.true8580; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v08581; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18582; VI-NEXT:    v_bfe_u32 v2, v1, 16, 18583; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v18584; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v28585; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08586; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v18587; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18588; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08589; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc8590; VI-NEXT:    v_bfe_u32 v2, v0, 16, 18591; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v08592; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v28593; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v08594; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08595; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc8596; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v08597; VI-NEXT:    v_alignbit_b32 v0, v0, v1, 168598; VI-NEXT:  .LBB72_2: ; %end8599; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8600; VI-NEXT:    s_setpc_b64 s[30:31]8601;8602; GFX9-LABEL: bitcast_v2bf16_to_v1i32:8603; GFX9:       ; %bb.0:8604; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8605; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18606; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc8607; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8608; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8609; GFX9-NEXT:    s_cbranch_execz .LBB72_28610; GFX9-NEXT:  ; %bb.1: ; %cmp.true8611; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v08612; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18613; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 18614; GFX9-NEXT:    s_movk_i32 s6, 0x7fff8615; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08616; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s68617; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v18618; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18619; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08620; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc8621; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 18622; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s68623; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v08624; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08625; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc8626; GFX9-NEXT:    s_mov_b32 s6, 0x70603028627; GFX9-NEXT:    v_perm_b32 v0, v0, v1, s68628; GFX9-NEXT:  .LBB72_2: ; %end8629; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8630; GFX9-NEXT:    s_setpc_b64 s[30:31]8631;8632; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v1i32:8633; GFX11-TRUE16:       ; %bb.0:8634; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8635; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v18636; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr18637; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo8638; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8639; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s08640; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false8641; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v1, v08642; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr08643; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow8644; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s08645; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB72_48646; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true8647; GFX11-TRUE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v08648; GFX11-TRUE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08649; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8650; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v08651; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v1, 16, 18652; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8653; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v0, 16, 18654; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v18655; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18656; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v08657; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff8658; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff8659; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)8660; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v2, v4, vcc_lo8661; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08662; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo8663; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8664; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v2.h8665; GFX11-TRUE16-NEXT:  .LBB72_4: ; %end8666; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08667; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8668; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, v18669; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8670;8671; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v1i32:8672; GFX11-FAKE16:       ; %bb.0:8673; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8674; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo8675; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v18676; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s08677; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8678; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s08679; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB72_28680; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.true8681; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v08682; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v08683; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8684; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v08685; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 18686; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)8687; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 18688; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v18689; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18690; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v08691; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff8692; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff8693; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)8694; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo8695; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08696; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo8697; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)8698; GFX11-FAKE16-NEXT:    v_perm_b32 v0, v0, v1, 0x70603028699; GFX11-FAKE16-NEXT:  .LBB72_2: ; %end8700; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s08701; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8702  %cmp = icmp eq i32 %b, 08703  br i1 %cmp, label %cmp.true, label %cmp.false8704 8705cmp.true:8706  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)8707  %a2 = bitcast <2 x bfloat> %a1 to <1 x i32>8708  br label %end8709 8710cmp.false:8711  %a3 = bitcast <2 x bfloat> %a to <1 x i32>8712  br label %end8713 8714end:8715  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8716  ret <1 x i32> %phi8717}8718 8719define inreg <1 x i32> @bitcast_v2bf16_to_v1i32_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {8720; SI-LABEL: bitcast_v2bf16_to_v1i32_scalar:8721; SI:       ; %bb.0:8722; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8723; SI-NEXT:    s_cmp_lg_u32 s18, 08724; SI-NEXT:    v_mul_f32_e64 v4, 1.0, s178725; SI-NEXT:    v_mul_f32_e64 v2, 1.0, s168726; SI-NEXT:    s_cbranch_scc0 .LBB73_48727; SI-NEXT:  ; %bb.1: ; %cmp.false8728; SI-NEXT:    v_lshrrev_b32_e32 v3, 16, v48729; SI-NEXT:    v_lshr_b64 v[0:1], v[2:3], 168730; SI-NEXT:    s_cbranch_execnz .LBB73_38731; SI-NEXT:  .LBB73_2: ; %cmp.true8732; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v48733; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v28734; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v18735; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v08736; SI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18737; SI-NEXT:    v_lshr_b64 v[0:1], v[0:1], 168738; SI-NEXT:  .LBB73_3: ; %end8739; SI-NEXT:    s_setpc_b64 s[30:31]8740; SI-NEXT:  .LBB73_4:8741; SI-NEXT:    ; implicit-def: $vgpr08742; SI-NEXT:    s_branch .LBB73_28743;8744; VI-LABEL: bitcast_v2bf16_to_v1i32_scalar:8745; VI:       ; %bb.0:8746; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8747; VI-NEXT:    s_cmp_lg_u32 s17, 08748; VI-NEXT:    s_cbranch_scc0 .LBB73_38749; VI-NEXT:  ; %bb.1: ; %cmp.false8750; VI-NEXT:    s_cbranch_execnz .LBB73_48751; VI-NEXT:  .LBB73_2: ; %cmp.true8752; VI-NEXT:    s_lshl_b32 s4, s16, 168753; VI-NEXT:    v_mov_b32_e32 v1, 0x40c000008754; VI-NEXT:    v_add_f32_e32 v0, s4, v18755; VI-NEXT:    v_bfe_u32 v2, v0, 16, 18756; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v08757; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v28758; VI-NEXT:    s_and_b32 s4, s16, 0xffff00008759; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v08760; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08761; VI-NEXT:    v_add_f32_e32 v1, s4, v18762; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc8763; VI-NEXT:    v_bfe_u32 v2, v1, 16, 18764; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v18765; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v28766; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v18767; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18768; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc8769; VI-NEXT:    v_lshrrev_b32_e32 v1, 16, v18770; VI-NEXT:    v_lshrrev_b64 v[0:1], 16, v[0:1]8771; VI-NEXT:    s_setpc_b64 s[30:31]8772; VI-NEXT:  .LBB73_3:8773; VI-NEXT:    s_branch .LBB73_28774; VI-NEXT:  .LBB73_4:8775; VI-NEXT:    v_mov_b32_e32 v0, s168776; VI-NEXT:    s_setpc_b64 s[30:31]8777;8778; GFX9-LABEL: bitcast_v2bf16_to_v1i32_scalar:8779; GFX9:       ; %bb.0:8780; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8781; GFX9-NEXT:    s_cmp_lg_u32 s17, 08782; GFX9-NEXT:    s_cbranch_scc0 .LBB73_38783; GFX9-NEXT:  ; %bb.1: ; %cmp.false8784; GFX9-NEXT:    s_cbranch_execnz .LBB73_48785; GFX9-NEXT:  .LBB73_2: ; %cmp.true8786; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00008787; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000008788; GFX9-NEXT:    v_add_f32_e32 v1, s4, v08789; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 18790; GFX9-NEXT:    v_add_u32_e32 v2, v2, v18791; GFX9-NEXT:    s_lshl_b32 s4, s16, 168792; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v28793; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v18794; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v18795; GFX9-NEXT:    v_add_f32_e32 v0, s4, v08796; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc8797; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 18798; GFX9-NEXT:    v_add_u32_e32 v2, v2, v08799; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v28800; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v08801; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v08802; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc8803; GFX9-NEXT:    v_mov_b32_e32 v2, 0xffff8804; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 16, v18805; GFX9-NEXT:    v_and_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_18806; GFX9-NEXT:    v_lshl_or_b32 v0, v1, 16, v08807; GFX9-NEXT:    s_setpc_b64 s[30:31]8808; GFX9-NEXT:  .LBB73_3:8809; GFX9-NEXT:    s_branch .LBB73_28810; GFX9-NEXT:  .LBB73_4:8811; GFX9-NEXT:    v_mov_b32_e32 v0, s168812; GFX9-NEXT:    s_setpc_b64 s[30:31]8813;8814; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v1i32_scalar:8815; GFX11-TRUE16:       ; %bb.0:8816; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8817; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 08818; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 08819; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB73_38820; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow8821; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s18822; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB73_48823; GFX11-TRUE16-NEXT:  .LBB73_2: ; %cmp.true8824; GFX11-TRUE16-NEXT:    s_and_b32 s1, s0, 0xffff00008825; GFX11-TRUE16-NEXT:    s_lshl_b32 s0, s0, 168826; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s18827; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s08828; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8829; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 18830; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 18831; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v08832; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08833; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v18834; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)8835; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v18836; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v38837; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v08838; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8839; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v28840; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo8841; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18842; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)8843; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v08844; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo8845; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v18846; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3)8847; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v2.l8848; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8849; GFX11-TRUE16-NEXT:  .LBB73_3:8850; GFX11-TRUE16-NEXT:    s_branch .LBB73_28851; GFX11-TRUE16-NEXT:  .LBB73_4:8852; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v0, s08853; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]8854;8855; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v1i32_scalar:8856; GFX11-FAKE16:       ; %bb.0:8857; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8858; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 08859; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 08860; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB73_38861; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow8862; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s18863; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB73_48864; GFX11-FAKE16-NEXT:  .LBB73_2: ; %cmp.true8865; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 168866; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00008867; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s18868; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s08869; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)8870; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 18871; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 18872; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v08873; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v08874; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v18875; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)8876; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v18877; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v38878; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v08879; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8880; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v28881; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo8882; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v18883; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)8884; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v08885; GFX11-FAKE16-NEXT:    v_dual_cndmask_b32 v1, v3, v5 :: v_dual_and_b32 v0, 0xffff, v08886; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)8887; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 16, v18888; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v0, v1, 16, v08889; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8890; GFX11-FAKE16-NEXT:  .LBB73_3:8891; GFX11-FAKE16-NEXT:    s_branch .LBB73_28892; GFX11-FAKE16-NEXT:  .LBB73_4:8893; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v0, s08894; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]8895  %cmp = icmp eq i32 %b, 08896  br i1 %cmp, label %cmp.true, label %cmp.false8897 8898cmp.true:8899  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)8900  %a2 = bitcast <2 x bfloat> %a1 to <1 x i32>8901  br label %end8902 8903cmp.false:8904  %a3 = bitcast <2 x bfloat> %a to <1 x i32>8905  br label %end8906 8907end:8908  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8909  ret <1 x i32> %phi8910}8911 8912define <2 x bfloat> @bitcast_v1i32_to_v2bf16(<1 x i32> %a, i32 %b) {8913; SI-LABEL: bitcast_v1i32_to_v2bf16:8914; SI:       ; %bb.0:8915; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8916; SI-NEXT:    v_mov_b32_e32 v2, v08917; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18918; SI-NEXT:    ; implicit-def: $vgpr08919; SI-NEXT:    ; implicit-def: $vgpr18920; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8921; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8922; SI-NEXT:    s_cbranch_execnz .LBB74_38923; SI-NEXT:  ; %bb.1: ; %Flow8924; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8925; SI-NEXT:    s_cbranch_execnz .LBB74_48926; SI-NEXT:  .LBB74_2: ; %end8927; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8928; SI-NEXT:    s_setpc_b64 s[30:31]8929; SI-NEXT:  .LBB74_3: ; %cmp.false8930; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v28931; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v28932; SI-NEXT:    ; implicit-def: $vgpr28933; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8934; SI-NEXT:    s_cbranch_execz .LBB74_28935; SI-NEXT:  .LBB74_4: ; %cmp.true8936; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v28937; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v08938; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v08939; SI-NEXT:    s_or_b64 exec, exec, s[4:5]8940; SI-NEXT:    s_setpc_b64 s[30:31]8941;8942; VI-LABEL: bitcast_v1i32_to_v2bf16:8943; VI:       ; %bb.0:8944; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8945; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18946; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc8947; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8948; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8949; VI-NEXT:  ; %bb.1: ; %cmp.true8950; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v08951; VI-NEXT:  ; %bb.2: ; %end8952; VI-NEXT:    s_or_b64 exec, exec, s[4:5]8953; VI-NEXT:    s_setpc_b64 s[30:31]8954;8955; GFX9-LABEL: bitcast_v1i32_to_v2bf16:8956; GFX9:       ; %bb.0:8957; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8958; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v18959; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc8960; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]8961; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]8962; GFX9-NEXT:  ; %bb.1: ; %cmp.true8963; GFX9-NEXT:    v_add_u32_e32 v0, 3, v08964; GFX9-NEXT:  ; %bb.2: ; %end8965; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]8966; GFX9-NEXT:    s_setpc_b64 s[30:31]8967;8968; GFX11-LABEL: bitcast_v1i32_to_v2bf16:8969; GFX11:       ; %bb.0:8970; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)8971; GFX11-NEXT:    s_mov_b32 s0, exec_lo8972; GFX11-NEXT:    v_cmpx_ne_u32_e32 0, v18973; GFX11-NEXT:    s_xor_b32 s0, exec_lo, s08974; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)8975; GFX11-NEXT:    s_and_not1_saveexec_b32 s0, s08976; GFX11-NEXT:  ; %bb.1: ; %cmp.true8977; GFX11-NEXT:    v_add_nc_u32_e32 v0, 3, v08978; GFX11-NEXT:  ; %bb.2: ; %end8979; GFX11-NEXT:    s_or_b32 exec_lo, exec_lo, s08980; GFX11-NEXT:    s_setpc_b64 s[30:31]8981  %cmp = icmp eq i32 %b, 08982  br i1 %cmp, label %cmp.true, label %cmp.false8983 8984cmp.true:8985  %a1 = add <1 x i32> %a, splat (i32 3)8986  %a2 = bitcast <1 x i32> %a1 to <2 x bfloat>8987  br label %end8988 8989cmp.false:8990  %a3 = bitcast <1 x i32> %a to <2 x bfloat>8991  br label %end8992 8993end:8994  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]8995  ret <2 x bfloat> %phi8996}8997 8998define inreg <2 x bfloat> @bitcast_v1i32_to_v2bf16_scalar(<1 x i32> inreg %a, i32 inreg %b) {8999; SI-LABEL: bitcast_v1i32_to_v2bf16_scalar:9000; SI:       ; %bb.0:9001; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9002; SI-NEXT:    s_cmp_lg_u32 s17, 09003; SI-NEXT:    s_cbranch_scc0 .LBB75_49004; SI-NEXT:  ; %bb.1: ; %cmp.false9005; SI-NEXT:    s_and_b32 s6, s16, 0xffff00009006; SI-NEXT:    s_lshl_b32 s7, s16, 169007; SI-NEXT:    s_cbranch_execnz .LBB75_39008; SI-NEXT:  .LBB75_2: ; %cmp.true9009; SI-NEXT:    s_add_i32 s16, s16, 39010; SI-NEXT:    s_and_b32 s6, s16, 0xffff00009011; SI-NEXT:    s_lshl_b32 s7, s16, 169012; SI-NEXT:  .LBB75_3: ; %end9013; SI-NEXT:    v_mov_b32_e32 v0, s79014; SI-NEXT:    v_mov_b32_e32 v1, s69015; SI-NEXT:    s_setpc_b64 s[30:31]9016; SI-NEXT:  .LBB75_4:9017; SI-NEXT:    ; implicit-def: $sgpr79018; SI-NEXT:    ; implicit-def: $sgpr69019; SI-NEXT:    s_branch .LBB75_29020;9021; VI-LABEL: bitcast_v1i32_to_v2bf16_scalar:9022; VI:       ; %bb.0:9023; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9024; VI-NEXT:    s_cmp_lg_u32 s17, 09025; VI-NEXT:    s_cbranch_scc0 .LBB75_49026; VI-NEXT:  ; %bb.1: ; %cmp.false9027; VI-NEXT:    s_cbranch_execnz .LBB75_39028; VI-NEXT:  .LBB75_2: ; %cmp.true9029; VI-NEXT:    s_add_i32 s16, s16, 39030; VI-NEXT:  .LBB75_3: ; %end9031; VI-NEXT:    v_mov_b32_e32 v0, s169032; VI-NEXT:    s_setpc_b64 s[30:31]9033; VI-NEXT:  .LBB75_4:9034; VI-NEXT:    s_branch .LBB75_29035;9036; GFX9-LABEL: bitcast_v1i32_to_v2bf16_scalar:9037; GFX9:       ; %bb.0:9038; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9039; GFX9-NEXT:    s_cmp_lg_u32 s17, 09040; GFX9-NEXT:    s_cbranch_scc0 .LBB75_49041; GFX9-NEXT:  ; %bb.1: ; %cmp.false9042; GFX9-NEXT:    s_cbranch_execnz .LBB75_39043; GFX9-NEXT:  .LBB75_2: ; %cmp.true9044; GFX9-NEXT:    s_add_i32 s16, s16, 39045; GFX9-NEXT:  .LBB75_3: ; %end9046; GFX9-NEXT:    v_mov_b32_e32 v0, s169047; GFX9-NEXT:    s_setpc_b64 s[30:31]9048; GFX9-NEXT:  .LBB75_4:9049; GFX9-NEXT:    s_branch .LBB75_29050;9051; GFX11-LABEL: bitcast_v1i32_to_v2bf16_scalar:9052; GFX11:       ; %bb.0:9053; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9054; GFX11-NEXT:    s_cmp_lg_u32 s1, 09055; GFX11-NEXT:    s_mov_b32 s1, 09056; GFX11-NEXT:    s_cbranch_scc0 .LBB75_39057; GFX11-NEXT:  ; %bb.1: ; %Flow9058; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s19059; GFX11-NEXT:    s_cbranch_vccz .LBB75_49060; GFX11-NEXT:  ; %bb.2: ; %end9061; GFX11-NEXT:    v_mov_b32_e32 v0, s09062; GFX11-NEXT:    s_setpc_b64 s[30:31]9063; GFX11-NEXT:  .LBB75_3:9064; GFX11-NEXT:  .LBB75_4: ; %cmp.true9065; GFX11-NEXT:    s_add_i32 s0, s0, 39066; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9067; GFX11-NEXT:    v_mov_b32_e32 v0, s09068; GFX11-NEXT:    s_setpc_b64 s[30:31]9069  %cmp = icmp eq i32 %b, 09070  br i1 %cmp, label %cmp.true, label %cmp.false9071 9072cmp.true:9073  %a1 = add <1 x i32> %a, splat (i32 3)9074  %a2 = bitcast <1 x i32> %a1 to <2 x bfloat>9075  br label %end9076 9077cmp.false:9078  %a3 = bitcast <1 x i32> %a to <2 x bfloat>9079  br label %end9080 9081end:9082  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9083  ret <2 x bfloat> %phi9084}9085 9086define <4 x i8> @bitcast_v2bf16_to_v4i8(<2 x bfloat> %a, i32 %b) {9087; SI-LABEL: bitcast_v2bf16_to_v4i8:9088; SI:       ; %bb.0:9089; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9090; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v29091; SI-NEXT:    v_mul_f32_e32 v4, 1.0, v19092; SI-NEXT:    v_mul_f32_e32 v5, 1.0, v09093; SI-NEXT:    ; implicit-def: $vgpr09094; SI-NEXT:    ; implicit-def: $vgpr19095; SI-NEXT:    ; implicit-def: $vgpr29096; SI-NEXT:    ; implicit-def: $vgpr39097; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9098; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9099; SI-NEXT:    s_cbranch_execnz .LBB76_39100; SI-NEXT:  ; %bb.1: ; %Flow9101; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9102; SI-NEXT:    s_cbranch_execnz .LBB76_49103; SI-NEXT:  .LBB76_2: ; %end9104; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9105; SI-NEXT:    s_setpc_b64 s[30:31]9106; SI-NEXT:  .LBB76_3: ; %cmp.false9107; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v49108; SI-NEXT:    v_alignbit_b32 v0, v2, v5, 169109; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v49110; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v09111; SI-NEXT:    ; implicit-def: $vgpr59112; SI-NEXT:    ; implicit-def: $vgpr49113; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9114; SI-NEXT:    s_cbranch_execz .LBB76_29115; SI-NEXT:  .LBB76_4: ; %cmp.true9116; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v49117; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v59118; SI-NEXT:    v_add_f32_e32 v3, 0x40c00000, v19119; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v09120; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v39121; SI-NEXT:    v_alignbit_b32 v0, v2, v0, 169122; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v09123; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v39124; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9125; SI-NEXT:    s_setpc_b64 s[30:31]9126;9127; VI-LABEL: bitcast_v2bf16_to_v4i8:9128; VI:       ; %bb.0:9129; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9130; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v19131; VI-NEXT:    ; implicit-def: $vgpr19132; VI-NEXT:    ; implicit-def: $vgpr29133; VI-NEXT:    ; implicit-def: $vgpr39134; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9135; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9136; VI-NEXT:    s_cbranch_execnz .LBB76_39137; VI-NEXT:  ; %bb.1: ; %Flow9138; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9139; VI-NEXT:    s_cbranch_execnz .LBB76_49140; VI-NEXT:  .LBB76_2: ; %end9141; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9142; VI-NEXT:    s_setpc_b64 s[30:31]9143; VI-NEXT:  .LBB76_3: ; %cmp.false9144; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v09145; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v09146; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v09147; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9148; VI-NEXT:    s_cbranch_execz .LBB76_29149; VI-NEXT:  .LBB76_4: ; %cmp.true9150; VI-NEXT:    v_lshlrev_b32_e32 v1, 16, v09151; VI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v19152; VI-NEXT:    v_bfe_u32 v2, v1, 16, 19153; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v19154; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v29155; VI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v09156; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v19157; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v19158; VI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v09159; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc9160; VI-NEXT:    v_bfe_u32 v2, v0, 16, 19161; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v09162; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v29163; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v09164; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v09165; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc9166; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v09167; VI-NEXT:    v_alignbit_b32 v4, v2, v1, 169168; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v19169; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v49170; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v49171; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9172; VI-NEXT:    s_setpc_b64 s[30:31]9173;9174; GFX9-LABEL: bitcast_v2bf16_to_v4i8:9175; GFX9:       ; %bb.0:9176; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9177; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v19178; GFX9-NEXT:    ; implicit-def: $vgpr19179; GFX9-NEXT:    ; implicit-def: $vgpr29180; GFX9-NEXT:    ; implicit-def: $vgpr39181; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc9182; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9183; GFX9-NEXT:    s_cbranch_execnz .LBB76_39184; GFX9-NEXT:  ; %bb.1: ; %Flow9185; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9186; GFX9-NEXT:    s_cbranch_execnz .LBB76_49187; GFX9-NEXT:  .LBB76_2: ; %end9188; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9189; GFX9-NEXT:    s_setpc_b64 s[30:31]9190; GFX9-NEXT:  .LBB76_3: ; %cmp.false9191; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v09192; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v09193; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v09194; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9195; GFX9-NEXT:    s_cbranch_execz .LBB76_29196; GFX9-NEXT:  .LBB76_4: ; %cmp.true9197; GFX9-NEXT:    v_lshlrev_b32_e32 v1, 16, v09198; GFX9-NEXT:    v_add_f32_e32 v1, 0x40c00000, v19199; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 19200; GFX9-NEXT:    s_movk_i32 s6, 0x7fff9201; GFX9-NEXT:    v_and_b32_e32 v0, 0xffff0000, v09202; GFX9-NEXT:    v_add3_u32 v2, v2, v1, s69203; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v19204; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v19205; GFX9-NEXT:    v_add_f32_e32 v0, 0x40c00000, v09206; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc9207; GFX9-NEXT:    v_bfe_u32 v2, v0, 16, 19208; GFX9-NEXT:    v_add3_u32 v2, v2, v0, s69209; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v09210; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v09211; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc9212; GFX9-NEXT:    s_mov_b32 s6, 0x70603029213; GFX9-NEXT:    v_perm_b32 v4, v0, v1, s69214; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v09215; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v19216; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v49217; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v49218; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9219; GFX9-NEXT:    s_setpc_b64 s[30:31]9220;9221; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v4i8:9222; GFX11-TRUE16:       ; %bb.0:9223; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9224; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v4, v09225; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v19226; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr0_hi169227; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo169228; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi169229; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo169230; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo9231; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9232; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s09233; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false9234; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)9235; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v49236; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v49237; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.h, v4.l9238; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v4.h9239; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr49240; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow9241; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s09242; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB76_49243; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true9244; GFX11-TRUE16-NEXT:    v_and_b32_e32 v1, 0xffff0000, v49245; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)9246; GFX11-TRUE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_lshlrev_b32 v0, 16, v49247; GFX11-TRUE16-NEXT:    v_add_f32_e32 v0, 0x40c00000, v09248; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9249; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 19250; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 19251; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v09252; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v09253; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v19254; GFX11-TRUE16-NEXT:    v_add3_u32 v3, v3, v1, 0x7fff9255; GFX11-TRUE16-NEXT:    v_add3_u32 v2, v2, v0, 0x7fff9256; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4)9257; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo9258; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v19259; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v2, v3, v5, vcc_lo9260; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)9261; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v0.h9262; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v29263; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v29264; GFX11-TRUE16-NEXT:  .LBB76_4: ; %end9265; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09266; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v0.h9267; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h9268; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9269;9270; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v4i8:9271; GFX11-FAKE16:       ; %bb.0:9272; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9273; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v19274; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19275; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29276; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39277; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo9278; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9279; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s09280; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB76_39281; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow9282; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09283; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB76_49284; GFX11-FAKE16-NEXT:  .LBB76_2: ; %end9285; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09286; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9287; GFX11-FAKE16-NEXT:  .LBB76_3: ; %cmp.false9288; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v09289; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v09290; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v09291; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09292; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB76_29293; GFX11-FAKE16-NEXT:  .LBB76_4: ; %cmp.true9294; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v09295; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff0000, v09296; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)9297; GFX11-FAKE16-NEXT:    v_dual_add_f32 v1, 0x40c00000, v1 :: v_dual_add_f32 v0, 0x40c00000, v09298; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v1, 16, 19299; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)9300; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v0, 16, 19301; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v19302; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v19303; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v09304; GFX11-FAKE16-NEXT:    v_add3_u32 v2, v2, v1, 0x7fff9305; GFX11-FAKE16-NEXT:    v_add3_u32 v3, v3, v0, 0x7fff9306; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_3)9307; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v2, v4, vcc_lo9308; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v09309; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v3, v5, vcc_lo9310; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3)9311; GFX11-FAKE16-NEXT:    v_perm_b32 v4, v0, v1, 0x70603029312; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v09313; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v19314; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v49315; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v49316; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09317; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9318  %cmp = icmp eq i32 %b, 09319  br i1 %cmp, label %cmp.true, label %cmp.false9320 9321cmp.true:9322  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)9323  %a2 = bitcast <2 x bfloat> %a1 to <4 x i8>9324  br label %end9325 9326cmp.false:9327  %a3 = bitcast <2 x bfloat> %a to <4 x i8>9328  br label %end9329 9330end:9331  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9332  ret <4 x i8> %phi9333}9334 9335define inreg <4 x i8> @bitcast_v2bf16_to_v4i8_scalar(<2 x bfloat> inreg %a, i32 inreg %b) {9336; SI-LABEL: bitcast_v2bf16_to_v4i8_scalar:9337; SI:       ; %bb.0:9338; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9339; SI-NEXT:    s_cmp_lg_u32 s18, 09340; SI-NEXT:    v_mul_f32_e64 v0, 1.0, s179341; SI-NEXT:    v_mul_f32_e64 v1, 1.0, s169342; SI-NEXT:    s_cbranch_scc0 .LBB77_49343; SI-NEXT:  ; %bb.1: ; %cmp.false9344; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v09345; SI-NEXT:    v_lshr_b64 v[4:5], v[1:2], 169346; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v09347; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v49348; SI-NEXT:    s_cbranch_execnz .LBB77_39349; SI-NEXT:  .LBB77_2: ; %cmp.true9350; SI-NEXT:    v_and_b32_e32 v0, 0xffff0000, v09351; SI-NEXT:    v_and_b32_e32 v1, 0xffff0000, v19352; SI-NEXT:    v_add_f32_e32 v0, 0x40c00000, v09353; SI-NEXT:    v_add_f32_e32 v1, 0x40c00000, v19354; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v09355; SI-NEXT:    v_lshr_b64 v[4:5], v[1:2], 169356; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v09357; SI-NEXT:    v_lshrrev_b32_e32 v5, 8, v49358; SI-NEXT:  .LBB77_3: ; %end9359; SI-NEXT:    v_mov_b32_e32 v0, v49360; SI-NEXT:    v_mov_b32_e32 v1, v59361; SI-NEXT:    s_setpc_b64 s[30:31]9362; SI-NEXT:  .LBB77_4:9363; SI-NEXT:    ; implicit-def: $vgpr49364; SI-NEXT:    ; implicit-def: $vgpr59365; SI-NEXT:    ; implicit-def: $vgpr39366; SI-NEXT:    s_branch .LBB77_29367;9368; VI-LABEL: bitcast_v2bf16_to_v4i8_scalar:9369; VI:       ; %bb.0:9370; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9371; VI-NEXT:    s_cmp_lg_u32 s17, 09372; VI-NEXT:    s_cbranch_scc0 .LBB77_39373; VI-NEXT:  ; %bb.1: ; %cmp.false9374; VI-NEXT:    s_lshr_b32 s6, s16, 249375; VI-NEXT:    s_lshr_b32 s8, s16, 169376; VI-NEXT:    s_lshr_b32 s7, s16, 89377; VI-NEXT:    s_cbranch_execnz .LBB77_49378; VI-NEXT:  .LBB77_2: ; %cmp.true9379; VI-NEXT:    s_lshl_b32 s4, s16, 169380; VI-NEXT:    v_mov_b32_e32 v0, 0x40c000009381; VI-NEXT:    v_add_f32_e32 v1, s4, v09382; VI-NEXT:    v_bfe_u32 v2, v1, 16, 19383; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v19384; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v29385; VI-NEXT:    s_and_b32 s4, s16, 0xffff00009386; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v19387; VI-NEXT:    v_cmp_u_f32_e32 vcc, v1, v19388; VI-NEXT:    v_add_f32_e32 v0, s4, v09389; VI-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc9390; VI-NEXT:    v_bfe_u32 v2, v0, 16, 19391; VI-NEXT:    v_add_u32_e32 v2, vcc, v2, v09392; VI-NEXT:    v_add_u32_e32 v2, vcc, 0x7fff, v29393; VI-NEXT:    v_or_b32_e32 v3, 0x400000, v09394; VI-NEXT:    v_cmp_u_f32_e32 vcc, v0, v09395; VI-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc9396; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v09397; VI-NEXT:    v_lshrrev_b64 v[4:5], 16, v[1:2]9398; VI-NEXT:    v_lshrrev_b32_e32 v0, 16, v19399; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v49400; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v49401; VI-NEXT:    s_setpc_b64 s[30:31]9402; VI-NEXT:  .LBB77_3:9403; VI-NEXT:    ; implicit-def: $sgpr79404; VI-NEXT:    ; implicit-def: $sgpr89405; VI-NEXT:    ; implicit-def: $sgpr69406; VI-NEXT:    s_branch .LBB77_29407; VI-NEXT:  .LBB77_4:9408; VI-NEXT:    v_mov_b32_e32 v2, s89409; VI-NEXT:    v_mov_b32_e32 v0, s169410; VI-NEXT:    v_mov_b32_e32 v3, s69411; VI-NEXT:    v_mov_b32_e32 v1, s79412; VI-NEXT:    s_setpc_b64 s[30:31]9413;9414; GFX9-LABEL: bitcast_v2bf16_to_v4i8_scalar:9415; GFX9:       ; %bb.0:9416; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9417; GFX9-NEXT:    s_cmp_lg_u32 s17, 09418; GFX9-NEXT:    s_cbranch_scc0 .LBB77_39419; GFX9-NEXT:  ; %bb.1: ; %cmp.false9420; GFX9-NEXT:    s_lshr_b32 s6, s16, 249421; GFX9-NEXT:    s_lshr_b32 s8, s16, 169422; GFX9-NEXT:    s_lshr_b32 s7, s16, 89423; GFX9-NEXT:    s_cbranch_execnz .LBB77_49424; GFX9-NEXT:  .LBB77_2: ; %cmp.true9425; GFX9-NEXT:    s_and_b32 s4, s16, 0xffff00009426; GFX9-NEXT:    v_mov_b32_e32 v0, 0x40c000009427; GFX9-NEXT:    v_add_f32_e32 v1, s4, v09428; GFX9-NEXT:    v_bfe_u32 v2, v1, 16, 19429; GFX9-NEXT:    v_add_u32_e32 v2, v2, v19430; GFX9-NEXT:    v_add_u32_e32 v2, 0x7fff, v29431; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v19432; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v1, v19433; GFX9-NEXT:    s_lshl_b32 s4, s16, 169434; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v3, vcc9435; GFX9-NEXT:    v_add_f32_e32 v0, s4, v09436; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v19437; GFX9-NEXT:    v_bfe_u32 v1, v0, 16, 19438; GFX9-NEXT:    v_add_u32_e32 v1, v1, v09439; GFX9-NEXT:    v_add_u32_e32 v1, 0x7fff, v19440; GFX9-NEXT:    v_or_b32_e32 v3, 0x400000, v09441; GFX9-NEXT:    v_cmp_u_f32_e32 vcc, v0, v09442; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v3, vcc9443; GFX9-NEXT:    v_lshrrev_b32_e32 v0, 16, v09444; GFX9-NEXT:    v_and_b32_e32 v1, 0xffff, v09445; GFX9-NEXT:    v_lshl_or_b32 v1, v2, 16, v19446; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v19447; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v19448; GFX9-NEXT:    s_setpc_b64 s[30:31]9449; GFX9-NEXT:  .LBB77_3:9450; GFX9-NEXT:    ; implicit-def: $sgpr79451; GFX9-NEXT:    ; implicit-def: $sgpr89452; GFX9-NEXT:    ; implicit-def: $sgpr69453; GFX9-NEXT:    s_branch .LBB77_29454; GFX9-NEXT:  .LBB77_4:9455; GFX9-NEXT:    v_mov_b32_e32 v0, s169456; GFX9-NEXT:    v_mov_b32_e32 v2, s89457; GFX9-NEXT:    v_mov_b32_e32 v3, s69458; GFX9-NEXT:    v_mov_b32_e32 v1, s79459; GFX9-NEXT:    s_setpc_b64 s[30:31]9460;9461; GFX11-TRUE16-LABEL: bitcast_v2bf16_to_v4i8_scalar:9462; GFX11-TRUE16:       ; %bb.0:9463; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9464; GFX11-TRUE16-NEXT:    s_cmp_lg_u32 s1, 09465; GFX11-TRUE16-NEXT:    s_mov_b32 s1, 09466; GFX11-TRUE16-NEXT:    s_cbranch_scc0 .LBB77_39467; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false9468; GFX11-TRUE16-NEXT:    s_lshr_b32 s2, s0, 249469; GFX11-TRUE16-NEXT:    s_lshr_b32 s4, s0, 169470; GFX11-TRUE16-NEXT:    s_lshr_b32 s3, s0, 89471; GFX11-TRUE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s19472; GFX11-TRUE16-NEXT:    s_cbranch_vccnz .LBB77_49473; GFX11-TRUE16-NEXT:  .LBB77_2: ; %cmp.true9474; GFX11-TRUE16-NEXT:    s_lshl_b32 s1, s0, 169475; GFX11-TRUE16-NEXT:    s_and_b32 s0, s0, 0xffff00009476; GFX11-TRUE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s19477; GFX11-TRUE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s09478; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9479; GFX11-TRUE16-NEXT:    v_bfe_u32 v2, v0, 16, 19480; GFX11-TRUE16-NEXT:    v_bfe_u32 v3, v1, 16, 19481; GFX11-TRUE16-NEXT:    v_or_b32_e32 v4, 0x400000, v09482; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v09483; GFX11-TRUE16-NEXT:    v_or_b32_e32 v5, 0x400000, v19484; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)9485; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, v3, v19486; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v39487; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, v2, v09488; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)9489; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v29490; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo9491; GFX11-TRUE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v19492; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)9493; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v09494; GFX11-TRUE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo9495; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v19496; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)9497; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.l, v0.l9498; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v1.h, v2.l9499; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)9500; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v19501; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v19502; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9503; GFX11-TRUE16-NEXT:  .LBB77_3:9504; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr39505; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr49506; GFX11-TRUE16-NEXT:    ; implicit-def: $sgpr29507; GFX11-TRUE16-NEXT:    s_branch .LBB77_29508; GFX11-TRUE16-NEXT:  .LBB77_4:9509; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s29510; GFX11-TRUE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s39511; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9512;9513; GFX11-FAKE16-LABEL: bitcast_v2bf16_to_v4i8_scalar:9514; GFX11-FAKE16:       ; %bb.0:9515; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9516; GFX11-FAKE16-NEXT:    s_cmp_lg_u32 s1, 09517; GFX11-FAKE16-NEXT:    s_mov_b32 s1, 09518; GFX11-FAKE16-NEXT:    s_cbranch_scc0 .LBB77_39519; GFX11-FAKE16-NEXT:  ; %bb.1: ; %cmp.false9520; GFX11-FAKE16-NEXT:    s_lshr_b32 s2, s0, 249521; GFX11-FAKE16-NEXT:    s_lshr_b32 s4, s0, 169522; GFX11-FAKE16-NEXT:    s_lshr_b32 s3, s0, 89523; GFX11-FAKE16-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s19524; GFX11-FAKE16-NEXT:    s_cbranch_vccnz .LBB77_49525; GFX11-FAKE16-NEXT:  .LBB77_2: ; %cmp.true9526; GFX11-FAKE16-NEXT:    s_lshl_b32 s1, s0, 169527; GFX11-FAKE16-NEXT:    s_and_b32 s0, s0, 0xffff00009528; GFX11-FAKE16-NEXT:    v_add_f32_e64 v0, 0x40c00000, s19529; GFX11-FAKE16-NEXT:    v_add_f32_e64 v1, 0x40c00000, s09530; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9531; GFX11-FAKE16-NEXT:    v_bfe_u32 v2, v0, 16, 19532; GFX11-FAKE16-NEXT:    v_bfe_u32 v3, v1, 16, 19533; GFX11-FAKE16-NEXT:    v_or_b32_e32 v4, 0x400000, v09534; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v0, v09535; GFX11-FAKE16-NEXT:    v_or_b32_e32 v5, 0x400000, v19536; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_1)9537; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, v3, v19538; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v3, 0x7fff, v39539; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, v2, v09540; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)9541; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v2, 0x7fff, v29542; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v0, v2, v4, vcc_lo9543; GFX11-FAKE16-NEXT:    v_cmp_u_f32_e32 vcc_lo, v1, v19544; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)9545; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v0, 16, v09546; GFX11-FAKE16-NEXT:    v_cndmask_b32_e32 v1, v3, v5, vcc_lo9547; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v19548; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)9549; GFX11-FAKE16-NEXT:    v_and_b32_e32 v1, 0xffff, v09550; GFX11-FAKE16-NEXT:    v_lshl_or_b32 v1, v2, 16, v19551; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)9552; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v19553; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v19554; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9555; GFX11-FAKE16-NEXT:  .LBB77_3:9556; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr39557; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr49558; GFX11-FAKE16-NEXT:    ; implicit-def: $sgpr29559; GFX11-FAKE16-NEXT:    s_branch .LBB77_29560; GFX11-FAKE16-NEXT:  .LBB77_4:9561; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s29562; GFX11-FAKE16-NEXT:    v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v1, s39563; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9564  %cmp = icmp eq i32 %b, 09565  br i1 %cmp, label %cmp.true, label %cmp.false9566 9567cmp.true:9568  %a1 = fadd <2 x bfloat> %a, splat (bfloat 0xR40C0)9569  %a2 = bitcast <2 x bfloat> %a1 to <4 x i8>9570  br label %end9571 9572cmp.false:9573  %a3 = bitcast <2 x bfloat> %a to <4 x i8>9574  br label %end9575 9576end:9577  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9578  ret <4 x i8> %phi9579}9580 9581define <2 x bfloat> @bitcast_v4i8_to_v2bf16(<4 x i8> %a, i32 %b) {9582; SI-LABEL: bitcast_v4i8_to_v2bf16:9583; SI:       ; %bb.0:9584; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9585; SI-NEXT:    v_mov_b32_e32 v5, v09586; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v49587; SI-NEXT:    v_lshlrev_b32_e32 v4, 24, v19588; SI-NEXT:    v_lshlrev_b32_e32 v3, 24, v39589; SI-NEXT:    ; implicit-def: $vgpr09590; SI-NEXT:    ; implicit-def: $vgpr19591; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9592; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9593; SI-NEXT:    s_cbranch_execnz .LBB78_39594; SI-NEXT:  ; %bb.1: ; %Flow9595; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9596; SI-NEXT:    s_cbranch_execnz .LBB78_49597; SI-NEXT:  .LBB78_2: ; %end9598; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9599; SI-NEXT:    s_setpc_b64 s[30:31]9600; SI-NEXT:  .LBB78_3: ; %cmp.false9601; SI-NEXT:    v_and_b32_e32 v0, 0xff, v59602; SI-NEXT:    v_and_b32_e32 v1, 0xff, v29603; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v09604; SI-NEXT:    v_lshlrev_b32_e32 v1, 16, v19605; SI-NEXT:    v_or_b32_e32 v0, v4, v09606; SI-NEXT:    v_or_b32_e32 v1, v3, v19607; SI-NEXT:    ; implicit-def: $vgpr29608; SI-NEXT:    ; implicit-def: $vgpr39609; SI-NEXT:    ; implicit-def: $vgpr59610; SI-NEXT:    ; implicit-def: $vgpr49611; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9612; SI-NEXT:    s_cbranch_execz .LBB78_29613; SI-NEXT:  .LBB78_4: ; %cmp.true9614; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v29615; SI-NEXT:    v_and_b32_e32 v0, 0xff, v09616; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v09617; SI-NEXT:    v_or_b32_e32 v1, v3, v09618; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v59619; SI-NEXT:    v_and_b32_e32 v0, 0xff, v09620; SI-NEXT:    v_lshlrev_b32_e32 v0, 16, v09621; SI-NEXT:    v_or_b32_e32 v0, v4, v09622; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v09623; SI-NEXT:    v_add_i32_e32 v1, vcc, 0x3000000, v19624; SI-NEXT:    s_or_b64 exec, exec, s[4:5]9625; SI-NEXT:    s_setpc_b64 s[30:31]9626;9627; VI-LABEL: bitcast_v4i8_to_v2bf16:9628; VI:       ; %bb.0:9629; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9630; VI-NEXT:    v_mov_b32_e32 v5, v09631; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v49632; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v19633; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v39634; VI-NEXT:    ; implicit-def: $vgpr09635; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9636; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9637; VI-NEXT:    s_cbranch_execnz .LBB78_39638; VI-NEXT:  ; %bb.1: ; %Flow9639; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9640; VI-NEXT:    s_cbranch_execnz .LBB78_49641; VI-NEXT:  .LBB78_2: ; %end9642; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9643; VI-NEXT:    s_setpc_b64 s[30:31]9644; VI-NEXT:  .LBB78_3: ; %cmp.false9645; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9646; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9647; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9648; VI-NEXT:    ; implicit-def: $vgpr59649; VI-NEXT:    ; implicit-def: $vgpr49650; VI-NEXT:    ; implicit-def: $vgpr29651; VI-NEXT:    ; implicit-def: $vgpr19652; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9653; VI-NEXT:    s_cbranch_execz .LBB78_29654; VI-NEXT:  .LBB78_4: ; %cmp.true9655; VI-NEXT:    v_add_u16_e32 v0, 3, v59656; VI-NEXT:    v_add_u16_e32 v2, 3, v29657; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09658; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09659; VI-NEXT:    v_mov_b32_e32 v2, 0x3009660; VI-NEXT:    v_add_u16_e32 v0, 0x300, v09661; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9662; VI-NEXT:    v_or_b32_e32 v0, v0, v19663; VI-NEXT:    s_or_b64 exec, exec, s[4:5]9664; VI-NEXT:    s_setpc_b64 s[30:31]9665;9666; GFX9-LABEL: bitcast_v4i8_to_v2bf16:9667; GFX9:       ; %bb.0:9668; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9669; GFX9-NEXT:    v_mov_b32_e32 v5, v09670; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v49671; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v19672; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v39673; GFX9-NEXT:    ; implicit-def: $vgpr09674; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc9675; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9676; GFX9-NEXT:    s_cbranch_execnz .LBB78_39677; GFX9-NEXT:  ; %bb.1: ; %Flow9678; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9679; GFX9-NEXT:    s_cbranch_execnz .LBB78_49680; GFX9-NEXT:  .LBB78_2: ; %end9681; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9682; GFX9-NEXT:    s_setpc_b64 s[30:31]9683; GFX9-NEXT:  .LBB78_3: ; %cmp.false9684; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9685; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD9686; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD9687; GFX9-NEXT:    ; implicit-def: $vgpr59688; GFX9-NEXT:    ; implicit-def: $vgpr49689; GFX9-NEXT:    ; implicit-def: $vgpr29690; GFX9-NEXT:    ; implicit-def: $vgpr19691; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]9692; GFX9-NEXT:    s_cbranch_execz .LBB78_29693; GFX9-NEXT:  .LBB78_4: ; %cmp.true9694; GFX9-NEXT:    v_add_u16_e32 v0, 3, v59695; GFX9-NEXT:    v_add_u16_e32 v2, 3, v29696; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09697; GFX9-NEXT:    s_movk_i32 s6, 0x3009698; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_09699; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v09700; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD9701; GFX9-NEXT:    v_or_b32_e32 v0, v0, v19702; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]9703; GFX9-NEXT:    s_setpc_b64 s[30:31]9704;9705; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v2bf16:9706; GFX11-TRUE16:       ; %bb.0:9707; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9708; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l9709; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l9710; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l9711; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo9712; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr09713; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v49714; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s09715; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB78_39716; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow9717; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s09718; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB78_49719; GFX11-TRUE16-NEXT:  .LBB78_2: ; %end9720; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09721; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9722; GFX11-TRUE16-NEXT:  .LBB78_3: ; %cmp.false9723; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h9724; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l9725; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi169726; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo169727; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9728; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l9729; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h9730; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo169731; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi169732; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s09733; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB78_29734; GFX11-TRUE16-NEXT:  .LBB78_4: ; %cmp.true9735; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 39736; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 39737; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9738; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l9739; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h9740; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9741; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l9742; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h9743; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9744; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l9745; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h9746; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09747; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]9748;9749; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v2bf16:9750; GFX11-FAKE16:       ; %bb.0:9751; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9752; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v09753; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v19754; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v39755; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo9756; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr09757; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v49758; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s09759; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB78_39760; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow9761; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09762; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB78_49763; GFX11-FAKE16-NEXT:  .LBB78_2: ; %end9764; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09765; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9766; GFX11-FAKE16-NEXT:  .LBB78_3: ; %cmp.false9767; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v59768; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v29769; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr59770; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9771; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v19772; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v39773; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr29774; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr39775; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9776; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v09777; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v19778; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)9779; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v19780; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr19781; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s09782; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB78_29783; GFX11-FAKE16-NEXT:  .LBB78_4: ; %cmp.true9784; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 39785; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 39786; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9787; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v09788; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v29789; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9790; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v09791; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v29792; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9793; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v09794; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v19795; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)9796; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v09797; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v19798; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)9799; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v19800; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s09801; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]9802  %cmp = icmp eq i32 %b, 09803  br i1 %cmp, label %cmp.true, label %cmp.false9804 9805cmp.true:9806  %a1 = add <4 x i8> %a, splat (i8 3)9807  %a2 = bitcast <4 x i8> %a1 to <2 x bfloat>9808  br label %end9809 9810cmp.false:9811  %a3 = bitcast <4 x i8> %a to <2 x bfloat>9812  br label %end9813 9814end:9815  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9816  ret <2 x bfloat> %phi9817}9818 9819define inreg <2 x bfloat> @bitcast_v4i8_to_v2bf16_scalar(<4 x i8> inreg %a, i32 inreg %b) {9820; SI-LABEL: bitcast_v4i8_to_v2bf16_scalar:9821; SI:       ; %bb.0:9822; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9823; SI-NEXT:    s_cmp_lg_u32 s20, 09824; SI-NEXT:    s_cbranch_scc0 .LBB79_49825; SI-NEXT:  ; %bb.1: ; %cmp.false9826; SI-NEXT:    s_and_b32 s4, s16, 0xff9827; SI-NEXT:    s_lshl_b32 s4, s4, 169828; SI-NEXT:    s_lshl_b32 s5, s17, 249829; SI-NEXT:    s_or_b32 s6, s5, s49830; SI-NEXT:    s_and_b32 s4, s18, 0xff9831; SI-NEXT:    s_lshl_b32 s4, s4, 169832; SI-NEXT:    s_lshl_b32 s5, s19, 249833; SI-NEXT:    s_or_b32 s7, s5, s49834; SI-NEXT:    s_cbranch_execnz .LBB79_39835; SI-NEXT:  .LBB79_2: ; %cmp.true9836; SI-NEXT:    s_add_i32 s18, s18, 39837; SI-NEXT:    s_and_b32 s5, s18, 0xff9838; SI-NEXT:    s_add_i32 s16, s16, 39839; SI-NEXT:    s_lshl_b32 s4, s19, 249840; SI-NEXT:    s_lshl_b32 s5, s5, 169841; SI-NEXT:    s_and_b32 s6, s16, 0xff9842; SI-NEXT:    s_or_b32 s4, s4, s59843; SI-NEXT:    s_lshl_b32 s5, s17, 249844; SI-NEXT:    s_lshl_b32 s6, s6, 169845; SI-NEXT:    s_or_b32 s5, s5, s69846; SI-NEXT:    s_add_i32 s6, s5, 0x30000009847; SI-NEXT:    s_add_i32 s7, s4, 0x30000009848; SI-NEXT:  .LBB79_3: ; %end9849; SI-NEXT:    v_mov_b32_e32 v0, s69850; SI-NEXT:    v_mov_b32_e32 v1, s79851; SI-NEXT:    s_setpc_b64 s[30:31]9852; SI-NEXT:  .LBB79_4:9853; SI-NEXT:    ; implicit-def: $sgpr69854; SI-NEXT:    ; implicit-def: $sgpr79855; SI-NEXT:    s_branch .LBB79_29856;9857; VI-LABEL: bitcast_v4i8_to_v2bf16_scalar:9858; VI:       ; %bb.0:9859; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9860; VI-NEXT:    s_cmp_lg_u32 s20, 09861; VI-NEXT:    s_cbranch_scc0 .LBB79_49862; VI-NEXT:  ; %bb.1: ; %cmp.false9863; VI-NEXT:    s_and_b32 s4, s16, 0xff9864; VI-NEXT:    s_lshl_b32 s5, s17, 89865; VI-NEXT:    s_or_b32 s4, s4, s59866; VI-NEXT:    s_and_b32 s5, s18, 0xff9867; VI-NEXT:    s_lshl_b32 s6, s19, 89868; VI-NEXT:    s_or_b32 s5, s5, s69869; VI-NEXT:    s_and_b32 s4, s4, 0xffff9870; VI-NEXT:    s_lshl_b32 s5, s5, 169871; VI-NEXT:    s_or_b32 s6, s4, s59872; VI-NEXT:    s_cbranch_execnz .LBB79_39873; VI-NEXT:  .LBB79_2: ; %cmp.true9874; VI-NEXT:    s_add_i32 s16, s16, 39875; VI-NEXT:    s_and_b32 s4, s16, 0xff9876; VI-NEXT:    s_lshl_b32 s5, s17, 89877; VI-NEXT:    s_add_i32 s18, s18, 39878; VI-NEXT:    s_or_b32 s4, s5, s49879; VI-NEXT:    s_and_b32 s5, s18, 0xff9880; VI-NEXT:    s_lshl_b32 s6, s19, 89881; VI-NEXT:    s_addk_i32 s4, 0x3009882; VI-NEXT:    s_or_b32 s5, s6, s59883; VI-NEXT:    s_and_b32 s4, s4, 0xffff9884; VI-NEXT:    s_lshl_b32 s5, s5, 169885; VI-NEXT:    s_or_b32 s4, s5, s49886; VI-NEXT:    s_add_i32 s6, s4, 0x30000009887; VI-NEXT:  .LBB79_3: ; %end9888; VI-NEXT:    v_mov_b32_e32 v0, s69889; VI-NEXT:    s_setpc_b64 s[30:31]9890; VI-NEXT:  .LBB79_4:9891; VI-NEXT:    ; implicit-def: $sgpr69892; VI-NEXT:    s_branch .LBB79_29893;9894; GFX9-LABEL: bitcast_v4i8_to_v2bf16_scalar:9895; GFX9:       ; %bb.0:9896; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9897; GFX9-NEXT:    s_cmp_lg_u32 s20, 09898; GFX9-NEXT:    s_cbranch_scc0 .LBB79_49899; GFX9-NEXT:  ; %bb.1: ; %cmp.false9900; GFX9-NEXT:    s_and_b32 s4, s16, 0xff9901; GFX9-NEXT:    s_lshl_b32 s5, s17, 89902; GFX9-NEXT:    s_or_b32 s4, s4, s59903; GFX9-NEXT:    s_and_b32 s5, s18, 0xff9904; GFX9-NEXT:    s_lshl_b32 s6, s19, 89905; GFX9-NEXT:    s_or_b32 s5, s5, s69906; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff9907; GFX9-NEXT:    s_lshl_b32 s5, s5, 169908; GFX9-NEXT:    s_or_b32 s6, s4, s59909; GFX9-NEXT:    s_cbranch_execnz .LBB79_39910; GFX9-NEXT:  .LBB79_2: ; %cmp.true9911; GFX9-NEXT:    s_add_i32 s16, s16, 39912; GFX9-NEXT:    s_and_b32 s4, s16, 0xff9913; GFX9-NEXT:    s_lshl_b32 s5, s17, 89914; GFX9-NEXT:    s_add_i32 s18, s18, 39915; GFX9-NEXT:    s_or_b32 s4, s5, s49916; GFX9-NEXT:    s_and_b32 s5, s18, 0xff9917; GFX9-NEXT:    s_lshl_b32 s6, s19, 89918; GFX9-NEXT:    s_or_b32 s5, s6, s59919; GFX9-NEXT:    s_addk_i32 s4, 0x3009920; GFX9-NEXT:    s_addk_i32 s5, 0x3009921; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff9922; GFX9-NEXT:    s_lshl_b32 s5, s5, 169923; GFX9-NEXT:    s_or_b32 s6, s4, s59924; GFX9-NEXT:  .LBB79_3: ; %end9925; GFX9-NEXT:    v_mov_b32_e32 v0, s69926; GFX9-NEXT:    s_setpc_b64 s[30:31]9927; GFX9-NEXT:  .LBB79_4:9928; GFX9-NEXT:    ; implicit-def: $sgpr69929; GFX9-NEXT:    s_branch .LBB79_29930;9931; GFX11-LABEL: bitcast_v4i8_to_v2bf16_scalar:9932; GFX11:       ; %bb.0:9933; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9934; GFX11-NEXT:    s_cmp_lg_u32 s16, 09935; GFX11-NEXT:    s_mov_b32 s4, 09936; GFX11-NEXT:    s_cbranch_scc0 .LBB79_49937; GFX11-NEXT:  ; %bb.1: ; %cmp.false9938; GFX11-NEXT:    s_and_b32 s5, s0, 0xff9939; GFX11-NEXT:    s_lshl_b32 s6, s1, 89940; GFX11-NEXT:    s_and_b32 s7, s2, 0xff9941; GFX11-NEXT:    s_lshl_b32 s8, s3, 89942; GFX11-NEXT:    s_or_b32 s5, s5, s69943; GFX11-NEXT:    s_or_b32 s6, s7, s89944; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff9945; GFX11-NEXT:    s_lshl_b32 s6, s6, 169946; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9947; GFX11-NEXT:    s_or_b32 s5, s5, s69948; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s49949; GFX11-NEXT:    s_cbranch_vccnz .LBB79_39950; GFX11-NEXT:  .LBB79_2: ; %cmp.true9951; GFX11-NEXT:    s_add_i32 s0, s0, 39952; GFX11-NEXT:    s_add_i32 s2, s2, 39953; GFX11-NEXT:    s_and_b32 s0, s0, 0xff9954; GFX11-NEXT:    s_lshl_b32 s1, s1, 89955; GFX11-NEXT:    s_and_b32 s2, s2, 0xff9956; GFX11-NEXT:    s_lshl_b32 s3, s3, 89957; GFX11-NEXT:    s_or_b32 s0, s1, s09958; GFX11-NEXT:    s_or_b32 s1, s3, s29959; GFX11-NEXT:    s_addk_i32 s0, 0x3009960; GFX11-NEXT:    s_addk_i32 s1, 0x3009961; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff9962; GFX11-NEXT:    s_lshl_b32 s1, s1, 169963; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9964; GFX11-NEXT:    s_or_b32 s5, s0, s19965; GFX11-NEXT:  .LBB79_3: ; %end9966; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)9967; GFX11-NEXT:    v_mov_b32_e32 v0, s59968; GFX11-NEXT:    s_setpc_b64 s[30:31]9969; GFX11-NEXT:  .LBB79_4:9970; GFX11-NEXT:    ; implicit-def: $sgpr59971; GFX11-NEXT:    s_branch .LBB79_29972  %cmp = icmp eq i32 %b, 09973  br i1 %cmp, label %cmp.true, label %cmp.false9974 9975cmp.true:9976  %a1 = add <4 x i8> %a, splat (i8 3)9977  %a2 = bitcast <4 x i8> %a1 to <2 x bfloat>9978  br label %end9979 9980cmp.false:9981  %a3 = bitcast <4 x i8> %a to <2 x bfloat>9982  br label %end9983 9984end:9985  %phi = phi <2 x bfloat> [ %a2, %cmp.true ], [ %a3, %cmp.false ]9986  ret <2 x bfloat> %phi9987}9988 9989define <4 x i8> @bitcast_v1i32_to_v4i8(<1 x i32> %a, i32 %b) {9990; SI-LABEL: bitcast_v1i32_to_v4i8:9991; SI:       ; %bb.0:9992; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9993; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v19994; SI-NEXT:    ; implicit-def: $vgpr19995; SI-NEXT:    ; implicit-def: $vgpr29996; SI-NEXT:    ; implicit-def: $vgpr39997; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc9998; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]9999; SI-NEXT:    s_cbranch_execnz .LBB80_310000; SI-NEXT:  ; %bb.1: ; %Flow10001; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10002; SI-NEXT:    s_cbranch_execnz .LBB80_410003; SI-NEXT:  .LBB80_2: ; %end10004; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10005; SI-NEXT:    s_setpc_b64 s[30:31]10006; SI-NEXT:  .LBB80_3: ; %cmp.false10007; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v010008; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v010009; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v010010; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10011; SI-NEXT:    s_cbranch_execz .LBB80_210012; SI-NEXT:  .LBB80_4: ; %cmp.true10013; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v010014; SI-NEXT:    v_lshrrev_b32_e32 v2, 16, v010015; SI-NEXT:    v_lshrrev_b32_e32 v3, 24, v010016; SI-NEXT:    v_lshrrev_b32_e32 v1, 8, v010017; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10018; SI-NEXT:    s_setpc_b64 s[30:31]10019;10020; VI-LABEL: bitcast_v1i32_to_v4i8:10021; VI:       ; %bb.0:10022; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10023; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v110024; VI-NEXT:    ; implicit-def: $vgpr110025; VI-NEXT:    ; implicit-def: $vgpr210026; VI-NEXT:    ; implicit-def: $vgpr310027; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10028; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10029; VI-NEXT:    s_cbranch_execnz .LBB80_310030; VI-NEXT:  ; %bb.1: ; %Flow10031; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10032; VI-NEXT:    s_cbranch_execnz .LBB80_410033; VI-NEXT:  .LBB80_2: ; %end10034; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10035; VI-NEXT:    s_setpc_b64 s[30:31]10036; VI-NEXT:  .LBB80_3: ; %cmp.false10037; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v010038; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v010039; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v010040; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10041; VI-NEXT:    s_cbranch_execz .LBB80_210042; VI-NEXT:  .LBB80_4: ; %cmp.true10043; VI-NEXT:    v_add_u32_e32 v0, vcc, 3, v010044; VI-NEXT:    v_lshrrev_b32_e32 v2, 16, v010045; VI-NEXT:    v_lshrrev_b32_e32 v3, 24, v010046; VI-NEXT:    v_lshrrev_b32_e32 v1, 8, v010047; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10048; VI-NEXT:    s_setpc_b64 s[30:31]10049;10050; GFX9-LABEL: bitcast_v1i32_to_v4i8:10051; GFX9:       ; %bb.0:10052; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10053; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v110054; GFX9-NEXT:    ; implicit-def: $vgpr110055; GFX9-NEXT:    ; implicit-def: $vgpr210056; GFX9-NEXT:    ; implicit-def: $vgpr310057; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10058; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10059; GFX9-NEXT:    s_cbranch_execnz .LBB80_310060; GFX9-NEXT:  ; %bb.1: ; %Flow10061; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10062; GFX9-NEXT:    s_cbranch_execnz .LBB80_410063; GFX9-NEXT:  .LBB80_2: ; %end10064; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10065; GFX9-NEXT:    s_setpc_b64 s[30:31]10066; GFX9-NEXT:  .LBB80_3: ; %cmp.false10067; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v010068; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v010069; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v010070; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10071; GFX9-NEXT:    s_cbranch_execz .LBB80_210072; GFX9-NEXT:  .LBB80_4: ; %cmp.true10073; GFX9-NEXT:    v_add_u32_e32 v0, 3, v010074; GFX9-NEXT:    v_lshrrev_b32_e32 v2, 16, v010075; GFX9-NEXT:    v_lshrrev_b32_e32 v3, 24, v010076; GFX9-NEXT:    v_lshrrev_b32_e32 v1, 8, v010077; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10078; GFX9-NEXT:    s_setpc_b64 s[30:31]10079;10080; GFX11-TRUE16-LABEL: bitcast_v1i32_to_v4i8:10081; GFX11-TRUE16:       ; %bb.0:10082; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10083; GFX11-TRUE16-NEXT:    v_mov_b32_e32 v2, v010084; GFX11-TRUE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v110085; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo1610086; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr3_lo1610087; GFX11-TRUE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo10088; GFX11-TRUE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10089; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s010090; GFX11-TRUE16-NEXT:  ; %bb.1: ; %cmp.false10091; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2)10092; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v210093; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v210094; GFX11-TRUE16-NEXT:  ; %bb.2: ; %Flow10095; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s010096; GFX11-TRUE16-NEXT:  ; %bb.3: ; %cmp.true10097; GFX11-TRUE16-NEXT:    v_add_nc_u32_e32 v2, 3, v210098; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)10099; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v210100; GFX11-TRUE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v210101; GFX11-TRUE16-NEXT:  ; %bb.4: ; %end10102; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010103; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v0.l, v2.l10104; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.l, v2.h10105; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]10106;10107; GFX11-FAKE16-LABEL: bitcast_v1i32_to_v4i8:10108; GFX11-FAKE16:       ; %bb.0:10109; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10110; GFX11-FAKE16-NEXT:    v_cmp_ne_u32_e32 vcc_lo, 0, v110111; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110112; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr210113; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr310114; GFX11-FAKE16-NEXT:    s_and_saveexec_b32 s0, vcc_lo10115; GFX11-FAKE16-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10116; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s010117; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB80_310118; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow10119; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s010120; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB80_410121; GFX11-FAKE16-NEXT:  .LBB80_2: ; %end10122; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010123; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]10124; GFX11-FAKE16-NEXT:  .LBB80_3: ; %cmp.false10125; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v010126; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v010127; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v010128; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s010129; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB80_210130; GFX11-FAKE16-NEXT:  .LBB80_4: ; %cmp.true10131; GFX11-FAKE16-NEXT:    v_add_nc_u32_e32 v0, 3, v010132; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)10133; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v2, 16, v010134; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v3, 24, v010135; GFX11-FAKE16-NEXT:    v_lshrrev_b32_e32 v1, 8, v010136; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010137; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]10138  %cmp = icmp eq i32 %b, 010139  br i1 %cmp, label %cmp.true, label %cmp.false10140 10141cmp.true:10142  %a1 = add <1 x i32> %a, splat (i32 3)10143  %a2 = bitcast <1 x i32> %a1 to <4 x i8>10144  br label %end10145 10146cmp.false:10147  %a3 = bitcast <1 x i32> %a to <4 x i8>10148  br label %end10149 10150end:10151  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10152  ret <4 x i8> %phi10153}10154 10155define inreg <4 x i8> @bitcast_v1i32_to_v4i8_scalar(<1 x i32> inreg %a, i32 inreg %b) {10156; SI-LABEL: bitcast_v1i32_to_v4i8_scalar:10157; SI:       ; %bb.0:10158; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10159; SI-NEXT:    s_cmp_lg_u32 s17, 010160; SI-NEXT:    s_cbranch_scc0 .LBB81_410161; SI-NEXT:  ; %bb.1: ; %cmp.false10162; SI-NEXT:    s_lshr_b32 s6, s16, 2410163; SI-NEXT:    s_lshr_b32 s7, s16, 1610164; SI-NEXT:    s_lshr_b32 s8, s16, 810165; SI-NEXT:    s_cbranch_execnz .LBB81_310166; SI-NEXT:  .LBB81_2: ; %cmp.true10167; SI-NEXT:    s_add_i32 s16, s16, 310168; SI-NEXT:    s_lshr_b32 s7, s16, 1610169; SI-NEXT:    s_lshr_b32 s6, s16, 2410170; SI-NEXT:    s_lshr_b32 s8, s16, 810171; SI-NEXT:  .LBB81_3: ; %end10172; SI-NEXT:    v_mov_b32_e32 v0, s1610173; SI-NEXT:    v_mov_b32_e32 v1, s810174; SI-NEXT:    v_mov_b32_e32 v2, s710175; SI-NEXT:    v_mov_b32_e32 v3, s610176; SI-NEXT:    s_setpc_b64 s[30:31]10177; SI-NEXT:  .LBB81_4:10178; SI-NEXT:    ; implicit-def: $sgpr810179; SI-NEXT:    ; implicit-def: $sgpr710180; SI-NEXT:    ; implicit-def: $sgpr610181; SI-NEXT:    s_branch .LBB81_210182;10183; VI-LABEL: bitcast_v1i32_to_v4i8_scalar:10184; VI:       ; %bb.0:10185; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10186; VI-NEXT:    s_cmp_lg_u32 s17, 010187; VI-NEXT:    s_cbranch_scc0 .LBB81_410188; VI-NEXT:  ; %bb.1: ; %cmp.false10189; VI-NEXT:    s_lshr_b32 s6, s16, 2410190; VI-NEXT:    s_lshr_b32 s7, s16, 1610191; VI-NEXT:    s_lshr_b32 s8, s16, 810192; VI-NEXT:    s_cbranch_execnz .LBB81_310193; VI-NEXT:  .LBB81_2: ; %cmp.true10194; VI-NEXT:    s_add_i32 s16, s16, 310195; VI-NEXT:    s_lshr_b32 s7, s16, 1610196; VI-NEXT:    s_lshr_b32 s6, s16, 2410197; VI-NEXT:    s_lshr_b32 s8, s16, 810198; VI-NEXT:  .LBB81_3: ; %end10199; VI-NEXT:    v_mov_b32_e32 v0, s1610200; VI-NEXT:    v_mov_b32_e32 v1, s810201; VI-NEXT:    v_mov_b32_e32 v2, s710202; VI-NEXT:    v_mov_b32_e32 v3, s610203; VI-NEXT:    s_setpc_b64 s[30:31]10204; VI-NEXT:  .LBB81_4:10205; VI-NEXT:    ; implicit-def: $sgpr810206; VI-NEXT:    ; implicit-def: $sgpr710207; VI-NEXT:    ; implicit-def: $sgpr610208; VI-NEXT:    s_branch .LBB81_210209;10210; GFX9-LABEL: bitcast_v1i32_to_v4i8_scalar:10211; GFX9:       ; %bb.0:10212; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10213; GFX9-NEXT:    s_cmp_lg_u32 s17, 010214; GFX9-NEXT:    s_cbranch_scc0 .LBB81_410215; GFX9-NEXT:  ; %bb.1: ; %cmp.false10216; GFX9-NEXT:    s_lshr_b32 s6, s16, 2410217; GFX9-NEXT:    s_lshr_b32 s7, s16, 1610218; GFX9-NEXT:    s_lshr_b32 s8, s16, 810219; GFX9-NEXT:    s_cbranch_execnz .LBB81_310220; GFX9-NEXT:  .LBB81_2: ; %cmp.true10221; GFX9-NEXT:    s_add_i32 s16, s16, 310222; GFX9-NEXT:    s_lshr_b32 s7, s16, 1610223; GFX9-NEXT:    s_lshr_b32 s6, s16, 2410224; GFX9-NEXT:    s_lshr_b32 s8, s16, 810225; GFX9-NEXT:  .LBB81_3: ; %end10226; GFX9-NEXT:    v_mov_b32_e32 v0, s1610227; GFX9-NEXT:    v_mov_b32_e32 v1, s810228; GFX9-NEXT:    v_mov_b32_e32 v2, s710229; GFX9-NEXT:    v_mov_b32_e32 v3, s610230; GFX9-NEXT:    s_setpc_b64 s[30:31]10231; GFX9-NEXT:  .LBB81_4:10232; GFX9-NEXT:    ; implicit-def: $sgpr810233; GFX9-NEXT:    ; implicit-def: $sgpr710234; GFX9-NEXT:    ; implicit-def: $sgpr610235; GFX9-NEXT:    s_branch .LBB81_210236;10237; GFX11-LABEL: bitcast_v1i32_to_v4i8_scalar:10238; GFX11:       ; %bb.0:10239; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10240; GFX11-NEXT:    s_cmp_lg_u32 s1, 010241; GFX11-NEXT:    s_mov_b32 s4, 010242; GFX11-NEXT:    s_cbranch_scc0 .LBB81_410243; GFX11-NEXT:  ; %bb.1: ; %cmp.false10244; GFX11-NEXT:    s_lshr_b32 s1, s0, 2410245; GFX11-NEXT:    s_lshr_b32 s2, s0, 1610246; GFX11-NEXT:    s_lshr_b32 s3, s0, 810247; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s410248; GFX11-NEXT:    s_cbranch_vccnz .LBB81_310249; GFX11-NEXT:  .LBB81_2: ; %cmp.true10250; GFX11-NEXT:    s_add_i32 s0, s0, 310251; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10252; GFX11-NEXT:    s_lshr_b32 s2, s0, 1610253; GFX11-NEXT:    s_lshr_b32 s1, s0, 2410254; GFX11-NEXT:    s_lshr_b32 s3, s0, 810255; GFX11-NEXT:  .LBB81_3: ; %end10256; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10257; GFX11-NEXT:    v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s310258; GFX11-NEXT:    v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s110259; GFX11-NEXT:    s_setpc_b64 s[30:31]10260; GFX11-NEXT:  .LBB81_4:10261; GFX11-NEXT:    ; implicit-def: $sgpr310262; GFX11-NEXT:    ; implicit-def: $sgpr210263; GFX11-NEXT:    ; implicit-def: $sgpr110264; GFX11-NEXT:    s_branch .LBB81_210265  %cmp = icmp eq i32 %b, 010266  br i1 %cmp, label %cmp.true, label %cmp.false10267 10268cmp.true:10269  %a1 = add <1 x i32> %a, splat (i32 3)10270  %a2 = bitcast <1 x i32> %a1 to <4 x i8>10271  br label %end10272 10273cmp.false:10274  %a3 = bitcast <1 x i32> %a to <4 x i8>10275  br label %end10276 10277end:10278  %phi = phi <4 x i8> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10279  ret <4 x i8> %phi10280}10281 10282define <1 x i32> @bitcast_v4i8_to_v1i32(<4 x i8> %a, i32 %b) {10283; SI-LABEL: bitcast_v4i8_to_v1i32:10284; SI:       ; %bb.0:10285; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10286; SI-NEXT:    v_mov_b32_e32 v5, v010287; SI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v410288; SI-NEXT:    v_lshlrev_b32_e32 v4, 8, v110289; SI-NEXT:    v_lshlrev_b32_e32 v1, 24, v310290; SI-NEXT:    ; implicit-def: $vgpr010291; SI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10292; SI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10293; SI-NEXT:    s_cbranch_execnz .LBB82_310294; SI-NEXT:  ; %bb.1: ; %Flow10295; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10296; SI-NEXT:    s_cbranch_execnz .LBB82_410297; SI-NEXT:  .LBB82_2: ; %end10298; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10299; SI-NEXT:    s_setpc_b64 s[30:31]10300; SI-NEXT:  .LBB82_3: ; %cmp.false10301; SI-NEXT:    v_and_b32_e32 v0, 0xff, v510302; SI-NEXT:    v_and_b32_e32 v2, 0xff, v210303; SI-NEXT:    v_or_b32_e32 v0, v0, v410304; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v210305; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v010306; SI-NEXT:    v_or_b32_e32 v1, v1, v210307; SI-NEXT:    v_or_b32_e32 v0, v0, v110308; SI-NEXT:    ; implicit-def: $vgpr510309; SI-NEXT:    ; implicit-def: $vgpr410310; SI-NEXT:    ; implicit-def: $vgpr210311; SI-NEXT:    ; implicit-def: $vgpr110312; SI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10313; SI-NEXT:    s_cbranch_execz .LBB82_210314; SI-NEXT:  .LBB82_4: ; %cmp.true10315; SI-NEXT:    v_add_i32_e32 v0, vcc, 3, v510316; SI-NEXT:    v_and_b32_e32 v0, 0xff, v010317; SI-NEXT:    v_add_i32_e32 v2, vcc, 3, v210318; SI-NEXT:    v_or_b32_e32 v0, v4, v010319; SI-NEXT:    v_and_b32_e32 v2, 0xff, v210320; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x300, v010321; SI-NEXT:    v_lshlrev_b32_e32 v2, 16, v210322; SI-NEXT:    v_and_b32_e32 v0, 0xffff, v010323; SI-NEXT:    v_or_b32_e32 v1, v1, v210324; SI-NEXT:    v_or_b32_e32 v0, v1, v010325; SI-NEXT:    v_add_i32_e32 v0, vcc, 0x3000000, v010326; SI-NEXT:    s_or_b64 exec, exec, s[4:5]10327; SI-NEXT:    s_setpc_b64 s[30:31]10328;10329; VI-LABEL: bitcast_v4i8_to_v1i32:10330; VI:       ; %bb.0:10331; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10332; VI-NEXT:    v_mov_b32_e32 v5, v010333; VI-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v410334; VI-NEXT:    v_lshlrev_b16_e32 v4, 8, v110335; VI-NEXT:    v_lshlrev_b16_e32 v1, 8, v310336; VI-NEXT:    ; implicit-def: $vgpr010337; VI-NEXT:    s_and_saveexec_b64 s[4:5], vcc10338; VI-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10339; VI-NEXT:    s_cbranch_execnz .LBB82_310340; VI-NEXT:  ; %bb.1: ; %Flow10341; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10342; VI-NEXT:    s_cbranch_execnz .LBB82_410343; VI-NEXT:  .LBB82_2: ; %end10344; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10345; VI-NEXT:    s_setpc_b64 s[30:31]10346; VI-NEXT:  .LBB82_3: ; %cmp.false10347; VI-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD10348; VI-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD10349; VI-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD10350; VI-NEXT:    ; implicit-def: $vgpr510351; VI-NEXT:    ; implicit-def: $vgpr410352; VI-NEXT:    ; implicit-def: $vgpr210353; VI-NEXT:    ; implicit-def: $vgpr110354; VI-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10355; VI-NEXT:    s_cbranch_execz .LBB82_210356; VI-NEXT:  .LBB82_4: ; %cmp.true10357; VI-NEXT:    v_add_u16_e32 v0, 3, v510358; VI-NEXT:    v_add_u16_e32 v2, 3, v210359; VI-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_010360; VI-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_010361; VI-NEXT:    v_mov_b32_e32 v2, 0x30010362; VI-NEXT:    v_add_u16_e32 v0, 0x300, v010363; VI-NEXT:    v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10364; VI-NEXT:    v_or_b32_e32 v0, v0, v110365; VI-NEXT:    s_or_b64 exec, exec, s[4:5]10366; VI-NEXT:    s_setpc_b64 s[30:31]10367;10368; GFX9-LABEL: bitcast_v4i8_to_v1i32:10369; GFX9:       ; %bb.0:10370; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10371; GFX9-NEXT:    v_mov_b32_e32 v5, v010372; GFX9-NEXT:    v_cmp_ne_u32_e32 vcc, 0, v410373; GFX9-NEXT:    v_lshlrev_b16_e32 v4, 8, v110374; GFX9-NEXT:    v_lshlrev_b16_e32 v1, 8, v310375; GFX9-NEXT:    ; implicit-def: $vgpr010376; GFX9-NEXT:    s_and_saveexec_b64 s[4:5], vcc10377; GFX9-NEXT:    s_xor_b64 s[4:5], exec, s[4:5]10378; GFX9-NEXT:    s_cbranch_execnz .LBB82_310379; GFX9-NEXT:  ; %bb.1: ; %Flow10380; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10381; GFX9-NEXT:    s_cbranch_execnz .LBB82_410382; GFX9-NEXT:  .LBB82_2: ; %end10383; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10384; GFX9-NEXT:    s_setpc_b64 s[30:31]10385; GFX9-NEXT:  .LBB82_3: ; %cmp.false10386; GFX9-NEXT:    v_or_b32_sdwa v0, v5, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD10387; GFX9-NEXT:    v_or_b32_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD10388; GFX9-NEXT:    v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD10389; GFX9-NEXT:    ; implicit-def: $vgpr510390; GFX9-NEXT:    ; implicit-def: $vgpr410391; GFX9-NEXT:    ; implicit-def: $vgpr210392; GFX9-NEXT:    ; implicit-def: $vgpr110393; GFX9-NEXT:    s_andn2_saveexec_b64 s[4:5], s[4:5]10394; GFX9-NEXT:    s_cbranch_execz .LBB82_210395; GFX9-NEXT:  .LBB82_4: ; %cmp.true10396; GFX9-NEXT:    v_add_u16_e32 v0, 3, v510397; GFX9-NEXT:    v_add_u16_e32 v2, 3, v210398; GFX9-NEXT:    v_or_b32_sdwa v0, v4, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_010399; GFX9-NEXT:    s_movk_i32 s6, 0x30010400; GFX9-NEXT:    v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_010401; GFX9-NEXT:    v_add_u16_e32 v0, 0x300, v010402; GFX9-NEXT:    v_add_u16_sdwa v1, v1, s6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD10403; GFX9-NEXT:    v_or_b32_e32 v0, v0, v110404; GFX9-NEXT:    s_or_b64 exec, exec, s[4:5]10405; GFX9-NEXT:    s_setpc_b64 s[30:31]10406;10407; GFX11-TRUE16-LABEL: bitcast_v4i8_to_v1i32:10408; GFX11-TRUE16:       ; %bb.0:10409; GFX11-TRUE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10410; GFX11-TRUE16-NEXT:    v_mov_b16_e32 v2.h, v0.l10411; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.l, 8, v1.l10412; GFX11-TRUE16-NEXT:    v_lshlrev_b16 v1.h, 8, v3.l10413; GFX11-TRUE16-NEXT:    s_mov_b32 s0, exec_lo10414; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr010415; GFX11-TRUE16-NEXT:    v_cmpx_ne_u32_e32 0, v410416; GFX11-TRUE16-NEXT:    s_xor_b32 s0, exec_lo, s010417; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB82_310418; GFX11-TRUE16-NEXT:  ; %bb.1: ; %Flow10419; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s010420; GFX11-TRUE16-NEXT:    s_cbranch_execnz .LBB82_410421; GFX11-TRUE16-NEXT:  .LBB82_2: ; %end10422; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010423; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]10424; GFX11-TRUE16-NEXT:  .LBB82_3: ; %cmp.false10425; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v2.h10426; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v2.l10427; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_hi1610428; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr2_lo1610429; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10430; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v0.l, v1.l10431; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v0.h, v1.h10432; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_lo1610433; GFX11-TRUE16-NEXT:    ; implicit-def: $vgpr1_hi1610434; GFX11-TRUE16-NEXT:    s_and_not1_saveexec_b32 s0, s010435; GFX11-TRUE16-NEXT:    s_cbranch_execz .LBB82_210436; GFX11-TRUE16-NEXT:  .LBB82_4: ; %cmp.true10437; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, v2.h, 310438; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, v2.l, 310439; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10440; GFX11-TRUE16-NEXT:    v_and_b16 v0.l, 0xff, v0.l10441; GFX11-TRUE16-NEXT:    v_and_b16 v0.h, 0xff, v0.h10442; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10443; GFX11-TRUE16-NEXT:    v_or_b16 v0.l, v1.l, v0.l10444; GFX11-TRUE16-NEXT:    v_or_b16 v0.h, v1.h, v0.h10445; GFX11-TRUE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10446; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.l, 0x300, v0.l10447; GFX11-TRUE16-NEXT:    v_add_nc_u16 v0.h, 0x300, v0.h10448; GFX11-TRUE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010449; GFX11-TRUE16-NEXT:    s_setpc_b64 s[30:31]10450;10451; GFX11-FAKE16-LABEL: bitcast_v4i8_to_v1i32:10452; GFX11-FAKE16:       ; %bb.0:10453; GFX11-FAKE16-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10454; GFX11-FAKE16-NEXT:    v_mov_b32_e32 v5, v010455; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v1, 8, v110456; GFX11-FAKE16-NEXT:    v_lshlrev_b16 v3, 8, v310457; GFX11-FAKE16-NEXT:    s_mov_b32 s0, exec_lo10458; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr010459; GFX11-FAKE16-NEXT:    v_cmpx_ne_u32_e32 0, v410460; GFX11-FAKE16-NEXT:    s_xor_b32 s0, exec_lo, s010461; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB82_310462; GFX11-FAKE16-NEXT:  ; %bb.1: ; %Flow10463; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s010464; GFX11-FAKE16-NEXT:    s_cbranch_execnz .LBB82_410465; GFX11-FAKE16-NEXT:  .LBB82_2: ; %end10466; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010467; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]10468; GFX11-FAKE16-NEXT:  .LBB82_3: ; %cmp.false10469; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v510470; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v210471; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr510472; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10473; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v110474; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v2, v310475; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr210476; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr310477; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10478; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v010479; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v110480; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)10481; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v110482; GFX11-FAKE16-NEXT:    ; implicit-def: $vgpr110483; GFX11-FAKE16-NEXT:    s_and_not1_saveexec_b32 s0, s010484; GFX11-FAKE16-NEXT:    s_cbranch_execz .LBB82_210485; GFX11-FAKE16-NEXT:  .LBB82_4: ; %cmp.true10486; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, v5, 310487; GFX11-FAKE16-NEXT:    v_add_nc_u16 v2, v2, 310488; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10489; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xff, v010490; GFX11-FAKE16-NEXT:    v_and_b32_e32 v2, 0xff, v210491; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10492; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v1, v010493; GFX11-FAKE16-NEXT:    v_or_b32_e32 v1, v3, v210494; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10495; GFX11-FAKE16-NEXT:    v_add_nc_u16 v0, 0x300, v010496; GFX11-FAKE16-NEXT:    v_add_nc_u16 v1, 0x300, v110497; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)10498; GFX11-FAKE16-NEXT:    v_and_b32_e32 v0, 0xffff, v010499; GFX11-FAKE16-NEXT:    v_lshlrev_b32_e32 v1, 16, v110500; GFX11-FAKE16-NEXT:    s_delay_alu instid0(VALU_DEP_1)10501; GFX11-FAKE16-NEXT:    v_or_b32_e32 v0, v0, v110502; GFX11-FAKE16-NEXT:    s_or_b32 exec_lo, exec_lo, s010503; GFX11-FAKE16-NEXT:    s_setpc_b64 s[30:31]10504  %cmp = icmp eq i32 %b, 010505  br i1 %cmp, label %cmp.true, label %cmp.false10506 10507cmp.true:10508  %a1 = add <4 x i8> %a, splat (i8 3)10509  %a2 = bitcast <4 x i8> %a1 to <1 x i32>10510  br label %end10511 10512cmp.false:10513  %a3 = bitcast <4 x i8> %a to <1 x i32>10514  br label %end10515 10516end:10517  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10518  ret <1 x i32> %phi10519}10520 10521define inreg <1 x i32> @bitcast_v4i8_to_v1i32_scalar(<4 x i8> inreg %a, i32 inreg %b) {10522; SI-LABEL: bitcast_v4i8_to_v1i32_scalar:10523; SI:       ; %bb.0:10524; SI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10525; SI-NEXT:    s_cmp_lg_u32 s20, 010526; SI-NEXT:    s_cbranch_scc0 .LBB83_410527; SI-NEXT:  ; %bb.1: ; %cmp.false10528; SI-NEXT:    s_and_b32 s4, s16, 0xff10529; SI-NEXT:    s_lshl_b32 s5, s17, 810530; SI-NEXT:    s_or_b32 s4, s4, s510531; SI-NEXT:    s_and_b32 s5, s18, 0xff10532; SI-NEXT:    s_lshl_b32 s5, s5, 1610533; SI-NEXT:    s_lshl_b32 s6, s19, 2410534; SI-NEXT:    s_and_b32 s4, s4, 0xffff10535; SI-NEXT:    s_or_b32 s5, s6, s510536; SI-NEXT:    s_or_b32 s6, s4, s510537; SI-NEXT:    s_cbranch_execnz .LBB83_310538; SI-NEXT:  .LBB83_2: ; %cmp.true10539; SI-NEXT:    s_add_i32 s16, s16, 310540; SI-NEXT:    s_and_b32 s4, s16, 0xff10541; SI-NEXT:    s_lshl_b32 s5, s17, 810542; SI-NEXT:    s_add_i32 s18, s18, 310543; SI-NEXT:    s_or_b32 s4, s5, s410544; SI-NEXT:    s_and_b32 s6, s18, 0xff10545; SI-NEXT:    s_addk_i32 s4, 0x30010546; SI-NEXT:    s_lshl_b32 s5, s19, 2410547; SI-NEXT:    s_lshl_b32 s6, s6, 1610548; SI-NEXT:    s_and_b32 s4, s4, 0xffff10549; SI-NEXT:    s_or_b32 s5, s5, s610550; SI-NEXT:    s_or_b32 s4, s5, s410551; SI-NEXT:    s_add_i32 s6, s4, 0x300000010552; SI-NEXT:  .LBB83_3: ; %end10553; SI-NEXT:    v_mov_b32_e32 v0, s610554; SI-NEXT:    s_setpc_b64 s[30:31]10555; SI-NEXT:  .LBB83_4:10556; SI-NEXT:    ; implicit-def: $sgpr610557; SI-NEXT:    s_branch .LBB83_210558;10559; VI-LABEL: bitcast_v4i8_to_v1i32_scalar:10560; VI:       ; %bb.0:10561; VI-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10562; VI-NEXT:    s_cmp_lg_u32 s20, 010563; VI-NEXT:    s_cbranch_scc0 .LBB83_410564; VI-NEXT:  ; %bb.1: ; %cmp.false10565; VI-NEXT:    s_and_b32 s4, s16, 0xff10566; VI-NEXT:    s_lshl_b32 s5, s17, 810567; VI-NEXT:    s_or_b32 s4, s4, s510568; VI-NEXT:    s_and_b32 s5, s18, 0xff10569; VI-NEXT:    s_lshl_b32 s6, s19, 810570; VI-NEXT:    s_or_b32 s5, s5, s610571; VI-NEXT:    s_and_b32 s4, s4, 0xffff10572; VI-NEXT:    s_lshl_b32 s5, s5, 1610573; VI-NEXT:    s_or_b32 s6, s4, s510574; VI-NEXT:    s_cbranch_execnz .LBB83_310575; VI-NEXT:  .LBB83_2: ; %cmp.true10576; VI-NEXT:    s_add_i32 s16, s16, 310577; VI-NEXT:    s_and_b32 s4, s16, 0xff10578; VI-NEXT:    s_lshl_b32 s5, s17, 810579; VI-NEXT:    s_add_i32 s18, s18, 310580; VI-NEXT:    s_or_b32 s4, s5, s410581; VI-NEXT:    s_and_b32 s5, s18, 0xff10582; VI-NEXT:    s_lshl_b32 s6, s19, 810583; VI-NEXT:    s_addk_i32 s4, 0x30010584; VI-NEXT:    s_or_b32 s5, s6, s510585; VI-NEXT:    s_and_b32 s4, s4, 0xffff10586; VI-NEXT:    s_lshl_b32 s5, s5, 1610587; VI-NEXT:    s_or_b32 s4, s5, s410588; VI-NEXT:    s_add_i32 s6, s4, 0x300000010589; VI-NEXT:  .LBB83_3: ; %end10590; VI-NEXT:    v_mov_b32_e32 v0, s610591; VI-NEXT:    s_setpc_b64 s[30:31]10592; VI-NEXT:  .LBB83_4:10593; VI-NEXT:    ; implicit-def: $sgpr610594; VI-NEXT:    s_branch .LBB83_210595;10596; GFX9-LABEL: bitcast_v4i8_to_v1i32_scalar:10597; GFX9:       ; %bb.0:10598; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10599; GFX9-NEXT:    s_cmp_lg_u32 s20, 010600; GFX9-NEXT:    s_cbranch_scc0 .LBB83_410601; GFX9-NEXT:  ; %bb.1: ; %cmp.false10602; GFX9-NEXT:    s_and_b32 s4, s16, 0xff10603; GFX9-NEXT:    s_lshl_b32 s5, s17, 810604; GFX9-NEXT:    s_or_b32 s4, s4, s510605; GFX9-NEXT:    s_and_b32 s5, s18, 0xff10606; GFX9-NEXT:    s_lshl_b32 s6, s19, 810607; GFX9-NEXT:    s_or_b32 s5, s5, s610608; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff10609; GFX9-NEXT:    s_lshl_b32 s5, s5, 1610610; GFX9-NEXT:    s_or_b32 s6, s4, s510611; GFX9-NEXT:    s_cbranch_execnz .LBB83_310612; GFX9-NEXT:  .LBB83_2: ; %cmp.true10613; GFX9-NEXT:    s_add_i32 s16, s16, 310614; GFX9-NEXT:    s_and_b32 s4, s16, 0xff10615; GFX9-NEXT:    s_lshl_b32 s5, s17, 810616; GFX9-NEXT:    s_add_i32 s18, s18, 310617; GFX9-NEXT:    s_or_b32 s4, s5, s410618; GFX9-NEXT:    s_and_b32 s5, s18, 0xff10619; GFX9-NEXT:    s_lshl_b32 s6, s19, 810620; GFX9-NEXT:    s_or_b32 s5, s6, s510621; GFX9-NEXT:    s_addk_i32 s4, 0x30010622; GFX9-NEXT:    s_addk_i32 s5, 0x30010623; GFX9-NEXT:    s_and_b32 s4, s4, 0xffff10624; GFX9-NEXT:    s_lshl_b32 s5, s5, 1610625; GFX9-NEXT:    s_or_b32 s6, s4, s510626; GFX9-NEXT:  .LBB83_3: ; %end10627; GFX9-NEXT:    v_mov_b32_e32 v0, s610628; GFX9-NEXT:    s_setpc_b64 s[30:31]10629; GFX9-NEXT:  .LBB83_4:10630; GFX9-NEXT:    ; implicit-def: $sgpr610631; GFX9-NEXT:    s_branch .LBB83_210632;10633; GFX11-LABEL: bitcast_v4i8_to_v1i32_scalar:10634; GFX11:       ; %bb.0:10635; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10636; GFX11-NEXT:    s_cmp_lg_u32 s16, 010637; GFX11-NEXT:    s_mov_b32 s4, 010638; GFX11-NEXT:    s_cbranch_scc0 .LBB83_410639; GFX11-NEXT:  ; %bb.1: ; %cmp.false10640; GFX11-NEXT:    s_and_b32 s5, s0, 0xff10641; GFX11-NEXT:    s_lshl_b32 s6, s1, 810642; GFX11-NEXT:    s_and_b32 s7, s2, 0xff10643; GFX11-NEXT:    s_lshl_b32 s8, s3, 810644; GFX11-NEXT:    s_or_b32 s5, s5, s610645; GFX11-NEXT:    s_or_b32 s6, s7, s810646; GFX11-NEXT:    s_and_b32 s5, s5, 0xffff10647; GFX11-NEXT:    s_lshl_b32 s6, s6, 1610648; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10649; GFX11-NEXT:    s_or_b32 s5, s5, s610650; GFX11-NEXT:    s_and_not1_b32 vcc_lo, exec_lo, s410651; GFX11-NEXT:    s_cbranch_vccnz .LBB83_310652; GFX11-NEXT:  .LBB83_2: ; %cmp.true10653; GFX11-NEXT:    s_add_i32 s0, s0, 310654; GFX11-NEXT:    s_add_i32 s2, s2, 310655; GFX11-NEXT:    s_and_b32 s0, s0, 0xff10656; GFX11-NEXT:    s_lshl_b32 s1, s1, 810657; GFX11-NEXT:    s_and_b32 s2, s2, 0xff10658; GFX11-NEXT:    s_lshl_b32 s3, s3, 810659; GFX11-NEXT:    s_or_b32 s0, s1, s010660; GFX11-NEXT:    s_or_b32 s1, s3, s210661; GFX11-NEXT:    s_addk_i32 s0, 0x30010662; GFX11-NEXT:    s_addk_i32 s1, 0x30010663; GFX11-NEXT:    s_and_b32 s0, s0, 0xffff10664; GFX11-NEXT:    s_lshl_b32 s1, s1, 1610665; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10666; GFX11-NEXT:    s_or_b32 s5, s0, s110667; GFX11-NEXT:  .LBB83_3: ; %end10668; GFX11-NEXT:    s_delay_alu instid0(SALU_CYCLE_1)10669; GFX11-NEXT:    v_mov_b32_e32 v0, s510670; GFX11-NEXT:    s_setpc_b64 s[30:31]10671; GFX11-NEXT:  .LBB83_4:10672; GFX11-NEXT:    ; implicit-def: $sgpr510673; GFX11-NEXT:    s_branch .LBB83_210674  %cmp = icmp eq i32 %b, 010675  br i1 %cmp, label %cmp.true, label %cmp.false10676 10677cmp.true:10678  %a1 = add <4 x i8> %a, splat (i8 3)10679  %a2 = bitcast <4 x i8> %a1 to <1 x i32>10680  br label %end10681 10682cmp.false:10683  %a3 = bitcast <4 x i8> %a to <1 x i32>10684  br label %end10685 10686end:10687  %phi = phi <1 x i32> [ %a2, %cmp.true ], [ %a3, %cmp.false ]10688  ret <1 x i32> %phi10689}10690